NCH-RSL15-284-101Q40-ACG

DATA SHEET

www.onsemi.com

Bluetooth⁾5.2 Wireless MCU

RSL15

1

40

Introduction

QFN40 5x5, 0.4P

CASE 485CR

®

RSL15 is an ultra−low power secure Arm Cortex −M33

processor−based Bluetooth Low Energy 5.2 wireless MCU designed

for connected smart devices in industrial and medical applications.

The comprehensive, yet easy−to−use Software Development Kit

(SDK) provides sample applications that demonstrate the hardware

capabilities to enable security with the Cybersecurity Platform,

acquire sensor data in Smart Sense mode, configure the built−in power

management and utilize Bluetooth Low Energy features.

WLCSP40

CASE 567HU

MARKING DIAGRAM

Key Features

• Bluetooth Low Energy 5.2 Certified with Key Features:

1

RSL15

AWLYYWWG

G

♦ Up to 10 simultaneous connections

♦ Long Range (Coded PHY)

♦ 2 Mbit PHY (High Speed)

♦ Angle of Arrival (AoA) and Angle of Departure (AoD)

♦ Extended Advertising

RSL15 = Specific Device Code

♦ Backwards compatibility and support for earlier Bluetooth Low

Energy specifications including 5.1, 5.0, 4.2, 4.1 and 4.0

• Ultra−low Power Operation:

A

= Assembly Location

= Wafer Lot

WL

YY

WW

G

= Year

= Work Week

= Pb−Free Package

♦ Sleep Mode (GPIO Wakeup) @ 3 V VBAT: 36 nA

♦ Sleep Mode (Crystal Oscillator, RTC Timer Wakeup) @ 3 V

VBAT: 57 nA

(Note: Microdot may be in either location)

♦ Smart Sense Mode allows some digital and analog peripherals to

remain active to monitor and acquire data from external sensors

at a very low system−level power consumption

♦ Continuous ADC operation in Smart Sense Mode with wakeup

on ADC threshold @ 3 V VBAT: 206 nA

♦ Peak Rx Current 1 Mbps @ 3 V VBAT: 2.7 mA

♦ Peak Tx Current 0 dBm Output Power @ 3 V VBAT: 4.3 mA

♦ Non−Connectable Advertising at 5 s Intervals @ 3 V VBAT:

1.1 mA (Average)

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

Throughout this document, in reference to memory

sizes, the unit KB denotes 1024 Bytes.

Key Features (continued)

• 80 KB RAM (64 KB user RAM, 16 KB

♦ Connectable Advertising at 5 s Intervals @ 3 V VBAT: 1.3 mA

(Average)

RAM for Baseband)

• Flexible Power Management:

• Rx Sensitivity (BLE Mode, 1 Mbps): −96 dBm

• Rx Sensitivity (BLE Mode, 2 Mbps): −94 dBm

• Configurable Tx Power: −17 dBm to +6 dBm

• Data Rate of 62.5 kbps to 2000 kbps

1.2 V – 3.6 V VBAT.

Directly connect 1.5 V Silver−oxide or 3 V

Coin Cells without any external active

components

• Two SPI ports with QSPI capability

• Arm Cortex−M33 processor clocked up to 48 MHz

™

• Cybersecurity Platform with Arm CryptoCell −312 for End−to−end

Product Security with Secure Boot, Root of Trust, Lifecycle

Management, Secure Key Management, and Application and Data

Security

®

• Arm TrustZone to enable secure execution zones

• Two flash memory sizes available,

284 KB Flash (QFN only) or 512 KB Flash

1

Publication Order Number:

April, 2023 − Rev. 4

RSL15/D

RSL15

ORDERING INFORMATION

Device

Flash Memory

284 KB

Package

QFN40

Shipping

NCH-RSL15-284-101Q40-ACG

NCH-RSL15-512-101Q40-ACG

NCH-RSL15-512-101WC40-ABG

1500 Tape/Reel

512 KB

QFN40

512 KB

WLCSP40

APPLICATIONS

Connected Device

• Drug Injection Pens

• Blood Glucose Meters

• Wearable Bracelets

• Blood Analyzers

• Virus Detectors

• Smart Toothbrushes

• Heart Rate Monitors

• Bottle Caps

• Sleep Monitors

• Avalanche Detectors

• Electronic Pens

• Electronic Bikes

• Bicycle Computers

• Pet Trackers

Smart Industry

• Electronic Tags

• Power Tools

• Shopping Cart Trackers

• Coldchain Monitors

• Electronic Labels

• Beverage Dispensers

• Charge Control Systems

• Worker Safety Applications

• Battery Management Systems

• Machine Monitors

• Data Loggers

• Helmets

• Pellet Tracking

• Electronic Wheel Nuts

• Food Tracking Sensors

• E−Stethoscopes

• Shavers

• Vacuum Cleaners

• SpO2 Monitors

• Wearable Head Bands

Smart Home

• Smart Circuit Breakers

• Smart Thermometers

• Smart Light Switches

• Smart Meters

• Coffee Makers

• Smart Refrigerators

• Air Purifiers

Smart Building

• Electronic Access Badges

• Air Filter Sensors

• Windows Surveillance

• Smoke Alarms

• Garage Door Controls

• Sprinkler Control Systems

• Key Pads

• Energy Harvesting Switches

• HVAC Systems

Smart City

• People and Asset Tracking

• Door Access Control

• Fleet Management Systems

• Outdoor Robots

• Bioprocessing Equipment

• Educational Robots

• Vending Machines

• Lighting Control

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2

RSL15

HIGH−LEVEL BLOCK DIAGRAM

Pulse Counter

Arm Cortex-M33

Bluetooth Low Energy 5.2

RF Front End

FPU

DSP Extension

TrustZone

Successive

Approx ADC

MPU

SPI/QSPI

(2x)

DMA

I2C

(2x)

Arm CryptoCell-312

Power Management

12-bit PWM

(5x)

Secure Boot ROM

4x Timer (24-bit)

8-bit

PWM-AO

Buck Converter

LDO

GPIO

UART / LIN

ACOMP

284 KB

Crystal and RC Oscillators

Debug via SWJ-DP

or

512 KB

Low-Speed

ADC

Flash Memory

Temp

Sensors

Current

Source

64 KB RAM

ULP Data Acquisition

Subsystem

(8 banks of 8 KB)

DAC

Figure 1. High−Level Block Diagram

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3

RSL15

FEATURES

Arm Cortex−M33 Processor

broad voltage supply range. Any voltage in the range of

1.2 V to 3.6 V can be used directly without the need for

external power conversion allowing for simple use of

common coin cell batteries such as 3 V coins cells and 1.5 V

silver oxide cells.

The Cortex−M33 32−bit Armv8−M processor is designed

for IoT and deeply embedded applications that require high

performance, power efficiency and security. The processor

has many features to execute high performance applications

such a Floating−Point Unit (FPU), DSP extensions and

Memory Protection Unit (MPU). Secure debug is done

through the SWJ−DP which combines JTAG−DP and

SW−DP for either JTAG probe or Serial Wire Debug (SWD)

connection.

Power Modes

Several power modes are available to reduce power

consumption while still maintaining system responsiveness.

Each mode is configurable with RAM retention and wakeup

sources. Smart Sense mode allows some digital and analog

peripherals to remain active to monitor and acquire data

from external sensors at a very low system−level power

consumption.

Cybersecurity Platform

The Cortex−M33 processor with TrustZone Armv8−M

security extensions forms the basis of the security platform.

The Arm CryptoCell−312 allows for end−to−end product

security with Secure Boot with Root of Trust, secure

lifecycle management, secure key management, and

application and data encryption using symmetric or

asymmetric cryptography. Arm TrustZone enables secure

software access control. User available cryptographic

services such as SHA1, SHA256, keyed−hash message

authentication code (HMAC) and True Random Number

Generator (TRNG) allow for development of custom

proprietary security solutions. The TRNG conforms to

NIST SP800−90B, NIST SP800−22, FIPS 140−2, and BSI

AIS−31.

Please note that this mobile telecommunications Radio

Access Network (RAN) equipment is designed for civil use,

which also meet the provisions of paragraphs a.2 to a.4 of the

Cryptography Note (Note 3 in Category 5—Part 2), having

an RF output power limited to 0.1 W (20 dBm) or less, and

supporting 16 or fewer concurrent users.

Flexible Clocking

Two crystal oscillators and two internal RC oscillators are

available on RSL15 to offer many clocking configurations.

The primary oscillator is based on a 48 MHz crystal, which

is necessary for any connected RF operation. The secondary

oscillator is based on a 32 kHz crystal, which can be used for

precision timing even in low power modes. When precision

timing is not required, the internal fast RC oscillator can be

used in place of the 48 MHz crystal oscillator for general

non−RF processing. Likewise, the internal 32 kHz RC

oscillator can be used in place of the 32 kHz crystal oscillator

for certain use cases. Additionally, 48 MHz and 32 kHz

external clocks can be driven into RSL15 from external

clock sources.

Analog to Digital Converters (ADCs)

RSL15 has two ADCs, a high−speed 12−bit SAR ADC for

fast conversion of analog inputs up to 2 Msps and Low Speed

ADC for slower conversion up to 50 ksps. There is also an

integrated temperature sensor that can be read by the Low

Speed ADC.

RF Subsystem

The RF architecture is based on a 2.4 GHz RF Front End

that implements the physical layer of the BLE 5.2 standard

as well as other proprietary or custom protocols. The modem

is of the FSK type with a single−ended RF Port, which

alleviates the need for an external balun.

Flexible I/O

General purpose I/O can be mapped to GPIO, SPI, QSPI,

I2C, UART, LIN, PWM, PCM, pulse counter, clock

input/output and analog functions. RSL15 facilitates an

analog comparator, as well as a DAC for generating bias

voltages for external components, and a current source

output.

RF Operation

Bluetooth 5.2 certified baseband and protocol stack has

features such as 2 Mbps RF link, Angle−Of−Arrival,

Angle−Of−Departure, and Coded PHY (“Long Range”).

The hardware enables implementation of custom protocols.

Memory Architecture

The memory architecture is centered around the Arm

Cortex−M33. The flash memory contains application code

as well as the protocol stack. The RAM architecture is

flexible allowing for powering only the amount of memory

needed for the application. A total of 64 KB user RAM is

available, implemented as eight times 8 KB. An additional

16 KB is available for the digital baseband hardware. A

DMA controller is available for easy data streaming

between a peripheral/interface and memories.

Localization

RSL15 supports Angle−of−Arrival (AoA) and

Angle−of−Departure (AoD) as defined by the Bluetooth

Low Energy standard along with RSSI for enhanced

localization capabilities.

Flexible Power Management

Built−in DC−DC converter with buck and LDO modes

requiring few external passive components allows for a

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4

RSL15

Software Development Kit

many other software components and tools to enable rapid

application development.

Contains Eclipse−based onsemi IDE plus support for

other industry standard development environments,

Bluetooth protocol stack, sample applications, libraries and

RoHS Compliant Device

RSL15 is RoHS compliant.

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5

RSL15

ARCHITECTURE OVERVIEW

Introduction

management and an extensive set of peripherals. The wide

supply voltage input, flexible I/O and clocking scheme offer

maximum design flexibility.

RSL15 is a highly integrated secure Arm Cortex−M33

based Bluetooth Low Energy 5.2 wireless MCU

system−on−chip with flash and RAM, built−in power

Detailed Block Diagram

Accumulator

POR

48MHz XTAL

32kHz XTAL

(XTALCLK_FAST)

(XTALCLK_SLOW)

FIFO

(Power-On

L N A

Reset)

Threshold

PA

RCCLK_FAST

Oscillator

RCCLK_SLOW

Oscillator

ULP Data

Acquisition

Clock Management

Synthesizer

RCCR

Brown-out

Detection

Pulse Counter

To Arm

Cortex-M33

Flash

284KB/

512KB

RF System

Successive

To Power Management

Approx ADC

SPI/QSPI

(2x)

Clock Detect

4x Timer (24-bit)

Watchdog Timer

Secure Boot ROM

I2C

Digital Base

Band

GPIO

ROM

(2x)

PLL

Functions

12-bit PWM

(5x)

16 KB RAM

MoDem

RAM (64KB)

8-bit

PWM-AO

8KB

Arm Cortex-M33

Floating Point Unit (FPU)

Memory Protection Unit (MPU)

CryptoCell-312

GPIO

Power Management

8KB

VBAT

VCC

UART / LIN

ACOMP

VDDPA

VDDM

VDDC

DC/DC

Converter

VDC

DMA Controller

Low-Speed

ADC

VDDRF LDO

VDDRF

TrustZone/TRNG

CAP1

CAP0

Temp

VDDA CHARGE

PUMP

Sensors

Current

Source

VDDA

VDDRET

VDDFLASH LDO

SWJ-DP interface

VDDFLASH

DAC

Figure 2. RSL15 Detailed Block Diagram

DMA Controller

Arm Cortex−M33 Processor

The Cortex−M33 32−bit Armv8−M processor is designed

for IoT and deeply embedded applications that require high

performance, power efficiency and security. The processor

has many features to execute high performance applications

such a Floating−Point Unit (FPU), DSP extensions and

Memory Protection Unit (MPU). Secure debug is done

through the dedicated Serial Wire Debug Port (SW−DP)

interface.

The Direct Memory Access (DMA) Controller allows

background transfers between peripherals and memories

without processor intervention. The processor can be in a

low power state or used for other computational tasks while

the transfer occurs. The DMA is connected to the processor,

peripherals and RAM memories and has four independent

channels.

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6

RSL15

Cybersecurity Platform

• PA (Power Amplifier) with up to +6 dBm output power

for Bluetooth

The Cortex−M33 processor with TrustZone Armv8−M

security extensions forms the basis of the security platform

that is extended with Arm CryptoCell−312.

• RSSI (Received Signal Strength Indication) with 60 dB

nominal range with 1 dB steps (not considering AGC)

• Fully integrated ultra−low power frequency synthesis

with fast settling time, with direct digital modulation in

transmission (pulse shape programmable)

• 48 MHz XTAL reference

• Fully−integrated FSK−based modem with

programmable pulse shape, data rate, and modulation

index

Secure Boot with Root of Trust

The secure boot ROM authenticates firmware in flash

with a certificate−based mechanism using a private−public

key scheme. This is the basis of the hardware Root of Trust.

This same mechanism ensures continuity of the hardware

Root of Trust after secure Firmware−Over−The−Air

(FOTA) update.

• Digital baseband (DBB) with link layer functionalities,

including automatic packet handling with preamble &

sync, CRC, and separate Rx and Tx 128−bytes FIFOs

• The 2.4 GHz radio front−end contains also a

highly−flexible digital baseband − in terms of

modulation schemes, configurability and

programmability – in order to support Bluetooth Low

Energy technology and proprietary protocols. It allows

for programmable data rates from 62.5 kbps up to

2 Mbps, FSK with programmable pulse shape and

modulation index.

Data and Application Encryption

User available cryptographic services including

AES−128, AES−256, SHA−256, Hash Message

Authentication Code (HMAC), PKA (Public Key

Accelerator), ChaCha and AIS−31 compliant True Random

Number Generator (TRNG) allow for development of

custom proprietary security solutions.

TrustZone

Enables secure software access control to protect critical

software and hardware resources.

• The 2.4 GHz radio front−end also includes Manchester

encoding and Data whitening. The packet handling

includes:

Secure Lifecycle State Management

Lifecycle states refers to the multiple states RSL15 could

go through during its lifetime. The first lifecycle state is the

Chip Manufacture (CM) Lifecycle State. The device

manufacture transitions to the Device Manufacture (DM)

Lifecycle State. At field deployment, it is transitioned to the

Secure (SE) Lifecycle State. A Return to Manufacturer

(RMA) State is also available. Lifecycle state management

ensures the authenticity, integrity and confidentiality of

code and data belonging to different stakeholders at each

lifecycle.

♦ Automatic preamble and sync word insertion

♦ Automatic packet length handler

♦ Basic address check

♦ Automatic CRC calculation and verification with a

programmable CRC polynomial

♦ Multi−frame support

• Coexistence signals to identify the RF front−end is busy

for Bluetooth or other traffic

In addition to the Secure Lifecycle States, an Energy

Harvesting (EH) Mode is available for applications that

require fast cold startup (initial application of VBAT) but do

not require secure boot with Root of Trust. This mode is

especially useful when RSL15 is used in energy harvesting

systems.

Bluetooth Low Energy

RSL15 is Bluetooth 5.2 certified with the following

Bluetooth LE features:

• Angle of Arrival (AoA) and Angle of Departure (AoD)

• LE Long Range (Coded PHY)

• 2 Mbit PHY (High Speed)

• LE Extended Advertising

RF Subsystem

The RSL15 2.4 GHz radio front−end implements the

physical layer for the Bluetooth Low Energy standard and

other standard, proprietary, or custom protocols.

It operates in the worldwide deployable 2.4 GHz ISM

band (2.4000 to 2.4835 GHz).

• High Duty Cycle Non−Connectable Advertising

• LE Channel Selection Algorithm #2

• Advertising Channel Index

• GATT Caching

• HCI support for debug keys in LE Secure Connections

• Sleep clock accuracy update mechanism

• ADI field in scan response data

RF Architecture

The 2.4 GHz radio front−end is based on a low−IF

architecture and comprises the following building blocks:

• High performance single−ended RF port which

alleviates the need for an external balun

• On−chip matching network with 50 W RF input

• Low power LNA (low noise amplifier), and mixer

• Host channel classification for secondary advertising

• Periodic Advertising Sync Transfer

• Backwards compatibility and support for earlier

Bluetooth Low Energy specifications including 5.1, 5.0,

4.2, 4.1 and 4.0

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7

RSL15

Power Management

1. BUCK Mode Operation

2. LDO Mode Operation

The flexible power management of RSL15 allows for a

wide range of battery voltages without the need for external

power conversion. Two key modes of the DC−DC converter

are:

The power management unit is shown in Figure 3.

VDC

VCC

CAP0 CAP1

DC−DC

BUCK/LDO

Converter

Charge

VDDA

Pump

VBAT

VDDA

VDDFLASH

LDO

VDDM LDO

VDDPA LDO

VDDO Domain

VDDFLASH

VDDC LDO

VDDO

VDDRF LDO

VDDRF

Brown Out Protection

Figure 3. Power Management Unit

BUCK Mode can be used for battery voltages above 1.4 V.

In this case the internal DC−DC converter regulates the

battery voltage VBAT to a voltage VCC of approximately

1.2 V. The VCC voltage is then converted (using a charge

pump) to an approximate 2.4 V voltage VDDA, which is

used to power the analog blocks (excluding the RF Blocks).

VCC and VDDA require external capacitors. Additionally,

BUCK Mode Operation requires an inductor to be placed

between the VCC and VDC pins.

LDO Mode is typically used for battery voltages at 1.4 V

and below (but can be used for the entire operating voltage).

In this case a linear LDO generates a voltage VCC of 1.2 V.

A charge pump then generates a 2.4 V voltage for the analog

blocks.

VDDRF is a regulated voltage used to supply the RF

system. VDDRF is trimmed by onsemi as part of the device

manufacturing process.

A separate supply exists for powering the flash, i.e.

VDDFLASH. VDDFLASH is trimmed by onsemi as part of

the device manufacturing process.

• VDDC is the voltage for the internal digital blocks –

excluding digital RAM and GPIOs. VDDC is trimmed

by onsemi as part of the device manufacturing process

• VDDM is the voltage for the RAM blocks. VDDM is

trimmed by onsemi as part of the device manufacturing

process

• VDDPA is the voltage used to supply the RF power

amplifier (used in RF Tx mode). The VDDPA setting

depends on the output power level selected

VDDO is an input to the RSL15 and constitutes the logical

high level for the digital I/Os, i.e. if VDDO is connected to

VBAT the GPIO signal swing will be between GND and

VBAT.

The RSL15 power management unit allows for operation

across wide temperature and voltages ranges at low power

consumption and monitors the battery voltage to ensure

reliable operation. If the battery voltage dips below the

Power−On Reset (POR) voltage, a POR is asserted to the

system. This also prevents possible damage to RSL15 when

the battery is inserted or removed.

Three additional regulators generate voltages for the

system (none require external components):

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8

RSL15

Reset

Standby Mode is low power but with faster wakeup time

than Sleep Mode.

The Power Management Unit automatically resets the

internal systems during power supply disruptions such as

insufficient battery voltage or during battery

insertion/removal. Upon power supply rise (such as battery

insertion), the system is held in Power−On−Reset until

sufficient internal voltages are reached and stabilized. When

POR is released, the boot ROM execution begins using the

RCCLK clock @ 3 MHz.

Smart Sense mode takes advantage of the low power

capability of Sleep Mode but also allows some digital and

analog peripherals to remain active with minimal processor

intervention. Smart Sense mode allows RSL15 to not only

remain responsive to external events, but also monitor and

acquire data from external sensors with very low

system−level power consumption.

A reset can also be issued by software, watchdog timer

expiration, invalid or missing clock detected by the clock

detector, or by asserting the nRESET pin.

Idle Mode allows for some power savings with the fastest

wakeup time through disabling of internal clocks.

Sleep, Standby and Smart Sense modes have the ability of

RAM retention (configurable amount of RAM to be

retained) and allow for configurable wakeup sources.

Wakeup sources include GPIO transition (pin−based

wakeup), timer, comparator, ADC threshold or sample FIFO

full.

Power Modes Overview

The power modes are available to reduce power

consumption while still maintaining system responsiveness.

The low power modes are Sleep, Standby, Smart Sense and

Idle.

Sleep Mode is the lowest power mode but with the longest

wakeup time.

An overview of the power modes is shown in Table 1. The

peripherals and subsystems available in each power mode

are described below.

Table 1. POWER MODES OVERVIEW

Power Mode

Description

Sleep Mode

The lowest power mode. Processor and RF subsystem powered down and not clocked.

Only selected wakeup sources are powered. Memory retention (and amount of memory retained)

is optional. Some peripherals are available in Sleep Mode. On wakeup, the ROM restores the

system before program execution begins.

Smart Sense Mode

Standby Mode

Smart Sense Mode takes advantage of the low power capability of Sleep Mode but also allows

some digital and analog peripherals to remain active with minimal processor intervention.

Smart Sense Mode allows RSL15 to not only remain responsive to external events, but also

monitor and acquire data from external sensors at a very low system−level power consumption.

A low power mode with faster wakeup time than Sleep Mode. Processor and RF subsystem

powered with lower voltage and not clocked. Only selected wakeup sources are powered.

Memory retention (and amount of memory retained) is configurable. Some peripherals are

available in Standby Mode. On wakeup, the program is executed directly out of retained RAM.

Idle Mode

Run Mode

A mode to save power for a short period of time when very fast wakeup is required. Processor,

RF subsystem and memory powered as in Run Mode but not clocked.

Processor, RF subsystem and memory powered normally – clocks are active, all peripherals

available.

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9

RSL15

Peripherals and Subsystems Availability in Power Modes

VDDA can be kept active even in Sleep, Smart Sense and

The different power modes allow for low power operation

in many types of applications. When applications utilize one

or more external sensors that require continued biasing

regardless of the power mode of RSL15, it may be possible

to use the VDDA voltage for this purpose.

Standby Modes.

Table 2 describes the peripherals available in all power

modes.

Table 2. POWER MODE PERIPHERAL AVAILABILITY

Power Mode

Run

On

n/a

On

Idle

On

Off

n/a

On

Standby

Off

Smart Sense

Off

Sleep

Off

Component

Processor

Baseband/RF

RAM Retention

CryptoCell

RTC

Off

Available

On or Off

Available

On or Off

Available

On or Off

Off

ULP Data Acquisition

Subsystem

Successive Approximation

ADC

On

On or Off

Off

Pulse Counter

Comparator

DAC

On

On or Off

Off

On or Off

Off

On or Off

Off

ACS−PWM

PWM

On or Off

Off

On or Off

Off

On or Off

Off

Low Speed ADC

32k Clock Output

I2C

Off

On or Off

Off

On or Off

Off

On or Off

Off

SPI

Off

UART

Off

LIN

Off

PCM

Off

Current Source

Temp Sensor

Off

ULP Data Acquisition Subsystem

This enables simple processing and storage of a limited

number of samples from a pulse counter or the Successive

Approximation ADC while in the low power mode, Smart

Sense mode, for the lowest power operation.

The ULP Data Acquisition Subsystem comprises a small

FIFO, Accumulator and Threshold Comparator that can be

used in combination with the Successive Approximation

ADC and pulse counter to perform data acquisition and

rudimentary data processing and decision making.

Available in all power modes.

wakeup source

FIFO

DMA

sample from SAR−ADC

Pulse count

Accumulator

wakeup source

Threshold

SRC_SEL

SUM_EN

Figure 4. ULP Data Acquisition Subsystem.

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10

RSL15

The ULP Data Acquisition Subsystem has various

when precision timing is required. Additionally, clocks can

be sourced externally with the 48 MHz and 32 kHz clock

inputs.

A built−in clock detector ensures a proper system reset in

case the system clock goes below 2 kHz.

features to further reduce power consumption such as Burst

Sampling Mode, which allows for bursts of high speed

sampling followed by an adjustable delay between sampling

bursts.

The pulse counter can be configured to accept inputs from

any of GPIO[3:0]. It counts pulses from these GPIOs during

a set window ranging from 1 to 1024 clock cycles (based on

a 32 kHz clock).

Overall, the ULP Data Acquisition Subsystem operation

can be summarized as follows:

General Purpose Input/Output (GPIO)

RSL15 contains highly flexible general purpose

input/output (GPIO) pins that can be configured as digital

input or output, communication interfaces, clocks, wakeup

sources or analog functions. Communication interfaces can

be routed to any GPIO. Other functions are available on

select GPIO, see section Pin Definition and Multiplexing.

Each GPIO has a software configurable pull up/down

resistor, debounce LPF for I2C and four drive strengths

options.

Accumulation

• An accumulation can be done with a configured

number of samples ranging from 1 to 16 samples

• This mode is enabled when SUM_EN is set on Figure 4

• The accumulated value is stored in the FIFO

Analog

Threshold Detection

Successive Approximation ADC (SAR ADC)

• Two thresholds can be configured: one when the input

value goes higher than the threshold, and one when the

input value goes lower than the threshold

• This mode allows the system to wake up after a

configured number of consecutive samples generated

are greater than or lower than the configurable

threshold.

The Successive Approximation ADC (SAR ADC)

generates 12−bit samples up to 2 Msps sample frequency.

The SAR ADC is auto calibrated during operation for

optimal INL/DNL performance.

Low Speed ADC Converter (LSAD)

This is a combined integrating and algorithmic ADC that

has a resolution varying from 8 to 14 bits depending on

configuration. While converting, the input signal can be

integrated across one or more clock cycles (depending on

configuration). ADC sampling rate can be up to 50 ksps.

This ADC converter is also used to monitor the VBAT input

voltage. It can also be configured to measure single ended or

differential input voltages.

Acquisition

• Acquired samples are stored in the FIFO. FIFO size can

be 1 to 16 samples

Clocking

Oscillators

The following oscillators are available:

• 48 MHz crystal oscillator (RFCLK) typically used in

RUN Mode when RF operation is required. Prescalers

exist to provide divided clocks (including system clock)

to other parts of the system

• A fast RC oscillator (RCCLK) can provide an

alternative to the 48 MHz crystal oscillator. However,

RF operation is not possible using the fast RC

Oscillator

Pulse Counter

A pulse counter can be driven by one of GPIO[3:0]. It

counts pulses from these GPIOs during a set interval.

Analog Comparator

RSL15 contains a low−power comparator that can be

active in Standby, Sleep and Smart Sense mode. It has 3

different settings to trade off response time with power

consumption, Low Power, Normal and High Speed, see

section Analog Comparator Specifications (ACOMP).

• A 32 kHz crystal oscillator (XTAL32K) typically used

in Sleep and Standby Modes for precision timing and to

maintain the real−time clock (RTC)

DAC

RSL15 contains a low−power DAC that can be used for

sensor biasing purposes. To optimize power consumption

there is also a buffer that can be disabled if the load is high

impedance.

• A slow RC oscillator (RC32) that can be an alternative

to the 32 kHz crystal oscillator for certain use cases.

Clock Management

Current Source

Flexible clock management allows the different clock

sources to be used in power−efficient ways and to minimize

external components. Internal RC oscillators can be used for

fast startup and then easily switched to crystal oscillators

A built−in current source with adjustable output from

1ꢀmA to 16 mA. The current source may be applied for

temperature measurements using an external thermistor

connected to a GPIO.

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11

RSL15

Peripherals

UART

The

general−purpose

Universal

Asynchronous

Timers

Receiver−Transmitter (UART) uses a standard data format

with one start bit, eight data bits and one stop bit.

There are four independent 24−bit timers that can operate

as single−shot, multi−shot or free−run. An interrupt can be

generated on timer expiration. Also, a GPIO interrupt can

capture and store the current timer value.

LIN

The Local Interconnect Network (LIN) is an

asynchronous 2−wire interface. The LIN module operates as

a responder node on the bus, supporting version 2.2 of the

LIN specification.

Watchdog

The independent watchdog timer cannot be disabled. It

must be reloaded at regular intervals. At the first timer

expiration, an interrupt is generated and the timer is

reloaded. At the second timer expiration, a reset is issued to

the system.

PCM

The highly configurable PCM (Pulse Code Modulation)

interface can be used to stream data in and out of RSL15.

PWM

RTC

The PWM (Pulse Width Modulation) controller can

output on five independent channels with configurable

period, duty cycle and offset. The PWM has 12−bit

resolution with an optional 8−bit dithering per channel for

lighting applications.

The RTC timer consists of a 32−bit free−running

up−counter, clocked by the 32 kHz clock.

Activity Counter

The activity counters help to analyze how long the system

has been running, and how much the CPU and the flash have

been used by the application in a period of time. This is

useful information to estimate and optimize the power

consumption of the application.

Additionally, one 8−bit ACS−PWM channel fixed on

GPIO[4] can be operational in low power modes.

I2C

The I2C controller consists of 2 independent channels of

the two−wire interface including a bidirectional clock line

(SCL) and bidirectional data line (SDA). The I2C interface

supports both master and slave mode operation. 100 kHz,

400 kHz and 1 MHz modes are supported.

Asynchronous Clock Counter

The asynchronous clock counter measure the timing of a

clock signal, such as STANDBYCLK or a clock provided on

a GPIO input, relative to the system clock.

CRC

SPI

This block provides an implementation of two standard

cyclic redundancy code (CRC) algorithms (CRC−CCITT

and CRC−32) which, if used, can ensure data integrity of a

user application’s code and data.

The SPI controller consists of 2 independent channels

with the standard 4−wire interface of SCLK, MOSI, MISO

and CS supporting master and slave mode. Each channel

also supports dual (DSPI) and quad (QSPI) modes in half or

full duplex mode.

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12

RSL15

Memory Map

The RSL15 memory map is shown in Figure 5 (512 KB

flash version only).

CPU access

BB access

Unused

Peripherals

32-bit registers

0x4005 3FFF

0x4000 0000

Unused

0x2001 3FFF

BB_DRAM1

8 KB

0x2001 2000

0x2001 1FFF

BB_DRAM0

8 KB

0x2001 0000

0x2000 FFFF

DRAM7

8 KB

0x2000 E000

0x2000 DFFF

DRAM6

8 KB

0x2000 C000

0x2000 BFFF

DRAM5

8 KB

0x2000 A000

0x2000 9FFF

DRAM4

8 KB

0x2000 8000

0x2000 7FFF

DRAM3

8 KB

0x2000 6000

0x2000 5FFF

DRAM2

8 KB

0x2000 4000

0x2000 3FFF

DRAM1

8 KB

0x2000 2000

0x2000 1FFF

DRAM0

8 KB

0x2000 0000

0x1FFF FFFF

Chip ID

0x1FFF FFFC

Unused

0x0017 FFFF

Flash Array1

160 KB

0x0015 8000

0x0015 7FFF

Flash Array2

352 KB

0x0010 0000

0x0008 08FF

Flash MNVR(trimming)

128 B + 128 B (duplicated)

0x0008 0800

0x0008 07FF

Flash NVR[0:7]

8 * 256 B

0x0008 0000

0x0006 11FF

Flash Data redundancy1-2

2 * 256 B

0x0006 1000

0x0006 0FFF

Flash Code redundancy1-2

2 * 2 KB

0x0006 0000

0x0000 7FFF

0x0000 0000

PROM

32 KB

Figure 5. RSL15 Memory Map

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13

RSL15

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol

VBAT

Parameter

Min

Max

3.63

Unit

V

Power supply voltage input

Digital I/O supply voltage input

RF front−end ground

Analog ground

VDDO

V

VSSRF

VSSA

−0.3

V

VSSC

Digital ground

−0.3

V

Vin

Voltage at any input pin

VSSC−0.3

VSSA − 0.3

VDDO + 0.3

VDDA + 0.3

V

Vin to LSAD

Voltage at GPIO selected as LSAD

input

V

RF

Maximum RF Input Power

18

dBm

T storage

Storage temperature range (Note 1)

−40

125

°C

Stresses exceeding those listed in the Absolute Maximum Ratings table may damage the device.

CAUTION: Class 2 ESD Sensitivity, JESD22*A114*B HBM +/−2000 V on all pins

CDM ESD Compliance on all pins: 500 V

Latch−up protection of 100mA, EIA/JESD78E on all pins

1. Storage temperature applies after soldering to PCB.

General Operating Conditions

Table 4. GENERAL OPERATING CONDITIONS

Parameter

Symbol

Conditions

Min

1.4

1.2

Typ

Max

Unit

DC−DC Converter Input

Voltage

VBAT

BUCK Mode

LDO Mode

3.6

V

VBAT supply rise time

Maximum rate of voltage rise

0.1

V/ms

DC−DC Converter / LDO

VCC

VDDA

1

1.2

2.4

1.32

V

Output Voltage (Note 2)

Analog blocks supply

voltage output (Note 2)

VDDA is generated by a charge pump that doubles

the VCC voltage

V

Flash supply voltage

output (Note 2)

VDDFLASH

VDDO

0.75

1.2

1.75

2.3

3.6

1.21

48

Digital I/O Supply Input

(Note 2)

V

RF Supply Output

(Note 2)

VDDRF

SYS_CLK

1.0

1.1

V

System Clock

8

MHz

(Note 3)

Operating Temperature

POR Voltage

−40

85

°C

VBAT

0.4

0.8

1.0

V

POR

If any limits in the General Operating Conditions table are exceeded, device functionality should not be assumed. Exposure beyond maximum

operating conditions for extended periods may affect device reliability.

2. VCC, VDDA, VDDFLASH and VDDRF Outputs are for connections to external filtering capacitors only. These regulated voltages are used

internally and are not intended for powering external devices.

3. Minimum SYS_CLK required for BLE Operation.

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14

RSL15

Power Consumption

mentioned in the table below are valid at 25°C,

VBAT = VDDO (Buck mode for VBAT > 1.4 V, LDO mode

for VBAT ≤ 1.4 V), 48 MHz (RFCLK) active, Radio ON and

internal supplies trimmed to factory defaults.

RF Current Consumption

Table 5 shows key peak current consumption values for

RF activity. Unless otherwise noted, the specifications

Table 5. RF CURRENT CONSUMPTION

Operating Conditions

VBAT

DC Conversion

Min

Typ

Max

Unit

Radio Receive Mode

Rx @ 125 kbps, 2.4 GHz

8 MHz system clock

Cortex−M33 running BLE baseband only

All Peripherals Disabled

64 KB RAM enabled

3.0 V

BUCK Mode

2.9

mA

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

4.4

6

Radio Receive Mode

Rx @ 500 kbps, 2.4 GHz

8 MHz system clock

Cortex−M33 running BLE baseband only

All Peripherals Disabled

64 KB RAM enabled

2.9

4.4

6

mA

Radio Receive Mode

Rx @ 1 Mbps, 2.4 GHz

8 MHz system clock

Cortex−M33 running BLE baseband only

All Peripherals Disabled

64 KB RAM enabled

2.7

4.3

5.8

3.2

4.9

6.7

4.3

6.7

9.1

8

Radio Receive Mode

Rx @ 2 Mbps, 2.4 GHz

8 MHz system clock

Cortex−M33 running BLE baseband only

All Peripherals Disabled

64 KB RAM enabled

Radio Transmit Mode

Tx @ 1 Mbps, 2.4 GHz, 0 dBm

8 MHz system clock

Cortex−M33 running BLE baseband only

All Peripherals Disabled

64 KB RAM enabled

Radio Transmit Mode

Tx @ 1 Mbps, 2.4 GHz, 3 dBm

8 MHz system clock

Cortex−M33 running BLE baseband only

All Peripherals Disabled

64 KB RAM enabled

12.3

16.9

10.6

16.5

22.5

11.4

17.8

24.1

Radio Transmit Mode

Tx @ 1 Mbps, 2.4 GHz, 5 dBm

8 MHz system clock

Cortex−M33 running BLE baseband only

All Peripherals Disabled

64 KB RAM enabled

Radio Transmit Mode

Tx @ 1 Mbps, 2.4 GHz, 6 dBm

8 MHz system clock

Cortex−M33 running BLE baseband only

All Peripherals Disabled

64 KB RAM enabled

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RSL15

Run Mode Current Consumption

mode for VBAT > 1.4 V, LDO mode for VBAT ≤ 1.4 V),

48 MHz (RFCLK) active, Radio OFF and internal supplies

trimmed to factory defaults.

Table 6 shows key current consumption values for Run

Mode. Unless otherwise noted, the specifications mentioned

in the table below are valid at 25°C, VBAT = VDDO (Buck

Table 6. RUN MODE CURRENT CONSUMPTION

DC

Conversion

BUCK Mode

LDO Mode

Operating Conditions

VBAT

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

Min

Typ

49

76

106

39

58

84

34

54

77

30

46

65

33

50

71

26

39

55

20

31

51

21

34

50

Max

Unit

8 MHz system clock

mA/MHz

Executing CoreMark from Flash

All peripherals disabled

64 KB RAM enabled

16 MHz system clock

BUCK Mode

LDO Mode

mA/MHz

Executing CoreMark from Flash

All peripherals disabled

64 KB RAM enabled

24 MHz system clock

BUCK Mode

LDO Mode

Executing CoreMark from Flash

All peripherals disabled

64 KB RAM enabled

48 MHz system clock

BUCK Mode

LDO Mode

Executing CoreMark from Flash

All peripherals disabled

64 KB RAM enabled

8 MHz system clock

BUCK Mode

LDO Mode

Executing CoreMark from RAM

All peripherals disabled

64 KB RAM enabled

16 MHz system clock

BUCK Mode

LDO Mode

Executing CoreMark from RAM

All peripherals disabled

64 KB RAM enabled

24 MHz system clock

BUCK Mode

LDO Mode

Executing CoreMark from RAM

All peripherals disabled

64 KB RAM enabled

48 MHz system clock

BUCK Mode

LDO Mode

Executing CoreMark from RAM

All peripherals disabled

64 KB RAM enabled

Idle Mode Current Consumption

mode for VBAT > 1.4 V, LDO mode for VBAT ≤ 1.4 V), 48

MHz (RFCLK) active, Radio OFF and internal supplies

trimmed to factory defaults.

Table 7 shows key current consumption values for Idle

Mode. Unless otherwise noted, the specifications mentioned

in the table below are valid at 25°C, VBAT = VDDO (Buck

Table 7. IDLE MODE CURRENT CONSUMPTION

Wakeup

Source

Operating Conditions

VBAT

DC Conversion

BUCK Mode

LDO Mode

Min

Typ

128

103

156

Max

Unit

System clock stopped

64 KB RAM enabled

GPIO

3.0 V

mA

1.8 V

1.25 V

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16

RSL15

Standby Mode Current Consumption

VDDO (Buck mode for VBAT > 1.4 V, LDO mode for

VBAT ≤ 1.4 V), 48 MHz (RFCLK) inactive, Radio OFF and

internal power supplies trimmed to factory defaults.

Table 8 shows key current consumption values for

Standby Mode. Unless otherwise noted, the specifications

mentioned in the table below are valid at 25°C, VBAT =

Table 8. STANDBY MODE CURRENT CONSUMPTION

Operating Conditions

Wakeup

Source

VBAT

DC Conversion

Min

Typ

Max

Unit

Clocks stopped

All peripherals disabled

8 KB RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K inactive

GPIO

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

17

20

mA

26

Clocks stopped

17.5

21

mA

All peripherals disabled

16 KB RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K inactive

26

Clocks stopped

17.6

21

All peripherals disabled

32 KB RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K inactive

26

Clocks stopped

18

All peripherals disabled

64 KB RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K inactive

21

26

Clocks stopped

RTC

timer

21

All peripherals disabled

8 KB RAM retained

32 kHz RC32 active

32 kHz XTAL32K inactive

22

29

Clocks stopped

RTC

timer

19

All peripherals disabled

8 KB RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K active

21

28

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RSL15

Sleep Mode Current Consumption

mode for VBAT > 1.4 V, LDO mode for VBAT ≤ 1.4 V),

48 MHz (RFCLK) inactive, Radio OFF and internal

supplies trimmed to factory defaults.

Table 9 shows key current consumption values for Sleep

Mode. Unless otherwise noted, the specifications mentioned

in the table below are valid at 25°C, VBAT = VDDO (Buck

Table 9. SLEEP MODE CURRENT CONSUMPTION

Wakeup

Source

Operating Conditions

Symbol

VBAT

DC Conversion

Min

Typ

Max

Unit

Clocks stopped

All peripherals disabled

No RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K inactive

Ids1

GPIO

3.0 V

BUCK Mode

36

nA

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

3.0 V

1.8 V

1.25 V

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

BUCK Mode

LDO Mode

37

60

System clocks stopped

All peripherals disabled

No RAM retained

32 kHz RC32 active

32 kHz XTAL32K inactive

Ids2

Ids3

Ids4

Ids5

RTC timer

83

nA

98

147

57

System clocks stopped

All peripherals disabled

No RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K active

66

97

System clocks stopped

All peripherals disabled

8 KB RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K active

165

233

253

208

303

473

303

448

701

System clocks stopped

All peripherals disabled

16 KB RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K active

System clocks stopped

All peripherals disabled

32 KB RAM retained

32 kHz RC32 inactive

32 kHz XTAL32K active

Ids6

RTC timer

nA

NOTES: • Buck mode measurements were captured with an additional 10 mF in parallel with VBAT and a 200 W resistor in series in order to

obtain a more accurate measurement with the measurement device.

• Current values include increases due to workarounds imposed by errata in section ‘RSL15 Errata for Chip Identification 2.02.00’.

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RSL15

ULP Data Acquisition Subsystem Performance

below are valid at 25°C, VBAT = VDDO (Buck mode for

VBAT > 1.4 V, LDO mode for VBAT ≤ 1.4 V), 48 MHz

(RFCLK) inactive, Radio OFF and internal supplies

trimmed to factory defaults.

Table 10 shows key current consumption values for ULP

Data Acquisition Subsystem in Smart Sense Mode. Unless

otherwise noted, the specifications mentioned in the table

Table 10. ULP DATA ACQUISITION SUBSYSTEM PERFORMANCE

Operating Condition

Min

Typ

Max

Unit

Continuous ADC operation in Smart Sense mode with wakeup on ADC threshold

206

nA

Configuration/conditions: VBAT = 3 V, BUCK Mode,

Successive Approximation ADC enabled and selected,

XTAL32K, VREF = VBAT reference selected,

ADC Fs = 256 sps, accumulation 4 samples. Processor would wake to Run mode by ADC

threshold but this is not included in this measurement

Continuous ADC operation in Smart Sense mode, wakeup on FIFO full, transfer content to

RAM

Configuration/conditions: VBAT = 3 V, BUCK Mode, 16 KB RAM retained, XTAL32K, Succes-

sive Approximation ADC enabled, VREF = VBAT, ADC Fs = 1 ksps, accumulation 16 sam-

ples, FIFO Size 16. Processor wakes to Run mode every 256 ms to transfer samples to

RAM

2.1

4.1

mA

nA

Continuous ADC operation in Smart Sense mode, wakeup on FIFO full, transfer content to

RAM

Configuration/conditions: VBAT = 3 V, BUCK Mode, 16 KB RAM retained. XTAL32K, Succes-

sive Approximation ADC enabled, VREF = VDDA, ADC Fs = 1 ksps,

Accumulation 16 samples, FIFO Size 16. Processor wakes to Run mode every 256 ms to

transfer samples to RAM

Continuous Pulse Counter accumulation in Smart Sense mode, wakeup when FIFO full,

transfer content to RAM

348

Configuration/conditions: VBAT = 3 V, BUCK Mode, 16 KB RAM retained, XTAL32K, Pulse

Counter enabled, Pulse Count Interval 1000 ms, accumulation of 5 samples, result stored in

FIFO. Processor wakes to Run mode every 5 s to transfer sample to RAM

NOTE: Current values include increases due to workarounds imposed by errata in section ‘RSL15 Errata for Chip Identification 2.02.00’.

Wakeup Timing Specifications

Table 11. WAKEUP TIMING SPECIFICATIONS

Description

Symbol

Conditions

Min

Typ

Max

Unit

Cold startup − VBAT applied to entering

RUN mode

To start of startup code execution

(Energy Harvesting state)

2.4

ms

To start of startup code execution

(Secure state) using secure bootloader

with two key certificates, one content

certificate, debug port locked and

application size of ~55 KB

236

GPIO wakeup from Sleep mode to RUN

mode, RAM execution

To start of wakeup function execution

in RAM (startup code is not executed).

VDDM retained

1.47

(Note 4)

ms

GPIO wakeup from Sleep mode to RUN

mode, flash execution

To start of startup code execution

1.55

ms

(Note 4)

GPIO wakeup from Sleep mode to RUN

mode, continuation from flash

To start of execution from last program

counter address (startup code is not

executed). VDDM retained

1.49

(Note 4)

GPIO wakeup from Standby mode to

RUN mode, continuation from flash

To start of execution from last program

counter address (startup code is not

executed). VDDC retained

125

90

ms

GPIO wakeup from IDLE mode to RUN

mode, continuation from RAM or flash

To start of execution from last program

counter address (startup code is not

executed). VDDC retained

4. Wakeup times may vary due to system capacitance and sleep period.

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RSL15

Table 12. EEMBC BENCHMARK SCORES (All RSL15 benchmark scores have been certified by EEMBC)

Description

EEMBC CoreMark

Symbol

Conditions

Min

Typ

Max

Units

177

CoreMark

Performance

Energy, Fixed Voltage

Energy, Best Voltage

1.8 V

60.5

58.3

63.1

1220

1070

EEMBC ULPMarkt−CoreMark

EEMBC ULPMarkt−CoreProfile

3 V

RF Specifications

Table 13 shows key RF specifications. Unless otherwise

noted, the specifications mentioned in the table below are

valid at 25°C, VBAT = VDDO (Buck mode for

VBAT > 1.4 V, LDO mode for VBAT ≤ 1.4 V).

Table 13. RF SPECIFICATIONS

Description

Symbol

Conditions

Min

Typ

50

Max

Units

GENERAL RADIO SPECIFICATIONS

RF Input Impedance

Input reflection coefficient

Data Rate

Z

in

W

S

11

−8

dB

R

FSK/MSK/GFSK (OQPSK as MSK)

62.5

1000

3000

4000

kbps

FSK

4−FSK

SYNTHESIZER SPECIFICATIONS

Frequency Range

F

RF

2360

2500

100

MHz

Hz

Rx Frequency Step

Receive mode frequency synthesizer

resolution

Tx Frequency Step

Transmit mode frequency synthesizer

resolution

600

Hz

PLL Settling Time

Receive Mode

Transmit Mode

15

5

25

10

ms

PLL Settling Time

RECEIVE MODE SPECIFICATIONS

BLE Sensitivity

LDO mode, VBAT = 1.8 V or

3.0 V

1 Mbps, 0.1% BER

−96

−94

−98

−102

−96

−94

−98

−102

−94

−91

−96

−100

3.5

dBm

dB

2 Mbps, 0.1% BER

500 kbps, 0.1% BER, BLE Long Range

125 kbps, 0.1% BER, BLE Long Range

1 Mbps, 0.1% BER

Buck mode, VBAT = 1.8 V

BLE Sensitivity

Buck mode,

VBAT = 3.0 V (WLCSP)

2 Mbps, 0.1% BER

500 kbps, 0.1% BER, BLE Long Range

125 kbps, 0.1% BER, BLE Long Range

1 Mbps, 0.1% BER

BLE Sensitivity

Buck mode,

VBAT = 3.0 V (QFN)

2 Mbps, 0.1% BER

500 kbps, 0.1% BER, BLE Long Range

125 kbps, 0.1% BER, BLE Long Range

Any phase relative to 50 W

Rx sensitivity degradation

VSWR1:4

RSSI effective range

RSSI step size

Without AGC

60

2.4

48

dB

Rx AGC Range

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RSL15

Table 13. RF SPECIFICATIONS (continued)

Description Symbol

Conditions

Min

Typ

Max

Units

RECEIVE MODE SPECIFICATIONS

Rx AGC Step Size

Programmable

6

0

dB

Max usable input signal level

TRANSMIT MODE SPECIFICATIONS

Transmit power range

0.1% BER

dBm

note 5

BLE, VDDPA is required for ≥ +3 dBm

or in low voltage conditions

−17

+6

dBm

Transmit power step size

Transmit power accuracy

1

dBm

Tx power 0 dBm. Full band. Relative to

the typical value.

−1.5

+1.5

Tx power 3 dBm. Full band. Relative to

the typical value.

dBm

Tx power 6 dBm. Full band. Relative to

the typical value.

nd

Power in 2 harmonic

0 dBm output level

−35

−40

−45

−55

dBm

rd

Power in 3 harmonic

th

Power in 4 harmonic

nd

Power in 2 harmonic with

EVB harmonic filter

rd

Power in 3 harmonic with

0 dBm output level

−60

2.5

dBm

dB

EVB harmonic filter

th

Power in 4 harmonic with

EVB harmonic filter

Tx power degradation

VSWR 1:4

Any phase relative to 50 W, for 0 dBm

output level

5. At +6 dBm Tx power, an antenna gain of +2.2 dBi or less must be used to ensure out−of−band regulatory emissions compliance.

Flash Specifications

Table 14. FLASH SPECIFICATIONS

Description

Symbol

Conditions

Code and Data Array

NVR Array

Min

100

1

Typ

Max

Units

Flash sector endurance

kcycles

Flash content retention period

Sector erase time

T = 55°C

25

years

ms

1

4

Mass write time

10

ms

Oscillator Specifications

Table 15. 32 kHz CRYSTAL OSCILLATOR (XTAL32K)

Parameter

Crystal Frequency

Startup time

Symbol

Conditions

Min

Typ

Max

Unit

kHz

s

XTAL32K

32.768

1

VBAT applied to stabilization

3

Internal load

Internal capacity to match crystal

unit load capacity. Steps of 0.4 pF

0

25.2

pF

External load Capacitance

Internal ESR

Maximum external capacity allowed

(package, routing, etc.)

3.5

pF

100

kW

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RSL15

Table 15. 32 kHz CRYSTAL OSCILLATOR (XTAL32K) (continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Operating current

Using optimal external component

(low CL and ESR)

25

nA

Duty cycle

40

50

60

%

Table 16. SLOW RC OSCILLATOR (RC32)

Parameter

Symbol

Notes

Min

Typ

32.768

Max

Unit

Factory trimmed

frequency

RC32

kHz

Calibrated frequency

tolerance

Conditions:

500

ppm

• temperature constant within 0.5°C

• calibrating at least every 10 seconds

• averaging window > 7.8 ms

• defined as 3 sigma

Startup time

After VBAT applied

2

ms

nA

Current consumption

Temperature comp enabled

120

Table 17. 48 MHz CRYSTAL OSCILLATOR (RFCLK)

Parameter

Crystal Frequency

Startup time

Symbol

Notes

Min

Typ

Max

Unit

MHz

ms

RFCLK

48

After VBAT Applied

Equiv. Series res.

1.5

80

Recommended XTAL

parameter ESR

20

6

W

Recommended XTAL

parameter CL

Differential equivalent load capacitance. The

effective differential capacitance (XTAL and

parasitics) must be <1 pF, the remaining being

capacitance to ground (parasitic completed by

on−chip load capacitance).

8

10

pF

Operating current

Duty cycle

100

mA

40

60

%

NOTE: RFCLK (48 MHz crystal) must be the clock source when writing to Flash.

Table 18. FAST RC OSCILLATOR (RCCLK)

Parameter

Symbol

Notes

Min

Typ

Max

Unit

Fast RC Oscillator

Output Frequency

RCCLK

3 MHz Output

12 MHz Output

24 MHz Output

3

MHz

12

24

Fast RC Oscillator

T = 0 to +45°C, 3 MHz Output

T = −40 to +85°C, 3 MHz Output

T = 0 to +45°C, 12 MHz Output

T = −40 to +85°C, 12 MHz Output

T = 0 to +45°C, 24 MHz Output

T = −40 to +85°C, 24 MHz Output

−1.5

−3.5

−5

1.5

3.5

5

%

temperature coefficient

(Note 6)

%

−15

−10

−25

40

15

10

25

60

Duty cycle

50

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22

RSL15

Table 18. FAST RC OSCILLATOR (RCCLK) (continued)

Parameter

Symbol

Notes

Min

Typ

5

Max

Unit

mA

ms

Current consumption

3 MHz Output

12 MHz Output

24 MHz Output

After VBAT Applied

18

38

Startup time

100

6. For setting of V = 1.2 V

CC

Analog Comparator Specifications (ACOMP)

Table 19. ANALOG COMPARATOR SPECIFICATIONS (ACOMP)

Parameter

Input voltage range

Input offset

Symbol

Conditions

Rail−to−rail input

Min

Typ

Max

Unit

V

0

VBAT

10

Full common mode range

Low power setting

Normal setting

−10

40

mV

Hysteresis

90

110

220

High speed setting

Low power setting

Normal setting

Comparator delay

120

1.5

0.2

10

ms

nA

mA

High speed setting

Low power setting

Normal setting

Current consumption

1.5

18

High speed setting

Current Source (CSRC) Specifications

Table 20. CURRENT SOURCE (CSRC) SPECIFICATIONS

Parameter

Output current

Symbol

Conditions

Min

Typ

10

1

Max

Unit

mA

1

16

Output current step size

Output voltage

mA

VDDA−0.4

V

Output resistance

Quiescent current

Line regulation

VOUT = VOUTmaz, Iout = 10 mA

Iout = 10 mA

5

MW

mA

3

5

10

nA/V

nA

Output current noise

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23

RSL15

Successive Approximation ADC (SAR ADC) Specifications

Table 21. SUCCESSIVE APPROXIMATION ADC (SAR ADC) SPECIFICATIONS

Parameter

Symbol

Conditions

Min

1.8

Typ

Max

3.6

Unit

V

ADC reference voltage

VREF

VBAT selected as reference VREF

GPIO[9] selected as reference VREF

VDDO

V

Resolution

12

Bits

V

Input voltage range

0

VREF

Differential input

voltage range

−VREF

V

Sampling rate

VREF ≥ 2.5 V

2

Msps

mV

VREF 2.0 V to 2.5 V

0.5

VREF 1.8 V to 2.0 V

0.125

LSB weight

Absolute gain error

INL

12 bits resolution at VREF = VBAT = 3.6 V

1.6

−2

−4

+2

4

%

LSB

%

DNL

−1.5

−5

1.5

5

Offset

After calibration

Gain error

After calibration

−1

1

Noise

RMS noise in LSB for a constant input voltage

2

LSBrms

pF

Input capacitance

Array calibration time

Current consumption

1

650

26

cycles

mA /

Msps

Low Speed ADC Converter (LSAD) Specifications

Table 22. LOW SPEED ADC CONVERTER (LSAD) SPECIFICATIONS

Parameter

Symbol

ADC_RES

Conditions

Min

Typ

Max

Unit

bits

V

Resolution

8

0

12

14

2

Input voltage range

ADCRANGE

ADC_INL

INL

−2

+2

mV

kHz

DNL

ADC_DNL

−1

+1

Channel sampling frequency

ADCCH_SF

8 channels are converted sequentially, ADC

running at 50 kHz

0.0195

6.25

Table 23. DAC SPECIFICATIONS

Parameter

Symbol

Vout

Conditions

Min

Typ

Max

Unit

V

Output voltage range

Output voltage step size

Output current

Cannot exceed VDDO

0.1

VDDA – 0.2

Vsteps

Iout

16

mV

mA

Max current results in a typ 50 mV

drop on the pad, VDDO > 2.2V

0

10

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RSL15

Temperature Sensor Specifications

Table 24. TEMPERATURE SENSOR SPECIFICATIONS

Parameter

Accuracy potential

Symbol

Conditions

Min

−2

Typ

Max

2

Unit

°C

Requires calibration by the customer

Uncalibrated

Temperature sensor output voltage

@ 25°C

0.9

0.95

21.3

100

1

V

Temperature sensor gain @ 25°C

LSB/

°C

Startup time

From enable to specified accuracy

200

10

ms

Active current consumption

mA

Pulse Counter Specifications

Table 25. PULSE COUNTER SPECIFICATIONS

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

ms

Pulse width

Pulse count duration

Using accumulation to reach max

0.976

16000

ms

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RSL15

GPIO Interface Specifications

Table 26. GPIO INTERFACE SPECIFICATIONS

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Voltage level for HIGH Input

VIH

0.75 x

VDDO

+0.3

V

Voltage level for LOW Input

Voltage level for HIGH Output

Voltage level for LOW Output

VIL

−0.3

0.25 x

V

7

VDDO

VOH

VDDO −

0.4

VOL

0.4

2

V

Voltage at GPIO selected as

LSAD input

Vlsad

VSSA −

0.3

Drive Strength (Note 8)

IOH

VDDO = 3.3 V

Drive = 0

11.8

23.7

47.4

71.1

3.2

mA

kW

Drive = 1

Drive = 2

Drive = 3

Drive = 0

Drive = 1

Drive = 2

Drive = 3

Drive = 0

Drive = 1

Drive = 2

Drive = 3

Drive = 0

Drive = 1

Drive = 2

Drive = 3

VDDO = 1.8 V

VDDO = 3.3 V

VDDO = 1.8 V

6.4

12.9

19.3

7.6

IOL

15.3

30.5

45.8

2.9

5.9

11.7

17.6

250

10

Weak Pull−up Resistor

Strong Pull−up Resistor

Pull−down Resistor

kW

250

kW

7. For VDDO < 1.8 V, VIL Max is 0.23 x VDDO.

8. Maximum accumulated current from all GPIO should not exceed 200 mA.

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26

RSL15

RSL15 ERRATA FOR CHIP IDENTIFICATION 2.02.00

Possible POR Waking from Sleep or Deep Sleep

The chip identification can be derived by reading the Chip

Version, Chip Major Revision and Chip Minor Revision bit

fields.

The RSL15 Firmware Package version 1.5 contains

implementations of the following errata workarounds.

Table 9 and Table 10 in datasheet Rev. 4 include current

increases due to workarounds imposed by these errata.

When RSL15 wakes from sleep or deep sleep mode a POR

due to brownout detection may occur. Deep sleep mode is

when GPIO is used as the sole wakeup source with no clocks

running.

Workaround:

Since a POR might occur when waking from sleep or deep

sleep mode, we recommend that the software initiate a POR

after waking from sleep or deep sleep mode, and handle each

wakeup event as a POR.

Some Registers Might Not Initialize Properly When

Waking from Deep Sleep

When RSL15 wakes from deep sleep mode, some

registers in the ACS might not be initialized properly. This

might cause GPIO4 and GPIO7 to toggle between driving

high and low, this may cause a high current scenario. Deep

sleep mode is when GPIO is used as the sole wakeup source

with no clocks running.

If the charge pump is enabled (which requires the 32kHz

standby clock enabled) during sleep mode, the POR reset

due to brownout detection will not occur and thus the

software initiated a POR after waking from sleep mode is not

required. Using sleep mode instead of deep sleep mode,

enabling the charge pump and 32 kHz standby clock

increases sleep mode current consumption by typical 80 nA

at 3 V buck, or typical 15 nA if 32 kHz standby clock was

already enabled. Note the charge pump cannot be enabled

during deep sleep mode so sleep mode must be used for this

workaround.

Workaround:

To ensure the ACS registers are initialized properly, either

use sleep mode instead of deep sleep mode, or software must

initiate POR after waking from deep sleep.

To prevent possible toggling and a possible high current

scenario, either use sleep mode instead of deep sleep mode,

or configure GPIO4 and GPIO7 as high impedance with pull

up or down before entering deep sleep mode and do not drive

them from external sources during the wakeup period. If

deep sleep mode is not used, GPIO4 and GPIO7 do not

exhibit this behaviour and have no restrictions on their use.

Baseband Timer Requires Sensor Power Enabled

The Baseband timer cannot wakeup the device if sensor

power is disabled.

Workaround:

Sensor power must be enabled for the Baseband timer to

wakeup the device.

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RSL15

TYPICAL CONNECTION DIAGRAMS

It is recommend to have external access to a UART for

the final product as temporary provisions can be made to

repurpose the GPIO during certification, as long there is no

impact to RF performance.

general diagnostics and for wired communication during

Bluetooth certification. It is also recommend to have a

method to load new firmware during Bluetooth certification.

Firmware can be loaded by any method such as the Serial

Wire Debug (SWD) with pins SWDIO, SWCLK, VDDO

(IO voltage domain) and a ground connection. Two GPIO

must be externally accessible for the UART. The UART

GPIO do not need to be permanently dedicated to UART in

BUCK Mode Operation

Figure 6 shows RSL15 external components and

connections for BUCK Mode operation with GPIO Levels

at GND and VBAT.

VBAT

C4

0402

2.2 μF

L1

0603

2.2 μH

C1

0402

4.7 μF

C5

0402

2.2 μF

C7

0402

1 μF

C3

0201

1 μF

C2

0201

100 pF

VSSD

VSSA

VSSD

C6

0402

1 μF

VSSD

ANT

L3

0201

1.8 nH

L2

0201

3 nH

VDDFLASH

RF

C8

04002

2.2 μF

C10

0201

1.5 pF

C9

0201

1.5 pF

XTAL32K_IN

VSSD

XTAL2

XTAL48M_IN

RSL15

XTAL32K_OUT

NRESET

XTAL1

XTAL48M_OUT

GPIO

SWDIO

SWCLK

GPIO_X

UART recommended for diagnostics

and Bluetooth certification

Figure 6. RSL15 BUCK Mode Connection Diagram, VDDO = VBAT

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RSL15

LDO Mode Operation

Figure 7 shows RSL15 external components and

connections for LDO Mode operation with GPIO Levels at

GND and VBAT.

VBAT

C4

0402

2.2 μF

C1

0402

4.7 μF

C5

0402

2.2 μF

C7

0402

1 μF

C3

0201

1 μF

C2

0201

100 pF

X

VSSD

VSSA

VSSD

C6

0402

1 μF

VSSD

ANT

L3

0201

1.8 nH

L2

0201

3 nH

VDDFLASH

RF

C8

04002

2.2 μF

C10

0201

1.5 pF

C9

0201

1.5 pF

XTAL32K_IN

VSSD

XTAL2

XTAL48M_IN

RSL15

XTAL32K_OUT

NRESET

XTAL1

XTAL48M_OUT

GPIO

SWDIO

SWCLK

GPIO_X

UART recommended for diagnostics

and Bluetooth certification

Figure 7. RSL15 LDO Mode Connection Diagram, VDDO = VBAT

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29

RSL15

External Component Overview

Table 27. RECOMMENDED EXTERNAL COMPONENTS

Nominal

Tolerance

Components

Function

Recommended Typical Value

4.7 mF // 100 pF (Note 9)

1 mF

20%

C1, C2

C3

VBAT decoupling

VDDO decoupling

VCC decoupling

C4

2.2 mF

− GRM155C80J225KE95D, Murata

− AMK105BJ225, Taiyo Yuden

20%

C5

C6

C7

C8

VDDRF decoupling

2.2 mF

1 mF

Pump capacitor for the charge pump

VDDA decoupling

1 mF

VDDFLASH decoupling

2.2 mF

20%

L1

DC−DC converter inductance

2.2 mH (See Table 28 below)

XTAL1

XTAL for 48 MHz oscillator

− 416F48022IKR, CTS Frequency Controls

− 8Q−48.000MEEV−T, TXC Corporation, Taiwan

XTAL2

XTAL for 32 kHz oscillator

External harmonic filter

− 9HT12−32.768KDZF−T, TXC Corporation

− MC–306, Epson

− CM8V−T1A, Micro Crystal Switzerland

C9, C10, L2, L3

C9 1.5 pF / C10 1.5 pF 0.25 pF, C0G/NP0, Murata

GRM0335C

L2 3 nH / L3 1.8 nH 0.1 nH, Murata LQP03TN

(Note 10)

NOTE: Capacitors C1 to C8 recommendations:

Multilayer ceramic caps with nominal voltage 6.3 V (to reduce capacitance drop due to DC biasing effect), ESR < 0.2 W over

frequency range 100k – 10MHz, Type X5R with max 15% variation over temperature range so 35% total capacitance tolerance.

9. The recommended decoupling capacitance uses 2 capacitors with the values specified.

10.For improved harmonic performance in environments where RSL15 is operating in close proximity to smartphones or base stations, FBAR

filters such as the Broadcom ACPF−7924 can be applied instead of the suggested discrete harmonic filter.

Table 28. RECOMMENDED DC−DC CONVERTER INDUCTANCE TABLE

Manufacturer

Part Number

Case Size

Comments

Murata

LQM18PN2R2MGHD

0603 SMD with

max

Default inductor used on evaluation board.

T

= 1.0 mm

Murata

LQM21PZ2R2MC0

0805 SMD with Recommended inductor for Vbat > 3.0V to minimize RX sensitivity degradation

= 0.55 mm

in Buck mode versus LDO mode operation. A low−profile, AEC−Q200 option.

T

max

NOTE: Recommended inductor ESR is 0.2 W Typ, 0.5 W Max and saturation current 200 mA Min.

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30

RSL15

PIN DEFINITIONS

QFN40 Pin Out

40

31

XTAL32K_IN

1

30

VSSRF

XTAL32K_OUT

NRESET

VPP

VDDRF

XTAL48M_OUT

VSUB

VSSD

XTAL48M_IN

SHLD

RSL15

RES

QFN 40

GPIO[0]

GPIO[1]

GPIO[9]

GPIO[10]

SWCLK

SWDIO

VDDO

10

GPIO[14]

21

11

20

Figure 8. QFN40 Pin Out

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RSL15

PIN DEFINITIONS

WLCSP40 Pin Out

RF

VSSA

VBAT

VDDA

VSSPA

VSSRF

G6

G1

G2

G3

G4

G7

VDC

VCC

VDDFLASH

F2

F3

F4

VDDRF

XTAL32K_OUT XTAL32K_IN

CAP0

CAP1

E7

E1

E2

E3

E4

XTAL48M_OUT

NRESET

VPP

VSSD

RES

D7

D1

D2

D3

D4

XTAL48M_IN

GPIO[0] GPIO[9]

GPIO[5] GPIO[13] GPIO[15] VSUB

C7

C1

C2

C3

C4

C5

C6

GPIO[1] GPIO[3]

GPIO[4] GPIO[12] GPIO[7] SWDIO

SWCLK

B1

B2

B3

B4

B5

B6

B7

GPIO[10] GPIO[2] GPIO[11] GPIO[6] GPIO[8] GPIO[14] VDDO

A1

A2

A3

A4

A5

A6

A7

Figure 9. WLCSP40 Pin Out

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RSL15

Pin Definition and Multiplexing

Legend:

RSL15 has very flexible pad multiplexing capabilities.

Most functions are available on any GPIO. Table 29: Pin

Definition lists all pins and their functionality while

Table 30: GPIO Multiplexing shows all multiplexed

functions available on the GPIO.

I = input; O = output; P = power;

Pull: PU = pull up; PD = pull down;

Table 29. PIN DEFINITION AND MULTIPLEXING

Pad Name

Description

Power Domain

Type

Pull

Pad #,

QFN

Ball #,

WLCSP

XTAL32K_IN

XTAL32K_OUT

NRESET

VPP

Input pin for 32 kHz XTAL

VBAT

VDDO

1

2

3

4

5

6

7

E2

E1

D1

D2

D3

D4

C1

Output pin for 32 kHz XTAL

Reset pin

I

PU

Flash high voltage access, do not connect (NC)

Core logic ground

P

VSSD

RES

RESERVED, do not connect

GPIO[0]

General Purpose I/O, see Table 30: GPIO Multi-

plexing

VDDO

I/O

P

PU/PD

GPIO[1]

GPIO[9]

GPIO[10]

GPIO[2]

GPIO[3]

GPIO[4]

GPIO[11]

GPIO[5]

GPIO[12]

GPIO[6]

GPIO[13]

GPIO[7]

GPIO[8]

GPIO[14]

GPIO[15]

General Purpose I/O, see Table 30: GPIO Multi-

plexing

8

B1

C2

A1

A2

B2

B3

A3

C3

B4

A4

C4

B5

A5

A6

C5

General Purpose I/O, see Table 30: GPIO Multi-

plexing

9

General Purpose I/O, see Table 30: GPIO Multi-

plexing

10

11

12

13

14

15

16

17

18

19

20

21

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO Multi-

plexing

General Purpose I/O, see Table 30: GPIO

Multiplexing

not

available

VDDO

Digital I/O voltage supply

VDDO

22

23

A7

B6

SWDIO

For Serial Wire Debug (SWD) or JTMS for

JTAG−DP

PU

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33

RSL15

Table 29. PIN DEFINITION AND MULTIPLEXING

Pad Name

Description

Power Domain

Type

Pull

Pad #,

QFN

Ball #,

WLCSP

SWCLK

For Serial Wire Debug (SWD) or JTCK for

JTAG−DP

VDDO

PU

24

B7

SHLD

Connect to ground

25

26

27

28

29

30

31

32

33

34

35

36

N/A

C7

C6

D7

E7

G7

G6

G4

F4

XTAL48M_IN

VSUB

Input pin for 48 MHz XTAL

Substrate ground (RF)

Output pin for 48 MHz XTAL

LDO for RF

P

XTAL48M_OUT

VDDRF

VSSRF

RF

P

RF analog ground

RF signal input/output (Antenna)

Ground for RF PA LDO

LDO for Flash

I/O

P

VSSPA

VDDA

VDDFLASH

CAP1

P

Charge pump capacitor

E4

E3

G3

CAP0

VDDA

Charge pump output for analog and flash sup-

plies

P

VCC

VDC

VBAT

VSSA

EP

VCC regulator decoupling

DC−DC output voltage to external LC filter

Battery input voltage

VBAT

P

37

38

39

40

F3

F2

G2

G1

N/A

Analog ground

Exposed pad, connect to ground

Table 30. GPIO MULTIPLEXING

GPIO

Mode

RTC_CLK_OUTPUT (Note 12)

RTC_CLK_INPUT

Description

0

RTC clock output

0:3

Input for external RTC clock source

Wakeup source from low power modes

Interrupt source

WAKEUP_SOURCE

INTERRUPT_SOURCE

PULSE_COUNTER_INPUT

JTAG_TDO JTAG

Pulse Counter Input

Test Data Out

2

3

JTAG_TDI JTAG

Test Data In

4

JTAG_TRST JTAG

Test Reset

4

ACS−PWM (Note 11)

SDAC_OUTPUT

Always On PWM in the Analog Control Subsystem (ACS)

SDAC output

7

9

SAR_ADC SUPPLY & REFERNCE

SAR ADC voltage supply and reference (VREF)

0:15

SAR_ADC_INPUT

LSAD_INPUT

SAR_ADC_INPUT

LSAD_INPUT

CURRENT_SOURCE_OUTPUT

ACOMP_INPUT

AOUT

CURRENT_SOURCE_OUTPUT

ACOMP_INPUT

AOUT

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RSL15

Table 30. GPIO MULTIPLEXING

GPIO

0:15

Mode

Description

SLOWCLK (output)

Clocking

SYSCLK (output)

USRCLK (output)

RCCLK (output)

SWCLK (output)

EXTCLK (output)

STANDBYCLK (output)

SENSORCLK (output)

0:15

UART0_RX

Interfaces

UART0_TX / LIN0_TX

LIN_RX

SPI0_MOSI/DATA0

SPI0_MISO/DATA1

SPI0_DATA2

SPI0_DATA3

SPI0_CS

SPI0_CLK

SPI1_MOSI/DATA0

SPI1_MISO/DATA1

SPI1_DATA2

SPI1_DATA3

SPI1_CS

SPI1_CLK

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C2_SDA

PWM0

PWM1

PWM2

PWM3

PWM4

PWM0_INV

PWM1_INV

PWM2_INV

PWM3_INV

PWM4_INV

PCM_SERI

PCM_SER0

PCM_FRAME

PCM_CLK

11. ACS−PWM has an equivalent 500 Ohm series resistor at the output.

12.RTC_CLK_OUTPUT output level is at VCC in Sleep Mode.

PCB LAYOUT GUIDELINES

3. Analog input signals should be shielded as well as

1. Decoupling capacitors should be placed as close to

the related balls as possible

2. Differential output signals should be routed as

symmetrically as possible

possible

4. Pay close attention to the parasitic coupling

capacitors

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35

RSL15

5. Special care should be made for PCB design in

order to obtain good RF performance

PACKAGE MARKING INFORMATION

Chip Identification

6. Multi−layer PCB should be used with a keep−out

area on the inner layers directly below the antenna

matching circuitry in order to reduce the stray

capacitances that influence RF performance

7. All the supply voltages should be decoupled as

close as possible to their respective pin with high

performance RF capacitors. These supplies should

be routed separately from each other and if

possible on different layers with short lines on the

PCB from the chip’s pin to the supply source

8. Digital signals should not be routed close to the

crystal or the power supply lines

9. Proper DC−DC component placement and layout

is critical to RX sensitivity performance in

DC−DC mode. Minimize parasitic capacitance and

inductance on the VDC node as much as possible.

10. [QFN only]: Ground EP by vias to a ground plane

and/or through at least two VSS pins to PCB

surface ground.

11. [QFN only]: Connect SHLD pin to EP, and

connect SHLD to an external ground trace

shielding XTAL48M_IN from SWCLK.

12. [WLCSP only] On−chip RF inductor coils need a

keep−out area on the top layer metal (refer to the

keep−out zone in the WLCSP40 PACKAGE

DIMENSIONS drawing)

13. [WLCSP only] Ground plain should be removed

under XTAL +/− signal pins and lines to ensure

parasitic capacitance is less than 1 pF

System identification is used to identify different system

components. For the RSL15 chip, the key identifier

components and values are as follows:

Chip Family: 0x0B

Chip Version: 0x02

Chip Major Revision: 0x02

ELECTROSTATIC DISCHARGE (ESD) SENSITIVE

DEVICE

CAUTION:ESD sensitive device. Permanent damage may

occur on devices subjected to high−energy

electrostatic discharges.

Proper

ESD

precautions in handling, packaging and testing

are recommended to avoid performance

degradation or loss of functionality.

SOLDER INFORMATION

The RSL15 QFN package is constructed with all RoHS

compliant material and should be reflowed accordingly.

This device is Moisture Sensitive Class MSL3 and must

be stored and handled accordingly. Re−flow according to

IPC/JEDEC standard J−STD−020C, Joint Industry

Standard: Re−flow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices. Hand

soldering is not recommended for this part.

For more information, see SOLDERRM/D available from

http://onsemi.com.

EXPORT CONTROL CLASSIFICATION NUMBER

(ECCN)

The ECCN designation for RSL15 is 5a991.g .

Arm, Cortex and TrustZone are registered trademarks and CryptoCell is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Bluetooth and the Bluetooth logo are registered trademarks of Bluetooth SIG.

ULPMark is a trademark of EEMBC in the US and/or elsewhere.

www.onsemi.com

36

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFN40 5x5, 0.4P

CASE 485CR

ISSUE C

DATE 27 AUG 2013

1

40

SCALE 2:1

NOTES:

L2

A

B

D

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30mm FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PIN ONE

LOCATION

L2

DETAIL A

E

MILLIMETERS

DIM MIN

MAX

1.00

0.05

L

A

A1

A3

b

0.80

−−−

0.15

C

0.20 REF

L1

0.15

0.25

0.15

C

D

D2

E

E2

e

L

5.00 BSC

TOP VIEW

3.40

3.60

DETAIL A

5.00 BSC

ALTERNATE TERMINAL

CONSTRUCTIONS

3.40

3.60

DETAIL B

(A3)

0.40 BSC

0.10

0.08

C

0.30

−−−

0.50

0.15

A

L1

L2

EXPOSED Cu

MOLD CMPD

0.12 REF

A1

SEATING

PLANE

NOTE 4

C

SIDE VIEW

GENERIC

MARKING DIAGRAM*

DETAIL B

ALTERNATE

M

0.10

C

A

B

1

CONSTRUCTION

D2

DETAIL A

XXXXXXXX

AWLYYWWG

G

11

M

0.10

C A B

21

E2

XXXXX = Specific Device Code

1

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

40

WL

YY

WW

G

40X b

40X

L

e

M

0.10

C

A B

e/2

BOTTOM VIEW

0.05

NOTE 3

(Note: Microdot may be in either location)

RECOMMENDED

SOLDERING FOOTPRINT

*This information is generic. Please refer

to device data sheet for actual part

marking.

5.30

40X

0.63

Pb−Free indicator, “G” or microdot “ G”,

3.64

may or may not be present.

1

5.30

3.64

PKG

OUTLINE

40X

0.25

0.40

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON83971E

QFN40, 5x5, 0.4P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP40 2.301x2.499x0.369

CASE 567HU

ISSUE O

DATE 29 APR 2022

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON44926H

WLCSP40 2.301x2.499x0.369

PAGE 1 OF 1

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

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under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

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ADDITIONAL INFORMATION

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


型号：	NCH-RSL15-284-101Q40-ACG
厂家：	ONSEMI
描述：	Bluetooth® 5.2安全无线MCU 无线
文件：	总39页 (文件大小：446K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCH-RSL15-284-101Q40-ACG [ONSEMI]

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