NCL30002DR2G_技术文档

NCL30002

Power Factor Corrected

Buck LED Driver

The NCL30002 is a switch mode power supply controller intended

for low to medium power single stage power factor (PF) corrected

LED Drivers. The device operates as a critical conduction mode

(CrM) buck controller to regulate LED current at a high power factor

for a specific line voltage range. The current limit threshold is tightly

trimmed allowing open loop control techniques to reduce parts count

while maintaining accurate current regulation and high power factor.

CrM operation is particularly suited for LED applications as very high

efficiency can be achieved even at low power levels. These are

important in LED lighting to comply with regulatory requirements and

meet overall system luminous efficacy requirements. In CrM, the

switching frequency will vary with line and load. Switching losses are

low as recovery losses in the output rectifier are negligible since the

current goes to zero prior to reactivating the main MOSFET switch.

The device features a programmable on time limiter, zero current

detect sense block, gate driver, trans−conductance error amplifier as

well as all PWM control circuitry and protection functions required to

implement a CrM switch mode power supply. Moreover, for high

efficiency, the device features low startup current enabling fast, low

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MARKING

DIAGRAM

8

1

L0002

ALYW

G

SOIC−8

D SUFFIX

CASE 751

1

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

PIN CONNECTION

MFP

Comp

Ct

V

CC

DRV

GND

ZCD

loss charging of the V

capacitor. The current sense protection

CC

threshold has been set at 485 mV to minimize power dissipation in the

external sense resistor. To support the environmental operation range

of Solid State Lighting, the device is specified across a wide junction

temperature range of −40°C to 125°C.

CS

(Top View)

ORDERING INFORMATION

†

Device

NCL30002DR2G

Package

Shipping

Features

• Very Low 24 mA Typical Startup Current

• Cycle−by−Cycle Current Protection

SOIC−8 2500 / Tape & Reel

(Pb−Free)

• Tightly Trimmed Low Current Sense Threshold of 485 mV 2%

• Low 2 mA Typical Operating Current

• Source 500 mA / Sink 800 mA Totem Pole Gate Driver

• Wide Operating Temperature Range

• Enable Function and Overvoltage Protection

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

Typical Applications

• LED Driver Power Supplies

• LED Based Bulbs

• Commercial and Residential LED Fixtures

1

Publication Order Number:

March, 2012 − Rev. 0

NCL30002/D

NCL30002

OVP

+

−

+

V

OVP

UVP

−

+

V

UVP

(Enable EA)

E/A

−

MFP

+

g

m

+

R

MFP

V

REF

V

CC

V

CC

Fault

Management

V

Control

COMP

V

EAH

Clamp

mV

DD

V

DD

Power Good

V

DD

PWM

270 mA*

−

+

Add Ct

Offset

C

t

S

R

Q

DRV

OCP

CS

LEB

195 ns*

+

−

V

CC

+

V

ILIM

Demag

+

DRV

S

Q

S

Q

−

+

R

V

ZCD

ZCD(ARM)

R

+

Reset

mV

DD

−

+

180 ms*

Off Timer

S

R

Q

V

ZCD(TRIG)

GND

ZCD

Clamp

* Typical Values Shown

All SR Latches are Reset Dominant

Figure 1. Block Diagram

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2

NCL30002

Table 1. PIN FUNCTION DESCRIPTION

Name

Function

1

MFP

The multi−function pin is connected to the internal error amplifier. By pulling this pin below the V

controller is disabled. In addition, this pin also has an over voltage comparator which will disable the controller in the

event of a fault.

threshold, the

uvp

2

3

COMP

The COMP pin is the output of the internal error amplifier. A compensation network connected between this pin and

ground sets the loop bandwidth.

C

The C pin sources a regulated current to charge an external timing capacitor. The PWM circuit controls the power

t

switch on time by comparing the C voltage to an internal voltage derived from V

. The C pin discharges the

t

Control

T

external timing capacitor at the end of the on time cycle.

4

5

CS

The CS input threshold is precisely trimmed to accurately sense the instantaneous switch current in the external

MOSFET. This signal is conditioned by an internal leading edge blanking circuit. The current limit threshold is tightly

trimmed for precise peak current control.

ZCD

The voltage of an auxiliary zero current detection winding is sensed at this pin. When the ZCD control block circuit

detects that the winding current has gone to zero, a control signal is sent to the gate drive block to turn on the

external MOSFET.

6

7

GND

DRV

This is the analog ground for the device. All bypassing components should be connected to the GND pin with a short

trace length.

The high current capability of the totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate

charge power MOSFETs. The driver stage provides both passive and active pull down circuits that force the output to

a voltage less than the turn−on threshold voltage of the power MOSFET when V

is not reached.

CC(on)

8

V

CC

This pin is the positive supply of the controller. The circuit starts to operate when V exceeds V

, nominally

CC

CC(on)

12 V and turns off when V goes below V

, typically 9.5 V. After startup, the operating range is 10.2 V up to

CC

CC(off)

20 V.

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3

NCL30002

Output Filter Cap

EMI Filter/ Rectifier / Surge Suppression Start−up Resistors

HVDC Filter Caps

C4

AC1

AC2

F1

Lemi1

L4

LED +

AC1

+

C6

RV1

MOV

Dovp

Rstart

Dbuck

Cout

Lout

−

AC2

D4

OVP Zener

LED −

Lemi2

Dvcc

R15

Rtop

Cvcc

U1

MFP Vcc

Comp DRV

Rin

Qbuck

Vcc Bootstrap

1

2

3

4

8

7

6

5

Rfb

CT

CS

GND

ZCD

Rgdrv

Rzcd

NCL30002

ZCD

Ct

Cfilter

Current Sense

R8

Ccomp

Rbottom

R2 (Optional)

Rsense

Feed Forward Compensation

On Time Capacitor

Figure 2. Simplified PFC Buck Application

Overview

Figure 2 illustrates the basic NCL30002 architecture for

a non-isolated low power high power factor LED driver. One

of the notable features of this architecture is the open loop

control. Notice that there is no direct measurement of the

LED current. Tight peak current control coupled with line

feed-forward compensation to vary the on-time allows for

accurate LED drive current. Fortunately in the vast majority

of LED bulb and luminaire applications, the LED forward

voltage range is well bounded and the line voltage may be

limited to one operating range. This is a huge advantage

which makes the simplicity of open loop control possible.

Buck switching on the low side eliminates a floating gate

drive but references the LED to the HV rail. Buck converters

only produce output when the input voltage exceeds the load

voltage. Consequently, the input current goes to zero near

the zero crossing of the line. The exact phase angle of this

event depends on the LED string voltage and the line

voltage. Unlike the boost PFC, the buck PFC has increased

distortion near the zero crossing. However even with cross

over distortion, high power factor and acceptable harmonics

can be achieved.

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4

NCL30002

Table 2. MAXIMUM RATINGS

Rating

Symbol

Value

−0.3 to 10

10

Unit

V

MFP Voltage

MFP Current

COMP Voltage

COMP Current

Ct Voltage

V

MFP

I

mA

V

−0.3 to 6.5

−2 to 10

−0.3 to 6

10

Control

I

mA

V

Ct

Ct Current

I

Ct

mA

V

CS Voltage

V

−0.3 to 6

10

CS

CS Current

I

mA

V

ZCD Voltage

ZCD Current

DRV Voltage

DRV Sink Current

DRV Source Current

Supply Voltage

Supply Current

V

−0.3 to 10

10

ZCD

I

mA

V

−0.3 to V

800

DRV

DRV(sink)

CC

I

mA

V

I

500

DRV(source)

V

−0.3 to 20

20

CC

I

mA

mW

°C/W

2

Power Dissipation (TA = 70°C, 2.0 Oz Cu, 55 mm Printed Circuit Copper Clad)

P

D

450

Thermal Resistance Junction−to−Ambient

(2.0 Oz Cu, 55 mm Printed Circuit Copper Clad)

Junction−to−Air, Low conductivity PCB (Note 3)

Junction−to−Air, High conductivity PCB (Note 4)

2

R

178

168

127

q

JA

q

Operating Junction Temperature Range

Maximum Junction Temperature

Storage Temperature Range

T

−40 to 125

150

°C

J

T

J(MAX)

T

−65 to 150

300

STG

Lead Temperature (Soldering, 10 s)

T

L

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Pins 1– 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.

Pins 1– 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A.

2. This device contains Latch−Up protection and exceeds ± ±100 mA per JEDEC Standard JESD78.

2

3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm of 2 oz copper traces and heat spreading area. As specified

for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.

2

4. As mounted on a 40 x 40 x 1.5 mm FR4 substrate with a single layer of 650 mm of 2 oz copper traces and heat spreading area. As specified

for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.

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5

NCL30002

Table 3. ELECTRICAL CHARACTERISTICS

V

= 2.4 V, V

= 4 V, Ct = 1 nF, V = 0 V, V

= 0 V, C

= 1 nF, V = 12 V, unless otherwise specified

MFP

Control

CS

ZCD

J

DRV CC

(For typical values, T = 25°C. For min/max values, T = −40°C to 125°C, unless otherwise specified)

J

Characteristic

Test Conditions

Symbol

Min

Typ

Max

Unit

STARTUP AND SUPPLY CIRCUITS

Startup Voltage Threshold

V

Increasing

Decreasing

V

11

8.8

2.2

−

12

9.5

2.5

24

12.5

10.2

2.8

V

CC

CC(on)

Minimum Operating Voltage

Supply Voltage Hysteresis

V

CC

CC(off)

H

V

UVLO

cc(startup)

Startup Current Consumption

0 V < V < V

− 200 mV

I

35

mA

CC

CC(on)

No Load Switching

Current Consumption

C

= open, 70 kHz Switching,

I

−

1.4

1.7

DRV

cc1

V

= 2 V

CS

Switching Current Consumption

70 kHz Switching, V = 2 V

I

−

2.1

2.6

mA

CS

cc2

Fault Condition Current Consumption

No Switching, V

= 0 V

I

0.75

0.95

MFP

cc(fault)

OVERVOLTAGE AND UNDERVOLTAGE PROTECTION

Overvoltage Detect Threshold

Overvoltage Hysteresis

V

= Increasing

V

2.5

20

−

2.67

60

2.85

100

800

V

MFP

OVP

V

mV

ns

OVP(HYS)

Overvoltage Detect Threshold

Propagation Delay

V

= 1 V to 3 V step,

t

500

MFP

OVP

V

= V

to V

= 10%

MFP

OVP

DRV

Undervoltage Detect Threshold

V

MFP

= Decreasing

V

0.25

80

0.31

200

0.4

V

UVP

Undervoltage Detect Threshold

Propagation Delay

V

= 2 V to 0 V step,

t

320

ns

MFP

UVP

= V

to V

= 10%

MFP

UVP

DRV

ERROR AMPLIFIER

Voltage Reference

T = 25°C

T = −40°C to 125°C

V

REF

2.397

2.359

2.510

2.623

2.661

V

J

Voltage Reference Line Regulation

Error Amplifier Current Capability

V

+ 200 mV < V < 20 V

V

−10

−

10

mV

CC(on)

CC

REF(line)

V

= V

+ 0.11 V

I

6

10

20

30

mA

MFP

REF

EA(sink)

V

MFP

= 1.08*V

I

EA(sink)OVP

REF

V

MFP

= 0.5 V

I

−110

−210

−250

EA(source)

Transconductance

V

MFP

= V

100 mV

gm

mS

REF

T = 25°C

T = −40°C to 125°C

90

70

110

120

135

J

Feedback Pin Internal Pull−Down

Resistor

V

MFP

= V

to V

R

2

4.6

10

MW

UVP

REF

MFP

Feedback Bias Current

Control Bias Current

V

= 2.5 V

I

0.25

−1

5

0.54

−

1.25

1

mA

V

MFP

V

= 0 V

I

Control

MFP

Maximum Control Voltage

I

= 10 mA,

= V

V

5.5

6

Control(pullup)

EAH

V

MFP

REF

Minimum Control Voltage to Generate

Drive Pulses

V

= Decreasing until

Ct

0.37

4.5

0.65

4.9

0.88

5.3

V

Control

DRV

(offset)

V

is low, V = 0 V

Ct

Control Voltage Range

V

– Ct

V

EA(DIFF)

EAH

(offset)

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6

NCL30002

Table 3. ELECTRICAL CHARACTERISTICS (Continued)

= 2.4 V, V = 4 V, Ct = 1 nF, V = 0 V, V = 0 V, C

V

= 1 nF, V = 12 V, unless otherwise specified

CC

MFP

Control

CS

ZCD

DRV

(For typical values, T = 25°C. For min/max values, T = −40°C to 125°C, unless otherwise specified)

J

Characteristic

Test Conditions

Symbol

Min

Typ

Max

Unit

RAMP CONTROL

Ct Peak Voltage

V

= open

V

4.535

240

4.93

270

5.25

292

V

COMP

Ct(MAX)

On Time Capacitor Charge Current

I

mA

COMP

= 0 V to V

charge

V

Ct

Ct(MAX)

Ct Capacitor Discharge Duration

PWM Propagation Delay

V

= open

t

−

50

150

220

ns

COMP

Ct(discharge)

V

Ct

= V

−100 mV to 500 mV

Ct(MAX)

dV/dt = 30 V/ms

= V

to V

t

130

PWM

V

Ct

− Ct

Control (offset)

= 10%

DRV

ZERO CURRENT DETECTION

ZCD Arming Threshold

ZCD Triggering Threshold

ZCD Hysteresis

V

= Increasing

V

1.25

0.6

500

− 2

9.8

−0.9

−

1.4

0.7

700

−

1.55

0.83

900

+ 2

V

ZCD

ZCD(ARM)

V

ZCD(TRIG)

V

ZCD

= Decreasing

V

mV

mA

V

ZCD(HYS)

ZCD Bias Current

V

= 5 V

I

ZCD

Positive Clamp Voltage

Negative Clamp Voltage

ZCD Propagation Delay

I

= 3 mA

V

10

12

ZCD

CL(POS)

CL(NEG)

I

= −2 mA

V

−0.7

100

−0.5

170

V

= 2 V to 0 V ramp,

t

ns

ZCD

dV/dt = 20 V/ms

to V

V

ZCD

= V

= 90%

DRV

ZCD(TRIG)

Minimum ZCD Pulse Width

t

−

70

−

ns

SYNC

Maximum Off Time in Absence of ZCD

Transition

Falling V

= 10% to

DRV

t

75

165

300

ms

DRV

start

Rising V

= 90%

DRIVE

Drive Resistance

I

= 100 mA

R

OL

−

12

6

20

13

W

source

OH

I

sink

Rise Time

10% to 90%

90% to 10%

t

−

35

25

−

80

70

ns

V

rise

Fall Time

t

fall

Drive Low Voltage

V

CC

= V

−200 mV,

V

out(start)

0.2

CC(on)

I

= 10 mA

sink

CURRENT SENSE

Current Sense Voltage Threshold

T = 25°C

V

ILIM

0.475

0.470

0.485

0.495

0.500

V

J

T = −40°C to 125°C

J

Leading Edge Blanking Duration

V

= 2 V, V

= 90% to 10%

t

100

40

195

100

350

170

ns

CS

DRV

LEB

Overcurrent Detection Propagation

Delay

dV/dt = 10 V/ms

= V to V = 10%

t

CS

V

CS

ILIM

DRV

Current Sense Bias Current

V

CS

= 2 V

I

−1

−

1

mA

CS

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7

NCL30002

TYPICAL CHARACTERISTICS

2.85

2.80

2.75

2.70

2.65

2.60

2.55

2.50

80

70

60

50

40

−50 −25

0

25

50

75

100

125

−50 −25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 3. Overvoltage Detect Threshold vs.

Junction Temperature

Figure 4. Overvoltage Hysteresis vs. Junction

Temperature

0.325

7

6

5

4

3

2

0.320

0.315

0.310

0.305

0.300

1

0

−50

−25

0

25

50

75

100

125

−50 −25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 5. Undervoltage Detect Threshold vs.

Junction Temperature

Figure 6. MFP Pin Internal Pull−Down Resistor

vs. Junction Temperature

2.54

2.53

2.52

2.51

2.50

2.49

2.48

2.47

2.46

−50 −25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Reference Voltage vs. Junction

Temperature

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8

NCL30002

TYPICAL CHARACTERISTICS

20

18

16

14

12

10

220

V

MFP

= V

+ 0.11 V

REF

215

210

205

200

195

190

V

= 0.5 V

100

MFP

8

6

185

180

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 8. Error Amplifier Sink Current vs.

Junction Temperature

Figure 9. Error Amplifier Source Current vs.

Junction Temperature

200

180

160

140

120

100

80

200

125

180

160

140

120

100

80

120

115

110

105

100

95

Phase

Transconductance

R

C

= 100 kW

= 2 pF

Control

60

V

= 2.5 Vdc, 1 Vac

= 12 V

MFP

40

CC

90

85

20

0

20

0

1000

T = 25°C

A

−50 −25

0

25

50

75

100

125

0.01

0.1

1

10

100

T , JUNCTION TEMPERATURE (°C)

J

f, FREQUENCY (kHz)

Figure 10. Error Amplifier Transconductance

vs. Junction Temperature

Figure 11. Error Amplifier Transconductance

and Phase vs. Frequency

290

285

280

275

270

265

260

255

250

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

245

240

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 12. Minimum Control Voltage to Generate

Drive Pulses vs. Junction Temperature

Figure 13. On Time Capacitor Charge Current

vs. Junction Temperature

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9

NCL30002

TYPICAL CHARACTERISTICS

6.0

5.5

5.0

170

160

150

140

130

120

4.5

4.0

110

100

−50 −25

0

25

50

75

100

125

−50 −25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 14. Ct Peak Voltage vs. Junction

Temperature

Figure 15. PWM Propagation Delay vs.

Junction Temperature

500

497

494

491

488

485

482

479

476

473

470

220

210

200

190

180

−50 −25

0

25

50

75

100

125

−50 −25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 16. Current Sense Voltage Threshold

vs. Junction Temperature

Figure 17. Leading Edge Blanking Duration vs.

Junction Temperature

205

200

195

190

185

180

175

18

16

14

12

10

8

R

OH

6

R

OL

4

170

165

2

0

−50

−25

0

25

50

75

100

125

−25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 18. Maximum Off Time in Absence of

ZCD Transition vs. Junction Temperature

Figure 19. Drive Resistance vs. Junction

Temperature

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NCL30002

TYPICAL CHARACTERISTICS

13

12

11

10

26

24

22

20

18

V

CC(on)

V

CC(off)

9

8

16

14

−50 −25

0

25

50

75

100

125

−50 −25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 20. Supply Voltage Thresholds vs.

Junction Temperature

Figure 21. Startup Current Consumption vs.

Junction Temperature

2.16

2.14

2.12

2.10

2.08

2.06

2.04

2.02

2.00

−50 −25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

Figure 22. Switching Current Consumption vs.

Junction Temperature

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11

NCL30002

THEORY OF OPERATION

High power factor, high efficiency, and small size are key

power factor is 0.7. So a certain amount of distortion can be

accepted while maintaining high power factor. This buck

topology meets the requirements for PF greater than 0.9 and

regulate LED current in a single power stage. Unlike the

boost converter, the NCL30002 buck controller operates in

several different modes over the line cycle.

parameters for LED drivers in the incandescent replacement

market. The NCL30002 has all the features required to

accomplish that is in a compact SOIC-8 package. Power

factor is broadly defined as:

P_in(avg)

PF +

V_in(rms) I_in(rms)

Buck Modes

This differs from the classical definition where there is a

phase angle difference between the input voltage and

current. However, the underlying concept of optimizing

power delivery by minimizing line current is the same.

Ideally, current would be directly proportional to the voltage

which is the case when the load is a resistor. Offline power

converters are active devices which are not purely resistive,

capacitive, or inductive often drawing distorted current

waveforms from the power lines. This distortion reduces

power factor by increasing input RMS current.

Preregulators using boost converters are the most common

method to correcting the distortion and making the offline

power supply appear to be a resistor as far as the power line

is concerned. Their performance is excellent achieving

power factor greater than 0.99. Regrettably, this two stage

approach negatively impacts efficiency and board area.

Fortunately, power factors greater than 0.9 are acceptable in

the general lighting market and in some applications like US

Energystart Integral LED bulbs, the minimum acceptable

1. “Zero” Input Current (I =0) - Buck converters

in

cannot deliver power when Vin is less than Vout.

The “dead time” where no current flows around

the zero crossing is dependent on the line voltage

and the load voltage.

2. Constant On-Time (T = constant) - This is the

on

same as the boost converter. Constant T forces

on

the peak current to be proportional to the input

voltage which is key to improved PF.

3. Constant Peak Current (I

= constant) – The

peak

NCL30002 limits the peak inductor and thus the

LED current. In this region, the unique nature of

the CrM buck means that the average output

current is equal to half the peak current. Also the

off time is fixed is this mode since the peak current

and the output voltage are virtually constant.

In the example below (Figure 23) in spite of the distortion,

the power factor is 0.97. The corresponding pre-filtered

output current is shown in Figure 24.

Mode 3 I

= Constant

peak

Mode 2 t = Constant

on

Mode 1 Input Current = 0

Figure 23. Theoretical Average Input Current over one half line cycle (conduction angle)

http://onsemi.com

12

NCL30002

Mode 3 I

= Constant

peak

Mode 2 t = Constant

on

Mode 1 Input Current = 0

Figure 24. Theoretical Average Output Current over one half line cycle (conduction angle)

On Time Control

An output capacitor filters the output current in the LED

string. The dynamic LED resistance, line frequency, and the

size of the filter capacitance determine the exact LED ripple.

The NCL30002 operates as a CrM controller. The

controller draws very low currents while the Vcc filter

capacitor charges to the start-up threshold. Since CrM

operation is not clocked at a fixed frequency and depends on

the state of the power circuit to initiate a new switching

cycle, a kick start timer turns on the gate driver to start a new

cycle. The kick start timer will do this anytime the driver is

off for more than about 180 msec as long as none of the

protection circuits are disabling the gate driver output.

The NCL30002 (refer to the block diagram − Figure 1) is

composed of 4 key functional blocks along with protection

circuitry to ensure reliable operation of the controller.

• On−Time Control

The on−time control circuitry (Figure 25) consists of a

precision current source which charges up an external

capacitor (C ) in a linear ramp. The voltage on C (after

t

removing an internal offset) is compared to an external

control voltage and the output of the comparator is used to

turn off the output driver thus terminating the switching

cycle. A signal from the driver is fed back to the on−time

control block to discharge the C capacitor thus preparing the

circuit for the start of the next switching cycle.

The state of V

regulation loop. The range of on−time is determined by the

charging slope of the C capacitor and is clamped at 4.93 V

t

is determined by the external

control

t

nominal. The C capacitor is sized to ensure that the required

t

on−time is reached at maximum output power and the

minimum input line voltage condition.

• Zero Current Detection Control

• MOSFET Gate Driver

• Startup and V Management

CC

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13

NCL30002

V

Control

MOSFET Conduction

COMP

V

DD

V

EAH

Output Rectifier Conduction

PWM

I

charge

−

+

Ct

+

t

on

I

primary

0 A

DRV

Ct

(offset)

V

Ct

V

− Ct

(offset)

Control

V

Ct(off)

V

Control

0 A

I

secondary

t

on(max)

DRV

Figure 25. On Time Control

0 V

V

out

Off Time Sequence

The off time is determined by the peak inductor current,

the inductance and the output voltage. In mode 2, the off time

is variable because the peak inductor current is not fixed.

However in mode 3, the off time is constant since the peak

current and the output voltage are both fixed. The auxiliary

winding used to provide bias to the NCL30002 is also used

to detect when the current has dropped to zero. This is

illustrated in Figure 26.

0 V

V

ZCD(WIND)

V

ZCD(WIND),off

0 V

V

ZCD(WIND),on

V

CL(POS)

V

ZCD(ARM)

V

ZCD(TRIG)

0 V

V

CL(NEG)

t

on

t

diode

t

off

t

SW

Figure 26. Ideal CrM Waveforms with ZCD Winding

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14

NCL30002

ZCD Detection Block

the ZCD input has a dual comparator input structure to arm

the latch when the ZCD detect voltage rises above 1.4 V

(nominal) thus setting the latch. When the voltage on ZCD

falls below 0.7 V (nominal) a zero current event is detected

and a signal is asserted which initiates the next switching

cycle. This is illustrated in Figure 27. The input of the ZCD

has an internal circuit which clamps the positive and

negative voltage excursions on this pin. The current into or

out of the ZCD pin must be limited to 10 mA with an

external resistor.

A dedicated circuit block is necessary to implement the

zero current detection. The NCL30002 provides a separate

input pin to signal the controller to turn the power switch

back on just after inductor current reaches zero. When the

output winding current reaches zero the winding voltage

will reverse. Since all windings of the inductor reflect the

same voltage characteristic this voltage reversal appears on

the bias winding. Coupling the winding voltage to the ZCD

input of the NCL30002 allows the controller to start the next

switching cycle at the precise time. To avoid false triggering,

V

arm

N

ZCD

V

trig

Demag

+

−

S

Q

Reset

Dominant

Latch

+

V

ZCD(ARM)

DRIVE

R

Q

+

−

+

V

ZCD(TRIG)

ZCD

Bias Winding Voltage

R

ZCD

ZCD Clamp

Figure 27. ZCD Operation

At startup, there is no energy in the ZCD winding and no

voltage signal to activate the ZCD comparators. To enable

the controller to start under these conditions, an internal

watchdog timer is provided which initiates a switching cycle

in the event that the output drive has been off for more than

180 ms (nominal).

CS

DRV

OCP

+

−

LEB

+

V

ILIM

R

sense

The timer is deactivated only under an OVP or UVP fault

condition which will be discussed in the next section.

optional

Figure 28. CS Circuitry with Optional

External RC Filter

CS

The dedicated CS pin of the NCL30002 senses the current

through the MOSFET switch and the output inductor. If the

voltage of the CS pin exceeds V

MFP Input

,the internal comparator

ILIM

The multi−function pin connects to the inverting terminal

of the transconductance amplifier, the undervoltage and

overvoltage protection comparators. This allows this pin to

perform several functions. To place the device in standby,

will detect the event and turn off the MOSFET. The peak

switch current is calculated using Equation 1:

V_ILIM

I_SW(peak)

+

(eq. 1)

R_sense

the MFP pin should be pulled below the V threshold. This

uvp

To avoid false detection, the NCL30002 incorporates

leading edge blanking circuit (LEB) which masks the CS

signal for a nominal time of 190 ns. If required, an optional

is illustrated in Figure 29. Additionally, raising the MFP pin

above V will also suspend switching activity but not place

ovp

the controller in the standby mode. This can be used

implement overvoltage monitoring on the bias winding and

add an additional layer of fault protection.

RC filter can be added between R

and CS to provide

sense

additional filtering. This is illustrated below.

http://onsemi.com

15

NCL30002

OVP

+

OVP Fault

POWER GOOD

UVP Fault

+

−

V

OVP

Bias

UVP

−

+

R

1

2

UVP

EA

(Enable EA)

MFP

−

+

gm

R

FB

Shutdown

V

REF

COMP

V

Control

C

COMP

Figure 29. Multi−Function Pin Operation

Design Tool

The positive input of the transconductance amplifier is

connected to a 2.51 V (nominal) reference. A filtered line

feed-forward signal (see Figure 2) is connected to the

negative input of the error amplifier and used to control the

on-time of controller.

The NCL30002 implements a unique control method to

achieve high power and superior current regulation even

though the average current is not directly sensed. There are

a number of design tradeoffs that can be made between peak

switch current, inductor size, and desired power factor that

can impact the current regulation accuracy, efficiency, and

physical size. These tradeoffs can be made by adjusting the

amount of line feed forward applied, selecting the amount of

time where the controller is operating in mode 2 and 3, as

well as factoring in the LED forward voltage range. To

simplify the component selection process and allow the

designer to interactively make these tradeoffs,

ON Semiconductor has developed an EXCELt based

Design Guide which allows step-by-step analysis. This tool

is available at onsemi.com along with a supporting

application note that illustrates a complete design and

provides typical application performance.

V_CCManagement

The NCL30002 incorporates a supervisory circuitry to

manage the startup and shutdown of the circuit. By

managing the startup and keeping the initial startup current

at less than 35 mA, a startup resistor connected between the

rectified ac line and V

charges the V

capacitor to

CC

V . Turn on of the device occurs when the startup

CC(on)

voltage has exceeded 12 V (nominal) when the internal

reference and switching logic are enabled. A UVLO

comparator with a hysteresis of 2.5 V nominal gives ample

time for the device to start switching and allow the bias from

the auxiliary winding to supply V

CC.

http://onsemi.com

16

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

8

1

DATE 16 FEB 2011

SCALE 1:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

−X−

A

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

8

5

4

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

S

M

Y

B

0.25 (0.010)

1

K

−Y−

MILLIMETERS

DIM MIN MAX

INCHES

G

MIN

MAX

0.197

0.157

0.069

0.020

A

B

C

D

G

H

J

K

M

N

S

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

C

N X 45

_

SEATING

PLANE

1.27 BSC

0.050 BSC

−Z−

0.10

0.19

0.40

0

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

8

0.020

0.244

0.10 (0.004)

M

J

H

D

8

0

_

0.25

5.80

0.50 0.010

6.20 0.228

M

S

X

0.25 (0.010)

Z

Y

GENERIC

MARKING DIAGRAM*

SOLDERING FOOTPRINT*

8

1

8

1

8

XXXXX

ALYWX

XXXXXX

AYWW

G

XXXXX

ALYWX

XXXXXX

AYWW

1.52

0.060

G

1

Discrete

(Pb−Free)

IC

(Pb−Free)

7.0

0.275

4.0

0.155

XXXXX = Specific Device Code

XXXXXX = Specific Device Code

A

L

= Assembly Location

= Wafer Lot

A

= Assembly Location

= Year

Y

W

G

= Year

= Work Week

= Pb−Free Package

WW

G

= Work Week

= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

0.6

0.024

1.270

0.050

mm

inches

ǒ

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB42564B

SOIC−8 NB

PAGE 1 OF 2

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

STYLE 1:

STYLE 2:

STYLE 3:

STYLE 4:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

6. EMITTER, #2

7. BASE, #1

6. SOURCE, #2

7. GATE, #1

7. BASE

8. EMITTER

8. EMITTER, #1

8. SOURCE, #1

8. COMMON CATHODE

STYLE 5:

STYLE 6:

PIN 1. SOURCE

2. DRAIN

STYLE 7:

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

3. DRAIN

3. BASE, #2

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

STYLE 10:

PIN 1. GROUND

2. BIAS 1

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

STYLE 12:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

STYLE 15:

PIN 1. ANODE 1

2. ANODE 1

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

STYLE 18:

STYLE 19:

PIN 1. SOURCE 1

2. GATE 1

STYLE 20:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

5. RXE

6. VEE

7. GND

8. ACC

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 21:

STYLE 22:

STYLE 23:

STYLE 24:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

PIN 1. I/O LINE 1

PIN 1. LINE 1 IN

PIN 1. BASE

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 25:

PIN 1. VIN

2. N/C

STYLE 26:

PIN 1. GND

2. dv/dt

STYLE 27:

PIN 1. ILIMIT

2. OVLO

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

5. V_MON

6. VBULK

7. VBULK

8. VIN

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB42564B

SOIC−8 NB

PAGE 2 OF 2

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	NCL30002DR2G
厂家：	ONSEMI
描述：	LED 驱动器，离线降压，功率因数校正驱动功率因数校正驱动器
文件：	总19页 (文件大小：325K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCL30002DR2G [ONSEMI]

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