NCL30030B1DR2G_技术文档

NCL30030

Combination Power Factor

Correction and

Quasi-Resonant Flyback

Controllers for LED Lighting

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This combination IC integrates power factor correction (PFC) and

quasi−resonant flyback functionality necessary to implement a

compact and highly efficient LED driver for high performance LED

lighting applications.

The PFC stage utilizes a proprietary multiplier architecture to

achieve low harmonic distortion and near−unity power factor while

operating in a Critical Conduction Mode (CrM). The circuit

incorporates all the features necessary for building a robust and

compact PFC stage while minimizing the number of external

components.

SOIC−16 NB MISSING PIN 2

CASE 751DT

MARKING DIAGRAM

1

16

BO/HV

PFB

The quasi−resonant current−mode flyback stage features a

proprietary valley−lockout circuitry, ensuring stable valley switching.

GND

MULT

PControl

PONOFF

QCT

PCS/PZCD

PDRV

QDRV

QCS

VCC

QZCD

th

This system works down to the 4 valley and toggles to a frequency

th

foldback mode with a minimum frequency clamp beyond the 4

valley to eliminate audible noise. Skip mode operation allows

excellent efficiency in light load conditions while consuming very low

standby power consumption.

Fault

QFB

NCL30030 = Specific Device Code

x

y

A

WL

Y

= A or B

= 1, 2 or 3

= Assembly Location

= Wafer Lot

= Year

Common General Features

• Wide V Range from 9 V to 30 V with Built−in Overvoltage

CC

Protection

• High−Voltage Startup Circuit

• Integrated High−Voltage Brown−Out Detector

WW

G

= Work Week

= Pb−Free Package

• Fault Input for Severe Fault Conditions, NTC Compatible (Latch and

Auto−Recovery Options)

ORDERING INFORMATION

• 0.5 A / 0.8 A Source / Sink Gate Drivers

• Internal Temperature Shutdown

See detailed ordering and shipping information on page 31 of

this data sheet.

PFC Controller Features

• Critical Conduction Mode with a Multiplier

• Minimum Frequency Clamp Eliminates Audible Noise

• Accurate Overvoltage Protection

• Timer−Based Overload Protection (Latched or

Auto−Recovery options)

• Optional Bi−Level Line−Dependent Output Voltage

(2:1 / 1.77:1 Versions)

• Adjustable Overpower Protection

• Fast Line / Load Transient Compensation

• Winding and Output Diode Short−Circuit Protection

• Boost Diode Short−Circuit Protection

• 4 ms Soft−Start Timer

• Feed−Forward for Improved Operation across Line and

• These are Pb−Free Devices

Load

Typical Applications

• Adjustable PFC Disable Threshold Based on Output

• High Power LED Drivers

• Commercial LED ballasts

• LED Signage Power Supplies

• Adapters

• Open Frame Power Supplies

• LED Electronic Control Gear

Power

QR Flyback Controller Features

• Valley Switching Operation with Valley−Lockout for

Noise−Free Operation

• Frequency Foldback with Minimum Frequency Clamp

for Highest Performance in Standby Mode

1

Publication Order Number:

March, 2015 − Rev. 1

NCL30030/D

NCL30030

( A u x )

Figure 1. NCL30030 Typical Application Circuit

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2

NCL30030

PUVP

Low/High Line

Brownout

High Voltage

Startups

BO/HV

V

+

−

PFB(HYS)

1

Latch

Auto−recovery

VCC(reset)

V

BO_BUF

VCC_OK

V

PFB(disable)

Detection, and

Logic

PFB

QR_EN

Reset

16

Central

Logic

PFC

OVP

K

Brownout

Low/High Line

POVP(xL)

POVP

V

D

CCOVP

Detection

I

VCC

start1/2

VCC_OK

VCC

Management

VCC_OK

10

VCC(reset)

C

CC

I

PControl(boost)

V

DD

K

LOW(HYS)

K

LOW

V

QR_EN

Soft−start

QILIM1

I

EA

+

V

QFB

V

PREF(xL)

QZCD

−

In Regulation

Soft−start

I

V

PCONTROL(MAX)

PONOFF

PControl

5

V

CONTROL

4

t

Disable PFC

Pdisable

PUVP

V

PCONTROL(MIN)

+

−

V

POFF

V

PONHYS

POVP

PUVP

PSKIP

PILIM1

PILIM2

Disable PFC

PSKIP

QDRV

Low/High Line

QRDRV

R

S

12

Q

Dominant

Reset

Latch

+

DV

−

t

on1x

PSKIP

Q

R

S

Q

Soft−start

In Regulation

PFCDRV

t

Dominant

Reset

Latch

Q(toutx)

V

QZCD

V

QZCD

PCONTROL

Q

Valley

ZCD

9

Low/High Line

Multiplier

V

Detect

BO_BUF

V

QZCD(hys)

+

MULT

t

QSkip

delay(QSKIP)

3

V

QZCD(th)

V

−

CT

Setpoint

Minimum

Frequency

Oscillator

QFB

VCO

QRDRV

LEB1

PILIM1

I

QCT

+

−

QCT

V

PILIM1

6

VCO

QRDRV

t

PILIM2

PFCDRV

PFC(offx)

Timer

I

QFB

R

QFB

QSkip

ZCD

PZCD

Detect

Valley

QSkip

Valley

QFB

Select

Logic

8

+

t

onQR(MAX)

QRDRV

V

QFB

V

VCO

−

PZCD

/K

+

PCS/PZCD

QFB

14

13

LEB2

PILIM2

V

+

QZCD

GND

V

−

15

TSD

S

QOVLD

nQILIM2

PDRV

Latch

PFCDRV

S

OVP

OTP

CCOVP

QILIM1

Fault

Logic

LEB1

+

V

Auto−recovery

t

QOVLD

+

−

I

OTP

Brownout

VCC(reset)

R

OVP

V

QZCD

Fault

7

V

QILIM1

LEB2

Fault(OVP)

I

QCS

Temperature

TSD

QCS

QILIM2

Counter

OTP

11

nQILIM2

+

V

Fault(OTP_in)

−

V

QILIM2

Figure 2. NCL30030 Functional Block Diagram

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3

NCL30030

Table 1. PIN FUNCTION DESCRIPTION

Pin Out

Name

Function

1

2

3

BO/HV

Performs input brown−out detection and line voltage range detection.

Removed for creepage distance.

MULT

This is the output of the multiplication of the BO and Control signals. A capacitor should be put on this

pin for filtering. Suggested values from 1 nF − 20 nF.

4

5

PControl

PONOFF

Output of the PFC transconductance error amplifier. A compensation network is connected between

this pin and ground to set the loop bandwidth.

A resistor between this pin and ground sets the PFC turn off threshold. The voltage on this pin is

compared to an internal voltage signal proportional to the output power. The PFC disabled threshold

is determined by the resistor on this pin and the internal pull–up current source, I

.

PONOFF

6

7

QCT

Fault

An external capacitor sets the frequency in VCO mode for the QR flyback controller.

The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds.

A precise pull up current source allows direct interface with an NTC thermistor. Fault detection trig-

gers a latch or auto−recovery depending on device option.

8

9

QFB

Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.

QZCD

Input to the demagnetization detection comparator for the QR Flyback controller. Also used to set the

overpower compensation.

10

11

12

13

14

VCC

QCS

Supply input.

Input to the cycle−by−cycle current limit comparator for the QR Flyback section.

QR flyback controller switch driver.

QDRV

PDRV

PFC controller switch driver.

PCS/PZCD

Input to the cycle−by−cycle current limit comparator for the PFC section. Also used to perform the

demagnetization detection for the PFC controller.

15

16

GND

PFB

Ground reference.

PFC feedback input from external resistor divider used to sense the PFC bulk voltage. This pin volt-

age is compared to an internal reference. There are three different reference voltage combinations

depending on ac mains voltage and version of the part.

Table 2. NCL30030 DEVICE OPTIONS

PFC Reference Voltage

(High Line / Low Line)

Device

Flyback Overload Protection

Fault OTP

Auto−Recovery

Latch

NCL30030B1DR2G

NCL30030B2DR2G

NCL30030B3DR2G

NCL30030A1DR2G*

NCL30030A2DR2G*

NCL30030A3DR2G*

Auto−Recovery

Latch

3.55 / 2 V

4 / 2 V

4 / 4 V

3.55 / 2 V

4 / 2 V

Latch

4 / 4 V

*Please contact local sales representative for availability

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4

NCL30030

Table 3. MAXIMUM RATINGS (Notes 1 through 6)

Rating

Symbol

Value

−0.3 to 700

20

Unit

V

High Voltage Brownout Detector Input Voltage

High Voltage Brownout Detector Input Current

PFC Low Voltage Feedback Input Voltage

PFC Low Voltage Feedback Input Current

PFC Zero Current Detection and Current Sense Input Voltage (Note 1)

PFC Zero Current Detection and Current Sense Input Current

PFC Control Input Voltage

1

V

BO/HV

I

mA

V

16

14

4

V

PFB

−0.3 to 9

0.5

I

mA

V

PFB

V

−0.3 to V

PCS/PZCD(MAX)

PCS/PZCD

I

−2/+5

−0.3 to 5

10

mA

V

PControl

PFC Control Input Current

4

I

mA

V

PControl

Supply Input Voltage

10

7

V

−0.3 to 30

30

CC(MAX)

Supply Input Current

I

mA

V/ms

V

Supply Input Voltage Slew Rate

dV /dt

CC

1

Fault Input Voltage

V

−0.3 to (V + 1.25)

Fault

CC

Fault Input Current

7

I

10

−0.3 to 10

3

mA

V

PFC Multiplier pin

3

V

MULT

PFC Multiplier pin

3

I

mA

V

QR Flyback Zero Current Detection Input Voltage

QR Flyback Zero Current Detection Input Current

QR Feedback Input Voltage

9

V

−0.9 to (V + 1.25)

QZCD

CC

9

I

−2/+5

−0.3 to 10

10

mA

V

6

V

QCT

QR Feedback Input Current

6

I

mA

V

QCT

QR Flyback Current Sense Input Voltage

QR Flyback Current Sense Input Current

QR Flyback Feedback Input Voltage

QR Flyback Feedback Input Current

PFC Driver Maximum Voltage (Note 2)

PFC Driver Maximum Current

11

8

V

−0.3 to 10

10

QCS

I

mA

V

−0.3 to 10

10

QFB

8

I

mA

V

13

V

PDRV

−0.3 to V

PDRV(high2)

I

500

800

mA

PDRV(SRC)

PDRV(SNK)

Flyback Driver Maximum Voltage (Note 2)

Flyback Driver Maximum Current

12

V

−0.3 to V

V

QDRV

QDRV(high2)

I

500

800

mA

QDRV(SRC)

QDRV(SNK)

PFC ON/OFF Threshold Adjust Input Voltage

PFC ON/OFF Threshold Adjust Input Current

Operating Junction Temperature

5

V

−0.3 to 10

V

PONOFF

5

I

10

mA

°C

PONOFF

N/A

T

J

−40 to 125

–60 to 150

Storage Temperature Range

T

STG

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device

functionality should not be assumed, damage may occur and reliability may be affected.

1. V

is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks

PCS/PZCD(MAX)

a current equal to (V

− 5 V)/(2 kW). A V

of 7 V generates a sink current of approximately 1 mA.

PCS/PZCD

PSC/PZCD

2. Maximum driver voltage is limited by the driver clamp voltage, V

, when V exceeds the driver clamp voltage. Otherwise,

XDRV(high2) CC

the maximum driver voltage is V

.

CC

3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond

those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied.

Functional operation should be restricted to the Recommended Operating Conditions.

4. This device contains Latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +100/−100 mA.

2

5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm of 2 oz copper traces and heat

spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.

6. Pin 1 is rated to the maximum voltage of the part, or 700 V.

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NCL30030

Table 3. MAXIMUM RATINGS (Notes 1 through 6)

Rating

Symbol

Value

Unit

Power Dissipation (T = 75°C, 1 Oz Cu, 0.155 Sq Inch Printed Circuit Copper

P

D

550

mW

A

Clad) Plastic Package SOIC−16NB

Thermal Resistance, Junction to Ambient 1 Oz Cu Printed Circuit Copper Clad)

Plastic Package SOIC−16NB

R

°C/W

q

JA

145

ESD Capability (Note 6)

V

Human Body Model per JEDEC Standard JESD22−A114F.

Machine Model per JEDEC Standard JESD22−A115−A.

Charge Device Model per JEDEC Standard JESD22−C101E.

HBM

MM

CDM

3000

200

750

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device

functionality should not be assumed, damage may occur and reliability may be affected.

1. V

is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks

PCS/PZCD(MAX)

a current equal to (V

− 5 V)/(2 kW). A V

of 7 V generates a sink current of approximately 1 mA.

PCS/PZCD

PSC/PZCD

2. Maximum driver voltage is limited by the driver clamp voltage, V , when V exceeds the driver clamp voltage. Otherwise,

XDRV(high2) CC

the maximum driver voltage is V

.

CC

3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond

those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied.

Functional operation should be restricted to the Recommended Operating Conditions.

4. This device contains Latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +100/−100 mA.

2

5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm of 2 oz copper traces and heat

spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.

6. Pin 1 is rated to the maximum voltage of the part, or 700 V.

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NCL30030

Table 4. ELECTRICAL CHARACTERISTICS: (V = 12 V, V

= 120 V, V

= open, V

= 1.9 V, V

= 4 V,

PDRV

CC

= 0 V, V

BO/HV

Fault

PFB

PControl

V

C

= 0 V, V

= 3 V, V

= 4 V, V

= 0 V, C

= 2 nF, C

= 100 nF , C

= 220 pF, C

= 1 nF,

PCS/PZCD

QFB

PONOFF

QCS

QZCD

MULT

VCC

QCT

= 1 nF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

QDRV

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

STARTUP AND SUPPLY CIRCUITS

Supply Voltage

Startup Threshold

Minimum Operating Voltage

Operating Hysteresis

Internal Latch / Logic Reset Level

10

V

increasing

decreasing

V

16

8.2

7.7

4.5

0.3

17

8.8

–

5.5

0.7

18

9.4

–

7.5

0.95

CC

CC(on)

CC(off)

V

CC

V

CC(on)

− V

V

CC(off)

CC(HYS)

CC(reset)

V

CC(inhibit)

V

CC

decreasing

V

Transition from I

to I

start2

V

CC

increasing, I = 650 mA

start1

HV/HV

Blanking Duration After V

10

t

3

–

25

ms

CC(off)

UVLO(blank)

Startup Current in Inhibit Mode

V

= 0 V

I

0.20

0.50

0.65

mA

CC

start1A

Startup Current

Operating Mode

V

= V

BO/HV

– 0.5 V,

CC

V

CC(on)

= 100 V

I

2.5

–

−

–

5

40

start2A

Minimum Startup Voltage

I

= 1 mA, V = V

– 0.5 V

1

V

start2A

CC

CC(on)

BO/HV(MIN)

V

CC

V

CC

Overvoltage Protection Threshold

Overvoltage Protection Delay

10

V

27

28

30.0

29

CC(OVP)

delay(VCC_OVP)

t

20.0

40.0

ms

mA

Supply Current

Before Startup, Fault or Latch

Flyback in Skip, PFC Disabled

Flyback in Skip, PFC in Skip

Flyback Enabled, QDRV Low, PFC

Disabled

Flyback Enabled, QDRV Low, PFC in

Skip

V

= V

−

0.15

0.3

0.5

0.28

0.43

1.03

1.38

CC

CC(on)

V

QFB

V

= 0.35 V, V

QFB

PSKIP

V

QZCD

0.85

V

= 1 V, V

−

1.1

1.83

QZCD

PFC and Flyback switching at 70 kHz

C

QDRV

= C

= open

I

−

1.5

2.8

4.03

5.23

PDRV

CC6

CC7

BROWN−OUT DETECTION

System Startup Threshold

V

increasing

decreasing

increasing

1

V

102

86

4

111

101

−

120

116

16

V

BO/HV

BO(start)

System Shutdown Threshold

Brown−out Hysteresis

V

BO/HV

BO(stop)

V

BO/HV

V

BO(hys)

BO(stop)

Brown−out Detection Blanking Time

V

BO/HV

decreasing, duration below

t

43

54

65

ms

V

for a Brown−out fault

BO(stop)

Brown−out Drive Disable Threshold

V

BO/HV

decreasing, threshold to

disable drive

1

V

20

30

40

V

BO(DRV_disable)

Line Level Detection Threshold

V

increasing

decreasing

increasing

1

V

216

43

240

54

264

65

V

BO/HV

lineselect

High to Low Line Mode Selector Timer

Low to High Line Mode Selector Timer

V

BO/HV

t

ms

high to low line

low to high line

V

BO/HV

t

200

–

350

–

450

42

Brownout Pin Off State Leakage

Current

V

= 500 V

I

mA

BO/HV

BO/HV(off)

PFC MAXIMUM OFF TIME TIMER

Maximum Off Time

13

t

100

700

200

1000

300

1300

ms

PFC(off1)

PFC(off2)

V

> V

PCS/PZCD

PILIM2

PFC CURRENT SENSE

Fixed Cycle by Cycle Current Sense

Threshold

14

V

1.35

250

−

1.5

325

100

1.65

400

V

PILIM1

Cycle by Cycle Leading Edge Blanking

Duration

t

ns

PCS(LEB1)

Cycle by Cycle Current Sense

Propagation Delay

t

PCS(delay1)

Abnormal Overcurrent Fault Threshold

14

V

1.8

2

2.2

V

PILIM2

Abnormal Overcurrent Fault Leading

Edge Blanking Duration

t

100

175

250

ns

PCS(LEB2)

Abnormal Overcurrent Fault

Propagation Delay

14

t

−

100

200

ns

PCS(delay2)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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NCL30030

Table 4. ELECTRICAL CHARACTERISTICS: (V = 12 V, V

= 120 V, V

= open, V

= 1.9 V, V

= 4 V,

PDRV

CC

= 0 V, V

BO/HV

Fault

PFB

PControl

V

C

= 0 V, V

= 3 V, V

= 4 V, V

= 0 V, C

= 2 nF, C

= 100 nF , C

= 220 pF, C

= 1 nF,

PCS/PZCD

QFB

PONOFF

QCS

QZCD

MULT

VCC

QCT

= 1 nF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

QDRV

J

Characteristics

PFC CURRENT SENSE

Conditions

Symbol

Min

Typ

Max

Unit

Multipler Cycle by Cycle Current Sense

Offset

BO = 180, PFB = 1.5 V

BO = 180 V, PFB = 1.5 V

14

V

−12

10

−

10

200

1.3

mV

ns

PILIM_MULT

Multiplier Cycle by Cycle Current Sense

Propagation Delay

t

100

1.0

PCS(delay_mult)

Pull−up Current Source

V

= 2.5 V

I

0.7

mA

PCS/PZCD

PFC REGULATION BLOCK

PFC Reference Voltage

See Table 2 for Options

V

> V

< V

16

4

V

PREF(HL)

3.47

3.92

1.95

3.92

3.55

4.00

2

3.62

4.08

2.05

4.08

V

BO/HV

BO(lineselect)

V

BO/HV

BO(lineselect)

PREF(LL)

4

Error Amplifier Current

Source

Sink

Source

Sink

PFC Enabled

mA

V

PFB

= 0.96 x V

= 1.04 x V

= 0.96 x V

= 1.04 x V

I

EA(SRCHL)

16

10

32

20

48

30

PREF(HL)

PREF(LL)

V

PFB

I

EA(SNKHL)

V

PFB

V

PFB

I

EA(SRCLL)

I

EA(SNKLL)

Open Loop Error Amplifier

Transconductance

V

= V

+/− 4 %

4

g

m

m_HL

100

200

300

mS

V

PFB

PREF(LL)

PREF(HL)

g

Maximum Control Voltage

V

* K

PControl

,

V

–

4.5

0.6

3.9

–

PFB

C

LOW(PFCxL)

PControl(MAX)

= 10 nF

PControl

Minimum Control Voltage (Lower

clamp)

V

* K

, C

= 10 nF

V

PControl(MIN)

–

V

PFB

POVP(xL)

EA Output Control Voltage Range

V

− V

4

DV

3.7

4.1

V

PControl(MAX)

PControl(MIN)

PControl

Ratio between the V Low Detect

out

Threshold and the Regulation Level

V

decreasing, V

/ V

16

K

0.940

0.945

0.950

PFB

BOOST

PREF(HL)

PREF(LL)

LOW(PFCHL)

LOW(PFCLL)

Ratio between the V Low Exit

out

Threshold and the Regulation Level

V

PFB

increasing

16

K

0.950

0.960

0.965

LOW(HYSHL)

LOW(HYSLL)

Source Current During V Low Detect

out

4

I

190

−6.5

4

240

–

290

0

mA

W

PControl(boost)

PFC In Regulation Threshold

Resistance of Internal Pull Down Switch

PFC SKIP MODE

V

increasing

I

PControl

In_Regulation

I

= 5 mA

R

25

50

PControl

Delta Between Skip Level and Lower

Clamp PControl Voltages

V

decreasing, measured from

4

DV

PSKIP

5

25

50

mV

PControl

V

PControl(MIN)

PFC Skip Hysteresis

V

increasing

4

V

25

–

50

75

60

mV

PControl

PSKIP(HYS)

Delay Exiting Skip Mode

PFC FAULT PROTECTION

Apply 1 V step from V

t

ms

PControl(MIN)

delay(PSKIP)

Ratio between the Hard Overvoltage

Protection Threshold and Regulation

Level

V

increasing

16

PFB

K

= V

/V

K

1.06

1.05

1.08

1.06

1.10

1.08

POVP(LL)

POVP(HL)

PFB PREF(LL)

POVP(LL)

K

POVP(HL)

/V

PFB PREF(HL)

Soft Overvoltage Protection Threshold

V

= soft overvoltage level

mV

PSOVP(LL)

D

= K

*V

−

D

20

–

55

POVP(LL)

POVP PREF(LL)

POVP(LL)

D

POVP(HL)

V

PSOVP(LL)

D

= K

*V

−

POVP(HL)

POVP PREF(HL)

PSOVP(HL)

V

PFC Feedback Pin Disable Threshold

PFC Feedback Pin Enable Threshold

PFC Feedback Pin Hysteresis

PFC Feedback Disable Delay

PFC ON TIME CONTROL

PFC Maximum On

V

decreasing

increasing

16

V

0.225

0.275

25

0.30

0.35

50

0.35

0.40

−

V

PFB

PFB(disable)

V

PFB

PFB(enable)

V

mV

ms

PFB(HYS)

t

20

30

40

delay(PFB)

V

= V

BO/HV

13

ms

PControl

PControl(MAX)

= 163 V

V

t

12.5

4.25

15

5.00

17.5

5.75

on1a

on1b

= 325 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

www.onsemi.com

8

NCL30030

Table 4. ELECTRICAL CHARACTERISTICS: (V = 12 V, V

= 120 V, V

= open, V

= 1.9 V, V

= 4 V,

PDRV

CC

= 0 V, V

BO/HV

Fault

PFB

PControl

V

C

= 0 V, V

= 3 V, V

= 4 V, V

= 0 V, C

= 2 nF, C

= 100 nF , C

= 220 pF, C

= 1 nF,

PCS/PZCD

QFB

PONOFF

QCS

QZCD

MULT

VCC

QCT

= 1 nF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

QDRV

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

PFC DISABLE

Voltage to Current Conversion Ratio

V

= 3 V, Low Line

= 3 V, High Line

5

I

13

15

17

mA

QFB

ratio1(QFB/PON)

ratio2(QFB/PON)

PFC Disable Threshold

V

decreasing

5

V

1.9

2.0

2.1

V

PONOFF

POFF

PFC Enable Hysteresis

V

= increasing

V

0.135

0.160

0.185

QFB

PONHYS

PONOFF Operating Mode Voltage

t

/T = 70%,

demag

R

= 191 kW, C

= 1 nF

PONOFF

V

= 1.8 V (decreasing)

V

1.08

1.8

1.20

2.0

1.32

2.2

QFB

PONOFF1

PONOFF2

= 3 V (decreasing)

QFB

PFC Disable Timer

Disable Timer

5

t

450

50

500

100

–

550

150

500

ms

Pdisable

t

Penable(filter)

PFC Enable Filter Delay

PFC Enable Timer

PONOFF Increasing

t

200

Penable

PFC MULTIPLIER

Multiplier maximum BO=180V

Multiplier maximum BO = 360V

Multiplier output

PControl = open, BO = 180 V

PControl = open, BO = 360 V

PControl = 2.5 V, BO = 180 V

PControl = 2.5 V, BO = 360 V

3

MULT_max_180

MULT_max_360

VmultLL

0.85

0.425

0.2125

0.98

1

1.15

0.575

V

0.5

Multiplier output

VmultHL

0.25

1

0.2875

1.02

Multiplier linearity with respect to BO at

low line.

PControl = 2.5 V, BO = 180 V and

BO = 120 V

Mult_linearityLL

(VMULT180/180V)/(VMULT120/120V)

Multiplier linearity with respect to BO at

high line.

PControl = 2.5 V, BO = 360 V and BO

= 300 V

3

Mult_linearityHL

0.99

1

1.01

(VMULT360/360V)/VMULT300/300V)

PFC GATE DRIVE

Rise Time (10−90%)

Fall Time (90−10%)

V

PDRV

from 10% to 90% of V

13

t

–

40

20

80

40

ns

W

CC

PDRV(rise)

90% to 10% of V

t

PDRV(fall)

PDRV

Driver Resistance

Source

Sink

R

−

13

7

−

PDRV(SRC)

PDRV(SNK)

Current Capability

Source

Sink

13

mA

V

= 2 V

= 10 V

I

–

500

800

–

PDRV

PDRV(SRC)

PDRV(SNK)

V

PDRV

High State Voltage

V

CC

= V

+ 0.2 V, R

= 10 kW

13

V

8

10

–

12

–

14

V

CC(off)

PDRV

PDRV(high1)

PDRV(high2)

V

CC

= 26 V, R

PDRV

Low State Voltage

V

Fault

= 4 V

V

–

0.25

PDRV(low)

PFC ZERO CURRENT DETECTION

Zero Current Detection Threshold

V

rising

falling

14

V

675

200

750

250

825

300

mV

PCS/PZCD

PZCD(rising)

PZCD(falling)

Hysteresis on Voltage Threshold

Propagation Delay

V

– V

14

V

PZCD(HYS)

375

50

500

100

625

170

mV

ns

PZCD(rising)

PZCD(falling)

Measure from V

=

t

PZCD

PCS/PZCD

to PDRV rising

V

PZCD(falling)

Input Voltage Excursion

Upper Clamp

Negative Clamp

14

V

I

= 1 mA

= −2 mA

V

6.5

−0.9

7

−0.7

7.5

0

PCS/PZCD

PCS/PZCD(MAX)

PCS/PZCD(MIN)

I

PCS/PZCD

Minimum detectable ZCD Pulse Width

Between V

and

to PDRV

14

t

–

70

200

ns

PZCD(rising)

SYNC

V

PZCD(falling)

ZCD blanking time

Measured DRV off to DRV on

T

450

700

1000

Pzcd_blank

QR FLYBACK GATE DRIVE

Rise Time (10−90%)

V

QDRV

from 10 to 90%

12

t

–

40

80

ns

QDRV(rise)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

www.onsemi.com

9

NCL30030

Table 4. ELECTRICAL CHARACTERISTICS: (V = 12 V, V

= 120 V, V

= open, V

= 1.9 V, V

= 4 V,

PDRV

CC

= 0 V, V

BO/HV

Fault

PFB

PControl

V

C

= 0 V, V

= 3 V, V

= 4 V, V

= 0 V, C

= 2 nF, C

= 100 nF , C

= 220 pF, C

= 1 nF,

PCS/PZCD

QFB

PONOFF

QCS

QZCD

MULT

VCC

QCT

= 1 nF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

QDRV

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

QR FLYBACK GATE DRIVE

Fall Time (90−10%)

90 to 10% of V

12

t

–

20

40

ns

QDRV

QDRV(fall)

Driver Resistance

Source

Sink

W

R

−

13

7

−

QDRV(SRC)

QDRV(SNK)

Current Capability

Source

Sink

12

mA

V

= 2 V

= 10 V

I

–

500

800

–

QDRV

QDRV(SRC)

QDRV(SNK)

V

QDRV

High State Voltage

V

CC

= V

V

+ 0.2 V, R

= 10 kW

12

V

8

10

–

12

–

14

V

CC(off)

QDRV

QDRV(high1)

QDRV(high2)

= 26 V, R

CC

QDRV

Low State Voltage

V

Fault

= 4 V

V

–

0.25

QDRV(low)

QR FLYBACK FEEDBACK

Internal Pull−Up Current Source

Feedback Input Open Voltage

8

I

46.75

4.5

50

5.0

4.0

53.25

5.5

mA

QFB

V

QFB(open)

V

QFB

to Internal Current Setpoint

K

R

3.8

4.2

QFB

Division Ratio

QFB Pull Up Resistor

V

= 0.4 V

8

340

400

460

kW

QFB

Valley Thresholds

st

V

nd

rd

th

Transition from 1 to 2 valley

V

decreasing

increasing

V

1.316

1.128

0.846

0.752

1.316

1.504

1.692

1.880

1.400

1.200

0.900

0.800

1.400

1.600

1.800

2.000

1.484

1.272

0.954

0.848

1.484

1.696

1.908

2.120

QFB

H2D

H3D

H4D

nd

Transition from 2 to 3 valley

rd

Transition from 3 to 4 valley

th

Transition from 4 valley to VCO

V

HVCOD

V

HVCOI

V

th

Transition from VCO to 4 valley

th

rd

nd

st

Transition from 4 to 3 valley

H4I

H3I

H2I

rd

Transition from 3 to 2 valley

nd

Transition from 2 to 1 valley

Skip Threshold

V

decreasing

increasing

8

V

0.35

25

–

0.40

50

–

0.45

75

V

QFB

QSKIP

Skip Hysteresis

V

mV

ms

QFB

QSKIP(HYS)

delay(QSKIP)

st

Delay Exiting Skip Mode to 1 QDRV

Apply 1 V step from V

t

10

QSKIP

Pulse

Maximum On Time

12

t

26

32

38

ms

onQR(MAX)

QR FLYBACK TIMING CAPACITOR

QCT Operating Voltage Range

V

= 0.5 V

6

V

3.815

18

4.000

20

4.185

22

V

QFB

QCT(peak)

On Time Control Source Current

Minimum voltage on QCT Input

V

= 0 V

I

mA

QCT

V

–

90

mV

kHz

QCT(min)

VCO(MIN)

Minimum Operating Frequency in VCO

Mode

V

QCT

= V

+ 100 mV

f

23.5

27

30.5

QCT(peak)

QR FLYBACK DEMAGNETIZATION INPUT

QZCD threshold voltage

V

decreasing

9

V

35

15

–

55

35

90

55

mV

ns

QZCD

QZCD(th)

QZCD hysteresis

V

increasing

V

QZCD(HYS)

QZCD

Demagnetization Propagation Delay

V

QZCD

step from 4.0 V to −0.3 V

t

150

250

DEM

Input Voltage Excursion

Upper Clamp

Negative Clamp

V

I

= 5.0 mA

= −2.0 mA

V

12.4

−0.9

12.7

−0.7

13.5

0

QZCD

QZCD(MAX)

I

V

QZCD

QZCD(MIN)

Blanking Delay After Turn−Off

9

t

2

3

4

ms

ZCD(blank)

Timeout After Last Demagnetization

Detection

During soft−start

After soft−start

12

t

80

5.1

100

6

120

6.9

Q(tout1)

Q(tout2)

QR FLYBACK CURRENT SENSE

Current Sense Voltage Threshold

V

increasing

11

V

0.760

0.800

0.840

V

QCS

QILIM1a

QILIM1b

V

QCS

increasing, V

= 1 V

QZCD

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

www.onsemi.com

10

NCL30030

Table 4. ELECTRICAL CHARACTERISTICS: (V = 12 V, V

= 120 V, V

= open, V

= 1.9 V, V

= 4 V,

PDRV

CC

= 0 V, V

BO/HV

Fault

PFB

PControl

V

C

= 0 V, V

= 3 V, V

= 4 V, V

= 0 V, C

= 2 nF, C

= 100 nF , C

= 220 pF, C

= 1 nF,

PCS/PZCD

QFB

PONOFF

QCS

QZCD

MULT

VCC

QCT

= 1 nF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

QDRV

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

QR FLYBACK CURRENT SENSE

Cycle by Cycle Leading Edge Blanking

Duration

Minimum on time minus t

11

t

220

–

275

125

350

175

ns

delay(ILIM_QR)

QCS(LEB1)

Cycle by Cycle Current Sense

Propagation Delay

t

QCS(delay1)

Immediate Fault Protection Threshold

V

QCS

increasing, V

= 4 V

11

V

QILIM2

1.125

90

1.200

120

1.275

150

V

QFB

Abnormal Overcurrent Fault Leading

Edge Blanking Duration

t

ns

QCS(LEB2)

Abnormal Overcurrent Fault

Propagation Delay

11

t

–

125

4

175

–

ns

QCS(delay2)

Number of Consecutive Abnormal

Overcurrent Detections to Enter Fault

Mode

n

QILIM2

Minimum Peak Current Level in VCO

Mode

V

= 0.4 V, V

increasing

11

I

peak(VCO)

11

28

12.5

14

33

%

QFB

QCS

Set point decrease for V

−250 mV

=

V

Increasing, V

= 4 V

V

OPP(MAX)

31.25

QZCD

QCS

QFB

Overpower Protection Delay

Pull−up Current Source

11

t

–

125

1.0

175

1.3

ns

QOPP(delay)

V

QCS

= 1.5 V

I

0.7

mA

QCS

QR FLYBACK FAULT PROTECTION

st

Soft−Start Period

Measured from 1 QDRV pulse to

11

t

2.8

60

4.0

80

5.0

ms

SSTART

V

QCS

= V

QILIM1

Flyback Overload Fault Timer

V

QCS

= V

t

100

QILIM1

QOVLD

COMMON FAULT PROTECTION

Overvoltage Protection (OVP)

Threshold

V

increasing

7

V

2.79

3.00

3.21

V

Fault

Fault(OVP)

Delay Before Fault Confirmation

Used for OVP Detection

Used for OTP Detection

ms

increasing

decreasing

t

22.5

30.0

37.5

Fault

delay(Fault_OVP)

delay(Fault_OTP)

V

Fault

Overtemperature Protection (OTP)

Threshold (Note 7)

V

decreasing

7

V

0.38

0.40

0.42

V

Fault

Fault(OTP_in)

Overtemperature Protection (OTP)

Exiting Threshold (Note 7)

V

increasing, B version

V

0.874

0.920

0.966

Fault

Fault(OTP_out)

OTP Pull−up Current Source (Note 7)

Fault Input Clamp Voltage

V

Fault

= V

+ 0.2 V

7

I

42.5

1.5

45.5

1.75

1.55

48.5

2.0

mA

V

Fault(OTP_in)

Fault(OTP)

Fault(clamp)

V

Fault

= open

V

R

Fault Input Clamp Series Resistor

1.32

1.82

kW

7. NTC with R

= 8.8 kW (TTC03-474)]

110

THERMAL PROTECTION

Thermal Shutdown

Temperature increasing

Temperature decreasing

N/A

T

−

150

40

−

°C

SHDN

Thermal Shutdown Hysteresis

T

SHDN(HYS)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

www.onsemi.com

11

NCL30030

DETAILED OPERATING DESCRIPTION

INTRODUCTION

must be considered to correctly size C . The increase in

CC

The NCL30030 is a combination critical mode (CrM)

power factor correction (PFC) and quasi−resonant (QR)

flyback controller optimized for high performance LED

driver applications.

current consumption due to external gate charge is

calculated using Equation 1.

(eq. 1)

I_{CC(gatecharge)}+ f @ Q_G

where f is the operating frequency and Q is the gate charge

of the external MOSFETs.

G

HIGH VOLTAGE STARTUP CIRCUIT

The NCL30030 integrates a high voltage startup circuit

accessible by the BO/HV pin. The BO/HV input is also used

for monitoring the ac line voltage and detecting brown−out

faults. The startup circuit is rated at a maximum voltage of

700 V to support higher voltages used in commercial

lighting such as 277 and 347 VAC.

LINE VOLTAGE SENSE

The BO/HV pin provides access to the brown−out and line

voltage detectors. The brown−out detector detects mains

interruptions and the line voltage detector determines the

presence of either 120 V or 230 V ac mains. Depending on

the detected input voltage range device parameters are

internally adjusted to optimize the system performance.

This pin can connect after the rectifier bridge to achieve

full wave rectification as shown in Figure 3. A diode is used

to prevent the pin from going below ground. A low value

resistor in series with the BO/HV pin can be used for

protection. A low value resistor is needed to reduce the

voltage offset while sensing the line voltage.

A startup regulator consists of a constant current source

that supplies current from the ac input terminals (V ) to the

in

supply capacitor on the V pin (C ). The startup circuit

CC

current (I

) is typically 3.75 mA. I

is disabled if

start2A

the VCC pin is below V

startup current is reduced to I

. In this condition the

, typically 0.5 mA. The

CC(inhibit)

start1A

internal high voltage startup circuit eliminates the need for

external startup components. In addition, the startup

regulator helps increase the system efficiency as it uses

negligible power in the normal operation mode.

Once C is charged to the startup threshold, V

typically 17 V, the startup regulator is disabled and the

controller is enabled. The startup regulator will remain

,

CC

CC(on)

EMI

Filter

AC

Input

disabled until V

falls below the minimum operating

CC

voltage threshold, V , typically 8.8 V. Once reached,

CC(off)

the PFC and flyback controllers are disabled reducing the

bias current consumption of the IC. The startup circuit is

BO/HV

then are then enabled allowing V to charge back up.

CC

NCL30030

A dedicated comparator monitors V when the QR stage

CC

is enabled and latches off the controller if V exceeds

CC

V

, typically 28 V.

The controller is disabled once a fault is detected. The

CC(OVP)

Figure 3. Brown−out and Line Voltage Detectors

Configuration

controller will restart the next time V reaches V

and

CC

CC(on)

all non−latching faults have been removed.

The supply capacitor provides power to the controller

during power up. The capacitor must be sized such that a

The flyback stage is enabled once V

is above the

BO/HV

brown−out threshold, V

, typically 111 V, and V

BO(start)

CC

reaches V . The high voltage startup is immediately

CC(on)

V

CC

voltage greater than V

is maintained while the

CC(off)

enabled when the voltage on V

crosses over the

BO/HV

auxiliary supply voltage is building up. Otherwise, V will

collapse and the controller will turn off. The operating IC

CC

brown−out start threshold, V

to ensure that device is

BO(start),

enabled quickly upon exiting a brown−out state. Figure 4

shows typical power up waveforms.

bias current, I , and gate charge load at the drive outputs

CC4

www.onsemi.com

12

NCL30030

Figure 4. Startup Timing Diagram

www.onsemi.com

13

NCL30030

A timer is enabled once V

drops below its stop

reduced by a factor of 3, resulting in a maximum output

BO/HV

threshold, V

, typically 101 V. If the timer, t

,

power independent of input voltage.

BO(stop)

BO

expires the device will begin monitoring the voltage on

and disable the PFC and flyback stages when that

The default power−up mode of the controller is low line.

V

The controller switches to “high line” mode if V

BO/HV

voltage is below the Brown−out Drive Disable threshold,

typically 30 V. This ensures that device

exceeds the line select threshold for longer than the low to

high line timer, t , typically 300 ms, as long as

V

BO(DRV_disable),

(low to high line)

switching is stopped in a low energy state which minimizes

inductive voltage kick from the EMI components and ac

it was not previously in high line mode. If the controller has

switched from “high line” to “low line” mode, the low to

mains. The timer, t , typically 54 ms, is set long enough to

high line timer, t , is inhibited until V

(low to high line) BO/HV

BO

ignore a single cycle drop−out.

falls below V . This prevents the controller from

BO(stop)

toggling back to “high line” until at least one V

BO(stop)

LINE VOLTAGE DETECTOR

transition has occurred. The timer and logic is included to

prevent unwanted noise from toggling the operating line

level.

The input voltage range is detected based on the peak

voltage measured at the BO/HV pin. Discrete values are

selected for the PFC stage gain (feedforward) depending on

the input voltage range. The controller compares V

an internal line select threshold, V

In “high line” mode the high to low line timer, t

(high to low

to

BO/HV

, (typically 54 ms) is enabled once V

falls below

line)

BO/HV

, typically

, the PFC stage

BO(lineselect)

V

.

It is reset once

V

exceeds

BO(lineselect)

BO/HV

240 V. Once V

exceeds V

BO/HV

BO(lineselect)

. The controller switches back to “low line”

BO(lineselect)

operates in “high line” (Commercial US − 277 Vac) or

“230 Vac” mode. In high line mode the maximum on time is

mode if the high to low line timer expires.

Figure 5. Line Detector Waveforms

www.onsemi.com

14

NCL30030

FAULT INPUT

the upper threshold, the external pull−up current has to be

higher than the pull−down capability of the clamp (set by

The NCL30030 includes a dedicated fault input

accessible via the Fault pin. The controller will enter triple

hiccup mode when the pin is pulled above the upper fault

R

at V ). The upper fault threshold is

Fault(clamp)

intended to be used for an overvoltage fault using a Zener

diode and a resistor in series from the auxiliary winding

threshold, V

, typically 3.0 V. The controller is

Fault(OVP)

disabled if the Fault pin voltage, V

, is pulled below the

voltage, V

. The controller goes into a triple hiccup once

Fault

AUX

lower fault threshold, V

, typically 0.4 V. The

Fault(OTP_in)

V

Fault

exceeds V

.

Fault(OVP)

lower threshold is normally used for detecting an

overtemperature fault. The controller operates normally

while the Fault pin voltage is maintained within the upper

and lower fault thresholds. Figure 6 shows the architecture

of the Fault input.

The Fault input signal is filtered to prevent noise from

triggering the fault detectors. Upper and lower fault detector

blanking delays, t and t are

both typically 30 ms. A fault is detected if the fault condition

is asserted for a period longer than the blanking delay.

A bypass capacitor is usually connected between the Fault

delay(Fault_OVP)

delay(Fault_OTP)

The lower fault threshold is intended to be used to detect

an overtemperature fault using an NTC thermistor. A pull up

and GND pins and it will take some time for V

to reach

Fault

current source I

, (typically 45.5 mA) generates a

its steady state value once I

is enabled. Therefore,

Fault(OTP)

voltage drop across the thermistor. The resistance of the

NTC thermistor decreases at higher temperatures resulting

in a lower voltage across the thermistor. The controller

detects a fault once the thermistor voltage drops below

a lower fault (i.e. overtemperature) is ignored during

soft−start. In Option B, I remains enabled while

Fault(OTP)

the lower fault is present independent of V in order to

CC

provide temperature hysteresis. The upper OVP fault

detection is enabled and remains active as long as the QR

flyback is enabled.

V . Part option A latches off the controller after

Fault(OTP_in)

an overtemperature fault is detected. For part option B the

controller is re−enabled once the fault is removed such that

Once the controller is latched, it is reset if a brown−out

V

increases above V

and V

reaches

condition is detected or if V is cycled down to its reset

Fault

Fault(OTP_out)

CC

. Figure 7 shows typical waveforms related to the

level, V

. In the typical application these conditions

CC(on)

CC(reset)

latch option where as Figure 8 shows waveforms of the

auto−recovery option.

occur only if the ac voltage is removed from the system.

Prior to reaching V

V

is set at 0 V.

CC(reset), fault(clamp)

An active clamp prevents the Fault pin voltage from

reaching the upper latch threshold if the pin is open. To reach

VAUX

Blanking

+

−

S

R

Q

Triple Hiccup

t

delay(Fault_OTP)

V

DD

V

Fault(OVP)

I

Fault(OTP)

Fault

−

+

Blanking

S

Q

Latch

V

t

fault(OTP)

delay(Fault_OTP)

R

NTC

Thermistor

Fault(clamp)

Soft−start

end

R

Option

V

Fault(clamp)

Hysteresis

Control

Auto−restart

Control

Auto−restart

Figure 6. Fault Detection Schematic

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15

NCL30030

Figure 7. Latch−off Function Timing Diagram

Figure 8. OTP Auto−Recovery Timing Diagram

QR FLYBACK VALLEY LOCKOUT

reduce switching losses and electromagnetic interference

(EMI).

The NCL30030 integrates a quasi−resonant (QR) flyback

controller. The power switch turn−off of the QR converter

is determined by the peak current set by the feedback loop.

The switch turn−on is determined by the transformer

demagnetization. The demagnetization is detected by

monitoring the transformer auxiliary winding voltage.

Turning on the power switch once the transformer is

demagnetized or reset reduces switching losses. Once the

transformer is demagnetized, the drain voltage starts ringing

at a frequency determined by the transformer magnetizing

inductance and the drain lump capacitance eventually

settling at the input voltage. A QR controller takes

advantage of the drain voltage ringing and turns on the

power switch at the drain voltage minimum or “valley” to

The operating frequency of a traditional QR flyback

controller is inversely proportional to the system load. That

is, a load reduction increases the operating frequency. This

traditionally requires a maximum frequency clamp to limit

the operating frequency. This causes the controller to

become unstable and jump (or hesitate) between two valleys

generating audible noise. The NCL30030 incorporates a

patent pending valley lockout circuitry to eliminate valley

jumping. Once a valley is selected, the controller stays

locked in this valley until the output power changes

significantly. Like a traditional QR flyback controller, the

frequency increases when the load decreases. Once a higher

valley is selected the frequency decreases very rapidly. It

www.onsemi.com

16

NCL30030

will continue to increase if the load is further reduced. This

or increases, the valley comparators toggle one after another

to select the proper valley. The activation of an “n” valley

comparator blanks the “n−1” or “n+1” valley comparator

technique extends QR operation over a wider output power

range while maintaining good efficiency and limiting the

maximum operating frequency. Figure 9 shows a qualitative

frequency vs output power relationship.

output depending if

respectively.

V

decreases or increases,

QFB

Figure 10 shows the internal arrangement of the valley

detection circuitry. An internal counter increments each

A valley is detected once V

flyback demagnetization threshold, V

55 mV. The controller will switch once the valley is detected

or increment the valley counter depending on QFB voltage.

falls below the QR

QZCD

, typically

QZCD(th)

st nd rd

time a valley is detected. The operating valley (1 , 2 , 3

th

or 4 ) is determined by the QFB voltage. As V

decreases

QFB

Figure 9. Valley Lockout Frequency vs Output Power Relationship

V

DD

I

QFB

R

QFB

Minimum

Frequency

Oscillator

V

DD

CT

Setpoint

QDRV

(internal)

QR Logic

S

Q

I

QCT

Dominant

Reset

QCT

Latch

Q

R

QCT

Discharge

QDRV

(internal)

demag

Timeout

QZCD

QZCD Comparator

R

OPPU

+

V

QZCD(th)

−

R

QCZD

Blanking

(t

QDRV

(internal)

)

blank

L

AUX

Figure 10. Valley Detection Circuitry

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17

NCL30030

Figure 11 shows the operating valley versus V

. Once

QFB

V

QFB

falls below V

. In VCO mode the peak current

HVCOD

a valley is asserted by the valley selection circuitry, the

controller is locked in this valley until V decreases or

is set to V

*KI

as shown in Figure 12. The

QILIM1

peak(VCO)

operating frequency in VCO mode is adjusted to deliver to

required output power.

QFB

increases such that V

reaches the next valley threshold.

QFB

A decrease in output power causes the controller to switch

from “n” to “n+1” valley until reaching the 4 valley.

A hysteresis between valleys provides noise immunity

and helps stabilize the valley selection in case of small

th

A further reduction of output power causes the controller

to enter the voltage control oscillator (VCO) mode once

perturbations on V

.

QFB

Valley

VCO

4th

3rd

2nd

1st

V_QFB

V_H2D

V_HVCOI

V_HVCODV_H4D

V_H3D

V_H4I

V_H3I

V_H2I

V_QILIM1*K_QFB

Figure 11. Selected Operating Valley versus V_QFB

Peak current

Setpoint

VCO

Skip

Mode

QR Mode

V_QILIM1

1st Valley

2nd

3rd

Fault

4th

I_peak(VCO)*V_QILIM1

V_QFB

V_QFB(TH)

V_QSKIPV_HVCODV_H4D

V_H3D

V_H2D

V_QILIM1*K_QFB

Figure 12. Operating Valley versus V_QFB

Figures 13 through 16 show drain voltage, V

and

valley to VCO mode are observed without any instabilities

or valley jumping.

QFB

V

simulation waveforms for a reduction in output

QCT

nd

rd rd

th

power. The transitions between 2 to 3 , 3 to 4 and 4

www.onsemi.com

18

NCL30030

Zoom 2

700

500

300

100

−100

Zoom 1

Zoom 3

V_drain

1

2.00

1.60

1.20

800m

400m

V_QFB

2

7.00

5.00

3.00

1.00

−1.00

V_QCT

3.64m

4.91m

6.18m

7.45m

8.72m

time in seconds

Figure 13. Operating Mode Transitions Between 2^ndto 3^rd, 3^rdto 4^thand 4^thValley to VCO Mode

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19

NCL30030

vdrain

feedback

vct

vdrain

feedback

vct

1

2

3

1

2

3

700

500

700

500

V_drain

1

300

1

2

100

−100

2.15

2.05

1.95

1.85

1.75

1.38

1.34

1.30

1.26

1.22

V_QFB

2

V_QFB

V_QCT

6.00

4.00

2.00

0

4.00

3.00

2.00

1.00

0

V_QCT

−2.00

3.70m

3.78m

3.86m

time in seconds

3.94m

4.02m

5.90m

5.95m

6.00m

time in seconds

6.05m

6.11m

Figure 14. Zoom 1: 2^ndto 3^rdValley

Transition

Figure 15. Zoom 2: 3^rdto 4^thValley

Transition

vdrain

feedback

vct

1

2

3

700

500

V_drain

300

1

100

−100

1.12

1.02

2

919m

819m

719m

V_QFB

8.00

6.00

4.00

2.00

0

V_QCT

7.10m

7.21m

7.32m

time in seconds

7.43m

7.55m

Figure 16. Zoom 3: 4^thValley to VCO Mode

Transition

VCO MODE

capacitor is charged with a constant current source, I

,

QCT

The controller enters VCO mode once V

falls below

typically 20 mA.

QFB

V

HVCOD

and remains in VCO until V

exceeds V

.

The capacitor voltage, V

, is compared to an internal

QCT

QFB

HVCOI

In VCO mode the peak current is set to V

*I

voltage level, V

, inversely proportional to V

The

QILIM1 peak(VCO)

f(QFB)

QFB

and the operating frequency is linearly dependent on V

.

relationship between and V

Equation 2).

and V

is given by

QFB

f(QFB)

QFB

The product of V

*I

is typically 12.5%. A

QILIM1 peak(VCO)

minimum frequency clamp, f

, typically 27 kHz,

VCO(MIN)

V_f(QFB)+ 5 * 2 @ V_QFB

(eq. 2)

prevents operation in the audible range. Further reduction in

output power causes the controller to enter skip operation.

The minimum frequency clamp is only enabled when

operating in VCO mode.

The VCO mode operating frequency is set by the timing

capacitor connected between the QCT and GND pins. This

A drive pulse is generated once V

exceeds V

f(QFB)

QCT

followed by the immediate discharge of the timing capacitor.

The timing capacitor is also discharged once the minimum

frequency clamp is reached. Figure 17 shows simulation

waveforms of V

, V

and output current while

f(QFB)

QDRV

operating in VCO mode.

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20

NCL30030

800m

600m

400m

200m

0

I_OUT

1

7.00

5.00

3.00

1.00

−1.00

V_QCT

3

2

V_f(QFB)

30.0

20.0

10.0

0

V_QDRV

−10.0

7.57m

7.78m

7.99m

8.20m

8.40m

time in seconds

Figure 17. VCO Mode Operating Waveforms

FLYBACK TIMEOUT

During startup, the voltage offset added by the overpower

In case of extremely damped oscillations, the QZCD

comparator may be unable to detect the valleys. In this

condition, drive pulses will stop waiting for the next valley

or ZCD event. The NCL30030 ensures continued operation

by incorporating a maximum timeout period after the last

demagnetization detection. The timeout signal is a substitute

for the ZCD signal for the valley counter. Figure 18 shows

the timeout period generator circuit schematic. The steady

compensation diode, D , prevents the QZCD Comparator

OPP

from accurately detecting the valleys. In this condition, the

steady state timeout period will be shorter than the inductor

demagnetization period causing continuous current mode

(CCM) operation. CCM operation lasts for a few cycles until

the voltage on the QZCD pin is high enough to detect the

valleys. A longer timeout period, t , (typically 100 ms)

Q(tout1)

is set during soft−start to limit CCM operation. Figures 19

and 20 show the timeout period generator related

waveforms.

state timeout period, t , is set at 6 ms to limit the

Q(tout2)

frequency step.

QZCD Comparator

+

QZCD

demag

D

OPP

R

OPPU

V

QZCD(th)

QR Logic

−

R

QCZD

Minimum

Frequency

Oscillator

Timeout

Blanking

QDRV

(internal)

L

AUX

t

ZCD(blank)

Steady

State

Timeout

(t

Soft−start

Complete

(internal)

)

out2

R

Soft−Start

Timeout

(t

out1

)

R

Figure 18. Timeout Period Generator Circuit Schematic

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21

NCL30030

V_QZCD

V_QZCD(th)

3

4

The 3rd valley is

validated

high

low

14

12

2^nd, 3^rd

^ndvalley is detected

The 2

The 3rd valley is not detected

by the QZCD Comparator

QZCD

Comparator

¹⁵Output

high

low

high

Timeout

low

16

Timeout adds a pulse to account for

the missing 3^rdvalley

high

low

Clk

17

Figure 19. Timeout Operation With a Missing 3^rdValley

V_QZCD

V_QZCD(th)

3

4

The 4^thvalley is

validated

high

low

3^rd, 4^th

18

14

high

QZCD

Comparator

¹⁵Output

low

high

Timeout

16

low

Timeout adds 2 pulses to account

^thvalleys

for the missing 3^rdand 4

high

low

Clk

17

Figure 20. Timeout Operation With Missing 3^rdand 4^thValleys

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22

NCL30030

QR FLYBACK CURRENT SENSE AND OVERLOAD

The Maximum Peak Current Comparator compares the

current sense signal to a reference voltage to limit the

maximum peak current of the system. The maximum peak

The power switch on time is modulated by comparing a

ramp proportional to the switch current to V /K using

QFB QFB

the PWM Comparator. The switch current is sensed across

a current sense resistor, R and the resulting voltage is

applied to the QCS pin. The current signal is blanked by a

leading edge blanking (LEB) circuit. The blanking period

eliminates the leading edge spike and high frequency noise

during the switch turn−on event. The LEB period,

current reference voltage, V

, is typically 0.8 V. The

QILIM1

maximum peak current setpoint is reduced by the overpower

compensation circuitry. An overload condition causes the

output of the Maximum Peak Current Comparator to

transition high and enable the overload timer. Figure 21

shows the implementation of the current sensing circuitry.

SENSE,

t

, is typically 275 ns. The drive pulse terminates

QCS(LEB1)

once the current sense signal exceeds V

/K

.

QFB QFB

V

DD

V

QFB

I

R

QFB

Skip

QFB

+

−

V

QSKIP

I

=

peak(VCO)

K

V

QCS(VCO)

QZCD

PWM

Comparator

/K

QFB

+

Overload Timer

Peak Current

Comparator

t

QOVLD

LEB

Count Down

Count Up

t

QCS(LEB1)

+

−

V

DD

V

QILIM1

Disable QDRV

V

QZCD

Short−Circuit

Comparator

QCS

LEB

t

Counter

nQILIM2

QCS(LEB2)

+

V

−

QILIM2

Figure 21. Current Sensing Circuitry Schematic

The overload timer integrates the duration of the overload

fault. That is, the timer count increases while the fault is

present and reduces its count once it is removed. The

and the overload timer counts down. The controller can latch

(option A) or allow for auto−recovery (option B) once the

overload timer expires. Auto−recovery requires a V triple

CC

overload timer duration, t

the PWM and Maximum Peak Current Comparators toggle

at the same time, the PWM Comparator takes precedence

, is typically 80 ms. If both

hiccup before the controller restarts. Figures 22 and 23

show operating waveforms for latched and auto−recovery

overload conditions.

QOVLD

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23

NCL30030

Figure 22. Latched Overload Operation

Figure 23. Auto−Recovery Overload Operation

A severe overload fault like a secondary side winding

short−circuit causes the switch current to increase very

rapidly during the on−time. The current sense signal

The NCL30030 protects against this fault by adding an

additional comparator, Fault Overcurrent Comparator. The

current sense signal is blanked with a shorter LEB duration,

significantly exceeds V . But, because the current

QILIM1

t , typically 120 ns, before applying it to the Fault

QCS(LEB2)

sense signal is blanked by the LEB circuit during the switch

turn on, the system current can get extremely high causing

system damage.

Overcurrent Comparator. The voltage threshold of the

comparator, V , typically 1.2 V, is set 50% higher than

QILIM2

V , to avoid interference with normal operation. Four

QILIM1

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24

NCL30030

consecutive faults detected by the Fault Overcurrent

overtemperature) is blanked. Soft−start ends once V

exceeds the peak current sense signal threshold.

SSTART

Comparator causes the controller to enter triple−hiccup

auto−recovery mode. The count to 4 provides noise

immunity during surge testing. The counter is reset each

time a QDRV pulse occurs without activating the Fault

Overcurrent Comparator. A 1 mA (typically) pull−up current

QR FLYBACK OVERPOWER COMPENSATION

The input voltage of the QR flyback stage varies with the

line voltage and operating mode of the PFC converter. At

low line the PFC bulk voltage is 220 V and at high line it will

be 390 V or 440 V, depending on the version of the part.

Additionally, the PFC can be disabled at which point the

PFC bulk voltage is set by the rectified peak line voltage.

An integrated overpower circuit provides a relative

source, I , pulls up the QCS pin to disable the controller

QCS

if the pin is left open.

QR FLYBACK SOFT−START

Soft−start is achieved by ramping up an internal reference,

V

SSTART

, and comparing it to current sense signal. V

constant output power across PFC bulk voltage, V . It

SSTART

bulk

ramps up from 0 V once the controller powers up. The

soft−start duration, t , is typically 4 ms.

During soft−start the timeout duration is extended and the

lower latch or OTP Comparator signal (typically for

also reduces the variation on V

enable or disable transitions. Figure 24 shows the circuit

schematic for the overpower detector.

during the PFC stage

QFB

SSTART

QZCD

D

R

OPPU

QZCD Comparator

OPP

+

V

QZCD(th)

−

R

OPPL

R

QCZD

Peak Current

Comparator

+

QFB

L

AUX

/4

+

V

QILIM1

−

Disable

QDRV

+

QCS(VCO)

Other Faults

+

K

PWM

Comparator

−

QCS

LEB

t

QCS(LEB1)

Figure 24. Overpower Compensation Circuit Schematic

The auxiliary winding voltage during the power switch on

time is a reflection of the input voltage scaled by the primary

The voltage is scaled down using R

negative voltage applied to the pin is referred to as V

and R

. The

OPPL

OPPU

.

OPP

to auxiliary winding turns ratio, N , as shown in

P,AUX

Figure 25.

The internal current setpoint is the sum of V

and peak

OPP

current sense threshold, V

. V

is also subtracted

QILIM1

OPP

from V

to compensate for the PWM Comparator delay

QFB

and improve the PFC on/off accuracy.

The current setpoint is calculated using Equation 3. For

example, a V

0.65 V.

of −0.15 V results in a current setpoint of

OPP

Current setpoint + V_QILIM1) V_OPP

(eq. 3)

To ensure optimal zero−crossing detection, a diode is

needed to bypass R

used to calculate R

during the off−time. Equation 4 is

OPPU

and R

.

OPPL

N_P,AUX@ V_bulk* V_OPP

R_QZCD) R_OPPU

(eq. 4)

+ *

R_OPPL

V_OPP

Figure 25. Auxiliary Winding Voltage Waveform

R

OPPU

is selected once a value is chosen for R

.

OPPL

R

is selected large enough such that enough voltage is

OPPL

Overpower compensation is achieved by scaling down the

on−time reflected voltage and applying it to the QZCD pin.

available for the zero crossing detection during the off−time.

www.onsemi.com

25

NCL30030

It is recommended to have at least 8 V applied on the QZCD

pin for good detection. The maximum voltage is internally

at the end of each switch cycle. Figure 26 shows the PFC

inductor current while operating in CrM. High power factor

and low harmonic distortion is achieved by shaping the input

clamped to V . The off−time voltage on the QZCD is given

CC

by Equation 5.

current, I (t), such that it is sinusoidal and in phase with the

in

ac line voltage, V (t).

in

R_OPPL

ǒ Ǔ

@ V_AUX* V_F

(eq. 5)

V_QZCD+ *

R_OZCD) R_OPPL

Where V

is the voltage across the auxiliary winding and

AUX

V is the D

forward voltage drop.

F

OPP

The ratio between R

and R

is given by

QZCD

OPPL

Equation 6. It is obtained combining Equations 4 and 5.

V_AUX* V_F* V_QZCD

R_OZCD

(eq. 6)

+

R_OPPL

V_QZCD

A design example is shown below:

System Parameters:

V

AUX

= 18 V

V = 0.6 V

F

Figure 26. Inductor Current in CrM

N

P,AUX

= 0.18

To achieve unity power factor and low harmonic

distortion the NCL30030 uses a peak current mode control

architecture where the cycle−by−cycle current limit is set by

a multiplier circuit. A block diagram of the control

architecture is shown in Figure 27. The control works by

generating a DC current proportional to the instantaneous

AC line voltage and multiplying that current with the error

voltage generated from the feedback error amplifier.

The multiplication factor is determined by the output of a

comparator which measures the error voltage against a high

frequency ramping signal. As the error voltage approaches

its maximum value, the multiplication factor approaches 1.

The output of the comparator toggles a switch to modulate

the DC current from the current generator. The modulated

current then feeds a resistor to set the peak current limit and

hence control the duty cycle for every switching period. An

external capacitor on the MULT pin is used to filter ripple

caused by the modulation.

The ratio between R

Equation 6 for a minimum V

and R

is calculated using

of 8 V.

QZCD

OPPL

QZCD

R_OZCD

18 * 0.6 * 8

+

[ 1.2

8

R_OPPL

R

QZCD

is arbitrarily set to 1 kW. R

is also set to 1 kW

OPPL

because the ratio between the resistors is close to 1.

The NCL30030 maximum overpower compensation or

peak current setpoint reduction is 31.25% for a V

−250 mV. We will use this value for the following example:

Substituting values in Equation 4 and solving for R

we obtain,

of

OPP

OPPU

R_QZCD) R_OPPU

0.18 @ 370 * (−0.25)

+ *

+ 271

R_OPPL

(−0.25)

R_OPPU+ 271 @ R_OPPL* R_QZCD

R_OPPU+ 271 @ 1k * 1k + 270k

This control architecture is effectively a dual loop control

method where the current generator shapes the peak current

setpoint such that it follows the AC input while the error

voltage adjusts the peak current to ensure that bulk voltage

regulation is maintained.

POWER FACTOR CORRECTION

The PFC stage operates in critical conduction mode

(CrM). In CrM the PFC inductor current, I (t), reaches zero

L

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26

NCL30030

BO/HV

Low/High Line

V

bulk

I

MULT

Ramp

Signal

Error

Amplier

R1

PFB

MULT

R2

+

−

Multiplier

Comparator

V

PREF

PWM

Comparator

PControl

PCS/PZCD

Reset PDRV

LEB1

Figure 27. Multiplier Block Diagram

PFC FEEDBACK

has a typical g of 200 mS. The PControl pin provides access

m

The PFC feedback circuitry is shown in Figure 28. A

resistor divider consisting of R1 and R2 scales down the PFC

to the amplifier output for compensation. The compensation

network is ground referenced allowing the PFC feedback

signal to detect undervoltage and overvoltage conditions as

shown in Figure 28.

The compensation network on the PControl pin is selected

to filter the bulk voltage ripple such that a constant control

voltage is maintained across the ac line cycle. A capacitor

between the PControl pin and ground sets a pole. A pole at

or below 20 Hz is enough to filter the ripple voltage for a 50

output voltage, V

to generate a PFC feedback signal.

bulk,

The feedback signal is applied to the inverting input of a

transconductance error amplifier which regulates V by

bulk

comparing the PFC feedback signal to an internal reference

voltage, V . The reference is connected to the

PREF

non−inverting input of the error amplifier and is trimmed

during manufacturing to achieve an accuracy of 2% across

temperature.

and 60 Hz system. The low frequency pole, f , of the system

p

is calculated using Equation 7.

gm

PFC OVP

POVP

(eq. 7)

f_p+

Circuitry

2pC_PControl

V

bulk

PFC UVP

where, C

ground.

is the capacitor on the PControl pin to

PControl

R1

Comparator

PFB

PUVP

The output of the error amplifier is held low when the PFC

is disabled by means of an internal pull−down transistor. The

pull down transistor is disabled once the PFC stage is

enabled. An internal voltage clamp is then enabled to

R2

+

V

PFB(disable)

Error

−

V

BOHV

PWM

Amplier

Multiplier

Comparator

quickly raise

V

to its minimum voltage,

PControl

PDRV Reset

+

V

, typically 0.6 V.

PControl(min)

V

PREF

V

−

PCS

PFC TRANSIENT RESPONSE

V

DD

The PFC bandwidth is set low enough to achieve good

power factor. However, a low bandwidth system is slow and

fast load transients can result in large output voltage

excursions. The NCL30030 incorporates dedicated circuitry

to help maintain regulation of the output voltage

independent of load transients.

V

PControl(MAX)

PControl

V

Disable PFC

PUVP

PControl(MIN)

An undervoltage detector monitors the ratio between

Figure 28. PFC Regulation Circuit Schematic

V

and V

. Once the ratio between V

and

PFB

PREF(xL)

PFB

exceeds K

, typically 5.5%, a pull−up

PREF(xL)

LOW(PFCxL)

current source on the PControl pin, I , is enabled

PControl(boost)

PFC ERROR AMPLIFIER

to speed up the charge of the compensation network. This

results in an increased on−time and thus output power.

A transconductance amplifier has a voltage−to−current

gain, g . That is, the amplifier’s output current is controlled

m

I

is typically 240 mA. The boost current source

by the differential input voltage. The NCL30030 amplifier

PControl(boost)

www.onsemi.com

27

NCL30030

is disabled once the ratio between V

and V

drops

V

(V

exceeds the

*K ) Soft−OVP reduces the on−time

POVP(xL) .

hard−OVP

level,

V

PFB

PREF(xL)

PFB

POVP

below K

, typically 4%.

LOW(PFCxL)

PREF(xL)

The boost current source becomes active as soon as the

PFC is enabled. Coupled with the lower control clamp, the

proportional to the delta between V

level. Soft−OVP is enabled once the delta, D

and the hard−OVP

PFB

,

POVP(xL)

boost current source assists in rapidly bringing V

to

between V

and the hard−OVP level is between 20 and 55

PControl

PFB

its set point to allow the bulk voltage to quickly reach

regulation. Achieving regulation is detected by monitoring

the error amplifier output current. The error amplifier output

current drops to zero once the PFC output voltage reaches

the target regulation level.

The maximum PFC output voltage is limited by the

overvoltage protection circuitry. The NCL30030

incorporates both soft and hard overvoltage protection. The

hard overvoltage protection function immediately

terminates and prevents further PFC drive pulses when

mV. Figure 29 shows a block diagram of the boost and

Soft−OVP circuits.

During power up, V

exceeds the regulation level

PControl

due to the system’s inherently low bandwidth. This causes

the bulk voltage to rapidly increase and exceed its

regulation. The on time starts to decrease when soft−OVP is

activated. Once the bulk voltage decreases to its regulation

level the PFC on time is no longer controlled by the

soft−OVP circuitry.

On−Time

Comparator

PDRV

RAMP

Generator

Low/High Line

Fixed

Reference

R

Q

PDRV

Dominant

PCS/PZCD

MULT

Reset

LEB1

Latch

Q

S

PWM

Comparator

V

DD

V

BOHV

V

POVP

A

Soft OVP

V

PControl(MAX)

PControl

Comparator

V

PControl(MIN)

Boost

Comparator

MULTIPLIER

V

DD

+

₋V * K

Error

Amplier

LOW

I

PControl(boost)

PFB

+

−

V

PREF

Regulation

Detector

Regulation OK

Figure 29. Boost and Soft−OVP Circuit Schematics

PFC CURRENT SENSE AND ZERO CURRENT

DETECTION

The NCL30030 uses a novel architecture combining the

PFC current sense and zero current detectors (ZCD) in a

single input terminal. Figure 30 shows the circuit schematic

of the current sense and ZCD detectors.

www.onsemi.com

28

NCL30030

t

Timer

PFC(off)

PDRV

Reset

PILIM2

Q

S

R

+

−

PFC Boost

Diode

V

PZCD(rising)

PFC Inductor

PFC Switch

PDRV

t

To PDRV Set

PZCD_Blank

R

Psense

PDRV

D

R

Q

R

PCS

CLK

R

+

−

PZCD

PDRV

PCS/PZCD

V

PZCD(falling)

Current Limit

Comparator

LEB1

t

PCS(LEB1)

PILIM1

+

PDRV

V

PILIM1

−

Short Circuit

Comparator

PDRV

LEB2

PILIM2

PCS(LEB2)

+

−

V

PILIM2

Figure 30. PFC Current Sense and ZCD Detectors Schematic

PFC CURRENT SENSE

comparator, V

, typically 2 V, is set 33% higher than

PILIM2

The PFC Switch current is sensed across a sense resistor,

V

PILIM1

, to avoid interference with normal operation.

R

, and the resulting voltage ramp is applied to the

Whenever a fault is detected by the Short Circuit

Comparator, the watchdog timer increases to 1 ms allowing

the system time to recover from the excessive over current.

The next PFC drive pulse is then initiated when the

watchdog timer expires.

Psense

PCS/PZCD pin. The current signal is blanked by a leading

edge blanking (LEB) circuit. The blanking period eliminates

the leading edge spike and high frequency noise during the

switch turn−on event. The LEB period, t

, is

PCS(LEB1)

typically 325 ns. The Current Limit Comparator disables the

PFC driver once the current sense signal exceeds the PFC

PFC ZERO CURRENT DETECTION

The off−time in a CrM PFC topology varies with the

instantaneous line voltage and is adjusted every switching

cycle to allow the inductor current to reach zero before the

next switching cycle begins. The inductor is demagnetized

once its current reaches zero. Once the inductor is

demagnetized the drain voltage of the PFC switch begins to

drop. The inductor demagnetization is detected by sensing

the voltage across the inductor using an auxiliary winding.

This winding is commonly known as a zero crossing

detector (ZCD) winding. This winding provides a scaled

version of the inductor voltage. Figure 31 shows the ZCD

winding arrangement.

current sense reference, V

, typically 1.5 V.

PILIM1

A severe overload fault like a PFC boost diode short

circuit causes the switch current to increase very rapidly

during the on−time. The current sense signal significantly

exceeds V

. But, because the current sense signal is

PILIM1

blanked by the LEB circuit during the switch turn on, the

system current can get extremely high causing system

damage.

The NCL30030 protects against this fault by adding an

additional comparator, PFC Short Circuit Comparator. The

current sense signal is blanked with a shorter LEB duration,

t , typically 175 ns, before applying it to the PFC

PCS(LEB2)

Short Circuit Comparator. The voltage threshold of the

www.onsemi.com

29

NCL30030

PFC Inductor

During startup there are no ZCD transitions to set the PFC

PWM Latch and generate a PDRV pulse. A watchdog timer,

, starts the drive pulses in the absence of ZCD

transitions. Its duration is typically 200 ms. The timer is also

useful if the line voltage transitions from low line to high line

and while operating at light load because the amplitude of

the ZCD signal may be too small to cross the ZCD arming

threshold. The watchdog timer is reset at the beginning of a

PFC drive pulse. It is disabled during a PFC hard

overvoltage and feedback input short circuit condition.

PFC Switch

Rectied

ac line

voltage

PFC

output

voltage

t

PFC(off1)

PDRV

R

Psense

R

PCS

R

PZCD

PCS/PZCD

PFC ENABLE & DISABLE

Figure 31. ZCD Winding Implementation

In some applications it is desired to disable the PFC at

lighter loads to increase the overall system efficiency. The

NCL30030 integrates a novel architecture that allows the

user to program the PFC disable threshold based on the

percentage of QR output power. The PFC enable circuitry is

inactive until the QR flyback soft start period has ended. A

voltage to current (V−I) converter generates a current

The ZCD voltage, V

is off and current flows through the PFC inductor. V

, is positive while the PFC Switch

ZCD

drops to and rings around zero volts once the inductor is

demagnetized. The next switching cycle begins once a

negative transition is detected on the PCS/PZCD pin. A

positive transition (corresponding to the PFC switch turn

off) arms the ZCD detector to prevent false triggering. The

proportional to V . This current is pulse width modulated

QFB

by the demagnetization time of the flyback controller to

generate a current, I , proportional to the output

arming of the ZCD detector, V

0.75 V. The trigger threshold, V

, is typically

PZCD(rising)

PONOFF

PZCD(falling)

power. An external resistor, R , between the

PONOFF

0.25 V. The NCL30030 also incorporates a blanking period,

which prevents detection of a ZCD event for

PONOFF and GND pins is used to scale the output power

signal. A capacitor, C , in parallel with R is

T

PZCD_Blank

PONOFF

700 ns after the PFC switch turn off.

required to average the signal on this pin. A good

compromise between voltage ripple and speed is achieved

The PCS/PZCD pin is internally clamped to 5 V with a

Zener diode and a 2 kW resistor. A resistor in series with the

PCS/PZCD pin is required to limit the current into pin. The

Zener diode also prevents the voltage from going below

ground. Figure 32 shows typical ZCD waveforms.

by setting the time constant of C

and R

to

PONOFF

160 ms.

The PONOFF pin voltage, V

, is compared to an

PONOFF

internal reference, V

(typically 2 V) to disable the PFC

POFF

stage. In high power SSL applications it is often desired to

control the PFC disable point from the secondary side. An

optocoupler can be used as a logic disable to ground the

PONOFF pin when the PFC needs to be disabled.

Once V

decreases below V , the PFC disable

POFF

PONOFF

timer, t

, is enabled. The PFC disable timer is typically

Pdisable

500 ms. The PFC stage is disabled once the timer expires.

The PFC stage is enabled once V exceeds V by

PONOFF

POFF

V

for a period longer than the PFC enable filter,

PONHYS

t

, typically 100 ms. A shorter delay for the PFC

Penable(filter)

Figure 32. ZCD Winding Waveforms

enable threshold is used to reduce the bulk capacitor

requirements during a step load response. Figure 33 shows

the block diagram of the PFC disable circuit.

www.onsemi.com

30

NCL30030

QFB

V to I

Converter

PFC Disable

Timer

Enable

QZCD

QDRV

Demag

Time

Calculator

Soft−Start Complete

Release

PControl

t

Pdisable

Reset

S

Disable PFC

Q

I

PONOFF

Dominant

Reset

PFC Enable

Timer

Latch

Q

R

PONOFF

Comparator

PONOFF

t

Penable

Filter Delay

−

+

t

Penable(filter)

C

PONOFF

+

−

V

POFF

R

PONOFF

Hysteresis Control

Figure 33. PFC On/Off Control Circuitry

PFC SKIP

AUTO−RECOVERY

The PFC stage incorporates skip cycle operation at light

loads to reduce input power. Skip operation disables the PFC

stage if the PControl voltage decreases below the skip

threshold. The skip threshold voltage is typically 25 mV

The controller is disabled and enters “triple−hiccup”

mode if V drops below V . The controller will also

CC

CC(off)

enter “triple−hiccup” mode if an overload fault is detected

on the non−latching version. A hiccup consists of V

CC

(DV ) above the PControl minimum voltage clamp,

PSKIP

falling down to V

and charging up to V

. The

CC(off)

CC(on)

V . The PFC stage is enabled once V

PControl(MIN)

controller needs to complete 3 hiccups before restarting.

PControl

increases above the skip threshold by the skip hysteresis,

. PFC skip is disabled during any initial PFC

startup and when the PFC is in a UVP. Skip operation will

become active after the PFC has reached regulation.

TEMPERATURE SHUTDOWN

V

PSKIP(HYS)

An internal thermal shutdown circuit monitors the

junction temperature of the IC. The controller is disabled if

the junction temperature exceeds the thermal shutdown

threshold, T

, typically 150°C. A continuous V

PFC AND FLYBACK DRIVERS

The NCL30030 maximum supply voltage, V

30 V. Typical high voltage MOSFETs have a maximum gate

voltage rating of 20 V. Both the PFC and flyback drivers

incorporate an active voltage clamp to limit the gate voltage

on the external MOSFETs. The PFC and flyback voltage

SHDN

CC

, is

CC(MAX)

hiccup is initiated after a thermal shutdown fault is detected.

The controller restarts at the next V once the IC

temperature drops below below T

shutdown hysteresis, T

The thermal shutdown fault is also cleared if V drops

CC(on)

by the thermal

SHDN

, typically 40°C.

SHDN(HYS)

CC

clamps, V

and V , are typically 12 V

QDRV(high2)

below V

, a brown−out fault is detected or if the line

PDRV(high2)

CC(reset)

with a maximum limit of 14 V.

voltage is removed. A new power up sequences commences

at the next V

once all the faults are removed.

CC(on)

ORDERING INFORMATION

Device

†

Package

Shipping

NCL30030B1DR2G

NCL30030B2DR2G

NCL30030B3DR2G

NCL30030A1DR2G*

NCL30030A2DR2G*

NCL30030A3DR2G*

SOIC16 NB LESS PIN 2

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*Please contact local sales representative for availability

www.onsemi.com

31

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−16 NB MISSING PIN 2

CASE 751DT

ISSUE O

DATE 18 OCT 2013

SCALE 1:1

NOTE 5

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

D

A

2X

16

9

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE PROTRUSION SHALL BE 0.10 mm IN EXCESS OF

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS

OR GATE BURRS SHALL NOT EXCEED 0.25 mm PER SIDE. DIMEN

SIONS D AND E ARE DETERMINED AT DATUM F.

5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING

PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.

0.10 C D

F

NOTE 4

E

E1

NOTE 6

A1

L

L2

C A-B D

1

8

0.20 C

SEATING

PLANE

C

MILLIMETERS

B

NOTE 5

15X b

DETAIL A

2X 4 TIPS

DIM MIN

MAX

1.75

0.25

0.49

0.25

10.00

M

0.25

A

A1

b

1.35

0.10

0.35

0.17

9.80

TOP VIEW

2X

c

0.10 C A-B

DETAIL A

D

E

6.00 BSC

0.10 C

E1

e

3.90 BSC

1.27 BSC

0.10 C

L

0.40

1.27

L2

0.203 BSC

e

END VIEW

A

SEATING

PLANE

C

GENERIC

SIDE VIEW

MARKING DIAGRAM*

RECOMMENDED

SOLDERING FOOTPRINT

16

15X

XXXXXXXXXX

AWLYWWG

1.52

1

16

1

9

XXXXX = Specific Device Code

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

7.00

WL

Y

WW

G

8

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

15X

0.60

1.27

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON77479F

SOIC−16 NB MISSING PIN 2

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

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


型号：	NCL30030B1DR2G
厂家：	ONSEMI
描述：	结合功率因数校正和准谐振反激的AC-DC控制器，优化用于LED照明控制器功率因数校正
文件：	总33页 (文件大小：1133K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCL30030B1DR2G [ONSEMI]

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