NCL30076AADR2G [ONSEMI]
Wide Analog Dimming Quasi-Resonant Buck Controller;
| 型号： | NCL30076AADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Wide Analog Dimming Quasi-Resonant Buck Controller |
| 文件： | 总15页 (文件大小：879K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quasi-Resonant Buck
Controller for Precise
Current Regulation and
Wide Analog Dimming
NCL30076
www.onsemi.com
The NCL30076 is a DC−DC buck controller for wide dimming
range down to 1% by analog dimming control to relieve audible noise
and flicker in PWM dimming. ON Semiconductor’s proprietary LED
current calculation technique driven by zero input offset amplifiers
performs precise constant current in the whole analog dimming range.
Multi−mode operation provides high efficiency with minimized
switching loss by QR at heavy load and deep analog dimming by DCM
at light load.
8
1
SOIC−8 NB
CASE 751
PWM dimming control is also provided in case that constant LED
color temperature is required. The NCL30076 has several protections
such as LED short protection, over current protection, thermal
shutdown and VDD over voltage protection for robust system
reliability.
MARKING DIAGRAM
L30076AA
AWLYYWW
Features
• Wide Analog Dimming Range: 1~100%
• Low CC Tolerance: 2% at 100% Load & 20% at 1% Load
• Low System BOM
L30076
AA
A
WL
YYWW
= Specific Device Code
= Default Trimming Option
= Assembly Location
= Wafer Lot Traceability Code
= 4 Digit Data Code
• LED Off Mode at Standby
• Low Standby Current
• PWM Dimming Available
• Gate Sourcing and Sinking Current of 0.5 A/0.8 A
PIN ASSIGNMENT
• Robust Protection Features
♦ LED Short Protection
♦ Over Current Protection
♦ Thermal Shutdown
BIAS
PG
CSZCD
DRV
♦ V Over Voltage Protection
DD
SG
FB
VDD
Typical Applications
DIM
• LED Lighting System
(Top View)
ORDERING INFORMATION
Device
NCL30076AADR2G
Package
Shipping
SOIC−8 NB
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
April, 2021 − Rev. 3
NCL30076/D
NCL30076
APPLICATION SCHEMATIC
200~500 Vin
PFC
VAC
Stage
FB
DRV
Dimming
Signal
DIM
CSZCD
RCS
NCL30076
SG
PG
BIAS
VDD
External source
Figure 1. Application Schematic
BLOCK DIAGRAM
|| VSHUTDOWN
VDD−ON
VDD
VPDIM
VON
VOF F
10 V /
8 V
VPWM
3.3 V
LDO
Q
DRV
S
BIAS
Soft
Start
VTO FF.SS
VTO FF.ZCD
VTO FF.FB
R
TOF F.FB
generator
VCS.LIM
CSZCD
OTA
VLED
VFB
FB
VREF
Precise LED
current calculator
Reference control
PWM dimming control
VPDIM
VSHUTDOWN
VCS.LIM
VTO FF.ZCD
ZCD
detector
DIM
Standby mode control
PG
SG
Over voltage protection
Over current protection
Thermal Shutdown
VDD
Protection
AR control
VCSZCD
VSHUTDOWN
T
J
Figure 2. Simplified Block Diagram
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2
NCL30076
PIN CONFIGURATION
BIAS
PG
CSZCD
DRV
SG
FB
VDD
DIM
(Top View)
Figure 3. Pin Configuration
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
BIAS
CSZCD
SG
Function
3.3 V BIAS
Description
1
2
3
4
5
6
7
8
This pin is 3.3 V LDO output to bias the internal digital circuit
This pin detects the switch current and the inductor current zero cross time
Signal Ground is close to control pin circuit such as CSZCD, DIM and FB
Output of feedback OTA
CS and ZCD Sensing
Signal Ground
Feedback
FB
DIM
Dimming Input
Power Supply
Output Drive
Dimming signal is provided to this pin
VDD
DRV
PG
IC operating current is supplied to this pin
This pin is connected to drive external switch
Power Ground
Power Ground is close to the capacitors at BIAS and VDD pin
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3
NCL30076
SPECIFICATIONS
MAXIMUM RATINGS
Parameter
Symbol
Value
−0.3 to 30
−0.3 to 5.5
550
Unit
V
VDD, DRV Pin Voltage Range
V
MV(MAX)
DIM, FB, CSZCD, BIAS Pin Voltage Range
V
V
LV(MAX)
Maximum Power Dissipation (T < 50°C)
P
mW
°C
A
D(MAX)
Maximum Junction Temperature
T
150
J(max)
Storage Temperature Range
T
−55 to 150
145
°C
STG
Junction−to−Ambient Thermal Impedance
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
R
°C/W
kV
θJA
ESD
2
HBM
CDM
ESD
1
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
− ESD Human Body Model per JEDEC Standard JESD22−A114
− ESD Charged Device Model per JEDEC Standard JESD22−C101
− Latch−up Current Maximum Rating 100 mA per JEDEC Standard JESD78
RECOMMENDED OPERATING RANGES
Parameter
Symbol
Min
Max
Unit
Junction Temperature
T
J
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (V = 15 V and T = −40~125°C unless otherwise specified)
DD
J
Parameter
VDD SECTION
Test Conditions
Symbol
Min
Typ
Max
Unit
IC Turn−On Threshold Voltage
IC Turn−Off Threshold Voltage
Startup Current
V
9.3
7.4
−
10.0
8.0
10.7
8.6
V
V
DD(ON)
V
DD(OFF)
V
DD
= V
− 1.6 V
I
250
6.5
400
8.0
mA
mA
mA
DD(ON)
DD(ST)
DD(OP)
Operating Current
I
−
Standby Current
I
−
200
300
DD(SB)
BIAS SECTION
BIAS Voltage
V
BIAS
3.23
3.25
3.30
3.30
3.37
3.35
V
T = 25~100°C (Note 4)
J
DIM SECTION
DIM Voltage for 100% V
V
DIM
= 1.9 V
V
DIM(REF−MAX)
1.755
1.730
50
1.80
1.78
75
1.845
1.827
100
V
REF
DIM Voltage for 99% V
V
V
REF
DIM(MAX−EFF)
Standby Enabling DIM Voltage
Standby Disabling DIM Voltage
Standby Delay Time
V
mV
mV
ms
DIM(SB−ENA)
V
60
100
10
140
DIM(SB−DIS)
t
9
11
SB(DELAY)
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4
NCL30076
ELECTRICAL CHARACTERISTICS (V = 15 V and T = −40~125°C unless otherwise specified) (continued)
DD
J
Parameter
FB SECTION
Test Conditions
Symbol
Min
Typ
Max
Unit
FB OTA Source Current
IFB = (V
− V
) x g
x 10
I
−14.0
9.0
−11.5
11.5
−9.0
14.0
mA
mA
LED
REF
M(FB)
FB(SOURCE)
V
REF
= 150 mV, V
= 100 mV
LED
FB OTA Sink Current
IFB = (V
− V
) x g
x 10
I
LED
REF
M(FB)
FB(SINK)
V
REF
= 50 mV, V
= 100 mV
LED
FB OTA Transconductance
FB OTA High Voltage
FB Minimum Clamping Voltage
CS SECTION
g
= I / {(V
− V
) x 10}
g
M(FB)
18
4.7
0.4
23
−
28
−
mmho
M(FB)
FB
REF
LED
V
= 150 mV, V
= 100 mV
V
V
V
REF
REF
LED
FB(HIGH)
V
= 0 mV, V
= 100 mV
V
0.5
0.6
LED
FB(CLP)
CS Regulation
V
155
390
145
160
410
155
165
430
165
mV
mV
mV
CS(REG−MAX)
CS Current Limit Maximum
CS Current Limit Minimum
DUTY SECTION
V
CS(LIM−MAX)
V
CS(LIM−MIN)
Leading Edge Blanking Time at
Turn−on
t
t
360
400
440
ns
LEB(TON)
Maximum Ton Time
t
45
50
55
ms
ns
ms
V
ON(MAX)
Minimum Toff Time
V
V
= 3.8 V
= 0.5 V
900
1.17
3.30
0.9
1250
1.30
3.43
1.1
1500
1.43
3.55
1.3
FB
OFF(MIN)
Maximum Toff Time
t
OFF(MAX)
FB
Maximum FB Voltage for Min. Toff
Minimum FB Voltage for Max. Toff
Quasi−Resonant Delay Time
DRV SECTION
V
FB(MAX−TOFF)
V
V
FB(MIN−TOFF)
t
0.45
0.50
0.55
ms
QR
DRV Low Voltage
V
−
−
0.2
13
V
V
DRV(LOW)
DRV High Voltage
V
= 15 V
V
11
60
25
12
DD
DRV(HIGH)
DRV Rising Time
C
C
= 3.3 nF
= 3.3 nF
t
100
55
145
105
ns
ns
DRV
DRV
DRV(R)
DRV Falling Time
t
DRV(F)
AUTO RESTART SECTION
Auto Restart Time at Protection
t
0.9
22
1.0
23
1.1
24
s
V
V
AR(PROT)
VDD OVER VOLTAGE PROTECTION SECTION
VDD Over Voltage Threshold Voltage
V
DD(OVP)
OVER CURRENT PROTECTION SECTION
CS Over Current Protection
Threshold
V
0.9
1.0
1.1
CS(OCP)
THERMAL SHUTDOWN SECTION
Thermal Shut Down Temperature
(Note 3)
T
130
25
150
30
170
35
°C
°C
SD
Thermal Shut Down Hysteresis
(Note 3)
T
SD(HYS)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Guaranteed by design.
4. Guaranteed by characterization.
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NCL30076
TYPICAL CHARACTERISTICS
(These characteristic graphs are normalized at T = 25°C)
A
1.006
1.004
1.002
1
1.006
1.004
1.002
1
0.998
0.996
0.994
0.998
0.996
0.994
−40
−20
0
20
40
60
80
100
120
140
−40
−20
0
20
40
60
80
100
120
140
Temperature (5C)
Temperature (5C)
Figure 4. VBIAS vs. Temperature
Figure 5. VDIM(MAX) vs. Temperature
1.03
1.02
1.01
1
1.006
1.004
1.002
1
0.99
0.98
0.97
0.998
0.996
0.994
−40
−20
0
20
40
60
80
100
120
140
−40
−20
0
20
40
60
80
100
120
140
Temperature (5C)
Temperature (5C)
Figure 6. gM(FB) vs. Temperature
Figure 7. VCS(REG−MAX) vs. Temperature
1.006
1.004
1.002
1
1.006
1.004
1.002
1
0.998
0.996
0.994
0.998
0.996
0.994
−40
−20
0
20
40
60
80
100
120
140
−40
−20
0
20
40
60
80
100
120
140
Temperature (5C)
Figure 9. VDD(OVP) vs. Temperature
Temperature (5C)
Figure 8. VCS(LIM−MIN) vs. Temperature
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6
NCL30076
APPLICATION INFORMATION
General
Therefore, NCL30076 supports low CC tolerance less
NCL30076 provides wide analog dimming down to 1%
than 2% at full load and 20% at 1% load in the system
variation.
with accurate CC regulation. According to buck inductor,
input voltage and output voltage, deep dimming down to
0.1~0.2% load can be achieved. Thanks to
ON Semiconductor’s proprietary LED current calculation
technique, NCL30076 is able to sense the current of LED
load connected at input voltage node with no upper limit of
the input voltage with high design flexibility and system
reliability. LED current sensed by internal zero input offset
amplifiers performs accurate CC regulation in the whole
analog dimming range. Therefore, CC tolerance is tightly
controlled within 2% at 100% load and 20% at 1% load.
Soft start
At startup, an internal soft start block gradually reduces
T
OFF
time from maximum T
limit so that LED current is
OFF
settled smoothly without overshoot current and unexpected
flash.
Standby Mode
When V
is lower than a standby threshold voltage for
DIM
10 ms, standby mode is triggered with LED turn−off and IC
current consumption is minimized.
Wide Analog Dimming
Auto Restart (AR) at Protection
Wide analog dimming range is obtained by transitioning
multi−mode operation between QR and DCM according to
the dimming condition. At full load condition, QR with
valley switching minimizes switching loss for high system
efficiency and DCM is activated at light load condition to
perform deep analog dimming. Internal LED current
calculator and a digital compensator provide dimming
linearity over the entire dimming range.
Once protection is triggered, IC operation stops for
1 second and begins soft start operation after the auto restart
time delay.
VDD Over Voltage Protection (OVP)
When VDD is higher than V
voltage protection is triggered.
threshold, over
DD (OVP)
Short LED Protection (SLP)
PWM Dimming
When LED is short circuited, the buck stage operates at
minimum switching frequency, so the maximum turn−off
time control protects the freewheeling diode from thermal
stress.
Analog dimming has benefits for less audible noise and
flicker compared to PWM dimming. However, PWM
dimming method is generally required to keep the constant
LED color temperature in specific applications. NCL30076
supports PWM diming by simply providing PWM dimming
signal to DIM pin.
Over Current Protection (OCP)
When CSZCD voltage exceeds the over current threshold
voltage, switching is immediately shut down after leading
edge blanking time in the short circuit condition of the
inductor or the freewheeling diode.
Precise CC Regulation
CC regulation is very important especially in
programmable LED driver system to keep constant LED
current under system variation of LED load, inductor,
temperature, etc. NCL30076 applies zero input offset
amplifiers at LED current calculator and OTA. Those blocks
can implement precise LED current sensing and FB voltage
generation.
Thermal Shot Down (TSD)
When IC junction temperature is higher than 150°C, TSD
is triggered and released when the temperature is lower than
120°C.
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NCL30076
BASIC OPERATION
Wide Analog Dimming
NCL30076 operates in QR at full load and in DCM at light
load for a wide dimming range. Figure 11 shows how
NCL30076 is the current mode buck controller in which
DRV is off when V reaches to V and DRV is on
CSZCD
CS.LIM
by inductor current zero cross signal (V
) in QR and
TOFF.ZCD
NCL30076 operates with V
.
T
generator output (V
) in DCM as shown in
DIM
OFF.FB
TOFF.FB
Figure 10. V
is calculated based on V
in precise
LED
CSZCD
ILBUC K x RCS
A(QR)
LED current calculator block composed of zero input offset
amplifiers and V
equation.
C
B
A
is controlled by DIM signal by below
REF
~320 mV
155 mV
V
DIM * 0.2 V
(eq. 1)
VREF [V] +
VCS .LIM
16 0 mV
B(DCM)
10
V
LED
is compared with V
by OTA to generate V .
REF FB
V
FB
sets V
as below equation.
VREF
CS.LIM
VFB
(eq. 2)
VCS.LIM [V] +
) 37.5 mV
t
10
VDIM
V
also controls V
signal by T
generator
after DRV is
FB
TOFF.FB
OFF.FB
VFB
in which V
turned off.
is triggered at T
TOFF.FB
OFF.FB
1.1 V
0.5 V
2.7
(eq. 3)
VDIM
TOFF.FB [ms] +
) 0.1
tOFF (MA X)
500 ms
V
FB * 1.1
TOFF
TOFF.FB
When V
drops after the inductor current zero cross,
CSZCD
TOFF.ZCD
IC counts t (0.5 ms) and trigger V
. In QR mode,
QR
TOFF.ZCD
V
signal is generated later than V
signal
TOFF.ZCD
TOFF.FB
and DRV on is determined by V
for valley
TOFF.ZCD
~ 1 V
1.8 V VDIM
0.2 V
0.1/0.07 5 V
switching. In DCM mode, DRV on is set by V
as
TOFF.FB
T
is longer than V
triggering time.
OFF.FB
TOFF.ZCD
Figure 11. Operation Mode vs. VDIM
• A: V controls V
and T
with QR switching as T
is determined by
FB
CS.LIM
OFF
DLED
PFC
CIN
CLED
DBUCK
VAC
ILED
Stage
T
T
is longer than
OFF.ZCD
OFF.ZCD
LBUCK
.
OFF.FB
• B: Operating mode is transitioned from QR to DCM at the
RZCD1
QBUCK
RZCD2
boundary between
A
and
B
region which is
VDIM − 0.2 V
DRV
ILED
=
10 x RCS
approximately half load. T
is determined by T
OFF
OFF.FB
CSZCD
as T
is longer than T
. When V
is further
OFF.FB
OFF.ZCD
DIM
RCS
reduced, V
is no longer controlled by V and
FB
CS.LIM
clamped to minimum V
(155 mV).
CS.LIM
VTO FF.ZCD
VTO FF.FB
• C: When V
is lower than 0.2 V, V
is pulled down to 0.5 V clamping voltage with min.
is set to 0 V and
DIM
REF
VPWM
VON
S
R
Q
V
FB
VOF F
DRV
VFB
TOF F.FB
generator
LED current under open loop control. When V
lower than 0.075/0.1 V, standby mode is triggered with
LED turn−off.
is
DIM
VCS.LIM
VCS.LIM
CSZCD
VLED
OTA
Precise LED
current calculator
LED = ILED x RCS
FB
Precise CC Regulation
V
VREF
Current sensing amplifier and OTA applies zero input
offset compensation technique for precise CC regulation
and dimming curve linearity in multi−mode operation
Table 1 shows CC tolerance measured by changing
inductor ( 15%), temperature (−10, 25, 90 °C), output
voltage (100, 200, 300 V) and controller 150 pcs (3 lot
variation) in 400 V input 100 W driver. As a result, CC
tolerance with system variables at 1% deep dimming
condition is less than 26% and less than 3.0% at full load
condition.
VTO FF.ZCD
ZCD
detector
Reference control
DIM
Standby mode control
VSTANDBY
Figure 10. NCL30076 Block Diagram
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8
NCL30076
Table 1. CC TOLERANCE (150 pcs)
Inductor : +15%
Temp. : −10 / 25 / 90 5C
100% Load
50% Load
10% Load
4.41
5% Load
5.32
2% Load
9.22
1% Load
16.23
V
OUT
V
OUT
V
OUT
: 100 V
: 200 V
: 300 V
1.99
1.83
1.86
2.29
3.77
3.70
3.06
4.10
4.76
5.23
8.64
14.44
*
4.33
5.80
10.57
13.48
20.54
*
V
: 100 / 200 / 300 V
5.45
6.94
25.38
OUT
*The main deviation factor is high temperature condition. The Total CC tolerance at 1% deep dimming condition without high temperature
condition is less than 20%.
Soft Start
During soft start operation, Internal soft start counter
T
contributes to T
by reduced from t
.
OFF.SS
OFF
OFF(max)
When T
reaches to the steady state level, V is
OFF_SS
FB
settled to regulation level and T
is finally decided to
OFF
T
or T
by load condition. In the end of the soft
OFF.FB
OFF.ZCD
start time, T
reaches to 0 and doesn’t affect T
OFF
OFF.SS
control anymore. Figure 14 shows how the soft start
operates at full load condition where T is not engaged
OFF.FB
as T
is set by T
in QR mode.
OFF
OFF.ZCD
• A: T
is determined by T
which is reduced from
OFF
OFF.SS
t
. V is pulled up and the system operates in
OFF(MAX) FB
DCM mode.
• B: T is controlled by T
as T is shorter
OFF.SS
is closer to V , and V starts
LED REF FB
OFF
OFF.ZCD
than T
. V
OFF.ZCD
falling.
• C: V is settled in regulation level and steady state starts.
FB
A
B
C
tOFF (MAX )
1300 ms
TOFF by
TOFF .ZCD
(VFB falls to
steady state level)
TOFF by
TOFF .ZCD
(steady
state)
TOFF by
TOFF .SS
Figure 12. NCL30076 Dimming Curve and CC
Tolerance
Standby Mode
Standby mode is triggered by V
Figure 13.
TOFF
TOFF .SS
TOFF .ZCD
as shown in
, DRV is shut
DIM
• A: When V
is lower than V
DIM(SB−ENA)
DIM
down. So, LED lamps turn off.
• B: After t (10 ms), standby mode is entered and
TOFF .FB
VFB
SB(DELAY)
NCL30076 current consumption drops to I
.
DD(SB)
• C: When V
is higher than V
, standby
DIM(SB−DIS)
DIM
mode is immediately terminated and IC starts up.
VREF
A
B
C
VLED
100 mV V
DIM(SB−DIS)
ILBUC K
75 mV V
DIM(SB−ENA)
VDRV
tSB(DELAY)
Standby Mode
Time
Figure 14. Soft Start Sequence
(Full Load Startup in QR)
VFB
Time
Figure 13. NCL30076 Standby Mode
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NCL30076
Protections
1300 ms, t
due to the absence of zero cross
OFF(MAX)
detection. Therefore, max. T
freewheeling diode from thermal stress and the diode
control protects the
• VDD Over Voltage Protection (OVP)
OFF
When VDD is higher than V
(23 V), VDD OVP
DD(OVP)
current is regulated close to the LED current set by V
.
is triggered with 1 sec AR timer. Open LED protection
can be implemented by VDD OVP when VDD is supplied
by auxiliary winding in the buck inductor.
DIM
• Thermal Shut Down (TSD)
When the junction temperature is higher than T , the
SD
system shuts down and the junction temperature is
monitored at every 1 second AR delay time. When the
• Over Current Protection (OCP)
When CSZCD voltage is higher than V
leading edge blanking time, t
(1 V) after
(400 ns), IC
CS(OCP)
temperature is lower than T – T
, the system
SD(HYS)
SD
LEB(TON)
restarts.
immediately shuts down with 1 sec AR timer.
• Short LED Protection (SLP)
When LED load is short−circuited, T
is lengthened to
OFF
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NCL30076
APPENDIX: DIMMING CURVE AND CC TOLERANCE WITH SYSTEM VARIABLES
− System: NCL30076 100 W (V : 400 V / V
: 100 ~ 300 V / I : 333 mA)
OUT OUT(MAX)
IN
− Temperature variation: −10 / 25 / 90 °C
− Inductance variation: 15% (1.36 mH ~ 1.84 mH)
− Output Voltage: 100 / 200 / 300 V
− NCL35076 Controller: 150 pcs (3 lot variation)
Wide Output Condition (100/200/300V)
NCL30076 150pcs (3lot) + Temp & Inductor variation
+/− 26%
+/− 15%
+/− 8%
+/− 7%
+/− 5%
Single Output Condition (100V)
NCL30076 150pcs (3lot) + Temp & Inductor variation
+/− 17%
+/− 10%
+/− 5%
+/− 6%
+/− 4%
Single Output Condition (200V)
NCL30076 150pcs (3lot) + Temp & Inductor variation
+/− 15%
+/− 10%
+/− 5%
+/− 4%
+/− 6%
Single Output Condition (300V)
NCL30076 150pcs (3lot) + Temp & Inductor variation
+/− 21%
+/− 12%
+/− 5%
+/− 7%
+/− 4%
Figure 15. CC Tolerance (150 pcs)
www.onsemi.com
11
NCL30076
PCB LAYOUT GUIDANCE
LBUCK
Jumper
1
2
4
3
Jumper
*
RZCD1 should be properly selected according to rated voltage.
Figure 16. Layout Guidance
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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