NCL38046PADR2G [ONSEMI]
Precise CC/CV/CP Secondary-side Controller Compatible with Analog and PWM Dimming Signal;
| 型号： | NCL38046PADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Precise CC/CV/CP Secondary-side Controller Compatible with Analog and PWM Dimming Signal |
| 文件： | 总14页 (文件大小：488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Precise CC/CV/CP
8
Secondary-side Controller
Compatible with Analog
and PWM Dimming Signal
1
SOIC−8
D SUFFIX
CASE 751−07
MARKING DIAGRAM
NCL38046
Features
NCL38046
XY
AWLYYWW
• Precise CC Regulation with +/− 0.5 mV Tolerance
• Compatible with Multiple Dimming Input Signals
♦ ADIM Pin Receives Analog Voltage Dimming Input
♦ PWM Pin Receives PWM Duty Dimming Input
NCL38046 = Specific Device Code
• Constant Power Regulation
XY
A
WL
YY
WW
= Dimming Option
• Dimming Curve Modulation
= Assembly Location
= Wafer Lot Number
= Year of Production
= Work Week Number
♦ Maximum and Minimum Dimming Input Limit
♦ Minimum Dimming Output Level Limit
♦ Linear or Logarithmic Dimming Curve – Externally Selectable
• Standby Mode
• 3.3 V Reference Voltage Output
• This is a Pb−Free Device
PIN CONNECTIONS
1
2
8
7
FB
VS
VDD
SET/REF
ADIM
CS
Typical Applications
• Power Conversion
• Lighting Ballast
3
4
6
5
GND
PDIM
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
NCL38046PADR2G
SOIC−8
2500 /
Tape & Reel
2500 /
Tape & Reel
SOIC−8
NCL38046AADR2G
Letter Coding
L1 : P (PDIM modulation), A (ADIM modulation)
L2 : Sequentially assigned from A to Z
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2023
1
Publication Order Number:
July, 2023 − Rev. 0
NCL38046/D
NCL38046
Figure 1. Application Schematic
Sink only
CV OTA
VDD
FB
UVLO
V
V
/
DD(ON)
D(OFF)
VS
CS
V
VS(REF)
Sink only
CC OTA
V
CS(REF)
REF Generator
(3.3 V LDO Output)
SET/REF
GND
True CP
Calculator
C
, R
SET SET
Detector
Digital
DIM Modulator
& STBY Control
ADIM
Detector
PDIM
Detector
ADIM
PDIM
pdim [%]
adim [%]
Figure 2. Simplified Block Diagram
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2
NCL38046
PIN DESCRIPTION
Pin N5
1
2
3
Pin Name
Pin Description
FB
Output of the feedback OTA.
IC operating current is supplied to this pin
VDD
SET/REF
At startup, external SET resistor and capacitor are detected to adjust the internal DIM modulator
parameters. Then, 3.3 V output is provided for an external use such as setting ADIM voltage.
4
5
6
7
8
ADIM
PDIM
GND
CS
ADIM detects an analog voltage signal.
PDIM detects a PWM duty current signal.
The controller ground.
This pin is connected to sense the output current.
This pin is connected to sense the output voltage.
VS
MAXIMUM RATINGS TABLE
Rating
Symbol
Value
−0.3 to 30
−0.3 to VDD
−0.3 to 6
150
Unit
V
VDD Pin Voltage Range
FB Pin Voltage Range
V
MV(MAX)
V
V
FB(MAX)
CS, VS, ADIM, PDIM, SET/REF Pin Voltage Range
Maximum Junction Temperature
V
V
LV(MAX)
T
°C
°C
J(MAX)
Storage Temperature Range
T
−60 to 150
Lead Temperature Soldering
T
SLD
260
°C
Reflow (SMD Styles Only), Pb*Free Versions (Note1)
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
ESD
ESD
1.5
1
kV
kV
HBM
CDM
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
THERMAL CHARACTERISTICS (Note 3)
Rating
Symbol
Value
Unit
Thermal Characteristics, SOIC−8
Thermal Resistance, Junction−to−Air
R
153
°C/W
Θ
JA
2
3. Mounted on a JEDEC standard 51−3 (1s0p) test board, 100 mm copper area, 1 oz copper thickness
RECOMMENDED OPERATING RANGES
Rating
Operating Junction Temperature Range
Symbol
Min
Max
Unit
T
J
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
NCL38046
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to 125°C, unless otherwise noted)
DD
J
Parameter
VDD SECTION
Test Condition
Symbol
Min
Typ
Max
Unit
IC Turn−On Threshold Voltage
IC Turn−Off Threshold Voltage
Startup Current
V
8.0
7.0
−
8.5
7.5
−
9.0
8.0
210
1.0
1.5
600
V
DD(ON)
V
V
DD(OFF)
V
= 7 V
I
ꢀ A
mA
mA
ꢀ A
DD
DD(ST)
Operating Current
I
−
0.8
1.3
−
I
I
= 0 ꢀ A, R
= 9.09 kΩ (Note 4)
PDIM
PDIM
SET
DD(OP−L)
DD(OP−H)
= 500 ꢀ A, R
= 9.09 (Note 4)
I
−
SET
Standby Current
SET/REF SECTION
SET Current
PDIM = 2% in1 kHz, No R
I
400
SET
DD(SB)
I
47.5
281
50.0
300
52.5
319
ꢀ A
SET
SET Reference Voltage
V
mV
When R
= 9.1 kꢁ,
SET SET(1)
SET
< V
SET(0)
V
SET(0)
< V
When R
When R
When R
When R
When R
When R
When R
= 13 kꢁ, V
= 18 kꢁ, V
= 24 kꢁ, V
= 33 kꢁ, V
= 43 kꢁ, V
= 56 kꢁ, V
< V
< V
< V
< V
< V
< V
< V
< V
< V
< V
< V
< V
V
V
V
V
V
V
V
519
732
999
545
765
571
798
mV
mV
mV
mV
mV
mV
mV
ꢀ s
SET
SET
SET
SET
SET
SET
SET
SET(1)
SET(2)
SET(3)
SET(4)
SET(5)
SET(6)
SET
SET
SET
SET
SET
SET
SET(2)
SET(3)
SET(4)
SET(5)
SET(6)
SET(7)
SET(1)
SET(2)
SET(3)
SET(4)
SET(5)
SET(6)
SET(7)
1040 1081
1348 1400 1452
1814 1880 1946
2367 2450 2534
3288 3400 3512
= open, V
< V
SET
SET(7)
SET Capacitor Detection Delay
Time
Design guaranteed
t
t
4.76
5
5.26
SET(CAP)
SET Resistor Detection Delay Time Design guaranteed
REF Regulation Voltage
487
512
538
ꢀ
s
SET(RES)
V
3.26
3.30
3.34
V
REF
PDIM and ADIM SECTION
PDIM High Threshold Current
PDIM Low Threshold Current
PDIM Maximum Current Limit
PDIM Regulation Voltage
PDIM Minimum Frequency Limit
ADIM Maximum Voltage
Increasing I
I
125
55
153
70
170
80
ꢀ A
ꢀ A
mA
V
PDIM
PDIM(TH−H)
Decreasing I
I
PDIM(TH−L)
PDIM
V
PDIM
= 0 V
I
0.8
2.9
65
1
1.2
3.1
−
PDIM(MAX)
I
= 250 ꢀ A
V
PDIM
3.0
−
PDIM
Design Guaranteed
f
Hz
V
PDIM(MIN)
V
2.47
2.50
2.53
ADIM(MAX)
VS SECTION
VS OTA Input Offset
V
−25
0
+25
mV
V
VS(OTA−IO)
VS Maximum Regulation Voltage
VS Standby Regulation Voltage
V
2.425 2.500 2.575
0.475 0.500 0.525
VS(REG−MAX)
D
ADIM
< D
in PA version
in AA version
V
VS(REG−SB)
V
PDIM
PDIM(SB−EN)
< V
ADIM(SB−EN)
V
CS SECTION
CS OTA Input Offset
V
−0.5
−0.3
0
0
0.5
0.3
mV
mV
Temp range: −40°C ꢂ 125°C
Temp range: 25°C ꢂ 85°C
Only 25°C
CS(OTA−IO)
−0.175
98
0
0.175 mV
CS Maximum Regulation Voltage
I
FB
= 0.5 mA in a closed loop regulation
V
100
102
mV
CS(REG−MAX)
Temp range: −40°C ꢂ 125°C
I
= 0.5 mA in a closed loop regulation
99
100
101
mV
FB
Temp range: 25°C ꢂ 85°C
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4
NCL38046
ELECTRICAL CHARACTERISTICS (V = 12 V and T = −40°C to 125°C, unless otherwise noted) (continued)
DD
J
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
CS Half Regulation Voltage
I
= 0.5 mA in a closed loop regulation
V
49.5
50.5
51.5
mV
FB
CS(REG−HALF)
Temp range: −40°C ꢂ 125°C (Note 5)
I
= 0.5 mA in a closed loop regulation
50
0.3
0.6
−28
50.5
1
51
1.7
1.4
−19
mV
mV
mV
ꢀ A
FB
Temp range: 25°C ꢂ 85°C (Note 5)
CS Minimum Regulation Voltage
I
FB
= 0.5 mA in a closed loop regulation
V
CS(REG−MIN)
Temp range: −40°C ꢂ 125°C
I
FB
= 0.5 mA in a closed loop regulation
1
Temp range: 25°C ꢂ 85°C
CS Fault Current
I
−24
CS(FAULT)
FB SECTION
FB Maximum Sink Current of
CS OTA
V
V
= 1 V
= 3 V
I
2.5
2.5
−
−
−
−
mA
mA
CS
FB(SINK−CS−MAX)
FB Maximum Sink Current of
VS OTA
I
FB(SINK−VS−MAX)
VS
Transconductance of CS OTA
Transconductance of VS OTA
g
g
−
−
7
3
−
−
mho
mho
M(CS)
M(VS)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1
1
RSET
* 3.3ꢀV @ ǒ
Ǔ
4. I is affected to R
value. If you want to know I with other R , I
SET
ꢀ
+ I
)
DD
SET
DD
DD(RSET changed)
DD
9.09k
5. The value has an offset due to MOD
to modulate a dimming curve. V
is calculated as shown below.
OUT(MIN)
CS(REG)
MOD
* MOD
OUT(MAX)
MOD
OUT(MIN)
V
+ Dim[%] @ slope ) offꢀset , where slope +
, offꢀset + MOD
* slope @ MOD
OUT(MAX) IN(MAX)
CS(REG)
* MOD
IN(MAX)
IN(MIN)
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5
NCL38046
APPLICATION INFORMATION
ADIM signal is detected by the ADIM voltage detector
and ADIM voltage input range is 0 ꢂ2.5 V. The detected
ADIM voltage is converted to adim signal (0% ~ 100%).
At startup, ADIM pin is buffered by SET/REF pin voltage
NCL38046 performs precise CC regulation in the wide
dimming range controlled by both PWM duty and analog
voltage signal. Dimming curve is internally modulated by an
effective dimming input range (e.g., 10% ꢂ 90%) and the
minimum dimming output level (e.g., 1%). Also, either
linear or logarithmic dimming curve is externally selected
by a SET capacitor. Constant power regulation is
implemented by CV regulation reference defined inversely
proportional to the dimming level where the CP level is
flexibly set by an external SET resistor.
as described in Section. REF Function. So, 10 kꢁ R
in
ADIM
Figure 4 is recommended when V
is set by the external
ADIM
voltage source not to conflict with an internal buffer
(SET/ref to ADIM) output.
CC/ CV Regulation
For high CC accuracy, an input voltage offset of the CC
regulation OTA is significantly reduced by a novel amplifier
design with high resolution trimming so that the input
voltage at room temperature is less than +/− 0.1 mV. When
a LED load is connected, CS pin voltage (V ) is regulated
CS
to V
, an internally generated CS reference voltage
CS(REF)
controlled by PDIM and ADIM inputs. When the LED load
is open, V drops to 0 V and CC OTA does not sink FB
CS
current and V is regulated to V
.
VS
VS(REF)
Figure 4. CC Reference Generation Block
Dimming Signal Modulation
In general, an external dimming signal generator such as
0 − 10 V dimmer doesn’t provide the full range of the
dimming signal. In such case, NCL38046 can scale either
pdim or adim signal by the internal modulator. As shown in
Figure 5, the modulator input signal, mod , has an effective
IN
input range between 10% and 90%. In other words, when
mod is 10%, mod
becomes the min value and mod
IN
OUT
OUT
doesn’t decrease although mod goes below 10% because
IN
mod
is clamped to 1% by mod . When mod
OUT(MIN) IN
OUT
is lower than 3%, NCL38046 enters STBY. In order to exist
STBY, mod should be higher than 5% because of STBY
threshold hysteresis.
IN
Figure 3. CC/CV Regulation Block
CC/ CV Regulation
mod
(= pdim
or adim
)
OUT
MOD
MOD
PDIM and ADIM Detection
As shown in Figure 4, PDIM pin voltage is regulated to
100%
3 V by the pull−up buffer. PDIM current, I , is compared
PDIM
with I
hysteretic current thresholds and the
PDIM(TH−H/L)
comparison output signal is converted to pdim signal
(0%ꢃ ꢂ ꢃ100%) by the duty extractor. When I is higher
Linear
PDIM
than the current threshold, it is considered as the on state in
the PWM duty. The recommended I on−state level is
PDIM
300 ꢂ 600 ꢀ A and PDIM pin is pulled down to 0 V when
is higher than 1 mA in order to limit the VDD
operating current. 200 Hz PWM frequency is recommended
to perform high resolution dimming.
I
PDIM
Logarithmic
mod
1%
3%
IN
(= pdim or admin)
10%
5%
Figure 5. Dimming Signal Modulation
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6
NCL38046
V
When mod is 90%, mod
becomes the max value and
CS(REF)
CS(REG−MAX)
IN
OUT
mod
doesnꢄt increase even though mod rises above
OUT
IN
V
pdim = 100%
pdim = 80%
pdim = 60%
pdim = 40%
pdim = 20%
90% by mod
.
IN(MAX)
Thereꢄre also two types of dimming curves (Linear and
Logarithmic).
Multiplier
Recently, LED drivers generally control the output
current by the dual dimming signals to set the maximum
output current and to implement the dimming function. In
order to perform the multiple dimming in NCL38046, adim
(0 ꢂ100ꢅ) and pdim (0 ꢂ100ꢅ) signals are multiplied
V
CS(REG−MIN)
adim
MOD
0%
100%
and scaled to V
to provide V
as shown
CS(REF−MAX)
CS(REF)
in Figure 6 and Figure 7. The dimming signal input is usually
modulated, and the maximum output current setting signal
is not modulated just to set the coefficient in the dimming
curve.
Figure 7. Dimming Curve in AA Version
When analog voltage signal at ADIM is used for the
maximum output current setting and PWM duty signal at
PDIM is used for dimming, PA version should be used.
V
is determined by (eq. 1) which corresponds to
CS(REF)
Figure 6.
VCS(REF)[V] + VCS(REF*MAX)[V] @ adim[%] @ pdimMOD[%]
(eq. 1)
When adim is used for dimming and pdim is to set the
maximum output current, AA version should be used.
V
is set by (eq. 2) corresponding to Figure 7.
CS(REF)
VCS(REF)[V] + VCS(REF*MAX)[V] @ pdim[%] @ adimMOD[%]
(eq. 2)
VCS(REF) dimming voltage range is limited by VCS(REF-MAX)
and VCS(REF-MIN).
V
CS(REF)
V
adim = 100%
adim = 80%
adim = 60%
adim = 40%
adim = 20%
CS(REG−MAX)
V
CS(REG−MIN)
pdim
MOD
0%
100%
Figure 6. Dimming Curve in PA Version
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7
NCL38046
CV Reference
With CP function in Figure 8, V
is set by (eq. 3)
VS(REF)
Constant voltage reference is determined by constant
power regulation block to protect the LED load and limit the
LED driver power when maximum output current is
and the LED load is safe even though adim is wrongly set to
100% because V , inversely proportional to adim, is
VS(REF)
set lower than the max load operating point. If adim is
correctly set back to 50%, V is set higher than the
incorrectly set. CV reference, V
, is determined by:
VS(REF)
VS(REF)
max load condition and the LED load current is regulated to
the right max load condition by CS regulation.
VVS(REF)[V] + 2.5 V @ KCP[%]ń dimCP[%]
(eq. 3)
When the LED load is open, the output voltage is regulated
little higher than the LED load forward voltage so that there
won’t be a large inrush current from the output capacitor to
the LED load when the LED load is connected again. In the
conventional LED driver with CP function, CV regulation
level is determined by total LED current level so that the
output voltage is regulated to the maximum output level at
LED open condition. In such condition, the LED load can be
damaged when the LED load is connected because the
output regulation level is much higher than the LED load
forward voltage.
where K [%] is a constant power coefficient and
CP
dim [%] is CP dim input which is adim in PA version or
CP
pdim in AA version. K is set by R
value as described
CP
SET
in Section. SET/REF Function. Also, V
is
VS(REF−MAX)
clamped to 2.5 V.
Figure 8 shows an example of the load operating point
assuming that the maximum current spec of an LED load is
at 50%
V
by setting adim at 50%
CS(REF−MAX)
(V = 1.25 V) and the output current dimming is
ADIM
controlled by pdim
.
MOD
Without CP function, the LED current will be twice than
its maximum current rating with the LED damage if adim is
mistakenly set to 100% (V
= 2.5 V).
ADIM
Figure 8. Operating Point by the Maximum Output Current Set Level
Standby Mode
As shown in Figure 9, V
is pulled down to 0 V for
SET/REF
When either adim or pdim is lower than a standby
threshold level which is PDIM = 3% in PA version or
64 ꢀ s once V is higher than V
. Then, SET/REF pin
DD
DD(ON)
SET/REF
is pulled up by 50 ꢀ A I . If V
is lower than V
SET
SET(0)
V
ADIM
= 75 mV in AA version, the CC OTA is disabled to
due to C
after 5 ꢀ s t
delay, C
connection is
SET
SET(CAP)
SET
terminate the output current regulation and CV OTA
reference, V , is changed to V ) to turn off
the LED load during standby mode.
detected. If V
decides that C
1.2 nF is used.
is higher than V
, NCL38046
is not connected. For C detection,
SET
SET/REF
SET(0)
VS(REF)
VS(REG−SB
SET
After C
detection for 512 ꢀ s t
detection, NCL38046 waits for R
SET
SET
SET/REF Function
delay until V
level is
SET(RES)
SET/REF
SET and REF Sequence
settled to R
x I , then V
is compared with
SET
SET
SET/REF
NCL38046 has a multi−functional pin, VSET/REF, for
setting internal parameters and providing 3.3 V reference
output for the external use.
internal references, V
9.1 / 13 / 18 / 24 / 33 / 43 / 56 kꢁ is used as shown in Table 1.
(n = 0 ꢂ7). For R
detection,
SET(n)
SET
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8
NCL38046
If SET/REF pin is open or short circuited, V
will
Once C
and R detections are completed, V
SET SET/REF
SET/REF
SET
be higher than V
or lower than V
high period) and I
RST SET
. In such case,
enabling time
is regulated to 3.3 V by internal LDO, and the 3.3 V
reference voltage can be utilized for various purpose in the
external circuit.
SET(7)
SET(0)
V
reset (S
SET/REF
(S
high period) in Figure 9 are repeated and FB pin
SET
voltage is slowly pulled down to reduce the power delivery
to the load until R is normally detected.
SET
Figure 9. SET/REF Functional Block and Sequence
REF Function
After C and R
regulated to 3.3 V. The reference voltage can be utilized to
set ADIM voltage by adding R resistor between
SET/REF and ADIM pin so that ADIM voltage, V
determined by:
Table 1. COMPONENTS AT SET FUNCTION
detection, SET/REF pin voltage is
SET
SET
R
K
CP
SET
9.1 kΩ
13 kΩ
18 kΩ
24 kΩ
33 kΩ
43 kΩ
56 kΩ
40%
50%
REF
, is
ADIM
60%
VADIM[V] + 3.3 V @ RADIMń(RREF ) RADIM
)
70%
(eq. 4)
80%
Variable resistor can be used for R
to externally
ADIM
90%
adjust the maximum output current level by ADIM.
During I enabling time (S high period), R
REF
100%
SET
SET
C
Dimming curve
Linear
network can affect R
detection level. In order to monitor
SET
SET
only R
impedance through SET/REF pin, ADIM pin
SET
0 nF
voltage is buffered same as SET/REF pin voltage and R
impedance from SET/REF pin becomes infinite with no
effect on the SET/REF voltage.
REF
1.2 nF
Logarithmic
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9
NCL38046
Table 2. NCL38046 OPTION TABBLE
st
nd
1
2
MOD
Input
STBY
Trigger
Letter
Letter
P/N
V
V
V
R
func.
K
CP
CS(REF−MAX)
CS(REF−MIN)
VS(REF−SB)
SET
NCL38046
P
A
A
A
a1
a2
b1
b2
c2
d3
e2
f1
f1
g22 (69%)
g22 (69%)
c2
d3
e2
st
nd
1
2
STBY
Letter
Letter
Threshold
P/N
CP_sel
h1
MOD
MOD
MOD
Log. Curve Eq.
IN(MIN)
IN(MAX)
OUT(MIN)
NCL38046
P
A
A
A
i2
j2
j2
k2
l5
m1
m1
h2
i2
k2
l5
MOD Input
CP dim input (dimCP
)
a1
a2
pdim
adim
h1
h2
adim
pdim
STBY Trigger
MODIN(MIN)
b1
b2
pdim
adim
i1
i2
0%
10%
VCS(REF−MAX)
STBY threshold
c1
c2
c3
c4
50 mV
j1
j2
j3
j4
6% / 8%
3% / 5%
2% / 3%
Disabled
100 mV
200 mV
500 mV
VCS(REF−MIN)
MODIN(MAX)
d1
d2
d3
d4
0%
k1
k2
k3
k4
100%
90%
85%
80%
0.4%
1%
2%
VVS(REF−SB)
MODOUT(MIN)
e1
e2
e3
e4
0 V
I1
I2
I3
I4
I5
10%
7.5%
5%
0.5 V
1 V
1.5 V
2%
1%
RSET Function
Logarithmic Curve Equation
f1
f2
K
set
CP
MOD
set
m1
m2
modout = modin^2
modout = modin^3
OUT(MIN)
KCP
g1 ꢂ g32
100% ꢂ 3% (3% step)
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10
NCL38046
PCB LAYOUT GUIDANCE
C
CMPC2
Opto
C
CMPC1
R
CMPC2
R
VS1
C
CMPV2
C
R
CMPV1
R
VDD
CMPV
FB
VS
8
R
R
VS2
FB
1
VDD
CS
7
R
C
CMP1
VDD
2
NCL38046
Power GND
SET/REF
GND
6
R
R
CS2
CS1
R
SET
3
Signal GND
ADIM
PDIM
5
R
ADIM
C
SET
4
I
PDIM
PWN Duty
Current
Analog Voltage
C
ADIM
V
ADIM
I
PDIM
Figure 10. NCL38046 Schematic
CS
R
CMPC1
7
Current sensing path
should be short.
R
GND
6
CS
C
CMPC2
We recommend that the FB
loop of CS should be short.
R
C
CMPC1
CMPC2
1
7
FB
CS
R
R
CMPC1
FB
Figure 11. NCL38046 Daughter Board
Figure 12. NCL38046 Layout Guidance
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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