NCN49599_技术文档

NCN49599

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Power Line Carrier Modem

The NCN49599 is a powerful power line communication SoC

combining low power Cortex M0 processor with a high precision

analogue front end. Based on a dual 4800 Baud S−FSK channel

technology, it offers an ideal compromise between speed and

robustness for operations in a harsh environment.

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It is functional compatible with its predecessor NCN49597,

extending frequencies up to Cenelec D band for use in applications

such as e-metering, home automation and street lighting.

The NCN49599 benefits for more than 10 years of field experience

in eMetering and delivers innovative features such as a smart

synchronisation and automatic baud rate detection.

1

56

Fully reprogrammable, it also supports building automation

standard or full custom protocol. The configurable GPIOs allow

connecting peripherals such as LCD or metering ICs.

QFN56 8x8, 0.5P

CASE 485CN

Features

• Power Line Carrier Modem for 50 and 60 Hz Mains

MARKING DIAGRAMS

• Embedded 1.2 A Highly Linear 2 stage Power Amplifier with current

limitation and thermal protection.

56

1

• Embedded ARM Cortex M0 Processor, Programmable Embedded

Software

ARM

ON

• Compliant with CENELEC EN 50065−1

• Dual S−FSK Channel

NCN49599

0C599−001

AWLYYWWG

• Programmable Carrier Frequencies in CENELEC A−D Band

• Half Duplex

e3

• Data Rate Selectable:

XXXX = Date Code

300 – 600 – 1200 − 2400 – 4800 baud (@ 50 Hz)

360 – 720 – 1440 − 2880 – 5760 baud (@ 60 Hz)

Y

ZZ

= Plant Identifier

= Traceability Code

• Repetition and Smart Synchronization Algorithm Boost the

Robustness of Communication

• Selectable UART/Full Duplex UART to Application Microcontroller

• SCI Port to Application Microcontroller

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 38 of this data sheet.

• SCI Baudrate Selectable: 9.6 – 19.2 – 38.4 − 115.2 kb

• Power Supply 3.3 V and 12 V

• Junction Temperature Range: −40°C to +125°C

• These Devices are Pb−Free and are RoHS Compliant

Typical Applications

• AMR: Automated Remote Meter Reading

• In Home Display

• Building Automation

• Solar Power

• Streetlight Control

• Transmission of Alerts (Fire, Gas Leak, Water Leak)

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

1

Publication Order Number:

March, 2013 − Rev. P0

NCN49599/D

NCN49599

APPLICATION

Application Example

JTAG

Interface

Meter

Interface

3V3_D

+12

D₇

3V3_A

C₁₈

3V3_D

C₁₇

R₁₉

C₁₉

C₁₆

TXD/PRES

R₂

C₂

3V3_D

U₁

C₁

C₃

R₃

R₁

TX_OUT

39

49

53

25

12, 13, 14, 20

15, 16

43

6

41

51

R₁₈

T_REQ

A−

32

C₅

TXD

RXD

+12

26

27

35

34

37

38

R₅

A_OUT

Application

m Controller

52

1

R₄

R₆

D₁

B−

R₁₂

C₄

BR0

R₁₄

B_OUT

A+

54, 55

50

BR1

+12

R₇

R₁₃

RESB

C₁₀

D₂

C₆

R₈

B+

TEST

SDO

2

R₉

NCN49599

C₁₁

Tr₁

1:2

R₁₀

C₈

30

29

28

RX_OUT

RX_IN

45

46

SDI

Optional

External

Flash

D₃

D₄

C₇

SCK

MAINS

R₁₁

CSB

SEN

31

33

REF_OUT

47

C₉

8, 9, 10, 11,

17, 18, 36

ALC_IN

42

48

GPIO bus

3V3_A

D₅

24

22 19

4

5

23

44

7

3

56

21

3V3_D

PC20130109.1

R₁₅

Y₁

R₁₆

C₁₂

R₁₇

C₁₃

C₁₄

C₁₅

D₆

Figure 1. Typical Application for the NCN49599S−FSK Modem

Figure 1 shows an S−FSK PLC modem build around

NCN49599. For synchronization the line frequency is

coupled in via R15, a 1 MW resistor. The Schottky diode pair

components are tuned for a space and mark frequency of

63.3 and 74 kHz respectively, typically for e−metering in the

CENELEC A−band. The output of the amplifier is coupled

D clamps the voltage within the input range of the zero

cross detector. In the receive path a 2 order high pass filter

via a DC blocking capacitor C to a 2:1 pulse transformer

Tr1. The secondary of this transformer is coupled to the

5

10

nd

blocks the mains frequency. The corner point defined by C ,

mains via a high voltage capacitor C . High energetic

transients from the mains are clamped by the protection

7

11

th

C , R and R . In the transmit path a 3 order low pass

8

10

11

filter build around the internal power operational amplifier

suppresses the 2 and 3 harmonics to be in line with the

CENELEC EN 50065−1 specification. The filter

diode combination D , D together with D , D . Because the

mains is not galvanic isolated care needs to be taken when

interfacing to a microcontroller or a PC!

3 4 1 2

nd

rd

Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION

Component

Function − Remark

TX_OUT coupling capacitor

Typ Value

Tolerance

20 %

Unit

nF

C

470

68

1

2

3

4

5

Low pass transmit filter

10 %

pF

10 %

pF

3

10 %

pF

2,7

10 %

nF

C , C , C , C ,

18

6

16

17

Decoupling block capacitor

High pass receive filter

100

−20 +80%

nF

C

19

C , C

1

10 %

nF

7

8

C , C

V

; V decoupling cap − ceramic

DD1V8

10

−20 +80%

mF

9

13

REF_OUT

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NCN49599

Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION

Component

Function − Remark

TX coupling cap; 1A rms ripple @ 70 kHz

High Voltage coupling capacitor; 630 V

Zero Cross noise suppression

X−tal load capacitor

Typ Value

10

Tolerance

20%

Unit

mF

C

10

C

11

C

12

220

20%

nF

100

20%

pF

C

, C

36

20%

pF

14

15

R

Low pass receive filter

3,3

1%

kW

1

2

R

Low pass receive filter

8,2

1%

R , R , R , R , R

Low pass transmit and High pass receive filter; Voltage Bias ;

Pull up

3

7

8

9

12,

10

1%

kW

R

, R

R

13

18, 19

R

Low pass transmit filter

3

1%

5%

1%

5%

kW

W

4

5

6

Low pass transmit filter

1

Low pass transmit filter

1,6

R

10

R

11

R

14

R

15

R

16

R

17

High pass receive filter

15

High pass receive filter

30

0,47

TX Coupling resistor ; 0.5 W

Zero Cross coupling HiV

Current protection

1

MW

kW

5

ILIM LED current

3,3

D , D

High current Schottky Clamp diodes

Unidirectional transient voltage suppressor

Double low current Schottky clamp diode

ILIM LED indication (optional)

Bidirectional transient voltage suppressor

X−tall

MBRA430

P6SMB6.8AT3G

BAS70−04

LED

1

2

D , D

3

4

D

5

6

7

1

1SMA12CA

48 MHz

Y

Tr

2:1 Coupling transformer

PLC modem

1

U

NCN49599

1

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NCN49599

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating

Symbol

Min

Max

13.2

3.9

Unit

V

Absolute max. power amplifier supply

Absolute max. digital power supply

V

− 0.3

CC_ABSM

DD_ABSM

EE

SS

V

− 0.3

V

SSA

0.3

−

Absolute max. analog power supply

V

3.9

V

DDA_ABSM

Absolute max. difference between digital and analog power supply

Absolute max. difference between digital and analog ground

Absolute max. difference between digital and power ground

V

− V

−0.3

0.3

V

DD

DDA_ABSM

V

SS

SSA_ABSM

V

− V

EE_ABSM

SS

NON 5V SAFE PINS: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, XIN, XOUT, ENB, TDO, TDI, TCK, TMS, TRSTB, TEST

Absolute maximum input for normal digital inputs and analog inputs

Absolute maximum voltage at any output pin

V

SS

V

SS

− 0.3

V

DD

V

DD

+ 0.3

V

IN_ABSM

V

OUT_ABSM

5V SAFE PINS: TX_ENB, TXD, RXD, BR0, BR1, IO0 .. IO7, RESB

Absolute maximum input for digital 5V safe inputs

V

− 0.3

6.0

3.9

V

5VS_ABSM

SS

Absolute maximum voltage at 5V safe output pin

V

OUT5V_ABSM

SS

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Normal Operating Conditions

Operating ranges define the limits for functional operation and parametric characteristics of the device as described in the

Normal Operating Conditions section and for the reliability specifications as listed in Detailed Hardware Description section.

Functionality outside these limits is not implied.

Total cumulative dwell time outside the normal power supply voltage range or the ambient temperature under bias, must be

less than 0.1% of the useful life as defined in Detailed Hardware Description section.

Table 3. OPERATING RANGES

Rating

Symbol

Min

3.0

Max

3.6

Unit

V

Power Supply Voltage Range

V

DD

V

CC

Power Operational Amplifier Voltage Range

Junction Temperature Range

6.0

12.0

125

85

V

T

J

−40

°C

Ambient Temperature Range

T

A

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NCN49599

PIN DESCRIPTION

QFN Packaging

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

ALC_IN

TX_OUT

NC

TX_EN

TEST

RES

IO1

BR0

BR1

SEN

B−

B+

3

VEE

RLIM

ILIM

VDD

VSS

IO3

IO4

IO5

IO0

TDO

TDI

4

5

6

7

NCN49599

8

9

10

11

12

13

14

IO2

CSB

SDO

SDI

TCK

Figure 2. QFN Pin−out of NCN49599 (Top view)

Table 4. NCN49599QFN PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

B−

I/O

In

Type

A

Description

Negative (−) input of operational amplifier B

Positive (+) input of operational amplifier B

Negative supply for power amplifiers A and B

Output B current limit set resistor

Current limit logic flag

1

2

B+

In

A

3, 56

4

VEE

RLIM

ILIM

P

A

5

Out

D

6, 25

7, 24

VDD

VSS

P

3.3V digital supply

P

Digital ground

8..11, 17, 18,

32, 36

IO0 .. IO7

TDO

In/Out

Out

In

D, 5V Safe

General Purpose I/O’s

Test data output

12

13

D, 5V Safe,

PD

TDI

Test data input

14

15

16

D, 5V Safe,

PD

TCK

TMS

In

Test clock

D, 5V Safe,

PD

Test mode select

D, 5V Safe,

PD

TRSTB

EXT_CLK_EN

TXD/PRES

XIN

In

Test reset bar (active low)

External Clock Enable input

19

20

D, 5V Safe

A

Output of transmitted data (TXD) or PRE_SLOT signal

(PRES)

Out

In

21

Xtal input (can be driven by an external clock)

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NCN49599

Table 4. NCN49599QFN PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

I/O

Type

Description

22

Xtal output (output floating when XIN driven by external

clock)

XOUT

Out

A

23

26

VDD1V8

TXD

P

1V8 regulator output. Foresee a decoupling capacitor

SCI transmit output

D, 5V Safe,

OD

Out

27

28

29

30

31

33

RXD

SCK

SDI

In

Out

In

D, 5V Safe

SCI receive input (Schmitt trigger input)

SPI interface external Flash

SPI interface external Flash (Schmitt trigger input)

SPI interface external Flash

SDO

CSB

Out

In

SPI interface external Flash (Schmitt trigger input)

D, 5V Safe,

PD

SEN

In

SPI interface Enable external Flash

34

35

37

38

BR1

BR0

In

D, 5V Safe

SCI baud rate selection

RESB

Master reset bar (Schmitt trigger input, active low)

D, 5V Safe,

PD

TEST

In

Hardware Test enable (Schmitt trigger input)

TX enable (active low)

39

D, 5V Safe,

OD

TX_ENB

Out

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

NC

TX_OUT

ALC_IN

VDDA

VSSA

Not connected pin. Tie to GND.

Out

In

A

P

A

D

A

P

A

Transmitter output

Automatic level control input

3.3V analog supply

Analog ground

RX_OUT

RX_IN

REF_OUT

ZC_IN

ENB

Out

In

Output of receiver low noise operational amplifier

Positive input of receiver low noise operational amplifier

Reference output for stabilization

50/60 Hz input for mains zero cross detection

Enable / shutdown power amplifier (active low)

Positive (+) input of operational amplifier A

Negative (−) input of operational amplifier A

Output of operational amplifier A

Positive supply for power amplifiers A and B

Output of operational amplifier B

Out

In

A+

In

A−

In

A_OUT

VCC

Out

B_OUT1

B_OUT2

Out

P:

A:

D:

Power pin

5V Safe:

IO that support the presence of 5V on bus line

Analog pin

Out:

In:

Output signal

Input signal

Digital pin

PD:

OD:

Internal Pull Down resistor

Open Drain Output

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NCN49599

Table 5. NCN49599QFN PIN FUNCTION DESCRIPTION IN ROM MODE*

Pin No.

11

Pin Name

IO0/RX_DATA

IO2/T_REQ

IO1/CRC

I/O

Out

In

Type

Description

D, 5V Safe, OD

D, 5V Safe

Data reception indication (in ROM mode)

Transmit Request input (in ROM mode)

Correct frame CRC indication (in ROM mode)

32

36

Out

D, 5V Safe, OD

*ROM mode: IO0,IO1 and IO2 has predefined function when NCN49599 boots from ROM

Detailed Pin Description

VDDA

VDDA is the positive analog supply pin. Nominal voltage

is 3.3 V. A ceramic decoupling capacitor C = 100 nF must

DA

be placed between this pin and the VSSA. Connection path

of this capacitance to the VSSA on the PCB should be kept

as short as possible in order to minimize the serial resistance.

REF_OUT

REF_OUT is the analog output pin which provides the

voltage reference used by the A/D converter. This pin must

be decoupled to the analog ground by a 1 mF ceramic

capacitance C . The connection path of this capacitor to

DREF

the VSSA on the PCB should be kept as short as possible in

order to minimize the serial resistance.

VSSA

VSSA is the analog ground supply pin.

VDD

VDD is the 3.3 V digital supply pin. A ceramic decoupling

capacitor C = 100 nF must be placed between this pin and

DD

Figure 3: Recommended Layout of the Placement of

Decoupling Capacitors

the VSS. Connection path of this capacitance to the VSS on

the PCB should be kept as short as possible in order to

minimize the serial resistance.

RX_IN

VSS

RX_IN is the positive analog input pin of the receiver low

noise input op−amp. Together with RX_OUT and

REF_OUT, an active high pass filter is realized. This filter

removes the main frequency (50 or 60 Hz) from the received

signal. The filter characteristics are determined by external

capacitors and resistors. A typical application schematic can

be found in paragraph 50/60 Hz Suppression Filter.

VSS is the digital ground supply pin.

VDD1V8

This is an additional power supply pin to decouple an

internal LDO regulator. The decoupling capacitor should be

placed as close as possible to this output pin as illustrated in

Figure 3.

ZC_IN

VEE

ZC_IN is the mains frequency analog input pin. The signal

is used to detect the zero cross of the 50 or 60 Hz sine wave.

This information is used, after filtering with the internal

PLL, to synchronize frames with the mains frequency. In

case of direct connection to the mains it is advised to use a

series resistor of 1 MW in combination with two external

clamp diodes in order to limit the current flowing through

the internal protection diodes.

VEE is the ground of the power amplifier. It is important

to foresee a separate power ground line to this connection

able to conduct 1.2 A without significant voltage drop. A

recommended layout is illustrated in Figure 3.

VCC

VCC is the supply connection to the power amplifier. This

connection should be able to conduct 1.2 A without

significant voltage drop. A decoupling capacitor should be

placed as close as possible to this power pin as illustrated in

Figure 3.

RX_DATA (in ROM Mode Only)

RX_DATA is a 5 V compliant open drain output. An

external pull−up resistor defines the logic high level as

illustrated in Figure 4. A typical value for the pull−up

resistance “R” is 10 kW. The signal on this output depends

on the status of the data reception. If NCN49599 waits for

RX_OUT

RX_OUT is the output analog pin of the receiver low

noise input op−amp. This op−amp is in a negative feedback

configuration.

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7

NCN49599

configuration RX_DATA outputs a pulse train with a 10 Hz

frequency. After Synchronization Confirm Time out

RX_DATA 0. If NCN49599 is searching for

synchronization RX_DATA = 1.

The crystal is a classical parallel resonance type with its

fundamental frequency equal to 48 MHz. For a typical load

=

capacitance C = 18 pF specified by the manufacturer of the

L

crystal, the value of C = 36 pF. The crystal has to fulfill

X

impedance characteristics specified in the NCN49599 data

sheet. As an oscillator is sensitive and precise, it is advised

to put the crystal as close as possible on the board and to

ground the case.

+5V

R

XOUT

Output

XOUT is the analog output pin of the oscillator. When the

clock signal is provided from an external generator, this

output must be floating. When working with a crystal, this

pin cannot be used directly as clock output because no

additional loading is allowed on the pin (limited voltage

swing).

V_SSD

EXT_CLK_E

PC20090722.2

EXT_CLK_E allows the user to connect an external clock

instead of using a quartz. When this pin pulled to VDD an

external clock has to be applied to the XIN pin. When

EXT_CLK_E is connected to VSS, the quartz oscillator is

operational.

Figure 4. Representation of 5V Safe Output

TDO, TDI, TCK, TMS, and TRSTB

All these pins are part of the JTAG bus interface. The

JTAG interface is used during production test of the IC and

will not be described here. Input pins (TDI, TCK, TMS, and

TRSTB) contain internal pull−down resistance. TDO is an

output. When not used, the JTAG interface pins may be left

floating.

TXD

TXD is the digital output of the asynchronous serial

communication (SCI) unit. In half−duplex transmission

(when booting from ROM) and in full−duplex mode (booted

from Flash or after download over UART) it is used to

realize the communication between the NCN49599 and the

application microcontroller. The TXD is an open drain IO

(5 V safe). External pull−up resistances (typically 10 kW)

are necessary to generate the 5 V level. See Figure 4 for the

circuit schematic.

TXD/PRES

TXD/PRES is the output for either the transmitting data

(TX_DATA) or a synchronization signal with the time−slots

(PRE_SLOT). TXD/PRES. More information can be found

in paragraph Local Port.

XIN

RXD

XIN is the analog input pin of the oscillator. It is connected

to the interval oscillator inverter gain stage. The clock signal

can be created either internally with the external crystal and

two capacitors or by connecting an external clock signal to

XIN. For the internal generation case, the two external

capacitors and crystal are placed as shown in Figure 5. For

the external clock connection, the signal is connected to XIN

and XOUT is left unused.

This is the digital input of the asynchronous SCI unit. It is

used in both half−duplex and full−duplex transmission (see

TXD pin description). This pin supports a 5 V level. It is used

to realize the communication between the NCN49599 and

the application microcontroller. RXD is a 5 V safe input.

T_REQ (in ROM Mode Only)

T_REQ is the transmission request input of the Serial

Communication Interface when used in half−duplex mode.

When pulled low its initiate a local communication from the

application micro controller to NCN49599. T_REQ is a 5 V

safe input. See also paragraph Serial Communication

Interface.

XTAL_IN

XTAL_OUT

48 MHz

EXT_CLK_E

PC20120530.2

BR1, BR0

BR0 and BR1 are digital input pins. They are used to select

the baud rate (bits/second) of the Serial Communication

Interface unit in half−duplex mode. The rate is defined

according to Table 29 BR1, BR0 Baud Rate. The values are

taken into account after a reset, hardware or software.

Modification of the baud rate during function is not possible.

BR0 and BR1 are 5 V safe.

C_X

V_SSA

Figure 5. Placement of the Capacitors and Crystal

with Clock Signal Generated Internally

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NCN49599

CRC (in ROM Mode Only)

gain. Low threshold is fixed to 0.4 V. A value under this

threshold will result in an increase of the gain. The high

threshold is fixed to 0.6 V. A value over this threshold will

result in a decrease of the gain. A serial capacitance is used

to block the DC components. The level adaptation is

performed during the transmission of the first two bits of a

new frame. Eight successive adaptations are performed. See

also paragraph Amplifier with Automatic Level Control

(ALC).

CRC is a 5 V compliant open drain output. An external

pull−up resistor defines the logic high level as illustrated in

Figure 4. A typical value for this pull−up resistance “R” is

10 kW. The signal on this output depends on the cyclic

redundancy code result of the received frame. If the cyclic

redundancy code is correct CRC = H during the pause

between two time slots.

RESB

RESB is a digital input pin. It is used to perform a

hardware reset of the NCN49599. This pin supports a 5 V

voltage level. The reset is active when the signal is low

(0 V).

SCK, SDI, SDO, CSB

These signals form the SPI interface to an optional

external Flash. See Reference 1.

SEN

TEST

SEN is the SPI enable signal. When pulled low

NCN49599 will boot from the internal program ROM.

When pulled high (connected to VDD) the SPI interface is

active and the IC will boot from the external Flash. Boot up

sequences are described in more detail in Reference 1.

TEST is a digital input pin with internal pull down resistor

used to enable the Hardware Test Mode of the chip. When

TEST is left open or forced to ground Normal Mode is

enabled. When TEST is forced to VDD the Hardware Test

Mode is enabled. This mode is used during production test

of the IC and will not be described here. TEST pin is not 5 V

safe.

IO0 .. IO7

IO0 to IO7 are 8 general purpose input/output pins. When

booting from ROM (SEN = VSS) IO0 .. IO2 have predefined

functions: RX_DATA, CRC and T_REQ respectively.

When booting from external Flash the user have access to all

8 of them. More information can be found in Reference 1.

TX_ENB

TX_ENB is a digital output pin. It is low when the

transmitter is activated. The signal is available to turn on the

line driver. TX_ENB is a 5 V safe with open drain output,

hence a pull−up resistance is necessary achieve the

requested voltage level associated with a logical one. See

also Figure 4 for reference.

A−, A+, A_OUT, B−, B+, B_OUT1, B_OUT2

These are the interface pins to the 2 highly linear power

operational amplifiers. Op Amp B is capable to drive 1.2 A.

RLIM

TX_OUT

RLIM is the connection to the current limit set resistor

defining the current protection level of power Op Amp B .

Connecting a 5 kW resistor between RLIM and VEE sets the

TX_OUT is the analog output pin of the transmitter. The

provided signal is the S−FSK modulated frames. A filtering

operation must be performed to reduce the second and third

order harmonic distortion. For this purpose an active filter

is suggested. See also paragraph Transmitter Output

TX_OUT.

current limit to I

= 1.2 A.

LIMIT

ILIM

ILIM is the current limitation flag. This digital output is

logic high when the output current of Op Amp B I

>

OUT_B

ALC_IN

I

.

LIMIT

ALC_IN is the automatic level control analog input pin.

The signal is used to adjust the level of the transmitted

signal. The signal level adaptation is based on the AC

component. The DC level on the ALC_IN pin is fixed

internally to 1.65 V. Comparing the peak voltage of the AC

signal with two internal thresholds does the adaptation of the

ENB

This digital input enables both power amplifiers A and B

when ENB is driven low. A logic high will shutdown the

amplifiers and put the outputs A_OUT, B_OUT1 and

B_OUT2 in tri−state.

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NCN49599

ELECTRICAL CHARACTERISTICS

DC and AC Characteristics

Oscillator: Pin XIN, XOUT

In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on

the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.

Table 6. OSCILLATOR

Parameter

Crystal frequency

Test Conditions

(Note 1)

Symbol

Min

−100 ppm

35

Typ

Max

+100 ppm

65

Unit

MHz

%

f

48

CLK

Duty cycle with quartz connected

Start−up time

(Note 1)

T

15

ms

pF

startup

Load capacitance external crystal

Series resistance external crystal

(Note 1)

C

18

6

L

(Note 1)

R

1

60

15

W

S

Maximum Capacitive load on

XOUT

XIN used as clock input

CL

pF

XOUT

Low input threshold voltage

High input threshold voltage

Low output voltage

XIN used as clock input

VIL

0.3 V

V

XOUT

DD

VIH

0.7 V

DD

XOUT

XIN used as clock input,

XOUT = 2 mA

VOL

0.3

XOUT

High input voltage

XIN used as clock input

VOH

V

DD

− 0.3

V

XOUT

1. Guaranteed by design. Maximum allowed series loss resistance is 60 W

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10

NCN49599

Zero Cross Detector and 50/60 Hz PLL: Pin ZC_IN

Table 7. ZERO CROSS DETECTOR AND 50/60 HZ PLL

Parameter

Test Conditions

Symbol

Imp

Min

−20

−2

Typ

Max

20

Unit

mA

V

Maximum peak input current

Maximum average input current

Mains voltage (ms) range

ZC_IN

During 1 ms

Imavg

2

ZC_IN

With protection resistor at

ZC_IN

V

MAINS

90

550

Rising threshold level

Falling threshold level

Hysteresis

(Note 2)

VIR

VIF

1.9

V

ZC_IN

(Note 2)

0.85

0.4

45

ZC_IN

(Note 2)

VHY

V

ZC_IN

Lock range for 50 Hz (Note 3)

Lock range for 60 Hz (Note 3)

Lock time (Note 3)

MAINS_FREQ = 0 (50 Hz)

MAINS_FREQ = 0 (60 Hz)

MAINS_FREQ = 0 (50 Hz)

MAINS_FREQ = 0 (60 Hz)

MAINS_FREQ = 0 (50 Hz)

Flock

Tlock

55

66

15

20

0.1

Hz

s

50Hz

60Hz

50Hz

60Hz

54

Lock time (Note 3)

s

Frequency variation without going

out of lock (Note 3)

DF

Hz/s

60Hz

Frequency variation without going

out of lock (Note 3)

MAINS_FREQ = 0 (60 Hz)

DF

0.1

25

Hz/s

50Hz

Jitter of CHIP_CLK (Note 3)

2. Measured relative to VSS

Jitter

−25

ms

CHIP_CLK

3. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed

by the digital test patterns.

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11

NCN49599

Transmitter External Parameters: Pin TX_OUT, ALC_IN, TX_ENB

To guarantee the transmitter external specifications the TX_CLK frequency must be 12 MHz 100 ppm.

Table 8. TRANSMITTER EXTERNAL PARAMETERS

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

Maximum peak output level

f

= 23 kHz

V

0.85

0.76

1.15

1.22

Vp

TX_OUT

f

= 148.5 kHz

TX_OUT

Level control at max. output

Second order harmonic distortion

Third order harmonic distortion

f

= 148.5 kHz

HD2

HD3

−55

−57

30

dB

Hz

pF

kW

TX_OUT

Level control at max. output

f

= 148.5 kHz

TX_OUT

Level control at max. output

Frequency accuracy of the gener-

ated sine wave

(Notes 4 and 6)

Df

TX_OUT

Capacitive output load at pin

TX_OUT

(Note 4)

(Note 5)

CL

TX_OUT

20

Resistive output load at pin

TX_OUT

RL

TX_OUT

5

Turn off delay of TX_ENB output

Td

0.25

2.9

0.5

3.1

ms

dB

TX_ENB

Automatic level control attenuation

step

ALC

step

Maximum attenuation

ALC

20.3

0.46

0.72

111

21.7

0.34

0.54

189

dB

V

range

ALC_IN

Low threshold level on ALC_IN

High threshold level on ALC_IN

Input impedance of ALC_IN pin

VTL

VTH

V

R

kW

dB

Power supply rejection ration of the

transmitter section

(Note 7)

(Note 8)

PSRR

10

35

TX_OUT

4. This parameter will not be tested in production.

5. This delay corresponds to the internal transmit path delay and will be defined during design.

6. Taking into account the resolution of the DDS and an accuracy of 100 ppm of the crystal.

7. A sinusoidal signal of 10 kHz and 100 mVpp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The

signal level at TX_OUT is measured to determine the parameter.

8. A sinusoidal signal of 50 Hz and 100 mVpp is injected between VDDA and VSSA. The digital AD converter generates an idle pattern. The

signal level at TX_OUT is measured to determine the parameter.

The LPF filter + amplifier must have a frequency characteristic between the limits listed below. The absolute output level

depends on the operating condition. In production the measurement will be done for relative output levels where the 0 dB

reference value is measured at 50 kHz with a signal amplitude of 100 mV.

Table 9. TRANSMITTER FREQUENCY CHARACTERISTICS

Attenuation

Min

−0.5

−1.3

−4.5

Max

0.5

Frequency (kHz)

Unit

dB

10

145.5

195

0.5

−1.5

−3.0

−18.0

−36.0

−50

245

500

1000

2000

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12

NCN49599

Receiver External Parameters: Pin RX_IN, RX_OUT, REF_OUT

Table 10. RECEIVER EXTERNAL PARAMETERS

Parameter

Input offset voltage 42 dB

Input offset voltage 0 dB

Test Conditions

Symbol

Min

Typ

Max

5

Unit

mV

Vp

AGC gain = 42 dB

AGC gain = 0 dB

V

OFFS_RX_IN

50

Max. peak input voltage (corres-

ponding to 62.5% of the SD full

scale)

AGC gain = 0 dB (Note 9)

V

0.85

1.15

MAX_RX_IN

Input referred noise of the analog

receiver path

AGC gain = 42 dB

(Notes 9 and 10)

NF

150

1

nV/ǠHz

mA

RX_IN

Input leakage current of receiver

input

I

−1

LE_RX_IN

Max. current delivered by

REF_OUT

I

−300

300

mA

Max_REF_OUT

Power supply rejection ratio of the

receiver input section

AGC gain = 42 dB (Note 11)

AGC gain = 42 dB (Note 12)

PSRR

10

35

dB

V

LPF_OUT

AGC gain step

AGC range

AGC

5.5

6.5

step

AGC

39.9

1.52

44.1

1.78

range

Analog ground reference output

voltage

V

REF_OUT

Signal to noise ratio at 62.5 % of

the SD full scale

(Notes 9 and 13)

SN

54

dB

Vp

AD_OUT

Clipping level at the output of the

gain stage (RX_OUT)

V

1.05

1.65

CLIP_AGC_IN

9. Input at RX_IN, no other external components.

10.Characterization data only. Not tested in production.

11. A sinusoidal signal of 10 kHz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT and

REF_OUT output is measured to determine the parameter.

12.A sinusoidal signal of 50 Hz and 100 mVpp is injected between VDDA and VSSA. The signal level at the differential LPF_OUT output is

measured to determine the parameter.

13.These parameters will be tested in production with an input signal of 95 kHz and 1 Vp by reading out the digital samples at the point AD_OUT

with the default settings of T_RX_MOD[7], SDMOD_TYP, DEC_TYP, and COR_F_ENA. The AGC gain is switched to 0 dB.

The receive LPF filter + AGC + low noise amplifier must have a frequency characteristic between the limits listed below.

The absolute output level depends on the operating condition.

Table 11. RECEIVER FREQUENCY CHARACTERISTICS

Attenuation

Min

−0.5

−1.3

−4.5

Max

0.5

Frequency (kHz)

Unit

dB

10

148.5

195

0.5

−2.0

−3.0

−18.0

−36.0

−50

245

500

1000

2000

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13

NCN49599

Power Amplifier Parameters: Pin A+, A−, A_OUT, B+, B−, BOUT1&2, VSS, VEE, ENB

Table 12. POWER AMPLIFIER GENERAL PARAMETERS

Parameter

Output shutdown time

Output enable time

Quiescent Current

Test Conditions

ENB 0 ³ 1

ENB 1 ³ 0

ENB = 0

Symbol

Min

Typ

60

Max

Unit

ns

5

10

40

ms

I

20

mA

°C

Q_EN

ENB = 1

I

140

+160

+135

200

Q_DIS

Thermal shutdown

(Note 14)

+150

Recovery from thermal shutdown

(Note 14)

°C

14.Characterization data only. Not tested in production.

Table 13. POWER AMPLIFIER EXTERNAL PARAMETERS OP AMP A

Parameter

Input Offset Voltage

Test Conditions

= +12 V, V = 0 V

Symbol

Min

Typ

3

Max

10

Unit

mV

V

CC

V

OS

EE

Offset vs Power Supply

Input Bias Current

V

CC

= +6 V, V = *6 V

PSRR

25

150

1

mV/V

nA

EE

(Note 15)

I

B

Input Voltage Noise Density

f = 1 kHz, V = GND,

e

n

250

nV/ǠHz

IN

BW = 131 kHz (Note 15)

Common−Mode Voltage Range

Common−Mode Rejection Ratio

Differential input impedance

Common−Mode input impedance

Open−Loop Gain

V

EE

−0.1

V − 3

CC

V

dB

CM

V

EE

* 0.1 v V

v V * 3

CMRR

70

85

0.2 | 1.5

0.2 | 3

100

CM

CC

GW | pF

dB

R = 500 W (Note 15)

L

80

Gain Bandwidth Product

Full Power Bandwidth

GWP

80

MHz

V/ ms

%

G = +5, V = 11 V (Note 15)

0.2

1.5

out

PP

Slew Rate

SR

60

Total Harmonic Distortion + Noise

THD+N

0.015

G = +1, R = 500 W, V = 8

L

O

V

PP

, f = 1 kHz, C = 220 mF,

IN

C

= 330 mF

OUT

G = +1, R = 50 W, V = 8 V ,

PP

THD+N

0.023

%

L

O

f = 100 kHz, C = 220 mF,

IN

C

= 330 mF

OUT

Voltage Output Swing from Rail

From Positive Rail

V

= +12 V, V = 0 V

CC

EE

IL = − 12 mA

V

0.3

1

V

OH

From Negative Rail

IL = + 12 mA

V

1

OL

SC

Short*Circuit Current

Output Impedance

I

280

0.25

mA

W

Closed Loop G = +4,

f = 100 kHz

Z

0

Capacitive Load Drive

C

100

pF

LOAD

15.Characterization data only. Not tested in production.

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14

NCN49599

Table 14. POWER AMPLIFIER EXTERNAL PARAMETERS OP AMP B

Parameter

Input Offset Voltage

Test Conditions

Symbol

Min

Typ

3

Max

10

Unit

mV

V

= +12 V, V = 0 V

V

OS

CC

EE

Offset vs Power Supply

Input Bias Current

= +12 V, V = 0 V

PSRR

25

150

1

mV/V

nA

EE

(Note 16)

I

B

Input Voltage Noise Density

f = 1 kHz, V = GND,

e

n

125

nV/ǠHz

IN

BW = 131 kHz

Common*Mode Voltage Range

Common*Mode Rejection Ratio

Differential input impedance

Common*Mode input impedance

Open*Loop Gain

V

EE

−0.1

V − 3

CC

V

dB

CM

V

* 0.1 v V

v V * 3

CMRR

GWP

70

85

0.2 | 11

0.2 | 22

100

EE

CM

CC

GW | pF

dB

R = 5 W (Note 16)

L

80

Gain Bandwidth Product

Full Power Bandwidth

60

MHz

kHz

G = +2, V = 11 V (Note 16)

200

400

out

PP

Slew Rate

SR

70

V/ ms

%

Total Harmonic Distortion + Noise

THD+N

0.015

G = +1, R = 50 W, V = 8 V ,

PP

L

O

f = 1 kHz

G = +1, R = 50 W, V = 8 V ,

PP

THD+N

0.067

%

L

O

f = 100 kHz

Voltage Output Swing from Rail

From Positive Rail

V

= +12 V, V = 0 V

CC

EE

I

= − 1.2 A @ T = 25°C

V

0.7

0.4

1

V

A

OUT

J

OH

I

= − 1.0 A @ T = 125°C

V

1

OUT

J

OH

SC

From Negative Rail

I

= + 1.2 A @ T = 25°C

OUT

J

I

= + 1.0 A @ T = 125°C

J

OUT

Short*Circuit Current

R

= 5 kW

I

1.2

LIM

Output Impedance

Closed Loop G = +1,

f = 100 kHz

Enabled Mode

Shutdown Mode

ENB = 0

ENB = 1

Z

0.065

12

W

MW

nF

0

Capacitive Load Drive

C

500

LOAD

16.Characterization data only. Not tested in production.

Power−on−Reset (POR)

Table 15. POWER−ON−RESET

Parameter

POR threshold

Test Conditions

Symbol

Min

2.1

1

Typ

Max

Unit

V

POR

2.7

Power supply rise time

0 to 3V

T

RPOR

ms

Digital Outputs: TDO, CLK_OUT

Table 16. DIGITAL OUTPUTS: TDO, CLK_OUT

Parameter

Low output voltage

High output voltage

Test Conditions

Symbol

Min

Typ

Max

Unit

V

I

= 3 mA

V

OL

0.4

XOUT

I

= −3 mA

V

OH

0.85 V

DD

V

XOUT

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15

NCN49599

Digital Outputs with Open Drain: TX_ENB, TXD

Table 17. DIGITAL OUTPUTS WITH OPEN DRAIN: TX_ENB, TXD, RX_DATA, CRC, T_REQ

Parameter

Low output voltage

Test Conditions

= 4 mA

Symbol

Min

Typ

Max

Unit

I

V

OL

0.4

V

XOUT

Digital Inputs: BR0, BR1

Table 18. DIGITAL INPUTS: BR0, BR1

Parameter

Test Conditions

Symbol

Max

Unit

V

Low input level

V

IL

0.2 V

DD

High input level

0 to 3 V

V

IH

0.8 V

V

DD

Input leakage current

I

−10

10

mA

LEAK

Digital Inputs with Pull Down: TDI, TMS, TCK, TRSTB, TEST

Table 19. DIGITAL INPUTS WITH PULL DOWN: TDI, TMS, TCK, TRSTB, TEST

Parameter

Low input level

Test Conditions

Symbol

Min

Typ

Max

Unit

V

0.2 V

IL

IH

DD

High input level

V

0.8 V

7

V

DD

Pull down resistor

(Note 17)

R

50

kW

PU

17.Measured around a bias point of V /2.

DD

Digital Schmitt Trigger Inputs: RXD, RESB

Table 20. DIGITAL SCHMITT TRIGGER INPUTS: RXD, RESB

Parameter

Rising threshold level

Falling threshold level

Input leakage current

Test Conditions

Symbol

Min

Typ

Max

Unit

V

0.80 V

T+

DD

0.2 V

V

T−

DD

I

−10

10

mA

LEAK

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16

NCN49599

Current Consumption

Table 21. CURRENT CONSUMPTION

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

Current consumption in receive mode

Current through V and V

I

RX

60

mA

DD

DDA

(Note 18)

Current consumption in transmit mode

Current consumption when RESB = 0

Current through V and V

I

TX

60

4

mA

DD

(Note 18)

Current through V and V

I

RESET

DD

(Note 18)

Current consumption when ENB = 0

Current consumption when ESNB = 1

Quiescent current though V

I

20

40

mA

CC

Q_EN

I

120

150

mA

CC

Q_HiZ

18.f

= 48 MHz.

CLK

INTRODUCTION

General Description

is done through a serial interface. The digital processing of

the signal is partitioned between hardwired blocks and a

microprocessor block. The microprocessor is controlled by

firmware. Where timing is most critical, the functions are

implemented with dedicated hardware. For the functions

where the timing is less critical, typically the higher level

functions, the circuit makes use of the ARM microprocessor

core.

The processor runs DSP algorithms and, at the same time,

handles the communication protocol. The communication

protocol, in this application, contains the MAC = Medium

Access Control Layer. The program is stored in a masked

ROM. Depending on the status of the SEN input, after power

on reset NCN49599 will boot from internal ROM or external

Flash or over the Serial Communication Interface. The

working data necessary for the processing is stored in an

internal RAM. At the back−end side the link to the

The NCN49599 is a single chip half duplex S−FSK

modem dedicated to power line carrier (PLC) data

transmission on low− or medium−voltage power lines. The

device offers complete handling of the protocol layers from

the physical up to the MAC. NCN49599 complies with the

CENELEC EMC standard EN 50065−1 and the

IEC 61334−5−1 standards. It operates from a 3.3 V and

12 V power supply and is interfaced to the power line by an

integrated power amplifier and transformer. An internal

PLL is locked to the mains frequency and is used to

synchronize the data transmission at data rates of 300, 600,

1200, 2400 and 4800 baud for a 50 Hz mains frequency, or

360, 720, 1440, 2880 and 5760 baud for a 60 Hz mains

frequency. In both cases this corresponds to 3, 6, 12 or 24

data bits per half cycle of the mains period.

S−FSK is a modulation and demodulation technique that

combines some of the advantages of a classical spread

spectrum system (e.g. immunity against narrow band

interferers) with the advantages of the classical FSK system

(low complexity). The transmitter assigns the space

frequency f^Sto “data 0” and the mark frequency fM to

“data 1”. The difference between S−FSK and the classical

FSK lies in the fact that f^Sand fM are now placed far from

each other, making their transmission quality independent

from each other (the strengths of the small interferences and

the signal attenuation are both independent at the two

frequencies). The frequency pairs supported by the

NCN49599 are in the range of 9 − 150 kHz with a typical

separation of 10 kHz.

application hardware is provided by

a

Serial

Communication Interface (SCI). The SCI is an easy to use

serial interface, which allows communication between an

external processor used for the application software and the

NCN49599 modem. The SCI works on two wires: TXD and

RXD. Baud rate is programmed by setting 2 bits (BR0,

BR1).

Because the low protocol layers are handled in the circuit,

the NCN49599 provides an innovative architectural split.

Thanks to this, the user has the benefit of a higher level

interface of the link to the PLC medium. Compared to an

interface at the physical level, the NCN49599 allows faster

development of applications. The user just needs to send the

raw data to the NCN49599 and no longer has to take care of

the protocol detail of the transmission over the specific

medium. This last part represents usually 50% of the

software development costs.

The conditioning and conversion of the signal is

performed at the analog front−end of the circuit. The further

processing of the signal and the handling of the protocol is

digital. At the back−end side, the interface to the application

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17

NCN49599

CLIENT

Application

SERVER

Application

SERVER

Application

SPY

Application

TEST

Application

NCN49597in

MASTER mode

NCN49597 in

SLAVE mode

NCN49597in

SLAVE mode

NCN49597in

MONITOR mode

NCN49597in

TEST mode

Major User Type

Figure 6. Application Examples

Minor User Type

PC201111 12.2

NCN49599 is intended to connect equipment using

Distribution Line Carrier (DLC) communication. It serves

two major and two minor types of applications:

• Major types:

• Minor type:

♦ Spy or Monitor:

Spy or Monitor mode is used to only listen to the

data that comes across the power line. Only the

physical layer frame correctness is checked. When

the frame is correct, it is passed to the external

processor.

♦ Master or Client:

A Master is a client to the data served by one or

many slaves on the power line. It collects data from

and controls the slave devices. A typical application

is a concentrator system

♦ Test Mode:

The Software Test Mode is used to test the

compliance of a PLC modem conforms to

CENELEC. EN 50065−1 by a continuous broadcast

♦ Slave or Server:

A Slave is a server of the data to the Master. A

typical application is an electricity meter equipped

with a PLC modem.

of f or f .

S

M

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18

NCN49599

Functional Description

The block diagram below represents the main functional units of the NCN49599:

VCC

A_OUT

A− A+

B− B+ RLIM ILIM

VDD1V8 VDDA

VDDD

B_OUT1

B_OUT2

EN

NCN49599

Current

Protect

B

A

TSD

Communication Controller

Power Amplifier

TxD

RxD

Serial

Comm.

Interface

Transmitter (S−FSK Modulator)

TO Application

Micro Controller

T_REQ

BR0

TX_ENB

TX_OUT

ALC_IN

LP

Filter

Transmit Data

& Sine Synthesizer

BR1

D/A

5

IO[7:3]

RX_DATA

CRC

Local Port

ARM

Risc

Core

TXD/PRES

Receiver (S−FSK Demodulator)

5

RX_OUT

RX_IN

JTAG I/F

TEST

Test

Control

FROM

Line Coupler

S−FSK

Demodulator

AAF

AGC

A/D

RESB

POR

Watchdog

Timer 1 & 2

REF

REF_OUT

ZC_IN

4

SPI I/F

SEN

TO

Flash SPI

External Flash

Clock and Control

Zero

crossing

Clock Generator

& Timer

Program/Data Program

RAM ROM

Interrupt

Control

PLL

OSC

PC20130109.2

VEE

VSSA

VSSD

XIN XOUT EXT_CLK_E

Figure 7. S−FSK Modem NCN49599 Block Diagram

Power Amplifier

The Power Amplifier block contains a Class A/B, low

distortion line driver. Its design is optimized to accept a

signal from the transmitter. The output stage is designed to

drive up to 1.2 A peak into an isolation transformer or simple

coil coupling to the mains. At output current of 1.2 A, the

output voltage is guaranteed to swing within 1 V or less of

either rail giving the user improved SNR. The input stage

contains an operational amplifier which can be configured

as a unity gain follower buffer or used to provide the first

stage of a 4−pole low pass filter. Current protection is set

with a single resistor, RLIM, together with a current limit

flag. Thermal protection is set by a voltage level at the

VWARN pin. The output stage goes into a high−impedance

state once the junction temperature has exceeded +150°C.

automatic gain control (AGC) block. This operation

maximizes the dynamic range of the incoming signal. The

signal is then converted to its digital representation using

sigma delta modulation. From then on, the processing of the

data is done in a digital way. By using dedicated hardware,

a direct quadrature demodulation is performed. The signal

demodulated in the base band is then low pass filtered to

reduce the noise and reject the image spectrum.

Clock and Control

According to the IEC 61334−5−1 standard, the frame data

is transmitted at the zero cross of the mains voltage. In order

to recover the information at the zero cross, a zero cross

detection of the mains is performed. A phase−locked loop

(PLL) structure is used in order to allow a more reliable

reconstruction of the synchronization. This PLL permits as

well a safer implementation of the ”repetition with credit”

function (also known as chorus transmission). The clock

generator makes use of a precise quartz oscillator master.

The clock signals are then obtained by the use of a

programmed division scheme. The support circuits are also

contained in this block. The support circuits include the

necessary blocks to supply the references voltages for the

AD and DA converters, the biasing currents and power

supply sense cells to generate the right power off and startup

conditions.

Transmitter

The NCN49599 Transmitter function block prepares the

communication signal which will be sent on the

transmission channel during the transmitting phase. This

block is connected to a power amplifier which injects the

output signal on the mains through a line−coupler.

Receiver

The analog signal coming from the line−coupler is low

pass filtered in order to avoid aliasing during the conversion.

Then the level of the signal is automatically adapted by an

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19

NCN49599

t

48 bit @ 2400 baud

PC20100609.1

20 ms

Figure 8. Data Stream is in Sync with Zero Cross of the Mains (example for 50 Hz)

Communication Controller

Local Port

The Communication Controller block includes the

micro−processor, its peripherals: RAM, ROM, UART,

TIMER, and the Power on reset. The processor uses the

ARM Reduced Instruction Set Computer (RISC)

architecture optimized for IO handling. For most of the

instructions, the machine is able to perform one instruction

per clock cycle. The microcontroller contains the necessary

hardware to implement interrupt mechanisms, timers and is

able to perform byte multiplication over one instruction

cycle. Depending on the status of the SEN input, after power

on reset NCN49599 will boot from internal ROM, external

Flash or over the Serial Communication Interface. Booting

from ROM will make the modem work conform to the

IEC−61334−5 standard. The RAM contains the necessary

space to store the working data. The back−end interface is

done through the Serial Communication Interface block

which works in half−duplex or full−duplex mode. This

back−end is used for data transmission with the application

micro controller and for the definition of the modem

configuration.

The controller uses 3 output ports to inform about the

actual status of the PLC communication. RX_DATA

indicates if Receiving is in progress, or if NCN49599 is

waiting for synchronization, or of it configures. CRC

indicates if the received frames are valid (CRC = OK).

TXD/PRES is the output for either the transmitting data

(TX_DATA) or a synchronization signal with the time−slots

(PRE_SLOT).

Serial Communication Interface

When booting from ROM the local communication is a

half duplex asynchronous serial link using a receiving input

(RxD) and a transmitting output (TxD). The input port

T_REQ is used to manage the local communication with the

application micro controller and the baud rate can be

selected depending on the status of two inputs BR0, BR1.

These two inputs are taken in account after an NCN49599

reset. Thus when the application micro controller wants to

change the baud rate, it has to set the two inputs and then

provoke a reset. When booting from Flash or over the SCI,

the Serial Communication Interface is Full Duplex.

DETAILED HARDWARE DESCRIPTION

Clock and Control

block is the clock signal CHIP_CLK, 8 times over sampled

with the bit rate. The oscillator makes use of precise 48 MHz

quartz. This clock signal together with CHIP_CLK is fed

into the Clock Generator and time block. Here several

internal clock signals and timings are obtained by the use of

a programmed division scheme.

According to the IEC 61334−5−1 standard, the frame data

is transmitted at the zero cross of the mains voltage. In order

to recover the information at the zero cross, a zero cross

detection of the mains is performed. A phase−locked loop

(PLL) structure is used in order to allow a more reliable

reconstruction of the synchronization. The output of this

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NCN49599

Clock and Control

CHIP_CLK

Zero

crossing

Clock Generator

& Timer

PLL

OSC

ZC_IN

PC20120530.1

EXT_CLK_E

XIN

XOUT

Figure 9. Clock and Control Block

Zero Cross Detector

case of direct connection to the mains it is advised to use a

series resistor of 1 MW in combination with two external

Schottky clamp diodes in order to limit the current flowing

through the internal protection diodes.

ZC_IN is the mains frequency analog input pin. The signal

is used to detect the zero cross of the 50 or 60 Hz sine wave.

This information is used, after filtering with the internal

PLL, to synchronize frames with the mains frequency. In

Clock & Control

3V3_A

BAS70−04

FROM

MAINS

ZC_IN

1 MW

ZeroCross

CHIP_CLK

Debounce

PLL

Filter

100 pF

PC2010608.1

Figure 10. Zero Cross Detector with Falling Edge De−bounce Filter

The zero cross detector output is logic zero when the input

is lower than the falling threshold level and a logic one when

the input is higher than the rising threshold level. The falling

edges of the output of the zero cross detector are de−bounced

by a period between 0.5 ms and 1 ms. The Rising edges are

not de−bounced.

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NCN49599

V_MAINS

VIR_{ZC_IN}

VIF_{ZC_IN}

t

ZeroCross

t_ZCD

t_DEBOUNCE= 0,5 .. 1 ms

10 ms

PC20090620.1

Figure 11. Zero Cross Detector Signals and Timing (example for 50 Hz)

50/60 Hz PLL

crossings. The PLL locks on the zero cross from negative to

positive phase. The bit rate is always an even multiple of the

mains frequency, so following combinations are possible:

The output of the zero cross detector is used as an input for

a PLL. The PLL generates the clock CHIP_CLK which is 8

times the bit rate and which is in phase with the rising edge

Table 22. CHIP_CLK IN FUNCTION OF SELECTED BAUD RATE AND MAINS FREQUENCY

BAUD[2:0]

000

MAINS_FREQ

Baudrate

300

CHIP_CLK

2400 Hz

4800 Hz

9600 Hz

19200 Hz

38400 Hz

2880 Hz

5760 Hz

11520 Hz

23040 Hz

46080 Hz

001

600

010

1200

2400

4800

360

50 Hz

011

100

000

001

720

010

1440

2880

5760

60 Hz

011

100

In case no zero crossings are detected the PLL freezes its internal timers in order to maintain the CHIP_CLK timing.

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NCN49599

V_MAINS

VIR_{ZC _IN}

t

6 bit @ 300 baud

ZeroCross

t_ZCD

PLL in lock

CHIP _CLK

Start of Physical PreFrame (*)

10 ms

PC20090 619 .3

*The start of the Physical Subframe is shifted back with R_ZC_ADJUST[7:0] x 13 mS = t

to compensate for the zero cross delay.

ZCD

Figure 12. Zero Cross Adjustment to Compensate for Zero Cross Delay (example for 50 Hz)

The phase difference between the zero cross of the mains

and CHIP_CLK can be tuned. This opens the possibility to

a number value stored in register R_ZC_ADJUST[7:0]. The

adjustment period or granularity is 13 ms. The maximum

adjustment is 255 x 13 ms = 3.32 ms which corresponds with

compensate for external delay t

(e.g. opto coupler) and

ZCD

th

for the 1.9 V positive threshold VIR

of the zero cross

1/6 of the 50 Hz mains sine period.

ZC_IN

detector. This is done by pre−loading the PLL counter with

Table 23. ZERO CROSS DELAY COMPENSATION

R_ZC_ADJUST[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

…

Compensation

0 ms

13 ms

26 ms

39 ms

…

1111 1111

3315 ms

Oscillator

The oscillator works with a standard parallel resonance

crystal of 48 MHz. XIN is the input to the oscillator inverter

gain stage and XOUT is the output.

XIN

XOUT

EXT_CLK_E

PC20120530.2

48 MHz

C_X

V_SSA

Figure 13. Placement of the Capacitors and Crystal

with Clock Signal Generated Internally

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NCN49599

For correct functionality the external circuit illustrated in

Figure 13 must be connected to the oscillator pins. For a

f

is equal to f

/ 8 or 6 MHz. All the receiver

RX_CLK

CLK

internal clock signals will be derived from f

RX_CLK.

crystal requiring a parallel capacitance of 18 pF C must be

X

Clock Generator and Timer

around 36 pF. (Values of capacitors are indicative only and

are given by the crystal manufacturer). To guarantee startup

the series loss resistance of the crystal must be smaller than

The CHIP_CLK and f

are used to generate a number

CLK

of timing signals used for the synchronization and interrupt

generation. The timing generation has a fixed repetition rate

which corresponds to the length of a physical subframe. (see

paragraph Reference 1)

The timing generator is the same for transmit and receive

mode. When NCN49599 switches from receive to transmit

and back from transmit to receive, the R_CHIP_CNT

counter value is maintained. As a result all timing signals for

receive and transmit have the same relative timing. The

following timing signals are defined as:

60 W. EXT_CLK_E should be strapped to V . If an

SSA

external clock of 48 MHz is used, this signal should be

connected to XIN and EXT_CLK_E needs to be pulled to

V

DD

The oscillator output f

= 48 MHz is the base frequency

CLK

for the complete IC. The clock frequency for the ARM f

ARM

= f

The clock for the transmitter, f

is equal to

CLK.

TX_CLK

f

/ 4 or 12 MHz. All the transmitter internal clock signals

CLK

will be derived from f

. The clock for the receiver,

TX_CLK

Start of the physical subframe

2871 2872

2879

0

1

2

3

4

5

6

7

8

9

63

64

65

R_CHIP_CNT

CHIP_CLK

BIT_CLK

BYTE_CLK

FRAME_CLK

PRE_BYTE_CLK

PRE_FRAME_CLK

PRE_SLOT

PC20090619.1

Figure 14. Timing Signals

CHIP_CLK: is the output of the PLL and 8 times the bit rate

on the physical interface. See also paragraph 50/60 Hz PLL.

PRE_BYTE_CLK is a signal which is 8 CHIP_CLK

sooner than BYTE_CLK. This signal is used as an interrupt

for the internal microcontroller and indicates that a new byte

for transmission must be generated.

BIT_CLK: is active at counter values 0, 8, 16, .. 2872 and

inactive at all other counter values. This signal is used to

indicate the transmission of a new bit.

PRE_FRAME_CLK is a signal which is 8 CHIP_CLK

sooner than FRAME_CLK. This signal is used as an

interrupt for the internal microcontroller and indicates that

a new frame will start at the next FRAME_CLK.

BYTE_CLK: is active at counter values 0, 64, 128, .. 2816

and inactive at all other counter values. This signal is used

to indicate the transmission of a new byte.

PRE_SLOT is logic 1 between the rising edge of

PRE_FRAME_CLK and the rising edge of FRAME_CLK.

This signal can be provided at the digital output pin

FRAME_CLK: is active at counter values 0 and inactive at

all other counter values. This signal is used to indicate the

transmission or reception of a new frame.

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NCN49599

TXD/PRES when R_CONF[7] = 0 (See paragraph Local

signal conditioning step, a digital to analog conversion is

performed. As for the receive path, a sigma delta modulation

technique is used. In the analog domain, the signal is low

pass filtered, in order to remove the high frequency

quantization noise, and passed to the automatic level

controller (ALC) block, where the level of the transmitted

signal can be adjusted. The determination of the signal level

is done through the sense circuitry.

Port and Table 26, field R_CONF_TXD_PRES_SEL) and can

be used by the external host controller to synchronize its

software with the FRAME_CLK of NCN49599.

Transmitter Path Description (S−FSK Modulator)

For the generation of the space and mark frequencies, the

direct digital synthesis (DDS) of the sine wave signals is

performed under the control of the microprocessor. After a

Transmitter(S−FSK Modulato)r

TX_EN

ALC

control

ARM

Interface

&

ALC_IN

Control

LP

Filter

Transmit Data

& Sine Synthesizer

TX_OUT

D/A

f_MIf_MQ

f_SI

f_SQ

TO RECEIVER

PC20091019.1

Figure 15. Transmitter Block Diagram

Sine Wave Generator

ARM Interface and Control

The interface with the ARM consists in a 8−bit data

registers R_TX_DATA, 2 control registers R_TX_CTRL

and R_ALC_CTRL, a flag TX_RXB defining transmit and

receive and 2 16−bit wide frequency step registers R_FM

A sine wave is generated with a direct digital synthesizer

DDS. The synthesizer generates in transmission mode a sine

wave either for the space frequency (f , data 0) or for the

S

mark frequency (f , data1). In reception the synthesizer

M

and R_FS defining f (mark frequency = data 1) and f

generates the sine and cosine waves for the mixing process,

M

S

(space frequency = data 0). All these registers are memory

mapped. Some of them are for internal use only and cannot

be accessed by the user.

f , f , f , f

quadrature). The space and mark frequencies are defined in

an individual step 16 bit wide register.

(space and mark signals in phase and

SI SQ MI MQ

Processing of the physical frame (preamble, MAC

address, CRC) is done by the ARM.

Table 24. FS AND FM STEP REGISTERS

ARM Register

R_FS[15:0]

Hard Reset

0000h

Soft Reset

0000h

Description

Step register for the space frequency f

S

R_FM[15:0]

0000h

Step register for the mark frequency f

M

18

The space and mark frequency can be calculated as:

• R_FS[15:0]_dec = Round(2 x f /f

)

S

DDS

18

• f = R_FS[15:0]_dec x f

/2

S

DDS

• R_FM[15:0]_dec = Round(2 x f /f

)

M

DDS

18

• f = R_FM[15:0]_dec x f

/2

DDS

♦ Where f

= 3 MHz is the direct digital

M

DDS

synthesizer clock frequency.

Or the content of both R_FS[15:0] and R_FM[15:0] are

defined as:

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NCN49599

After a hard or soft reset or at the start of the transmission

(when TX_RXB goes from 0 to 1) the phase accumulator

must start at it’s 0 phase position, corresponding with a 0 V

TX_ENB is 1 when the NCN49599 is in receive mode.

TX_ENB is 0 when NCN49599is in transmit mode. When

going from transmit to receive mode (TX_RXB goes from

1 to 0) the TX_ENB signal is kept active for a short period

output level. When switching between f and f the phase

M

S

accumulator must give a continuous phase and not restart

from phase 0

of t

.

dTX_ENB

The control logic for the transmitter generates a signal

When NCN49599 goes into receive mode (when

TX_RXB goes from 1 to 0) the sine wave generator must

make sure to complete the active sine period.

The control logic for the transmitter generates a signal

TX_ENB to enable the integrated power amplifier.

TX_DATA which corresponds to the transmitted S−FSK

signal. When transmitting f TX_DATA is logic 1. When

M

transmitting f TX_DATA is logic 0. When the transmitter

S

is not enabled (TX_RXB = 0) TX_DATA goes to logic 1 at

the next BIT_CLK.

BIT_CLK

TX_DATA

TX_RXB

TX_ENB

TX_OUT

PC20090610.1

t_{dTX_ENB}

Figure 16. TX_ENB Timing

DA Converter

After hard or soft reset the level is set at minimum level

(maximum attenuation) When going to reception mode

(when TX_RXB goes from 1 to 0) the level is kept in

memory so that the next transmit frame starts with the old

level. The evaluation of the level is done during 1

CHIP_CLK period.

A digital to analog SD converter converts the sine wave

digital word to a pulse density modulated (PDM) signal. The

PDM signal is converted to an analog signal with a first order

switched capacitor filter.

Low Pass Filter

Depending on the value of peak level on ALC_IN the

attenuation is updated:

rd

A 3 order continuous time low pass filter in the transmit

path filters the quantization noise and noise generated by the

SD DA converter. The typical corner frequency f

138 kHz and is internally trimmed to compensate for

process variation. This filter can be tuned to f = 195 kHz

to allow operating in the D−band as described in

• Vp

< VTL

: increase the level with one 6 dB

ALC

ALC_IN

=

−3dB

step

• VTL

level

≤ Vp

≤ VTH : don’t change the

ALC

ALC_IN

−3dB

Reference 1.

• Vp

> VTH

: decrease the level with one 6 dB

ALC_IN

step

ALC

Amplifier with Automatic Level Control (ALC)

The gain changes in the next CHIP_CLK period.

An evaluation phase and a level adjustment take 2

CHIP_CLK periods. ALC operation is enabled only during

the first 16 CHIP_CLK cycles after a hard or soft reset or

after going into transmit mode.

The automatic level control can be disabled by setting

register R_ALC_CTRL[3] = 1. In this case the transmitter

output level is fixed to the programmed level in the register

R_ALC_CTRL[2:0]. See Reference 1.

The pin ALC_IN is used for level control of the

transmitter output level. First peak detection is done. The

peak value is compared to two thresholds levels:

VTL

and VTH

. The result of the peak

ALC_IN

detection is used to control the setting of the level of

TX_OUT. The level of TX_OUT can be attenuated in 8 steps

of 3 dB typical.

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NCN49599

Table 25. FIXED TRANSMITTER OUTPUT ATTENUATION

ALC_CTRL[2:0]

Attenuation

0 dB

000

001

010

011

100

101

110

111

−3 dB

−6 dB

−9 dB

−12 dB

−15 dB

−18 dB

−21 dB

Power Amplifier

Coupling and filtering

The integrated power amplifier consists of 2 independent

operational amplifiers. The first or input stage is designed to

build a 2 order low pass filter or to be used as unity gain

Because the complete analog part of the S−FSK

modulator inside NCN49599 is referenced to the analogue

ground REF_OUT, and its output is DC coupled to the

nd

follower buffer. The second or power stage is a low

distortion Class A/B line driver able to deliver 1.2 A peak

current with the output voltage guaranteed to swing within

1 V or less of either rail giving the user improved SNR.

Current protection is set with a single resistor, RLim. The

output stage goes into a high*impedance state once the

junction temperature has exceeded +150_C

TX_OUT pin, a decoupling capacitor C is needed when

connecting it to the Power Amplifier. To suppress the second

1

and third order harmonic of the generated S−FSK signal it

nd

th

is recommended to use a 2 or 3 order low pass filter. In

th

Figure 17 a MFB topology of a 3 order filter is illustrated

to be compliant with the European CENELEC EN 50056−1

standard for signaling on low*voltage electrical

installations in the frequency range 3 kHz to 148.5 kHz.

R₃

R₄

R₅

C₄

R₆

R₂

R₁

C₂

C₁

C₃

C₅

V_CC

R₈

B−

B+

A_OUT

A−

A+

C₆

R₇

B_OUT1

TO COUPLER

B_OUT2

EN

A

Power Amplifier

R₂₂

Transmitter (S−FSK Modulator)

TX_EN

ARM

Interface

&

A

LP

Filter

Control

TX_OUT

PC20120831.2

Figure 17. Power Amplifier and Filtering

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NCN49599

Noise and stability

Optimal stability and noise rejection will be achieved with

power*supply decoupling capacitors close to VCC.

• The thermal resistance from junction to ambient Rth

j−a

• The output current I_outB or I

L

• The output voltage. V_outB or V

L

The thermal resistance from junction to ambient Rth

Current protection

j−a

strongly depends on board design. R

= 50 K/W in free air

The current protection is set by the R

resistor. It limits

thJA

LIM

is a typical value which may be used even if NCN49599 is

soldered on a PCB mounted in a small closed box, provided

the transmission of frames are infrequent and widely spread

in time. This typical value is also used in the generation of

the curves plotted in Figures 18 and 19.

the output both when sourcing and sinking current. Once the

protection is trigged the ILIM flag will go logic High

signaling the user to take any necessary action. When the

current output recovers, the ILIM flag will return to logic

Low. To guarantee correct operation it is recommended to

Figure 18 shows the SOA in function of output current I

set R

= 5 kW

L

LIM

and output voltage V with the ambient temperature as

independent parameter. The maximum allowed current is

800 mA RMS. For that reason it is recommended to limit the

This ensures the current will not exceed 1.2 A causing

damage. See also paragraph Safe Operating Area.

L

Thermal protection

output current by using R

= 5 kW. This current limitation

LIM

In the event load conditions cause internal over*heating,

the amplifier will go into shutdown to prevent damage.

Thermal shutdown takes place at an internal junction

temperature of approximately 160_C; the amplifier will

recover to the Enabled mode when the junction temperature

cools back down to approximately 145_C.

is plotted as a horizontal line. The maximal output voltage

is limited by V , V and V . This results in the

CC,max

OH

OL

straight line on the right hand side of the V − I plot. The

L

area below and left from these limitations is considered as

safe. The relation between output voltage and current is the

impedance as seen at the output of the power operational

amplifier. Constant impedance lines are represented by

canted lines.

Safe Operating Area

The Safe operating area (SOA) of the power amplifier is

defined by 3 parameters:

Figure 18. SOA in V_L–IL space (bottom left corner is safe) with R_thJA= 50 K/W

Although voltage−versus−current is the normal

representation of safe operating area, a PLC line driver can

only control one of these variables: voltage and current are

linked through the mains impedance. Figure 19 displays

exactly the same information as Figure 18 but might be

easier to work with. Here constant current values are now

represented as canted lines.

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NCN49599

Figure 19. SOA in ZL–VL Space (bottom right corner is safe)

Receiver Path Description

pass active filter to attenuate the mains frequency. This high

pass filter output is followed by a gain stage which is used

in an automatic gain control loop. This block also performs

a single ended input to differential output conversion. This

gain stage is followed by a continuous time low pass filter

Receiver Block Diagram

The receiver takes in the analog signal from the line

coupler, conditions it and demodulates it in a data−stream to

the communication controller. The operation mode and the

baud rate are made according to the setting in R_CONF,

R_FS and R_FM. The receive signal is applied first to a high

pass filter. Therefore NCN49599 has a low noise operational

amplifier at the input stage which can be used to make a high

th

to limit the bandwidth. A 4 order sigma delta converter

converts the analog signal to digital samples. A quadrature

demodulation for f and f is than performed by an internal

S

M

DSP, as well the handling of the bits and the frames.

RX_OUT

Receiver(Analog Path)

FROM

LOW NOISE

DIGITAL

OPAMP

RX_IN

4th

TO

Gain

LPF

order

DIGITAL

SDAD

REF_OUT

REF

1,65 V

PC20090610.2

Figure 20. Analog Path of the Receiver

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NCN49599

FROM TRANSMITTER

Receiver (Digital Path)

Quadrature Demodulator

f_MQf_SIf_SQ

f_MI

f_MQ

f_SI

2^nd

Decimator

I_M

FROM

ANALOG

Sliding

Filter

f_M

Noise

Shaper

1^st

Compen−

sator

2^nd

Decimator

Q_M

Decimator

Sliding

Filter

2^nd

I_S

Sliding

Filter

TO

GAIN

Abs

value

accu

Decimator

f_S

AGC

Control

f_SQ

2^nd

Decimator

Q_S

Sliding

Filter

PC20110610.3

Figure 21. Digital Path of the Receiver ADC and Quadrature Demodulation

50/60 Hz Suppression Filter

noise operational amplifier. REF_OUT is the analog output

pin which provides the voltage reference (1.65 V) used by

the A/D converter. This pin must be decoupled from the

NCN49599 receiver input provides a low noise input

operational amplifier in a follower configuration which can

be used to make a 50/60 Hz suppression filter with a

minimum number of external components. Pin RX_IN is the

positive input and RX_OUT is the output of the input low

analog ground by a 1 mF ceramic capacitance (C

). It is

DREF

not allowed to load this pin.

R₂

RX_OUT

RX_IN

2

Receiver (S−FSK Demodulator)

LOW NOISE

OPAMP

C₂

C₁

V_IN

3

Received

Signal

TO AGC

R₁

REF_OUT

4

REF

1,65 V

C_DREF

PC20090722.1

V_SSA

Figure 22. External Component Connection for 50/60 Hz Suppression Filter

RX_IN is the positive analog input pin of the receiver low

noise input op−amp. Together with the output RX_OUT an

active high pass filter is realized. This filter removes the

main frequency (50 or 60 Hz) from the received signal. The

filter characteristics are determined by external capacitors

and resistors. Typical values are given in Table 26. For these

values and after this filter, a typical attenuation of 85 dB at

50 Hz is obtained. Figure 22 represents external

components connection. In a typical application the

coupling transformer in combination with a parallel

capacitance forms a high pass filter with a typical

attenuation of 60 dB. The combined effect of the two filters

decreases the voltage level of 230 Vrms at the mains

frequency well below the sensitivity of the NCN49599.

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NCN49599

T

20

−20

−60

−100

−140

10

100

1k

10k

100k

Frequency (Hz)

Figure 23. Transfer Function of 50 Hz Suppression Circuit

Table 26. VALUE OF THE RESISTORS AND CAPACITORS

Component

Value

1.5

1

Unit

nF

C

1

2

nF

C

mF

DREF

R

22

kW

1

2

11

Remark: The analog part of NCN49599 is referenced to the

internal analog ground REF_OUT = 1.65 V (typical value).

If the external circuitry works with a different analogue

reference level one must be sure to place a decoupling

capacitor.

f

= 138 kHz and is internally trimmed to compensate for

−3dB

process variation.

A/D Converter

th

The output of the low pass filter is input for an analog 4

order sigma−delta converter. The DAC reference levels are

supplied from the reference block. The digital output of the

converter is fed into a noise shaping circuit blocking the

quantization noise from the band of interest, followed by a

decimation and a compensation step.

Auto Gain Control (AGC)

The receiver path has a gain stage which is used for

automatic gain control. The gain can be changed in 8 steps

of 6 dB. The control of the AGC is done by a digital circuit

which measures the signal level after the AD converter, and

regulates the average signal in a window around a

percentage of the full scale. The AGC works in two cycles:

a measurement cycle at the rising edge of the CHIP_CLK

and an update cycle starting at the next CHIP_CLK.

Quadrature Demodulator

The quadrature demodulation block takes the AD signal

and mixes it with the in−phase and quadrature phase of the

f and f carrier frequencies. After a low pass filter and

S

M

rectification the mixer output signals are further processed

in software. There the accumulation over a period of

CHIP_CLK is done which results in the discrimination of

data 0 and data 1.

Low Noise Anti Aliasing Filter

rd

The receiver has a 3 order continuous time low pass filter

in the signal path. This filter is in fact the same block as in

the transmit path which can be shared because NCN49599

works in half duplex mode. The typical corner frequency

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NCN49599

Bit Sync

cross detector and loop delay in the Rx−filter circuitry will

cause a shift between the physical transmitted bit and the

received S−FSK signal as illustrated in Figure 24.

At the transmit side the data−stream is in sync and in phase

with the zero crossing of the mains. The complex impedance

of the power line together with propagation delay in the zero

Mains

t

Transmitted

bit stream

Bit 0

Bit1

Bit 2 Bit 3 Bit 4

Bit 5

Bit 6 Bit 7 Bit 8

Modulation

Transmission over the Power Line

PC20101119 .1

Bit delay

Figure 24. Bit Delay Cause by Transmission Over a Power Line

To compensate for this delay between physical and

Communication Controller

demodulated bit a synchro bit value is introduced. It shifts

forward the Hardware Demodulating process up to seven

chip clocks. See Figure 25.

The Communication Controller block includes the ARM

CORTEX M0 32 bit RISC processor, its peripherals: Data

and Program RAM, Program ROM, TIMERS 1 and 2,

Interrupt Control, SPI interface to an optional external Flash

memory, TEST Control, Watchdog and Power On Reset

(POR), I/O ports and the Serial Communication Interface

(SCI). The micro−processor is programmed to handle the

physical layer (chip synchronization), and the MAC layer

conform to IEC 61334−5−1. The program is stored in a

masked ROM. Depending on status of the SEN input, after

power on reset NCN49599 will boot from internal ROM ,

external Flash or over the serial interface. The RAM

contains the necessary space to store the program and the

working data. The back−end interface is done through the

Local Port and Serial Communication Interface block. This

back−end is used for data transmission with the application

micro controller (containing the application layer for

concentrator, power meter, or other functions) and for the

definition of the modem configuration.

SBV[2:0] = 0

SBV[2:0] = 3

CHIP_CLK

Bit 0

Bit1

Bit 2

PC20101119 .2

Figure 25. Compensation for Bit Delay by Shifting

Forward the Start of the Demodulating Process

The synchro bit value can be set using register SBV [2:0].

Table 27. SYNCHRO BIT VALUE

SBV[2:0]

000

Bit Delay

More boot options and further details can be found in

Reference 1.

The following section will give a brief overview of the

functionality when boot from ROM. More details can be

found in Reference 1.

0 CHIP_CLK

1 CHIP_CLK

2 CHIP_CLK

3 CHIP_CLK

4 CHIP_CLK

5 CHIP_CLK

6 CHIP_CLK

7 CHIP_CLK

001

010

011

100

101

110

111

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32

NCN49599

Communication Controller

Data / Program

RAM

TxD

RxD

Serial

Comm.

Interface

T_REQ

BR0

Program

ROM

BR1

5

ARM

Risc

Core

IO[9:3]

RX_DATA

CRC

Timer 1 & 2

Local Port

TO

TRANSMIT

TXD/ PRES

FROM

RECEIVER

POR

RESB

Interrupt

Control

Watchdog

Test

Control

Flash SPI

TEST

PC20120530.4

Figure 26. Communication Controller

Local Port

(CRC) is correct. TXD/PRES is the output for either the

transmitting data (TX_DATA) or a synchronization signal

with the time−slots (PRE_SLOT).

When booting from ROM (SEN = VSS) IO[9:3] have no

function. These IO’s can be addressed when booting from

the external Flash. See also Reference 1.

The controller uses 3 output ports to inform the actual

status of the PLC communication. RX_DATA indicates if

NCN49599 is waiting for its configuration, if it is in research

of synchronization, or if it is receiving data. CRC indicates

if the received frames are valid: the cyclic redundancy code

Table 28. OVERVIEW FUNCTIONALITY LOCAL PORT

Port

Function

Data reception

Value

Explanation

Waiting for configuration

Remark

RX_DATA

10 Hz

Output is oscillating

0

1

0

1

After Synchro Confirm Time−out

Research of synchronization

CRC

CRC OK

During the pause between 2 timeslots when a

correct frame is received

0

1

0

1

Transmit of f

S

TX_DATA

R_CONF[7] = 1

R_CONF[7] = 0

M

TXD/PRES

See Figure 14

PRE_SLOT

Serial Communication Interface (SCI)

The Serial Communication Interface allows asynchronous communication. It can communicate with a UART = Universal

Asynchronous Receiver Transmitter, ACIA = Asynchronous Communication Interface Adapter and all other chips that employ

standard asynchronous serial communication. The serial communication interface has following characteristics:

• Half duplex.

• Standard NRZ format.

• Start bit, 8 data bits and 1 stop bit.

• Hardware programmable baud−rate via BR0 and BR1 pins (9600, 19200, 38400 and 115200 baud).

• 0−5 V levels with open drain for TxD.

• 0−5V levels for RxD and T_REQ.

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33

NCN49599

3V3_D

NCN49597

TxD

RxD

T_REQ

Serial

Comm.

Interface

Application

Micro

Controller

BR0

BR1

ARM

Risc

Core

5

IO[9:3]

RX_DATA

CRC

Local Port

TXD/PRES

Communication Controller

PC20120530.5

Figure 27. Connection to the Application Microcontroller

Serial Communication Interface Physical Layer Description

The following pins control the serial communication interface.

TXD: Transmit data output.

It is the data output of the NCN49599 and the input of the application micro controller.

RXD: Receive data input.

It is the data input of the NCN49599 and the output of the application micro controller.

T_REQ: Transmit Request input

Request for data transmission received from the application micro controller

BR0, BR1: Baud rate selection inputs.

These pins are externally strapped to a value or controlled by the external application micro controller.

Table 29. BR1, BR0 BAUD RATES

BR1

BR0

SCI Baud Rate

115200

9600

0

1

0

1

0

1

19200

38400

IDLE(mark)

LSB

D0

MSB

IDLE(mark)

D7

Stop

t_BIT

Start

t_BIT

D1

D2

D3

D4

D5

D6

8 data bits

1 character

PC20080523.3

Figure 28. Data format

Arbitration and Transfer

In order to avoid collisions between the data sent by the NCN49599 and the application micro controller, the NCN49599

is chosen as the transmitting controller. This means that when there is no local transfer, the NCN49599 can initiate a local

communication without taking account of the application micro controller state. On the other hand, when the application micro

controller wants to send data (using a local frame), it must first send a request for communication through the local input port

named T_REQ (Transmitting Request). Then the NCN49599 answers with a status message.

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34

NCN49599

Transfer from application micro controller to NCN49599

When the application micro controller wants to initiate a local transfer, it must pull down the T_REQ signal. The NCN49599

answers within the t delay with the status message in which the application micro controller can read if the communication

POLL

channel is available. If the communication is possible, the application micro controller can start to send its local frame within

the t delay. It should pull up the T_REQ signal as soon as the first character (STX) has been sent. If the beginning of the local

SR

frame is not received before the t delay was issued, the NCN49599 ignores the local frame. At the end of the data reception

SR

sent by the application micro controller on the RxD line, the NCN49599 sends a byte on the TxD line in order to inform about

the status of the transmitting <ACK> (=0x06) or <NAK> (=0x15).

Remark: If the application micro controller only wants to know the state of the NCN49599, it has just to pull up the T_REQ

signal after the reception of the status message.

T_REQ

t_POLL

TxD

RxD

StatusMessage

ACK

t_SR

t_ACK

Local Frame from Base Micro

PC20080523.5

Figure 29. Transfer from Application microcontroller to NCN49599

If the length and the checksum of the local frame are both correct, the NCN49599 acknowledges with an <ACK> character.

In other cases, it answers with a <NAK> character. In case of <NAK> response, or no acknowledgement from NCN49599 in

the t

time−out, a complete sequence must be restarted to repeat the frame.

ACK

Transfer from NCN49599 to application micro controller

When the NCN49599 wants to send a frame, it can directly send it without any previous request.

T_REQ

Local Frame from

NCN49599

Local Frame from

NCN49599

Local Frame from

NCN49599

TxD

RxD

t_ACK

t_WBC

t_ACK

t_WBC

NAK

ACK

PC20080523.6

Figure 30. Transfer from NCN49599 to Application Micro Controller

If the length and the checksum of the local frame are both correct, the application micro controller acknowledges with an

<ACK> character. In other cases, it answers with a <NAK> character. In case of <NAK> response from the Application micro

controller, the NCN49599 will repeat the frame only once after a delay corresponding to t

(Wait Before Continue). A non

WBC

response from the application micro controller or a framing error when an <ACK> character is awaited is considered as an

acknowledgment.

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35

NCN49599

Character time−out in Reception

The time between two consecutive characters in a local frame should not exceed t (Time−out Inter Character):

IC

t

IC

Character

t

PC2008052.37

Figure 31. Character Time−out

After this delay, the frame reception is finished. If the length and the checksum are both correct, the local frame is taken in

account otherwise all previous characters are discarded. The time out Inter Character (t ) is set by default at 10ms after a reset.

IC

The time out Inter character (t ) is modified by the bit 7 of repeater parameter in the configuration frame. See Reference [1]:

IC

• Bit 7 = 1 −> the t value is constant at 10 ms,

IC

• Bit 7 = 0 −> the t value represents 5 characters depending on the communication speed (defined by two local input

IC

ports BR0 and BR1).

Table 30. SERIAL COMMUNICATION TIME−OUT VALUES

Time−out

Meaning

Value

Tpoll

Delay max. awaited by the base micro between the T_REQ pull down and the status

message transmission (delay polling)

20 ms

Tsr

Tack

Twbc

Tic

Delay max. awaited by the NCN49599 between the end of the status transmitting and the

reception of the STX character in the base micro frame (delay status/reception)

200 ms

40 ms

5 ms

Delay max. awaited by either the NCN49599 or the base micro between the end of a

transmitting and the reception of the ACK or NAK character sent by the other (delay ack).

Delay max. awaited by either the NCN49599 or the base micro between the end of a

reception and the transmission of the next frame (delay waiting before continue).

Delay max. awaited by either the NCN49599 or the base micro

between two characters (delay inter characters)

Programmable with the bit 7 of repeater parameter in the configura-

tion frame

Bit 7 = 1

Bit 7 = 0

10 ms

4800 baud

10 ms

5 ms

9600 baud

19200 baud

38400 baud

2.5 ms

1.25 ms

Watchdog

The watchdog supervises the ARM and in case the firmware doesn’t acknowledge at periodic times, a hard reset is generated.

Configuration Registers

A number of configuration registers can be accessed by the user by sending a WriteConfig_Request over the SCI interface.

See also Reference [1]. A brief overview of the accessible configuration registers is given below:

R_CONFIG register configures the NCN49599 in the correct mode. The R_CONFIG register is controlled by the embedded

software and can be accessed via a WriteConfig_Request.

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36

NCN49599

Table 31. R_CONF[9:0]

ARM Register

R_CONF[7]

Hard Reset

Soft Reset

Description

TXD/PRES_SEL

MODE

0

000

00

0

−

R_CONF[5:3]

R_CONF[2:1]

BAUDRATE

MAINS_FREQ

R_CONF[0]

Where:

TXD/PRES_SEL: 0:

1:

TXD/PRES is PRE_SLOT output pin

TXD/PRES is TX_DATA output pin

MODE:

000 :

001 :

010 :

011 :

1xx :

00:

01:

10:

11:

Initialization

Master Mode

Slave Mode

Reserved

Test Mode

BAUDRATE:

6 data bits per mains period = 300 baud @ 50 Hz

12 data bits per mains period = 600 baud @ 50 Hz

24 data bits per mains period = 1200 baud @ 50 Hz

48 data bits per mains period = 2400 baud @ 50 Hz

50 Hz

MAINS_FREQ: 0:

1:

60 Hz

R_FS and R_FM step registers are defining the space and mark frequency. Explanation on the values can be found in paragraph

Sine wave generator. This register can be accessed via a WriteConfig_Request.

Table 32. FS AND FM STEP REGISTERS

ARM Register

R_FS[15:0]

Hard Reset

0000h

Soft Reset

0000h

Description

Step register for the space frequency f

S

R_FM[15:0]

0000h

Step register for the mark frequency f

M

R_ZC_ADJUST register defines the value which is pre−loaded in the PLL counter. This is used to fine tune the phase difference

between CHIP_CLK and the – to + zero cross of the mains. Explanation on the values can be found in paragraph 50/60 Hz

PLL.

Table 33. ZC_ADJUST REGISTERS

ARM Register

Hard Reset

Soft Reset

Description

R_ZC_ADJUST[7:0]

02h

Fine tuning of phase difference between CHIP_CLK and rising edge of

Mains zero cross

R_ALC_CTRL register enables or disables the Automatic Level Control. In case ALC is disabled the attenuation of the TX

output driver is fixed according to the value in R_ALC_CTRL[2:0]. Explanation on the attenuation values can be found in

paragraph Amplifier with Automatic Level Control.

Table 34. ALC_CTRL REGISTERS

ARM Register

Hard Reset

Soft Reset

Description

R_ALC_CTRL[3:0]

00h

Control register for the automatic level control

Where:

R_ALC_CTRL[3]: 0:

1:

R_ALC_CTRL[2:0]:

Automatic level control is enabled

Automatic level control is disabled and attenuation is fixed

Fixed attenuation value

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37

NCN49599

Table 35. FIXED TRANSMITTER OUTPUT ATTENUATION

ALC_CTRL[2:0]

Attenuation

0 dB

000

001

010

011

100

101

110

111

−3 dB

−6 dB

−9 dB

−12 dB

−15 dB

−18 dB

−21 dB

Reset and Low Power

NCN49599 has 2 reset modes: hard reset and soft reset.

The hard reset initializes the complete IC (hardware and ARM) excluding the data RAM for the ARM. This makes sure that

start−up of hardware and ARM is guaranteed. A hard reset is active when pin RESB = 0 or when the power supply V < V

DD

POR

(See Table 15). When switching on the power supply the output of the crystal oscillator is disable until a few 1000 clock pulses

have been detected, this to enable the oscillator to start up.

The soft reset initializes part of the hardware. The soft reset is activated when going into initialization mode for the duration

of maximum 1 CHIP_CLK. Initialization mode is entered by R_CONF[5:3] = 000.

The concept of NCN49599 has a number of provisions to have low power consumption. When working in transmit mode

the analogue receiver path and most of the digital receive parts are disabled. When working in receive mode the analog

transmitter and most if the digital transmit parts, except for the sine generation, are disabled.

When the pin RESB = 0 the power consumption is minimal. Only a limited power is necessary to maintain the bias of a

minimum number of analog functions and the oscillator cell.

REFERENCE

In this document references are made to:

1. Design Manual NCN49599

4. DLMS UA 1000−2 Ed. 7.0 DLMS/COSEM

Architecture and Protocols

http://www.onsemi.com

http://www.dlms.com/documentation/dlmsuacolou

redbookspasswordprotectedarea/index.html

5. IEC 61334−5−1 Lower layer S−FSK Profile.

http://webstore.iec.ch/preview/info_iec61334−5−1

%7Bed2.0%7Db.pdf

6. IEC 61334−5−1 Lower layer S−FSK Profile.

http://webstore.iec.ch/preview/info_iec61334−5−1

%7Bed2.0%7Db.pdf

2. EN 50065−1: Signaling on low−voltage electrical

installations in the frequency range 3 kHz to

148.5 kHz

http://connect.nen.nl/~/Preview.aspx?artfile=4257

28&RNR=66840

3. ERDF−CPT−Linky−SPEC−FONC−CPL version

V1.0 Linky PLC profile functional specification

http://www.erdfdistribution.fr/medias/Linky/ERD

F−CPT−Linky−SPEC−FONC−CPL.pdf

Table 36. ORDERING INFORMATION

†

Device

Temperature Range

Package

Shipping

NCN49599MNG

−40°C – 125°C

QFN−56

(Pb−Free)

Tube

NCN49599MNTWG

−40°C – 125°C

QFN−56

(Pb−Free)

Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

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38

NCN49599

PACKAGE DIMENSIONS

QFN56 8x8, 0.5P

CASE 485CN

ISSUE O

D

A B

NOTES:

L

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

PIN ONE

LOCATION

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.25mm FROM THE TERMINAL TIP

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

L1

DETAIL A

E

ALTERNATE

CONSTRUCTIONS

MILLIMETERS

DIM MIN

MAX

1.00

0.05

A

A1

A3

b

0.80

0.00

0.20 REF

EXPOSED Cu

MOLD CMPD

0.15

C

0.20

0.30

D

D2

E

E2

e

K

L

L1

8.00 BSC

0.15

C

TOP VIEW

DETAIL B

6.50

6.70

8.00 BSC

DETAIL B

(A3)

6.70

0.10

C

ALTERNATE

0.50 BSC

CONSTRUCTION

0.20

0.30

0.05

−−−

0.50

0.15

A

0.08

A1

SEATING

C

PLANE

NOTE 4

SIDE VIEW

D2

RECOMMENDED

MOUNTING FOOTPRINT*

M

0.10

C A B

8.30

6.74

DETAIL A

56X L

56X

0.60

M

0.10

C A B

1

E2

6.74

8.30

1

56

K

e

56X b

56X

0.32

PKG

OUTLINE

e/2

M

0.10

C A B

0.50

PITCH

NOTE 3

0.05

C

BOTTOM VIEW

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where

personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCN49599/D

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39


型号：	NCN49599
厂家：	ONSEMI
描述：	Power Line Carrier Modem 电力线载波调制解调器调制解调器
文件：	总39页 (文件大小：425K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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