NCN8024RDWR2G [ONSEMI]
智能卡接口;
| 型号： | NCN8024RDWR2G |
| 厂家： | 
ONSEMI |
| 描述： | 智能卡接口 |
| 文件： | 总16页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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NCN8024R
Smart Card Interface IC
The NCN8024R is a single smart card interface IC. It is dedicated
for 3.0 V/5.0 V smart card reader/writer applications. The card V
CC
supply is provided by a very low drop−out and low noise regulator
(LDO).
The device is fully compatible with the ISO 7816−3 and EMV
standards as well as with standards specifying conditional access in
Set−Top−Box (STB) including NDS.
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MARKING
The smart card interface IC is available in SOIC−28 and TSSOP−28
packages providing the industry−standard features required by STB
smart card interfaces.
DIAGRAMS
28
1
Features
NCN8024R
AWLYYWWG
• Single IC Card Interface
SOIC−28
CASE 751F
• Fully Compatible with ISO 7816−3, EMV and Related Standards
Including NDS and Other STB Standards (Nagravision, Irdeto, …)
• Three Bidirectional Buffered I/O Level Shifters (C4, C7 and C8 Card
Pins)
• 3.0 V or 5.0 V 5% Regulated Card Power Supply such as I
≤
CC
NCNR
8024G
ALYW
70 mA with 3.0 V ≤ V
≤ 5.5 V @ 3.0 V (Class B) and 4.85 V ≤
DDP
V
DDP
≤ 5.5 V @ 5.0 V (Class A)
TSSOP−28
CASE 948AA
• Independent Power Supply Range on Controller Interface
(2.7 V < V < 5.5 V)
DD
• Handles 5.0 V and 3.0 V Smart Cards (Class A & B)
• Thermal and Short Circuit Protection on all Card Pins
NCN8024R = Specific Device Code
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
= Pb−Free Package
A
• Support up to 27 MHz Clock with Internal Division Ratio 1/1, 1/2,
1/4 and 1/8 through CLKDIV1 and CLKDIV2 Pins
G
• ESD Protection on Card Pins up to 8 kV+ (Human Body Model)
• Activation/Deactivation Sequences (ISO7816)
• Fault Protection Mechanisms Enabling Automatic Device
Deactivation in Case of Overload, Overheating, Card Take−off or
Power Supply Drop−out (OCP, OTP, UVP)
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
• Interrupt Signal INT for Card Presence and Faults
• External Under−Voltage Lockout Threshold Adjustment on V
DD
(PORADJ Pin)
• Available in Two Package Formats: SOIC−28 and TSSOP−28
• These are Pb−Free Devices
Typical Application
• Pay TV, Set−Top−Box Decoder with Conditional Access and
Pay−per−View
• Conditional Access Modules (CAM)
• POS / ATM
• Access Control, Identification
©
Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
October, 2012 − Rev. 1
NCN8024R/D
NCN8024R
VDDP
10 uF
100 nF
VDDP
VDD
100 nF
Microcontroller
VDD
INT
VDD
R1
R2
CRD_PRES
CRD_PRES
SMART CARD
PORADJ
DET
DET
GND
GND
CMDVCC
5V/3V
100 nF
220 nF
GND
Vpp
CRD_VCC
CRD_RST
CRD_CLK
CRD_AUX1
CRD_AUX2
CRD_IO
Vcc
RST
CLK
C4
GND
5
6
7
1
2
3
CLKDIV1
CLKDIV2
I/O
C8
8
4
CLKIN
RSTIN
I/Ouc
CRD_GND
GNDP
AUX1uc
AUX2uc
GND
GND
Figure 1. Typical Smart Card Interface Application
CLKDIV1
AUX2uc
AUX1uc
I/Ouc
1
28
27
26
25
24
23
22
21
20
19
18
17
CLKDIV2
5V/3V
2
3
NC
GNDP
NC
4
CLKIN
5
6
VDDP
NC
INT
GND
7
VDD
NC
8
RSTIN
9
CRD_PRES
CRD_PRES
10
11
12
13
14
CMDVCC
PORADJ
CRD_I/O
CRD_AUX2
CRD_AUX1
CRD_GND
CRD_VCC
CRD_RST
CRD_CLK
16
15
Figure 2. SOIC−28 and TSSOP−28 Pinout (Top View)
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2
NCN8024R
VDD
21
VDDP
6
9
CRD_PRES
CRD_PRES
Interrupt Block
Card Detection
INT
23
3
10
Supply Voltage
Monitoring
5V/3V
CMDVCC 19
3.0 V / 5.0 V LDO
CRD_VCC
17
14
4
18
1
PORADJ
CLKDIV1
CRD_GND
GNDP
CLKDIV2
2
Thermal Control
24
CLKIN
Clock Dividers
CRD_CLK
CRD_RST
15
16
11
13
12
25
20
NC
Control Logic
and Sequencer
Card Pin
Drivers
RSTIN
I/Ouc
CRD_I/O
26
27
28
22
AUX2uc
CRD_AUX2
CRD_AUX1
AUX1uc
GND
Figure 3. NCN8024R Block Diagram
PIN FUNCTION AND DESCRIPTION
Pin #
Name
CLKDIV1
CLKDIV2
5V/3V
Type
Input
Input
Input
Description
1
2
3
This pin coupled with CLKDIV2 is used to program the clock frequency division ratio (Table 1).
This pin coupled with CLKDIV1 is used to program the clock frequency division ratio (Table 1).
Allows selecting card V power supply voltage. CRD_V = 5 V when 5V/3V = HIGH or 3 V when
CC
CC
5V/3V = LOW
4
5
6
7
8
9
GNDP
NC
GND
Regulator Power Supply Ground
Not Connected
−
VDDP
NC
Power Regulator Power Supply
−
−
Not Connected
Not Connected
NC
CRD_PRES
Input
Card presence pin active (card present) when CRD_PRES = Low. A built−in debounce timer of
about 8 ms is activated when a card is inserted. Convenient for Normally Open (NO) smart card
connector.
10
CRD_PRES
Input
Card presence pin active (card present) when CRD_PRES = High. A built−in debounce timer of
about 8 ms is activated when a card is inserted. Convenient for Normally Closed (NC) smart card
connector.
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3
NCN8024R
PIN FUNCTION AND DESCRIPTION
Pin #
Name
Type
Description
11
CRD_I/O
Input/
This pin handles the connection to the serial I/O (C7) of the card connector. A bi−directional level
Output translator adapts the serial I/O signal between the card and the micro controller. An 11 kW (typical)
pullup resistor to CRD_V provides a High impedance state for the smart card I/O link.
CC
12
13
CRD_AUX2
CRD_AUX1
Input/
This pin handles the connection to the chip card’s serial auxiliary AUX2 I/O pin (C8). A bi−directional
Output level translator adapts the serial I/O signal between the card and the micro controller. An 11 kW
(typical) pullup resistor to CRD_V provides a High impedance state for the smart card C8 pin.
CC
Input/
This pin handles the connection to the chip card’s serial auxiliary AUX1 I/O pin (C4). A bi−directional
Output level translator adapts the serial I/O signal between the card and the micro controller. An 11 kW
(typical) pullup resistor to CRD_V provides a High impedance state for the smart card C4 pin.
CC
14
15
CRD_GND
CRD_CLK
GND
Card Ground
Output This pin is connected to the CLOCK card connector’s pin (Chip card’s pin C3). The Clock signal
comes from the CLKIN input through clock dividers and level shifter.
16
17
CRD_RST
CRD_VCC
Output This pin is connected to the chip card’s RESET pin (C2) through the card connector. A level
translator adapts the external Reset (RSTIN) signal to the smart card.
Power This pin is connected to the smart card power supply pin. An internal DC/DC converter is
programmable using the pin 5V/3V to supply either 5 V or 3 V output voltage. An external distributed
ceramic capacitor ranging from 80 nF to 1.2 mF recommended must be connected across
CRD_VCC and CRD_GND. This set of capacitor must be low ESR (< 100 mW).
18
19
20
PORADJ
CMDVCC
RSTIN
Input
Input
Input
Power−on reset threshold adjustment input pin for changing the reset threshold with an external
resistor power divider. Recommended to be connected to ground when unused.
Command VCC pin. Activation sequence Enable/Disable pin (active Low). The activation sequence is
enabled by toggling CMDVCC High to Low and when a card is present.
This Reset input connected to the host and referred to V (microcontroller side), is connected to
DD
the smart card Reset pin through the internal level shifter which translates the level according to the
CRD_V programmed value.
CC
21
VDD
Power This pin is connected to the system controller power supply. It configures the level shifter input
stage to accept the signals coming from the controller. A 0.1 mF capacitor shall be used to bypass
the power supply voltage. When V is below 2.30 V typical the card pins are disabled.
DD
22
23
GND
INT
GND
Ground
Output The interrupt request is activated LOW on this pin. This is enabled when a card is present and the
card presence is detected by CRD_PRES or CRD_PRES pins. Similarly an interrupt is generated
when CRD_V is overloaded. 20 kW typical integrated pullup resistor to V
.
CC
DD
24
25
26
CLKIN
NC
Input
Clock Input for External Clock
Not Connected
I/Ouc
Input/
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
Output serial I/O signal between the smart card and the external controller. A built−in constant 11 kW
(typical) resistor provides a high impedance state.
27
28
AUX1uc
AUX2uc
Input/
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
Output serial C4 signal between the smart card and the external controller. A built−in constant 11 kW
(typical) resistor provides a high impedance state.
Input/
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
Output serial C8 signal between the smart card and the external controller. A built−in constant 11 kW
(typical) resistor provides a high impedance state.
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4
NCN8024R
ATTRIBUTES
Characteristics
Values
ESD protection
Human Body Model (HBM) (Note 1)
Card Pins (Card Interface Pins 9 − 17)
8 kV
2 kV
All Other Pins
Machine Model (MM)
Card Pins (Card Interface Pins 9 − 17)
400 V
150 V
All Other Pins
Moisture sensitivity (Note 2) SOIC−28 and TSSOP−28
Level 3
Flammability Rating Oxygen
Index: 28 to 34
UL 94 V−0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test
1. Human Body Model (HBM), R = 1500 W, C = 100 pF.
2. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 3)
Rating
DC/DC Converter Power Supply Voltage
Power Supply from Microcontroller Side
External Card Power Supply
Symbol
Value
Unit
V
V
DDP
−0.3 v V
v 5.5
DDP
V
DD
−0.3 v V v 5.5
V
DD
CRD_V
−0.3 v CRD_V v 5.5
V
CC
CC
Charge Pump Output
V
UP
−0.3 v V v 5.5
UP
Digital Input Pins
V
−0.3 v V v V
DD
V
V
in
in
Digital Output Pins (I/Ouc, AUX1uc, AUX2uc, INT)
Smart Card Output Pins
V
out
−0.3 v V v V
out DD
V
out
−0.3 v V v CRD_V
CC
V
out
Thermal Resistance Junction−to−Air
SOIC−28
TSSOP−28
R
q
JA
75
76
°C/W
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
T
−40 to +85
−40 to +125
+125
°C
°C
°C
°C
A
T
J
T
Jmax
T
stg
−65 to + 150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T = +25°C
A
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NCN8024R
POWER SUPPLY SECTION (V = 3.3 V; V
= 5 V; T
= 25°C; F
= 10 MHz)
DD
DDP
amb
CLKIN
Symbol
Rating
Min
Typ
Max
Unit
V
DC/DC Converter Power Supply,
CRD_V = 5 V
V
DDP
CC
|I | v 70 mA (EMV Conditions)
4.75
4.85
CC
|I | v 70 mA (NDS Conditions)
5.0
5.5
CC
CRD_V = 3 V
CC
|I | v 70 mA
CC
3.0
−
I
I
Inactive Mode
−
−
1
mA
DDP
DC Operating Supply Current, F
= 10 MHz,
⎢ = 0 (CMDVCC = Low)
−
3.0
mA
DDP
CLKIN
Cout
= 33 pF, ⎢I
CRD_CLK
CRD_VCC
I
DC Operating Supply Current,
mA
DDP
CRD_V = 5 V, I
= 70 mA
= 70 mA
−
−
80
80
CC
CRD_VCC
CRD_VCC
CRD_V = 3 V, I
CC
V
Operating Voltage
Inactive Mode 0 Standby Current
Operating Current − F = 10 MHz,
2.7
−
−
−
−
5.5
60
1
V
DD
VDD
VDD
I
I
mA
mA
−
CLK_IN
Cout
= 33 pF, ⎢I
⎢ = 0 (CMDVCC = Low)
CRD_CLK
CRD_VCC
UVLOV
Undervoltage Lockout (UVLO), No External Resistor at Pin PORADJ (Connec-
2.20
50
2.30
100
2.40
180
V
DD
ted to GND), Falling V Level
DD
UVLOHys
UVLO Hysteresis, No External Resistor at Pin PORADJ
(Connected to GND) (Note 4)
mV
PORADJ PIN
V
V
External Rising Threshold Voltage on V for Power On Reset − Pin PORADJ
1.20
1.15
30
1.27
1.20
80
1.34
1.28
100
V
V
PORth+
PORth−
PORHys
DD
External Falling Threshold voltage on V for Power On Reset − Pin PORADJ
DD
V
Hysteresis on V
(pin PORADJ) (Note 4)
mV
ms
PORth
t
Width of Power−On Reset Pulse (Note 4)
No External Resistor on PORADJ
External Resistor on PORADJ
POR
4
4
8
8
12
12
I
IL
Low Level Input Leakage Current, V <0.5 V (Pulldown Current Source)
5
mA
IL
LOW DROP OUT REGULATOR
C
Output Capacitance on card power supply CRD_V (Notes 4 and 5)
80
100 +
220
1200
nF
V
CRD_VCC
CC
CRD_V
Output Card Supply Voltage (including ripple)
CC
CC
3.0 V CRD_V Mode @ I ≤ 70 mA
2.85
4.75
4.60
3.00
5.00
5.00
3.15
5.25
5.25
CC
CC
5.0 V CRD_V Mode @ I ≤ 70 mA with 4.85 V VDDP 5.5 V (NDS)
CC
CC
5.0 V CRD_V Mode @ I ≤ 70 mA with 4.75 V VDDP 5.5 V (EMV)
CC
CC
CRD_V
Current Pulses 40 nAs (t < 400 ns & |I | ≤ 200 mA peak)
V
CC
3.0 V mode / Ripple ≤ 250 mV (2.9 V ≤ VDDP ≤ 5.5 V)
Current Pulses 40 nAs (t < 400 ns & |I | ≤ 200 mA peak)
2.70
4.60
3.00
5.00
3.20
5.25
CC
5.0 V mode / Ripple ≤ 250 mV (4.85 V ≤ VDDP ≤ 5.5 V)
I
Card Supply Current
mA
CRD_VCC
@ CRD_V = 3.0 V
70
70
CC
@ CRD_V = 5.0 V
CC
I
Short−Circuit Current − CRD_V Shorted to Ground
120
150
300
mA
mV
CRD_VCC_SC
CC
DV
Output Card Supply Voltage Ripple Peak−to−Peak − f
200 MHz (Load Transient with 65 mA Peak Current) (Note 4)
= 100 Hz to
CRD_VCC
ripple
CRD_V
Slew Rate on CRD_V Up or Down (Note 4)
0.22
V/ms
CCSR
CC
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Guaranteed by design and characterization
5. These values take into account the tolerance of the cms capacitor used. The allowed values are single or distributed capacitor combination
not exceeding 1.2 mF with 100 nF + 220 nF typical and recommended. It is recommended to use X5R or X7R−type capacitors with very
low ESR (< 100 mW) for optimal performances.
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6
NCN8024R
HOST INTERFACE SECTION CLKIN, RSTIN, I/Ouc, AUX1uc, AUX2uc, CLKDIV1, CLKDIV2, CMDVCC, 5V/3V
(V = 3.3 V; V
= 5 V; T
= 25°C; F = 10 MHz)
DD
DDP
amb
CLKIN
Symbol
Rating
Min
−
Typ
−
Max
27
Unit
MHz
V
F
Clock Frequency on Pin CLKIN (with Divider Ratio w 2) (Note 6)
CLKIN
V
IL
Input Voltage Level Low: CLKIN, RSTIN, I/Ouc, AUX1uc, AUX2uc, CLKDIV1,
CLKDIV2, CMDVCC, 5V/3V
−0.3
−
0.3 x V
DD
V
Input Voltage Level High: CLKIN, RSTIN, I/O, AUX1, AUX2, CLKDIV1, CLKDIV2,
CMDVCC, 5V/3V
0.7 x V
−
−
−
V + 0.3
DD
V
IH
DD
|I |
IL
CLKDIV1, CLKDIV2, CMDVCC, RSTIN, CLKIN, 5V/3V Low Level Input Leakage
−
−
1.0
mA
mA
Current, V = 0 V
IL
|I
IH
|
CLKDIV1, CLKDIV2, CMDVCC, RSTIN, CLKIN, 5V/3V Low Level Input Leakage
1.0
Current, V = V
IH
DD
V
Input Voltage Level Low: I/Ouc, AUX1uc, AUX2uc
Input Voltage Level High: I/Ouc, AUX1uc, AUX2uc
−0.3
−
−
−
−
V
V
IL
0.5
V
IH
0.7 x V
V
+ 0.3
DD
DD
|I |
IL
I/Ouc, AUX1uc, AUX2uc Low Level Input Leakage Current, V = 0 V
−
−
600
10
mA
mA
IL
|I
IH
|
I/Ouc, AUX1uc, AUX2uc High Level Input Leakage Current, V = V
IH
DD
I/Ouc, AUX1uc, AUX2uc data channels, @ Cs v 30 pF
V
OH
High Level Output Voltage (CRD_I/O = CRD_AUX1 = CRD_AUX2 = CRD_V
)
CC
I
I
= 0
0.9 x V
−
−
V
DD
V
DD
+ 0.1
+ 0.1
V
V
OH
OH
DD
DD
= −40 mA for V > 2 V (I = −20 mA for V ≤ 2 V)
0.75 x V
DD
OH
DD
V
Low Level Output Voltage (CRD_I/O= CRD_AUX1 = CRD_AUX2 = 0 V)
= +1 mA
OL
I
OL
0
−
−
0.3
V
t
Ri/Fi
Input Rising/Falling Times (Note 6)
Output Rising/Falling Times (Note 6)
−
1.2
ms
t
Ro/Fo
−
−
−
−
0.1
1
ms
MHz
kW
V
F
Maximum Frequency through Bidirectional I/O, AUX1 and AUX2 Channels (Note 6)
I/0uc, AUX1uc, AUX2uc Pullup Resistor
bidi
R
8.0
11
16
pu
V
OH
Output High Voltage
INT @ I = −15 mA (Source)
0.6 x V
−
−
OH
DD
V
Output Low Voltage
V
OL
INT @ I = 2 mA (Sink)
0
−
0.30
60
OL
R
INT
INT Pullup Resistor
40
50
kW
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
6. Guaranteed by design and characterization
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7
NCN8024R
SMART CARD INTERFACE SECTION, CRD_IO, CRD_AUX1, CRD_AUX2, CRD_CLK, CRD_RST, CRD_PRES,
CRD_PRES (V = 3.3 V; V
= 5 V; T
= 25°C; F
= 10 MHz)
DD
DDP
amb
CLKIN
Symbol
Rating
Min
Typ
Max
Unit
CRD_RST @ CRD_V = 3.0 V, 5.0 V
CC
V
Output RESET V @ I = −200 mA
0.9 x CRD_V
0
−
−
CRD_V
0.20
V
V
OH
OL
OH
rst
CC
CC
V
Output RESET V @ I = 200 mA
OL
rst
V
0
CC
−
−
0.4
CRD_V
V
V
Output RESET V @ I = −20 mA
OH
OL
OH
rst
V
CRD_V − 0.4
Output RESET V @ I = 20 mA
CC
OL
rst
t
−
−
−
−
100
100
ns
ns
Output RESET Risetime @ C = 100 pF (Note 7)
R
F
out
t
Output RESET Falltime @C = 100 pF (Note 7)
out
t
d
−
−
2
ms
RSTIN to CRD_RST Delay − Reset Enabled (Note 7)
CRD_CLK @ CRD_V = 3.0 V or 5.0 V
CC
F
Output Frequency (Note 7)
−
−
18
MHz
CRDCLK
V
Output CRD_CLK V @ I = −200 mA
0.9 x CRD_V
0
−
−
CRD_V
+0.2
V
V
OH
OL
OH
clk
CC
CC
V
Output CRD_CLK V @ I = 200 mA
OL
clk
V
0
CC
−
−
0.4
CRD_V
V
V
Output CRD_CLK V @ I = −70 mA
OH
OL
OH
clk
V
CRD_V −0.4
Output CRD_CLK V @ I = 70 mA
CC
OL
clk
F
t
45
−
55
%
Output Duty Cycle (Note 7)
DC
Rise & Fall time (Note 5)
−
−
−
−
16
16
ns
ns
Output CRD_CLK Risetime @ C = 30 pF
Output CRD_CLK Falltime @ C = 30 pF
rills
out
out
t
ulsa
SR
0.2
−
−
V/ns
Slew Rate @ Cout = 33 pF (Note 7)
CRD_AUX1, CRD_AUX2, CRD_IO @ CRD_V = 3.0 V, 5.0 V
CC
Input Voltage High Level (5 V Mode)
Input Voltage High Level (3 V Mode)
Input Voltage Low Level
V
V
2.3
1.6
−
−
CRD_V +0.3
V
V
V
IH
IH
IL
CC
CRD_V +0.3
CC
0.80
V
0.30
Low Level Input Current V = 0 V
−
−
IL
I
IL
I
High Level Input Current V = CRD_V
−
−
600
10
mA
mA
IH
CC
IH
Output V
Output V
OH
V
@ I = −40 mA
−
OH
OH
0.75 x CRD_V
CRD_V +0.1
V
CC
CC
OL
V
@ I = 1 mA, V = 0 V
−
−
−
OL
OL
IL
0
0.30
1.2
V
Input Rising/Falling Times
t
−
ms
Ri/Fi
Output Rising/Falling Times / C = 80 pF
out
t
−
8.0
−
0.1
16
ms
kW
ns
Ro/Fo
R
PU
CRD_AUX1, CRD_AUX2, CRD_IO Pullup Resistor
11
t
IO
Propagation delay I
Edge) (Note 7)
−> CRD_IO and CRD_IO −> IOuc (Falling
−
200
Ouc
t
Active pull−up pulse width buffers I/O, AUX1 & AUX2 (Note 7)
−
200
−
ns
V
pu
CRD_PRES, CRD_PRES
V
V
Card Presence Voltage High Level
Card Presence Voltage Low Level
0.7 x V
−0.3
V
+ 0.3
0.3 x V
IH
IL
DD
DD
DD
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Guaranteed by design and characterization
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8
NCN8024R
SMART CARD INTERFACE SECTION, CRD_IO, CRD_AUX1, CRD_AUX2, CRD_CLK, CRD_RST, CRD_PRES,
CRD_PRES (V = 3.3 V; V
= 5 V; T
= 25°C; F
= 10 MHz)
DD
DDP
amb
CLKIN
Symbol
Rating
Min
Typ
Max
Unit
CRD_PRES, CRD_PRES
mA
|I
|
High level input leakage current, V = V
IH
IH
DD
CRD_PRES
CRD_PRES
Low level input leakage current, V = 0 V
CRD_PRES
CRD_PRES
3
10
1
|I |
IL
IL
1
10
3
8
T
Debounce Time CRD_PRES and CRD_PRES (Note 7)
CRD_IO, CRD_AUX1, CRD_AUX2 Current Limitation
CRD_CLK Current Limitation
5
−
12
15
ms
mA
mA
mA
ms
debounce
I
−
CRD_IO
CRD_CLK
CRD_RST
I
−
−
70
I
CRD_RST Current Limitation
−
−
20
t
act
Activation Time (Note 7)
30
30
−
−
100
250
−
t
Deactivation Time (Note 7)
−
ms
deact
Temp
Shutdown Temperature
160
°C
SD
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Guaranteed by design and characterization
POWER SUPPLY
The NCN8024R smart card interface has two power
application, to adjust the V UVLO threshold. If not used
PORADJ pin is connected to Ground (recommended even
if it may be left unconnected).
The input supply voltage is continuously monitored to
prevent under voltage operation. At power up, the system
initializes the internal logic during POR timing and no
further signal can be provided or supported during this
period.
DD
supplies: V and V
.
DD
DDP
V
DD
is usually common to the system controller and the
interface. The applied V ranges from 2.7 V up to 5.5 V.
DD
If V
goes below 2.30 V typical (UVLO
) a
DD
VDD
power−down sequence is automatically performed. In that
case the interrupt (INT) pin is set Low.
A Low Drop−Out (LDO) and low noise regulator is used
to provide the 3 V or 5 V power supply voltage (CRD_V
to the card. VDDP is the LDO’s input voltage. CRD_V is
the LDO output. The typical distributed reservoir output
capacitor connected to CRD_V is 100 nF + 220 nF. To
minimize dI/dt effects the capacitor of 100 nF is connected
as close as possible to the CRD_V ’s pin and the 220 nF
one as close as possible to the card connector C1 pin. Both
feature very low ESR values (lower than 50 mW). The
decoupling capacitors on V
100 nF and 10 mF have also to be connected close to the
respective IC pins.
The CRD_VCC pin can source up to 70 mA continuously
over the VDDP range, the absolute maximum current being
internally limited below 150 mA (Typical at 120 mA).
The system is ready to operate when the input voltage has
)
CC
reached the minimum
V . Considering this, the
DD
NCN8024R will detect an Under−Voltage situation when
the input supply voltage will drop below 2.30 V typical.
CC
When V goes down below the UVLO falling threshold a
CC
DD
deactivation sequence is performed.
The device is inactive during power−on and power−off of
CC
the V supply (8 ms reset pulse).
DD
PORADJ pin is used to modify the UVLO threshold
according to the below relationship considering an external
resistor divider R1 / R2 (see block diagram Figure 1):
and V
respectively
DD
DDP
R1 ) R2
UVLO +
VPOR
R2
If PORADJ is connected to Ground the V
UVLO
DD
threshold (V falling) is typically 2.30 V. In some cases it
DD
There’s no specific sequence for applying V or V
.
DD
DDP
can be interesting to adjust this threshold at a higher value
They can be applied to the interface in any sequence. After
powering the device INT pin remains Low until a card is
inserted.
and by the way increase the V supply dropout detection
DD
level which enables a deactivation sequence if the V
voltage is too low.
DD
For example, there are microcontrollers for which the
minimum supply voltage insuring a correct operating is
SUPPLY VOLTAGE MONITORING
The supply voltage monitoring block includes the Power
On Reset (POR) circuitry and the under voltage lockout
higher than 2.70 V, increasing UVLO
(V falling) is
VDD
DD
consequently necessary. Considering for instance a resistor
(UVLO) detection (V
voltage dropout detection).
DD
PORADJ pin allows the user, according to the considered
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9
NCN8024R
STANDBY MODE
bridge with R1 = 56 kW, R2 = 42 kW and V
= 1.20 V
POR−
After a Power−on reset, the circuit enters the standby
mode. A minimum number of circuits are active while
waiting for the microcontroller to start a session:
typical the V dropout detection level can be increased up to:
DD
59k ) 42k
UVLO +
VPOR− + 2.75 V
42k
• All card contacts are inactive
The minimum dropout detection voltage should be higher
than 2 V.
The maximum detection level may be up to VDD.
• Pins I/Ouc, AUX1uc and AUX2uc are in the
high−impedance state (11 kW pull−up resistor to V
• Card pins are inactive and pulled Low
• Supply Voltage monitoring is active
)
DD
CLOCK DIVIDER:
The input clock can be divided by 1/1, 1/2, 1/4, or 1/8,
depending upon the specific application, prior to be applied
to the smart card driver. These division ratios are
programmed using pins CLKDIV1 and CLKDIV2 (see
Table 1). The input clock is provided externally to pin
CLKIN.
POWER−UP
In the standby mode the microcontroller can check the
presence of a card using the signals INT and CMDVCC as
shown in Table 2:
Table 2. Card Presence State
Table 1. Clock Frequency Programming
INT
CMDVCC
HIGH
State
CLKDIV1
CLKDIV2
F
CRD_CLK
HIGH
LOW
Card present
Card not present
0
0
1
1
0
1
0
1
CLKIN/8
CKLKIN / 4
CLKIN
HIGH
If a card is detected present (CRD_PRES or CRD_PRES
active) the controller can start a card session by pulling
CMDVCC Low. Card activation is run (t0, Figure 5). This
Power−Up Sequence makes sure all the card related signals
CLKIN / 2
The clock input stage (CLKIN) can handle a 27 MHz
maximum frequency signal. Of course, the ratio must be
defined by the user to cope with Smart Card considered in
a given application
In order to avoid any duty cycle out of the 45% / 55%
range specification, the divider is synchronized by the last
flip flop, thus yielding a constant 50% duty cycle, whatever
be the divider ratio 1/2, 1/4 or 1/8. On the other hand, the
output signal Duty Cycle cannot be guaranteed 50% if the
division ratio is 1 and if the input Duty Cycle signal is not
within the 46 − 56% range at the CLKIN input.
When the signal applied to CLKIN is coming from the
external controller, the clock will be applied to the card
under the control of the microcontroller or similar device
after the activation sequence has been completed.
DATA I/O, AUX1 and AUX2 LEVEL SHIFTERS
The three bidirectional level shifters I/O, AUX1 and
AUX2 adapt the voltage difference that might exist between
the micro−controller and the smart card. These three
channels are identical. The first side of the bidirectional
level shifter dropping Low (falling edge) becomes the driver
side until the level shifter enters again in the idle state pulling
High CRD_IO and I/Ouc.
are LOW during the CRD_V positive going slope. These
CC
lines are validated when CRD_V is stable and above the
minimum voltage specified. When the CRD_V voltage
reaches the programmed value (3.0 V or 5.0 V), the circuit
activates the card signals according to the following
sequence (Figure 5):
CC
CC
• CRD_V is powered−up at its nominal value (t1)
CC
• I/O, AUX1 and AUX2 lines are activated (t2)
• Then Clock channel is activated and the clock signal is
applied to the card (typically 500 ns after I/Os lines)
(t3)
• Finally the Reset level shifter is enabled (typically
500 ns after clock channel) (t4)
The clock can also be applied to the card using a RSTIN
mode allowing controlling the clock starting by setting
RSTIN Low (Figure 4). Before running the activation
sequence, that is before setting Low CMDVCC RSTIN is set
High. The following sequence is applied:
• The Smart Card Interface is enable by setting
CMDVCC LOW (RSTIN is High).
• Between t2 (Figure 4) and t5 = 200 ms, RSTIN is reset
to LOW and CCLK will start precisely at this moment
allowing a precise count of clock cycles before toggling
CRST Low to High for ATR (Answer To Reset)
request.
• CRST remains LOW until 200 ms; after t5 = 200 ms
CRST is enabled and is the copy of RSTIN which has
no more control on the clock.
Passive 11 kW pull−up resistors have been internally
integrated on each terminal of the bidirectional channel. In
addition with these pull−up resistors, an active pull−up
circuit provides a fast charge of the stray capacitance.
The current to and from the card I/O lines is limited
internally to 15 mA and the maximum frequency on these
lines is 1 MHz.
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10
NCN8024R
If controlling the clock with RSTIN is not necessary
The internal activation sequence activates the different
channels according to a specific hardware built−it sequencing
internally defined but at the end the actual activation
sequencing is the responsibility of the application software
and can be redefined by the micro−controller to comply with
the different standards and the different ways the standards
manage this activation (for example light differences exist
between the EMV and the ISO7816 standards).
(Normal Mode), then /CMDVCC can be set LOW with
RSTIN LOW. In that case, CLK will start minimum 500 ns
after the transition on I/O (Figure 5), and to obtain an ATR,
CRST can be set High by RSTIN also about 500 ns after the
clock channel activation (tact).
CMDVCC
CVCC
CIO
ATR
CCLK
RSTIN
CRST
t0
t1 t2
t4
t5
−200 ms
Figure 4. Activation Sequence − RSTIN mode (RSTIN Starting High)
CMDVCC
CVCC
CIO
ATR
CCLK
RSTIN
CRST
t4
t0
t1 t2 t3
t
act
Figure 5. Activation Sequence − Normal Mode
POWER−DOWN
When the communication session is completed the
NCN8024R runs a deactivation sequence by setting High
CMDVCC. The below power down sequence is executed:
• CRD_RST is forced to Low
• CRD_CLK is set Low 12 ms after CRD_RST.
• CRD_IO, CRD_AUX1 and CRD_AUX2 are pulled Low
• Finally CRD_V supply can be shut−off.
CC
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11
NCN8024R
CMDVCC
CRD_RST
CRD_CLK
CRD_IO
CRD_VCC
t
deact
Figure 6. Deactivation Sequence
FAULT DETECTION
• Card pin current limitation: in the case of a short circuit
to ground. No feedback is provided to the external MPU.
• LDO operation: the internal circuit continuously senses
In order to protect both the interface and the external smart
card, the NCN8024R provides security features to prevent
failures or damages as depicted here after.
the CRD_V voltage (in the case of either over or
CC
• Card extraction detection
under voltage situation).
• V under voltage detection
DD
• LDO operation: under−voltage detection on V
overload on VUP
or
DDP
• Short−circuit or overload on CRD_V
CC
• Overheating
• Card pin current limitation: in the case of a short circuit
to ground. No feedback is provided to the external
MPU
CRD_PRES
INT
CMDVCC
Debounce
Debounce
CRD_VCC
Powerdown Resulting of
Card Extraction
Powerdown Caused by
Short−Circuit
Figure 7. Fault Detection and Interrupt Management
Interrupt Pin Management:
A card session is opened by toggling CMDVCC High to
Low.
Before a card session, CMDVCC is supposed to be in a
High position. INT is Low if no card is present in the card
connector (Normally open or normally closed type). INT is
High if a card is present. If a card is inserted (INT = High)
During a card session, CMDVCC is Low and INT pin
goes Low when a fault is detected. In that case a deactivation
is immediately and automatically performed (see Figure 6).
When the microcontroller resets CMDVCC to High it can
sense the INT level again after having got completed the
deactivation.
As illustrated by Figure 7 the device has a debounce timer
of 8 ms typical duration. When a card is inserted, output INT
goes High only at the end of the debounce time. When the
card is removed a deactivation sequence is automatically
and immediately performed and INT goes Low.
and if V drops below the UVLO threshold then INT pin
DD
drops Low immediately. It turns back High when V
increases again over the UVLO limit (including hysteresis),
a card being still present.
DD
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12
NCN8024R
ESD PROTECTION
CRD_RST,
CRD_CLK,
CRD_IO,
CRD_AUX1,
The NCN8024R includes devices to protect the pins
against the ESD spikes voltages. To cope with the different
ESD voltages developed across these pins, the built in
structures have been designed to handle either 2 kV, when
related to the micro controller side, or 8 kV when connected
with the external contacts (HBM model). Practically, the
CRD_AUX2, CRD_PRES and CRD_PRES pins can sustain
8 kV. The CRD_VCC pin has the same ESD protection and
can source up to 70 mA continuously, the absolute
maximum current being internally limited with a max at
150 mA. The CRD_VCC current limit depends on V
and CRD_VCC.
DDP
VDD
+3.3V
XTAL1 XTAL2
AUX2uc
AUX1uc
CLKDIV1
CLKDIV2
5V/3V
I/Ouc
3.3 V Microcontroller
NC
GNDP
100 nF
10 mF
CLKIN
INT
NC
VDDP
GND
NC
100 nF
VDD
NC
RSTIN
CMDVCC
CRD_PRES
CRD_PRES
CRD_I/O
PORADJ
Optional R1/R2 resistor divider − if not
used PORADJ has to be connnected to
Ground
CRD_AUX2
CRD_VCC
CRD_RST
R1
R2
100 kW
CRD_AUX1
CRD_GND
VDD
CRD_CLK
+3.3V
220 nF
1
2
3
4
5
6
7
8
VCC
RST
CLK
C4
100 nF
GND
VPP
I/O
C8
DET
Normally Open
SMART CARD
Figure 8. Application Schematic
Package
ORDERING INFORMATION
Device
†
Shipping
NCN8024RDWR2G
SOIC−28
(Pb−Free)
1000 / Tape & Reel
NCN8024RDTBR2G*
TSSOP−28
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Consult Sales Office
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13
NCN8024R
PACKAGE DIMENSIONS
SOIC−28 WB
CASE 751F−05
ISSUE H
−X−
D
28
15
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBER
PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN
EXCESS OF B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
H
E
M
M
Y
0.25
−Y−
1
14
PIN 1 IDENT
MILLIMETERS
DIM MIN
MAX
2.65
0.29
0.49
0.32
18.05
7.60
A
A1
B
2.35
0.13
0.35
0.23
17.80
7.40
A
L
C
0.10
D
E
−T− SEATING
G
A1
G
H
1.27 BSC
PLANE
C
10.05
0.41
0
10.55
0.90
8
B
L
M
M
M
S
S
Y
_
_
0.025
T X
SOLDERING FOOTPRINT*
8X
11.00
28X
1.30
1
28
28X
0.52
1.27
PITCH
14
15
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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14
NCN8024R
PACKAGE DIMENSIONS
TSSOP28
CASE 948AA
ISSUE A
NOTES:
e
B
28
15
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DETAIL A
E1 E
PIN ONE
LOCATION
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
2X
MILLIMETERS
1
14
DIM MIN
−−−
A1 0.05
A2 0.80
0.19
b1 0.19
MAX
1.20
0.15
1.05
0.30
0.25
0.20
0.16
9.80
0.20 C B A
0.05
A
A
A
b
A2
A
A
D
c
c1
D
0.09
0.09
9.60
0.10
C
SEATING
PLANE
E
6.40 BSC
E1 4.30
4.50
e
L
L1
R
R1 0.09
S
01
02
03
0.65 BSC
A1
28X
b
0.45
0.75
C
1.00 REF
02
0.10 C B A
0.09
−−−
−−−
−−−
8
S
H
0.20
0
R1
_
_
12 REF
_
(b)
b1
R
12 REF
_
GAUGE PLANE
c
c1
L
(L1)
0.25
01
03
RECOMMENDED
SECTION A−A
SOLDERING FOOTPRINT*
DETAIL A
28X
0.42
28X
1.15
6.70
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
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NCN8024R/D
相关型号：
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