NCP1011AP133 [ONSEMI]
0.25A SWITCHING REGULATOR, 143kHz SWITCHING FREQ-MAX, PDIP7, PLASTIC, DIP-7;
| 型号： | NCP1011AP133 |
| 厂家： | 
ONSEMI |
| 描述： | 0.25A SWITCHING REGULATOR, 143kHz SWITCHING FREQ-MAX, PDIP7, PLASTIC, DIP-7 开关 光电二极管 |
| 文件： | 总24页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1010, NCP1011,
NCP1012, NCP1013,
NCP1014
Self−Supplied Monolithic
Switcher for Low Standby−
Power Offline SMPS
http://onsemi.com
The NCP101X series integrates a fixed−frequency current−mode
controller and a 700 V voltage MOSFET. Housed in a PDIP7 package,
the NCP101X offers everything needed to build a rugged and
low−cost power supply, including soft−start, frequency jittering,
short−circuit protection, skip−cycle, a maximum peak current setpoint
and a Dynamic Self−Supply (no need for an auxiliary winding).
Unlike other monolithic solutions, the NCP101X is quiet by nature:
during nominal load operation, the part switches at one of the available
frequencies (65−100−130 kHz). When the current setpoint falls below
a given value, e.g. the output power demand diminishes, the IC
automatically enters the so−called skip cycle mode and provides
excellent efficiency at light loads. Because this occurs at typically 1/4
of the maximum peak value, no acoustic noise takes place. As a result,
standby power is reduced to the minimum without acoustic noise
generation.
MARKING
DIAGRAM
PDIP−7
CASE 626A
AP SUFFIX
P101xAPyy
8
1
1
x
= 0, 1, 2, 3 or 4
yy = 06(65 kHz), 10(100 kHz), 13(130 kHz)
PIN CONNECTIONS
Short−circuit detection takes place when the feedback signal fades
away, e.g. in true short−circuit conditions or in broken Optocoupler
cases. External disabling is easily done either simply by pulling the
feedback pin down or latching it to ground through an inexpensive
SCR for complete latched−off. Finally soft−start and frequency
jittering further ease the designer task to quickly develop low−cost and
robust offline power supplies.
VCC
NC
NC
FB
GND
NC
1
2
3
4
8
7
DRAIN
5
For improved standby performance, the connection of an auxiliary
winding stops the DSS operation and helps to consume less than
100 mW at high line. In this mode, a built−in latched overvoltage
protection prevents from lethal voltage runaways in case the
Optocoupler would brake.
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 22 of this data sheet.
Features
• Latched Overvoltage Protection with Auxiliary
Winding Operation
• Built−in 700 V MOSFET with Typical Rds
and 23 W
of 11 W
(ON)
• Frequency Jittering for Better EMI Signature
• Large Creepage Distance Between High−Voltage Pins
• Current−Mode Fixed Frequency Operation:
65 kHz–100 kHz−130 kHz
• Below 100 mW Standby Power if Auxiliary Winding is
Used
• Internal Temperature Shutdown
• Skip−Cycle Operation at Low Peak Currents Only: No
Acoustic Noise!
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient and AC
Analysis
• Dynamic Self−Supply, No Need for an Auxiliary
Winding
Typical Applications
• Internal 1.0 ms Soft−Start
• Low Power AC/DC Adapters for Chargers
• Auto−Recovery Internal Output Short−Circuit
• Auxiliary Power Supplies (USB, Appliances,
Protection
TVs, etc.)
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
July, 2003 − Rev. 2
NCP1010/D
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Indicative Maximum Output Power from NCP1014
Rdson−Ip
230 VAC
14 W
100−250 VAC
6.0 W
11 W−450 mA DSS
11 W−450 mA Auxiliary Winding
19 W
8.0 W
1. Informative values only, with: Tamb = 50°C, Fswitching = 65 kHz, circuit mounted on minimum copper area as recommended.
Vout
+
+
100−250 VAC
1
2
3
4
8
7
5
+
NCP101X
Gnd
Figure 1. Typical Application Example
Quick Selection Table
NCP1010*
NCP1011*
NCP1012**
NCP1013**
NCP1014***
Rds
[W]
23
11
(on)
Ipeak [mA]
Freq [kHz]
100
250
250
350
450
65
100 130
65
100 130
65
100 130
65
100 130
65
100
* Release to market Q4, 2003.
** 65 kHz version release in Q3, 2003.
*** Release to market Q3, 2003.
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2
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
VCC
Powers the Internal Circuitry
This pin is connected to an external capacitor of typically 10 mF.
The natural ripple superimposed on the V participates to the
CC
frequency jittering. For improved standby performance, an auxiliary
V
CC
can be connected to pin 1. The V also includes an active
CC
shunt which serves as an opto fail−safe protection.
2
3
4
NC
NC
FB
−
−
−
−
Feedback Signal Input
By connecting an optocoupler to this pin, the peak current setpoint
is adjusted accordingly to the output power demand.
5
−
7
8
Drain
−
Drain Connection
The internal drain MOSFET connection.
−
−
NC
Gnd
−
This unconnected pin ensures adequate creepage distance.
−
The IC Ground
Startup Source
V
CC
Iref = 7.4 mA
IV
−
+
1
8
GND
VCC
Drain
CC
Vclamp*
Rsense
S
High when V t 3 V
CC
UVLO
Management
I?
R
IV
CC
250 ns
L.E.B.
Q
Reset
2
3
4
7
NC
NC
60, 100 or
130 kHz
Clock
Q
Set
EMI Jittering
4 V
Flip−Flop
DCmax = 65%
Driver
Reset
V
CC
18 k
Error flag armed?
NC
−
+
0.5 V
+
Overload?
−
Startup Sequence
Overload
Soft−start
5
Drain
FB
Drain
*Vclamp = VCC
+ 200 mV (8.7 V Typical)
OFF
Figure 2. Simplified Internal Circuit Architecture
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3
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 10
−0.3 to 700
15
Unit
V
Power Supply Voltage on all pins, except Pin 5 (Drain)
Drain Voltage
V
CC
−
V
Maximum Current into Pin 1 when Activating the 8.7 V Active Clamp
Thermal Resistance, Junction−to−Air – PDIP−7
Maximum Junction Temperature
I_V
mA
°C/W
°C
CC
JA
R
100
q
T
JMAX
150
Storage Temperature Range
−
−60 to +150
2.0
°C
ESD Capability, HBM Model (All pins except HV)
ESD Capability, Machine Model
−
−
kV
V
200
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4
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = 0°C to +125°C, Max T = 150°C,
J
J
J
V
CC
= 8.0 V unless otherwise noted.)
Rating
Pin
Symbol
Min
Typ
Max
Unit
SUPPLY SECTION AND V MANAGEMENT
CC
V
V
V
V
Increasing Level at which the Current Source Turns−off
1
1
1
1
1
VCC
7.9
6.9
4.4
−
8.5
7.5
9.1
8.1
5.1
−
V
V
CC
CC
CC
CC
OFF
Decreasing Level at which the Current Source Turns−on
Decreasing Level at which the Latch−off Phase Ends
Decreasing Level at which the Internal Latch is Released
VCC
ON
VCC
VCC
4.7
V
latch
reset
3.0
V
Internal IC Consumption, MOSFET Switching at 65 kHz
Internal IC Consumption, MOSFET Switching at 100 kHz
Internal IC Consumption, MOSFET Switching at 130 kHz
ICC1
−
0.92
1.1
(Note 1)
mA
1
1
ICC1
ICC1
−
−
0.95
0.98
1.15
(Note 1)
mA
mA
1.2
(Note 1)
Internal IC Consumption, Latch−off Phase, V = 6.0 V
1
1
1
ICC2
Vclamp
ILatch
−
290
200
7.4
−
mA
mV
mA
CC
Active Zener Voltage Positive Offset to VCC
Latch−off Current
160
6.3
260
9.2
OFF
POWER SWITCH CIRCUIT
Power Switch Circuit On−state Resistance
NCP1012/13/14 (Id = 50 mA)
5
Rds
−
W
(ON)
T = 25°C
T = 125°C
j
11
19
16
24
j
NCP1010/11 (Id = 50 mA)
T = 25°C
T = 125°C
j
23
43
−
−
j
Power Switch Circuit and Startup Breakdown Voltage
(ID = 100 mA, T = 25°C)
5
BVdss
700
−
−
V
(off)
j
Power Switch and Startup Breakdown Voltage Off−state
Leakage Current
Ids(OFF)
mA
T = 25°C (Vds = 700 V)
T = 125°C (Vds = 700 V)
j
5
5
−
−
50
30
−
−
j
Switching Characteristics
ns
(RL = 50 W, Vds Set for Idrain = 0.7 x Ilim)
Turn−on Time (90%−10%)
Turn−off Time (10%−90%)
5
5
ton
toff
−
−
20
10
−
−
INTERNAL START−UP CURRENT SOURCE
High−voltage Current Source, V = 8.0 V
1
1
IC1
IC2
5.0
−
8.0
10
10
−
mA
mA
CC
High−voltage Current Source, V = 0
CC
CURRENT COMPARATOR T = 25°C (Note 1)
J
Maximum Internal Current Setpoint, NCP1010
Maximum Internal Current Setpoint, NCP1011
Maximum Internal Current Setpoint, NCP1012
Maximum Internal Current Setpoint, NCP1013
Maximum Internal Current Setpoint, NCP1014
5
5
5
5
5
−
Ipeak (23)
Ipeak (23)
Ipeak (11)
Ipeak (11)
Ipeak (11)
−
−
100
250
250
350
450
25
−
−
mA
mA
mA
mA
mA
%
225
315
−
275
385
−
Default Internal Current Setpoint for Skip Cycle Operation,
Percentage of Max Ip
I
−
−
Lskip
Propagation Delay from Current Detection to Drain OFF State
Leading Edge Blanking Duration
−
−
T
T
−
−
125
250
−
−
ns
ns
DEL
LEB
1. See characterization curves for temperature evolution.
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5
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
ELECTRICAL CHARACTERISTICS (continued) (For typical values T = 25°C, for min/max values T = 0°C to +125°C,
J
J
Max T = 150°C, V = 8.0 V unless otherwise noted.)
J
CC
Rating
Pin
Symbol
Min
Typ
Max
Unit
INTERNAL OSCILLATOR
Oscillation Frequency, 65 kHz Version, T = 25°C (Note 2)
−
−
−
−
f
f
f
60
90
117
−
65
100
72
110
143
−
kHz
kHz
kHz
%
j
OSC
OSC
OSC
Oscillation Frequency, 100 kHz Version, T = 25°C (Note 2)
j
Oscillation Frequency, 130 kHz Version, T = 25°C (Note 2)
130
j
Frequency Dithering Compared to Switching Frequency
(with active DSS)
f
"3.3
dither
Maximum Duty−cycle
−
Dmax
60
67
72
%
FEEDBACK SECTION
Internal Pull−up Resistor
4
−
Rup
Tss
−
−
18
−
−
kW
Internal Soft−start (Guaranteed by Design)
SKIP CYCLE GENERATION
Default Skip Mode Level on FB Pin
TEMPERATURE MANAGEMENT
Temperature Shutdown
1.0
ms
4
Vskip
−
0.5
−
V
−
−
TSD
−
−
−
150
50
−
−
°C
°C
Hysteresis in Shutdown
2. See characterization curves for temperature evolution.
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.50
−2.0
−3.0
−4.0
−5.0
−6.0
−7.0
−8.0
−9.0
−10.0
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. IC1 @ VCC = 8.0 V, FB = 1.5 V
vs. Temperature
Figure 4. ICC1 @ VCC = 8.0 V, FB = 1.5 V
vs. Temperature
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
9.00
8.90
8.80
8.70
8.60
8.50
8.40
8.30
8.20
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. ICC2 @ VCC = 6.0 V, FB = Open
vs. Temperature
Figure 6. VCC OFF, FB = 1.5 V vs.
Temperature
68
68
67
67
66
66
65
8.00
7.90
7.80
7.70
7.60
7.50
7.40
7.30
7.20
7.10
7.00
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. VCC ON, FB = 3.5 V vs. Temperature
Figure 8. Duty Cycle vs. Temperature
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
9.00
8.80
8.60
8.40
8.20
8.00
7.80
7.60
7.40
7.20
7.00
500
480
460
440
420
400
380
360
340
320
300
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. ILatch, FB = 1.5 V vs. Temperature
Figure 10. Ipeak−RR, VCC = 8.0 V, FB = 3.5 V
vs. Temperature
160
140
120
100
80
25.00
130 kHz
100 kHz
20.00
15.00
10.00
5.00
60
40
0.00
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Frequency vs. Temperature
Figure 12. ON Resistance vs. Temperature,
NCP1012/1013
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8
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
APPLICATION INFORMATION
Introduction
No acoustic noise while operating: Instead of skipping
cycles at high peak currents, the NCP101X waits until the
peak current demand falls below a fixed 1/4 of the maximum
limit. As a result, cycle skipping can take place without
having a singing transformer … You can thus select cheap
magnetic components free of noise problems.
The NCP101X offers a complete current−mode control
solution (actually an enhanced NCP1200 controller section)
together with a high−voltage power MOSFET in a
monolithic structure. The component integrates everything
needed to build a rugged and low−cost Switch−Mode Power
Supply (SMPS) featuring low standby power. The quick
selection table details the differences between references,
mainly peak current setpoints and operating frequency.
SPICE model: A dedicated model to run transient
cycle−by−cycle simulations is available but also an
averaged version to help you closing the loop. Ready−to−use
templates can be downloaded in OrCAD’s PSpice, and
INTUSOFT’s IsSpice4 from ON Semiconductor web site,
NCP101X related section.
No need for an auxiliary winding: ON Semiconductor
Very High Voltage Integrated Circuit technology lets you
supply the IC directly from the high−voltage DC rail. We call
it Dynamic Self−Supply (DSS). This solution simplifies the
transformer design and ensures a better control of the SMPS
in difficult output conditions, e.g. constant current
operations. However, for improved standby performance,
Dynamic Self−Supply
When the power supply is first powered from the mains
outlet, the internal current source (typically 8.0 mA) is
biased and charges up the V capacitor from the drain pin.
CC
an auxiliary winding can be connected to the V pin to
disable the DSS operation.
CC
Once the voltage on this V capacitor reaches the VCC
CC
OFF
level (typically 8.5 V), the current source turns off and
pulses are delivered by the output stage: the circuit is awake
and activates the power MOSFET. Figure 13 details the
internal circuitry.
Short−circuit protection: By permanently monitoring the
feedback line activity, the IC is able to detect the presence of
a short−circuit, immediately reducing the output power for
a total system protection. Once the short has disappeared, the
controller resumes and goes back to normal operation.
Vref OFF = 8.5 V
Drain
Vref ON = 7.5 V
Fail−safe optocoupler and OVP: When an auxiliary
winding is connected to the V pin, the device stops its
CC
Vref Latch = 4.7 V*
internal Dynamic Self−Supply and takes its operating power
from the auxiliary winding. A 8.7 V active clamp is
+
Startup Source
−
connected between V and ground. In case the current
CC
injected in this clamp exceeds a level of 7.4 mA (typical),
the controller immediately latches off and stays in this
V
CC
Internal Supply
position until the user cycle V
down to 3.0 V (e.g.
CC
unplugging the converter from the wall). By adjusting a
+
limiting resistor in series with the V terminal, it becomes
+
Vref
CC
CV
VCC
+200 mV
(8.7 V Typ.)
CC
OFF
possible to implement an over voltage protection function,
latching off the circuit in case of broken optocoupler or
feedback loop problems.
*In fault condition
Low standby−power: If SMPS naturally exhibits a good
efficiency at nominal load, they begin to be less efficient
when the output power demand diminishes. By skipping
unneeded switching cycles, the NCP101X drastically
reduces the power wasted during light load conditions. An
auxiliary winding can further help decreasing the standby
power to extremely low levels by invalidating the DSS
operation. Typical measurements show results below
80 mW @ 230 VAC for a typical 7.0 W universal power
supply.
Figure 13. The Current Source Regulates VCC
by Introducing a Ripple
Being loaded by the circuit consumption, the voltage on
the V capacitor goes down. When the DSS controller
CC
detects that V has reached 7.5 V (VCC ), it activates the
CC
ON
internal current source to bring V toward 8.5 V and stops
again: a cycle takes place whose low frequency depends on
CC
the V capacitor and the IC consumption. A 1.0 V ripple
CC
takes place on the V pin whose average value equals
CC
(VCC
+ VCC )/2. Figure 14 portrays a typical
OFF
ON
operation of the DSS.
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
8.5 V
8.00
7.5 V
Vcc
6.00
4.00
2.00
0
Device
Internally
Pulses
Startup Period
Figure 14. The Charge/Discharge Cycle Over a 10 mF VCC Capacitor
As one can see, the V capacitor shall be dimensioned to
offer an adequate startup time, i.e. ensure regulation is
activates again to attempt a new restart. If the error has gone,
the IC automatically resumes its operation. If the default is
still there, the IC pulses during 8.5 V down to 7.5 V and
enters a new latch−off phase. The resulting burst operation
guarantees a low average power dissipation and lets the
SMPS sustain a permanent short−circuit. Figure 15 presents
the corresponding diagram.
CC
reached before V crosses 7.5 V (otherwise the part enters
CC
the fault condition mode). If we know that DV = 1.0 V
and ICC1 (max.) is 1.1 mA (for instance we selected an 11 W
device switching at 65 kHz), then the V capacitor can
CC
ICC1 · tstartup
(eq. 1)
be calculated using: C w
. Let’s
DV
suppose that the SMPS needs 10 ms to startup, then we will
calculate C to offer a 15 ms period. As a result, C should be
greater than 20 mF thus the selection of a 33 mF/16 V
capacitor is appropriate.
Current Sense
Information
4 V
+
−
FB
Short Circuit Protection
To
Latch
Reset
Division
The internal protection circuitry involves a patented
arrangement that permanently monitors the assertion of an
internal error flag. This error flag is, in fact, a signal that
instructs the controller that the internal maximum peak
current limit is reached. This naturally occurs during the
startup period (Vout is not stabilized to the target value) or
when the optocoupler LED is no longer biased, e.g in a
short−circuit condition or when the feedback network is
broken. When the DSS normally operates, the logic checks
V
CC
VCC
Signal
ON
Max
Ip
Flag
Clamp
Active?
for the presence of the error flag every time V crosses
CC
VCC . If the error flag is low (peak limit not active) then
ON
Figure 15. Simplified NCP101X Short−Circuit
Detection Circuitry
the IC works normally. If the error signal is active, then the
NCP101X immediately stops the output pulses, reduces its
internal current consumption and does not allow the startup
The protection burst duty−cycle can easily be computed
through the various timing events as portrayed by Figure 16.
source to activate: V drops toward ground until it reaches
CC
the so−called latch−off level, where the current source
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Tsw
1 V Ripple
Tstart
Tlatch
Latch−off
Level
Figure 16. NCP101X Facing a Fault Condition (Vin = 150 VDC)
Vds(t)
The rising slope from the latch−off level up to 8.5 V
DV1 · C
IC1
is expressed by: tstart +
. The time during which
toff
DV2 · C
the IC actually pulses is given by tsw +
.
Vr
ICC1
Vin
dt
Finally, the latch−off time can be derived
DV3 · C
ICC2
using the same formula topology: tlatch +
.
From these three definitions, the burst duty−cycle
tsw
(eq. 2)
can be computed: dc +
.
tstart ) tsw ) tlatch
ton
DV2
t
dc +
.
Feeding the
(eq. 3)
DV3
DV2
DV1
ICC1 · ǒ
Ǔ
)
)
ICC2
ICC1
IC1
Tsw
equation with values extracted from the parameter section
gives a typical duty−cycle of 13%, precluding any lethal
thermal runaway while in a fault condition.
Figure 17. A typical drain−ground waveshape
where leakage effects are not accounted for.
DSS Internal Dissipation
By looking at Figure 17, the average result can easily be
derived by additive square area calculation:
The Dynamic Self−Supplied pulls energy out from the
drain pin. In Flyback−based converters, this drain level can
easily go above 600 V peak and thus increase the stress on the
DSS startup source. However, the drain voltage evolves with
time and its period is small compared to that of the DSS. As
a result, the averaged dissipation, excluding capacitive losses,
(eq. 4)
toff
Tsw
(eq. 5)
t Vds(t) u+ Vin · (1 * d) ) Vr ·
By developing equation 5, we obtain:
ton
Tsw
toff
Tsw
(eq. 6)
t Vds(t) u+ Vin * Vin ·
) Vr ·
can be derived by: P
+ ICC1 · t Vds(t) u .
.
DSS
Figure 17 portrays a typical drain−ground waveshape where
leakage effects have been removed.
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Lp
Vr
Where:
(eq. 7)
Toff can be expressed by: toff + Ip ·
where
Vnom is the auxiliary voltage at nominal load.
Vstdby is the auxiliary voltage when standby is entered.
Lp
Ton can be evaluated by: ton + Ip ·
Vin
(eq. 8)
.
Plugging equations 7 and 8 into equation 6 leads to
Itrip is the current corresponding to the nominal operation.
It thus must be selected to avoid false tripping in overshoot
conditions.
(eq. 9)
t Vds(t) u+ Vin and thus, P
+ Vin ICC1
.
DSS
The worse case occurs at high line, when Vin equals
370 VDC. With ICC1 = 1.1 mA (65 kHz version), we can
expect a DSS dissipation around 407 mW. If you select a
higher switching frequency version, the ICC1 increases and
it is likely that the DSS consumption exceeds that number.
In that case, we recommend to add an auxiliary winding in
order to offer more dissipation room to the power MOSFET.
Please read application note “Evaluating the Power
Capability of the NCP101X Members” to help in selecting
the right part/configuration for your application.
ICC1 is the controller consumption. This number slightly
decreases compared to ICC1 from the spec since the part in
standby does almost not switch.
VCC
is the level above which Vauxiliary must be
ON
maintained to keep the DSS in the OFF mode. It is good to
shoot around 8.0 V in order to offer an adequate design
margin, e.g. to not reactivate the startup source (which is not
a problem in itself if low standby power does not matter).
Since Rlimit shall not bother the controller in standby, e.g.
keep Vauxiliary to around 8.0 V (as selected above), we
purposely select a Vnom well above this value. As explained
before, experience shows that a 40% decrease can be seen on
auxiliary windings from nominal operation down to standby
mode. Let’s select a nominal auxiliary winding of 20 V to
offer sufficient margin regarding 8.0 V when in standby
(Rlimit also drops voltage in standby…). Plugging the
values in equation 10 gives the limits within which Rlimit
shall be selected:
Lowering the Standby Power with an Auxiliary Winding
The DSS operation can bother the designer when a) its
dissipation is too high b) extremely low standby power is a
must. In both cases, one can connect an auxiliary winding to
disable the self−supply. The current source then ensures the
startup sequence only and stays in the off state as long as
V
does not drop below VCC or 7.5 V. Figure 18 shows
CC
ON
that the insertion of a resistor (Rlimit) between the auxiliary
DC level and the V pin is mandatory a) not to damage the
CC
internal 8.7 V active zener diode during an overshoot for
instance (absolute maximum current is 15 mA) b) to
implement the fail−safe optocoupler protection as offered by
the active clamp. Please note that there cannot be bad
interaction between the clamping voltage of the internal
20 * 8.7
6.3m
12 * 8
1.1m
v Rlimit v
, that is to say :
(eq. 11)
1.8 k t Rlimit t 3.6 k
If we design a power supply delivering 12 V, then the ratio
between auxiliary and power must be: 12/20 = 0.6. The OVP
latch will activate when the clamp current exceeds 6.3 mA.
This will occur when Vauxiliary grows−up to: 8.7 V + 1.8 k
x (6.4m + 1.1m) = 22.2 V for the first boundary or 8.7 V +
3.6 k x (6.4m +1.1m) = 35.7 V for second boundary. On the
power output, it will respectively give 22.2 x 0.6 = 13.3 V
and 35.7 x 0.6 = 21.4 V. As one can see, tweaking the Rlimit
value will allow the selection of a given overvoltage output
level. Theoretically predicting the auxiliary drop from
nominal to standby is an almost impossible exercise since
many parameters are involved, including the converter time
constants. Fine tuning of Rlimit thus requires a few
iterations and experiments on a breadboard to check
Vauxiliary variations but also output voltage excursion in
fault. Once properly adjusted, the fail−safe protection will
preclude any lethal voltage runaways in case a problem
would occur in the feedback loop.
zener and VCC
since this clamping voltage is actually
OFF
built on top of VCC
(200 mV typical).
with a fixed amount of offset
OFF
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (Vnom), this voltage can drop to below
10 V (Vstby) when entering standby. This is because the
recurrence of the switching pulses expands so much that the
low frequency refueling rate of the V capacitor is not
CC
enough to keep a constant auxiliary voltage. Figure 19
portrays a typical scope shot of a SMPS entering deep
standby (output unloaded). So care must be taken when
calculating Rlimit 1) to not trigger the V over current
CC
latch [by injecting 6.3 mA (min. value) into the active
clamp] in normal operation but 2) not to drop too much
voltage over Rlimit when entering standby. Otherwise the
DSS could reactivate and the standby performance would
degrade. We are thus able to bound Rlimit between two
equations:
Vnom * Vclamp
Vstby * VCC
ON
(eq. 10)
v Rlimit v
Itrip
ICC1
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Drain
VCC = 8.5 V
ON
VCC
= 7.5 V
OFF
−
+
+
Startup Source
V
CC
Rlimit
D1
+
−
+
+
+
CVcc
CAux
Laux
Vclamp = 8.7 V typ.
Permanent
Latch
+
−
+
I > 7.4m
(typ.)
Ground
Figure 18. A more detailed view of the NCP101X offers better insight on how to
properly wire an auxiliary winding.
u30 ms
Figure 19. The burst frequency becomes so low that it is difficult to keep
an adequate level on the auxiliary Vcc . . .
When an OVP occurs, all switching pulses are
permanently disabled, the output voltage thus drops to zero.
However, the recurrent frequency in skip often enters the
audible range and a high peak current obviously generates
acoustic noise in the transformer. The noise takes its origins
in the resonance of the transformer mechanical structure
which is excited by the skipping pulses. A possible
solution, successfully implemented in the NCP1200 series,
also authorizes skip cycle but only when the power demand
as dropped below a given level. At this time, the peak
current is reduced and no noise can be heard. Figure 20
pictures the peak current evolution of the NCP101X
entering standby.
The V cycles up and down between 8.5–4.7 V and stays
CC
in this state until the user unplugs the power supply and
forces V to drop below 3.0 V (VCC
). Below this
CC
reset
value, the internal OVP latch is reset and when the high
voltage is reapplied, a new startup sequence can take place
in an attempt to restart the converter.
Lowering the Standby Power with Skip−Cycle
Skip cycle offers an efficient way to reduce the standby
power by skipping unwanted cycles at light loads.
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
100%
Peak current
at nominal power
Skip cycle
current limit
25%
Figure 20. Low Peak Current Skip Cycle Guarantees Noise−Free Operation
Full power operation involves the nominal switching
the benefit to artificially reduce the measurement noise on
a standard EMI receiver and pass the tests more easily. The
frequency and thus avoids any noise when running.
Experiments carried on a 5.0 W universal mains board
unveiled a standby power of 300 mW @ 230 VAC with the
DSS activated and dropped to less than 100 mW when an
auxiliary winding is connected.
EMI sweep is implemented by routing the V
ripple
CC
(induced by the DSS activity) to the internal oscillator. As a
result, the switching frequency moves up and down to the
DSS rhythm. Typical deviation is "3.3% of the nominal
frequency. With a 1.0 V peak−to−peak ripple, the frequency
will equal 65 kHz in the middle of the ripple and will
Frequency Jittering for Improved EMI Signature
By sweeping the switching frequency around its nominal
value, it spreads the energy content on adjacent frequencies
rather than keeping it centered in one single ray. This offers
increase as V rises or decrease as V ramps down.
CC
CC
Figure 21 portrays the behavior we have adopted.
VCC
OFF
V
CC
Ripple
67.15 kHz
65 kHz
62.85 kHz
VCC
Internal Sawtooth
ON
Figure 21. The VCC ripple is used to introduce a frequency jittering on the internal oscillator sawtooth.
Here, a 65 kHz version was selected.
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Soft−Start
The soft−start is also activated during the over current burst
(OCP) sequence. Every restart attempt is followed by a
soft−start activation. Generally speaking, the soft−start will
The NCP101X features an internal 1.0 ms soft−start
activated during the power on sequence (PON). As soon as
V
CC
reaches VCC , the peak current is gradually
be activated when V ramps up either from zero (fresh
OFF
CC
increased from nearly zero up to the maximum internal
clamping level (e.g. 350 mA). This situation lasts 1.0 ms
and further to that time period, the peak current limit is
blocked to the maximum until the supply enters regulation.
power−on sequence) or 4.7 V, the latch−off voltage
occurring during OCP. Figure 22 portrays the soft−start
behavior. The time scales are purposely shifted to offer a
better zoom portion.
8.5 V
V
CC
0 V (Fresh PON)
or
4.7 V (Overload)
Current
Sense
Max Ip
1.0 ms
Figure 22. Soft−start is activated during a start−up sequence or an OCP condition.
Non−Latching Shutdown
and ground. By pulling FB below the internal skip level
(Vskip), the output pulses are disabled. As soon as FB is
relaxed, the IC resumes its operation. Figure 23 depicts the
application example.
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
1
2
3
4
8
7
5
Drain
ON/OFF
+
CV
cc
Figure 23. A non−latching shutdown where pulses are stopped as long as the NPN is biased.
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Full Latching Shutdown
When the OVP level exceeds the zener breakdown
voltage, the NPN biases the PNP and fires the equivalent
SCR, permanently bringing down the FB pin. The
switching pulses are disabled until the user unplugs the
power supply.
Other applications require a full latching shutdown, e.g.
when an abnormal situation is detected (over temp or
overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
Rhold
12 k
OVP
1
2
3
4
8
7
10 k
BAT54
5
Drain
+
CV
cc
10 k
Figure 24. Two Bipolars Ensure a Total Latch−Off of the SMPS in Presence of an OVP
Rhold ensures that the SCR stays on when fired. The bias
current flowing through Rhold should be small enough to let
maximum power the device can thus evacuate is:
Tjmax * Tambmax
(eq. 12)
Pmax +
which gives around
1.0 W for an ambient of 50°C. The losses inherent to the
MOSFET Rds can be evaluated using the following
R
−
qJ A
the V ramp up (8.5 V) and down (7.5 V) when the SCR
CC
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolars can be MMBT2222
and MMBT2907 for the discrete latch. The MMBT3946
features two bipolars NPN+PNP in the same package and
could also be used.
(ON)
1
3
2
(eq. 13)
formula: Pmos + · Ip · d · Rds
, where Ip
is the worse case peak current (at the lowest line input), d is
the converter operating duty−cycle and Rds , the
(ON)
(ON)
MOSFET resistance for Tj = 100°C. This formula is only
valid for Discontinuous Conduction Mode (DCM)
operation where the turn−on losses are null (the primary
current is zero when you restart the MOSFET). Figure 25
gives a possible layout to help dropping the thermal
resistance. When measured on a 35 mm (1 oz.) copper
thickness PCB, we obtained a thermal resistance of 75°C/W.
Power Dissipation and Heatsinking
The NCP101X welcomes two dissipating terms, the DSS
current−source (when active) and the MOSFET. Thus,
Ptot = P
+ P . When the PDIP7 package is
MOSFET
DSS
surrounded by copper, it becomes possible to drop its
thermal resistance junction−to−ambient, R down
to 75°C/W and thus dissipate more power. The
qJ−A
Figure 25. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Design Procedure
1. In any case, the lateral MOSFET body−diode shall
never be forward biased, either during start−up
(because of a large leakage inductance) or in
normal operation as shown by Figure 26.
The design of an SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices:
350
250
150
50.0
−50.0
> 0 !!
1.004M
1.011M
1.018M
1.025M
1.032M
Figure 26. The Drain−Source Wave Shall Always be Positive . . .
As a result, the Flyback voltage which is reflected on the
drain and source), N the Np:Ns turn ratio, Vout the
output voltage, Vf the secondary diode forward
drop and finally, Ip the maximum peak current.
Worse case occurs when the SMPS is very close to
regulation, e.g. the Vout target is almost reached
and Ip is still pushed to the maximum.
drain at the switch opening cannot be larger than the input
voltage. When selecting components, you thus must adopt
a turn ratio which adheres to the following equation:
(eq. 14)
N · (Vout ) Vf) t Vin
. For instance, if you
min
operate from a 120 V DC rail and you deliver 12 V, we can
select a reflected voltage of 100 VDC maximum: 120–100
> 0. Therefore, the turn ratio Np:Ns must be smaller than
100/(12 + 1) = 7.7 or Np:Ns < 7.7. We will see later on how
it affects the calculation.
Taking into account all previous remarks, it becomes
possible to calculate the maximum power that can be
transferred at low line.
When the switch closes, Vin is applied across the primary
inductance Lp until the current reaches the level imposed by
the feedback loop. The duration of this event is called the ON
time and can be defined by:
2. A current−mode architecture is, by definition,
sensitive to subharmonic oscillations.
Subharmonic oscillations only occur when the
SMPS is operating in Continuous Conduction
Mode (CCM) together with a duty−cycle greater
than 50%. As a result, we recommend to operate
the device in DCM only, whatever duty−cycle it
implies (max. = 65%). However, CCM operation
with duty−cycles below 40% is possible.
Lp · Ip
Vin
(eq. 16)
Ton +
At the switch opening, the primary energy is transferred
to the secondary and the flyback voltage appears across
Lp, resetting the transformer core with a slope of
N · (Vout ) Vf)
. Toff, the OFF time is thus:
3. Lateral MOSFETs have a poorly dopped
body−diode which naturally limits their ability to
sustain the avalanche. A traditional RCD clamping
network shall thus be installed to protect the
MOSFET. In some low power applications,
a simple capacitor can also be used since
Lp
Lp · Ip
N · (Vout ) Vf)
(eq. 17)
Toff +
If one wants to keep DCM only, but still need to pass the
maximum power, we will not allow a dead−time after the
core is reset, but rather immediately restart. The switching
time can be expressed by:
Lf
Vdrain max + Vin ) N · (Vout ) Vf) ) Ip ·Ǹ
Ctot
(eq. 15) , where Lf is the leakage inductance, Ctot
the total capacitance at the drain node (which is
increased by the capacitor you will wire between
1
1
Tsw + Toff ) Ton + Lp · Ip · ǒ
Ǔ
)
Vin N · (Vout ) Vf)
(eq. 18)
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
The Flyback transfer formula dictates that:
Example 1, a 12 V 7.0 W SMPS operating on a large
mains with NCP101X:
Pout
1
2
2
(eq. 19)
+
· Lp · Ip · Fsw
which, by extracting
h
Vin = 100 VAC to 250 VAC or 140 VDC to 350 VDC once
rectified, assuming a low bulk ripple
Ip and plugging into equation 19, leads to:
2 · Pout
h · Fsw · Lp
1
1
· ǒ
Ǔ
Tsw + Lp
)
Ǹ
Efficiency = 80%
Vin N · (Vout ) Vf)
Vout = 12 V, Iout = 580 mA
Fswitching = 65 kHz
(eq. 20)
Extracting Lp from equation 20 gives:
2
(Vin · Vr) · h
Ip max = 350 mA – 10% = 315 mA
Lp
critical
+
2
2
2 · Fsw · [Pout · (Vr ) 2 · Vr · Vin ) Vin )]
Applying the above equations leads to:
(eq. 21) , with Vr = N . (Vout + Vf) and h the efficiency.
If Lp critical gives the inductance value above which
DCM operation is lost, there is another expression we can
write to connect Lp, the primary peak current bounded by
the NCP101X and the maximum duty−cycle that needs to
stay below 50%:
Selected maximum reflected voltage = 120 V
with Vout = 12 V, secondary drop = 0.5 V → Np:Ns = 1:0.1
Lp critical = 3.2 mH
Ip = 292 mA
Duty−cycle worse case = 50%
Idrain RMS = 119 mA
DCmax · Vinmin · Tsw
(eq. 22)
Lpmax +
where Vinmin
Ipmax
corresponds to the lowest rectified bulk voltage, hence the
longest Ton duration or largest duty−cycle. Ip max is the
available peak current from the considered part, e.g. 350 mA
typical for the NCP1013 (however, the minimum value of
this parameter shall be considered for reliable evaluation).
Combining equations 21 and 22 gives the maximum
theoretical power you can pass respecting the peak current
capability of the NCP101X, the maximum duty−cycle and
the discontinuous mode operation:
P
P
= 354 mW at Rdson = 24 W (Tj > 100°C)
MOSFET
= 1.1 mA x 350 V = 385 mW, if DSS is used
DSS
Secondary diode voltage stress = (350 x 0.1) + 12 = 47 V
(e.g. a MBRS360T3, 3.0 A/60 V would fit)
Example 2, a 12 V 16 W SMPS operating on narrow
European mains with NCP101X:
Vin = 230 VAC " 15%, 276 VDC for Vin min to 370 VDC
once rectified
2
2
2
Pmax :+ Tsw · Vinmin · Vr · h ·
Efficiency = 80%
Fsw
2
Vout = 12 V, Iout = 1.25 A
Fswitching = 65 kHz
(2 · Lpmax · Vr ) 4 · Lpmax · Vr · Vinmin
2
(eq. 23)
) 2 · Lpmax · Vinmin )
From equation 22 we obtain the operating duty−cycle
Ip max = 350 mA – 10% = 315 mA
Ip · Lp
Vin · Tsw
current circulating in the MOSFET:
(eq. 24)
d +
which lets us calculate the RMS
Applying the equations leads to:
Selected maximum reflected voltage = 250 V
with Vout = 12 V, secondary drop = 0.5 V → Np:Ns = 1:0.05
Lp = 6.6 mH
d
(eq. 25)
IdRMS + Ip · Ǹ
obtain the average dissipation in the MOSFET:
. From this equation, we
3
Ip = 0.305 mA
1
3
2
(eq. 26)
Pavg + · Ip · d · Rds
to which switching
(ON)
Duty−cycle worse case = 0.47
Idrain RMS = 121 mA
losses shall be added.
If we stick to equation 23, compute Lp and follow the
above calculations, we will discover that a power supply
built with the NCP101X and operating from a 100 VAC line
minimum will not be able to deliver more than 7.0 W
continuous, regardless of the selected switching frequency
(however the transformer core size will go down as
Fswitching is increased). This number grows up
significantly when operated from a single European mains
(18 W). Application note “Evaluating the Power Capability
of the NCP101X Members” details how to assess the
available power budget from all the NCP101X series.
P
= 368 mW at Rdson = 24 W (Tj > 100°C)
MOSFET
P
DSS
= 1.1 mA x 370 V = 407 mW, if DSS is used below an
ambient of 50°C.
Secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 V
(e.g. a MBRS340T3, 3.0 A/40 V)
Please note that these calculations assume a flat DC rail
whereas a 10 ms ripple naturally affects the final voltage
available on the transformer end. Once the Bulk capacitor has
been selected, one should check that the resulting ripple (min
Vbulk?) is still compatible with the above calculations. As an
example, to benefit from the largest operating range, a 7.0 W
board was built with a 47 mF bulk capacitor which ensured
discontinuous operation even in the ripple minimum waves.
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
MOSFET Protection
As in any Flyback design, it is important to limit the
drain excursion to a safe value, e.g. below the MOSFET
BVdss which is 700 V. Figure 27 presents possible
implementations:
HV
HV
HV
Cclamp
Dz
Rclamp
D
D
1
2
3
4
8
7
1
2
3
4
8
7
1
2
3
4
8
7
5
5
5
+
+
+
CVcc
CVcc
C
CVcc
Praded
Praded
Praded
17A
17B
17C
Figure 27. Different Options to Clamp the Leakage Spike
Figure 27A: The simple capacitor limits the voltage
according to equation 15. This option is only valid for low
power applications, e.g. below 5.0 W, otherwise chances
exist to destroy the MOSFET. After evaluating the leakage
inductance, you can compute C with equation 15. Typical
values are between 100 pF and up to 470 pF. Large
capacitors increase capacitive losses…
current. Worse case occurs when Ip and Vin are maximum
and Vout is close to reach the steady−state value.
Figure 27C: This option is probably the most expensive of
all three but it offers the best protection degree. If you need a
very precise clamping level, you must implement a zener
diode or a TVS. There are little technology differences
behind a standard zener diode and a TVS. However, the die
area is far bigger for a transient suppressor than that of zener.
A 5.0 W zener diode like the 1N5388B will accept 180 W
peak power if it lasts less than 8.3 ms. If the peak current in
the worse case (e.g. when the PWM circuit maximum
current limit works) multiplied by the nominal zener voltage
exceeds these 180 W, then the diode will be destroyed when
the supply experiences overloads. A transient suppressor
like the P6KE200 still dissipates 5.0 W of continuous power
but is able to accept surges up to 600 W @ 1.0 ms. Select the
zener or TVS clamping level between 40 to 80 volts above
the reflected output voltage when the supply is heavily
loaded.
Figure 27B: The most standard circuitry called the RCD
network. You calculate Rclamp and Cclamp using the
following formulae:
2 · Vclamp · (Vclamp * (Vout ) Vf sec) · N)
Rclamp +
2
Lleak · Ip · Fsw
(eq. 27)
Vclamp
Vripple · Fsw · Rclamp
(eq. 28)
Cclamp +
Vclamp is usually selected 50−80 V above the reflected
value N x (Vout + Vf). The diode needs to be a fast one and
a MUR160 represents a good choice. One major drawback
of the RCD network lies in its dependency upon the peak
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Typical Application Examples
Dynamic Self−Supply and
a simplified zener−type
feedback. This configuration was selected for cost reasons
and a more precise circuitry can be used, e.g. based on a
TL431:
A 6.5 W watt NCP1012−based Flyback converter
Figure 28 shows a converter built with a NCP1012
delivering 6.5 W from a universal input. The board uses the
D6
B150
C1
2.2 nF
1N4007
1N4007
TR1
1
4
8
7
E3
470 m/25 V
R2
150 k
D5
U160
D1 D2
2
1
6
5
E1
R1
47 R
10 m/400 V
IC1
NCP1012
ZD1
11 V
J2
CZM5/2
1
5
IC2
PC817
1
2
VCC
HV
E2
2
R3
100 R
4
8
GND
GND
GND GND
FB
3
7
J1
CEE7.5/2
R4
180 R
D3 D4
1N4007
1N4007
10 m/16 V
C2
2n2/Y
Figure 28. An NCP1012−Based Flyback Converter Delivering 6.5 Watts
The converter built according to Figure 29 layouts, gave
the following results:
• Efficiency at Vin = 100 VAC and Pout = 6.5 W = 75.7%
• Efficiency at Vin = 230 VAC and Pout = 6.5 W = 76.5%
Figure 29. The NCP1012−Based PCB Layout . . . and its Associated Component Placement
A 7.0 watt NCP1013−based Flyback converter featuring
low standby power
Figure 30 depicts another typical application showing a
NCP1013−65 kHz operating in a 7.0 W converter up to
70°C of ambient temperature. We can grow−up the output
power since an auxiliary winding is used, the DSS is
disabled, and thus offering more room for the MOSFET. In
this application, the feedback is made via a TLV431 whose
low bias current (100 mA min) helps to lower the no−load
standby power.
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NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
Vbulk
1N4148
D4
R4 22
L2
22 mH
D2
C8
10 nF
400 V
R7
100 k/
1 W
MBRS360T3
12 V @
0.6 A
T1
Aux
+
+
+
C10
33 mF/25 V
100 mF/16 V
+
C7
GND
C6 C8
470 mF/16 V
T1
D3
MUR160
R2
3.3 k
R3
1 k
NCP1013P06
C2
47 mF/
450 V
+
R5
39 k
1
8
V
GND
NC
CC
2 NC
3 NC
4 FB
7
5
D
+
100 mF/10 V
C3
C4
C9
1 nF
IC1
SFH6156−2
100 nF
IC2
TLV431
R6
4.3 k
C5
2.2 nF
Y1 Type
Figure 30. A Typical Converter Delivering 7.0 W from a Universal Mains
Measurements have been taken from a demonstration
board implementing Figure 30’s sketch and the following
results were achieved, with either the auxiliary winding in
place or through the Dynamic Self−Supply:
A9619−C, Lp = 3.0 mH, Np:Ns = 1:0.1, 7.0 W
application on universal mains, including auxiliary winding,
NCP1013−65kHz.
A0032−A, Lp = 6.0 mH, Np:Ns = 1:0.055, 10 W
application on European mains, DSS operation only,
NCP1013−65 kHz.
Vin = 230 VAC, auxiliary winding, Pout = 0, Pin = 60 mW
Vin = 100 VAC, auxiliary winding, Pout = 0, Pin = 42 mW
Coilcraft
1102 Silver Lake Road
CARY IL 60013
Email: info@coilcraft.com
Tel.: 847−639−6400
Fax.: 847−639−1469
Vin = 230 VAC, Dynamic Self−Supply, Pout = 0,
Pin = 300 mW
Vin = 100 VAC, Dynamic Self−Supply, Pout = 0,
Pin = 130 mW
Pout = 7.0 W, h = 81% @ 230 VAC, with aux winding
Pout = 7.0 W, h = 81.3 @ 100 VAC, with aux winding
For a quick evaluation of Figure 30 application example,
the following transformers are available from Coilcraft:
http://onsemi.com
21
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
ORDERING INFORMATION
Frequency
(kHz)
R
DS(on)
(W)
Device Order Number
NCP1010AP065
NCP1010AP100
NCP1010AP133
NCP1011AP065
NCP1011AP100
NCP1011AP133
NCP1012AP065
NCP1012AP100
NCP1012AP133
NCP1013AP065
NCP1013AP100
NCP1013AP133
NCP1014AP065
NCP1014AP100
Package Type
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
Shipping
Ipk (mA)
100
100
100
250
250
250
250
250
250
350
350
350
450
450
65
100
130
65
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
50 Units / Rail
23
23
23
23
23
23
11
11
11
11
11
11
11
11
100
130
65
100
130
65
100
130
65
100
http://onsemi.com
22
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
PACKAGE DIMENSIONS
7−LEAD PDIP
AP SUFFIX
CASE 626A−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
8
5
4. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
5. DIMENSIONS A AND B ARE DATUMS.
B
L
M
1
4
MILLIMETERS
INCHES
MIN
J
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
NOTE 3
A
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
K
L
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
_
1.01
−−−
0.030
10
_
0.040
−T−
SEATING
PLANE
N
D
K
G
H
M
M
M
0.13 (0.005)
T
A
B
http://onsemi.com
23
NCP1010, NCP1011, NCP1012, NCP1013, NCP1014
The products described herein (NCP1010, 1011, 1012, 1013, 1014), may be covered by one or more of the following U.S. patents:
6,271,735; 6,385,060, 6,587,357. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
JAPAN: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800−282−9855 Toll Free USA/Canada
NCP1010/D
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