NCP1091DG [ONSEMI]
控制器,PoE-PD 接口,集成式,带可编程 UVLO;型号: | NCP1091DG |
厂家: | ONSEMI |
描述: | 控制器,PoE-PD 接口,集成式,带可编程 UVLO 驱动 控制器 光电二极管 接口集成电路 驱动程序和接口 |
文件: | 总12页 (文件大小:176K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCP1090, NCP1091,
NCP1092
Integrated IEEE 802.3af
PoE-PD Interface Controller
Description
The NCP1090, NCP1091 and NCP1092 are members of
ON Semiconductor’s high power HIPOt Power over Ethernet
Powered Device (PoE−PD) product family and integrate an IEEE
802.3af PoE−PD interface controller.
http://onsemi.com
The 3 variants all incorporate the required functions as such
detection, classification, under voltage lockout, inrush and operational
current limit. A power good signal has been added to guarantee a good
enabling/disabling of the DC−DC controller. In addition, the
NCP1091 offers a programmable under−voltage while the NCP1092
provide an auxiliary pin for applications supporting auxiliary supplies.
The NCP1090, NCP1091 and NCP1092 are fabricated in a robust
high voltage process and integrates a rugged vertical N−channel
DMOS suitable for the most demanding environments and capable of
withstanding harsh environments such as hot swap and cable ESD
events.
The NCP1090, NCP1091 and NCP1092 complement
ON Semiconductor’s ASSP portfolio in industrial devices and can be
combined with stepper motor drivers, CAN bus drivers and other
high−voltage interfacing devices to offer complete solutions to the
industrial and security market.
SOIC−8
S SUFFIX
CASE 751AZ
TSSOP−8
T SUFFIX
CASE 948S
PIN CONFIGURATION
1
VPORTP
INRUSH
CLASS
DET
*
PGOOD
RTN
VPORTN
(Top View)
* NCP1090 = NC
NCP1091 = UVLO
NCP1092 = AUX
Features
• Fully Supports IEEE 802.3af Specifications
• Programmable Classification Current
• Adjustable Under Voltage Lock Out (NCP1091 Only)
• Open−Drain Power Good Indicator
8
XXXXX
AYWWG
G
• 130 mA Inrush Current Limit
1
• 500 mA Operational Current Limit
XXXXXX = Specific Device Code
• Pass Switch Disabling Input for Rear Auxiliary Supply Operation
A
Y
WW
G
= Assembly Location
= Year
= Work Week
(NCP1092 Only)
• Over−temperature Protection
= Pb−Free Package
• Industrial Temperature Range −40°C to 85°C with Full Operation up
to 125°C Junction Temperature
• 0.5 W Hot−swap Pass−switch
ORDERING INFORMATION
• Vertical N−channel DMOS Pass−switch Offers the Robustness of
†
Device
Package
Shipping
Discrete MOSFETs
NCP109xxxx
SOIC−8
(Pb−Free)
2500/Tape &
Reel
NCP109xxxx
TSSOP−8
(Pb−Free)
2500/Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
February, 2011 − Rev. 2
NCP1090/D
NCP1090, NCP1091, NCP1092
VPORTP
DETECTION
INTERNAL
SUPPLY
THERMAL
SHUTDOWN
&
VOLTAGE
REFERENCE
DET
UVLO
EXTERNAL
SELECTION
UVLO
NCP1091 only
VPORT
MONITOR
CLASS
CLASSIFICATION
IEEE Interface
Shutdown
(AUX supply priority)
AUX
NCP1092 only
HOT SWAP SWITCH
CONTROL & CURRENT
LIMIT BLOCKS
PGOOD
POWER GOOD
INDICATOR
INRUSH &
OPERATIONAL
CURRENT LIMIT
INRUSH
RTN
VPORTN
Figure 1. NCP1090/91/92 Functional Block Diagram
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2
NCP1090, NCP1091, NCP1092
Simplified Application Diagrams
RJ−45
VPORTP
Rdet
Data
Pairs
DB1
DET
PGOOD
Rclass
CLASS
To DC−DC
Converter
NCP1090
Rinrush
INRUSH
RTN
DB2
NC
Spare
Pairs
VPORTN
Figure 2. Typical Application Circuit using the NCP1090
RJ−45
VPORTP
Rdet
Data
Pairs
DB1
DET
PGOOD
Rclass
CLASS
To DC−DC
Converter
NCP1091
Rinrush
INRUSH
UVLO
Ruvlo1
Ruvlo2
RTN
DB2
Spare
Pairs
VPORTN
Figure 3. Typical Application Circuit using the NCP1091 with External UVLO Setting
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3
NCP1090, NCP1091, NCP1092
Table 1. PIN DESCRIPTION
Pin No.
NCP1090 NCP1091 NCP1092
Name
Type
Description
INRUSH
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
6
Output
Current limit programming pin. Connect a resistor between
INRUSH and VPORTN.
CLASS
DET
Output
Classification current programming pin. Connect a resistor
between CLASS and VPORTN.
Output,
Open Drain
Detection pin. Connect a 24.9 kW resistor between DET and
VPORTP for a valid PD detection signature.
VPORTN
RTN
Ground
Negative input power. Connected to the source of the internal
pass−switch
Ground
DC−DC controller power return. Connected to the drain of the
internal pass−switch
PGOOD
Output,
Open Drain
Open Drain Power Good Indicator. Pin is in HZ mode when the
power good signal is active.
NC
7
−
−
−
−
No connection
UVLO
−
7
Input
Under−voltage lockout input. Voltage with respect to VPORTN.
Connect a resistor−divider from VPORTP to UVLO to
VPORTNx to set an external UVLO threshold.
AUX
−
−
7
8
Input
Input
Auxiliary Pin. When this pin is pulled up, the Pass Switch is
disabled and allows a supply transition from PSE to the rear
auxiliary supply connected between VPORTP and RTN.
VPORTP
8
8
Positive input power. Voltage with respect to VPORTN.
Operating Conditions
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
VPORTP
RTN
Parameter
Input power supply
Analog ground supply 2
Analog output
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−40
−
Max
72
Units
Conditions
Voltage with respect to VPORTN
Pass−switch in off−state (voltage with respect to VPORTN)
Voltage with respect to VPORTN
Voltage with respect to VPORTN
Voltage with respect to VPORTN
Voltage with respect to VPORTN
Voltage with respect to RTN
V
V
72
CLASS
INRUSH
AUX
72
V
Analog output
3.6
72
V
Analog input
V
UVLO
PGOOD
Ta
Analog input
3.6
72
V
Analog output
V
Ambient temperature
Junction temperature
85
°C
°C
°C
Tj
125
175
Tj−TSD
Junction temperature
(Note 1)
−
Thermal shutdown condition
T
stg
Storage Temperature
−55
150
°C
TθJA
Thermal Resistance,
Junction to Air (Note 2)
150
160
240
260
°C/W
SOIC−8
TSSOP−8
ESD−HBM
ESD−CDM
ESD−MM
LU
Human Body Model
Charged Device Model
Machine Model
2
kV
V
per EIA−JESD22−A114 standard
per ESD−STM5.3.1 standard
per EIA−JESD22−A115−A standard
per JEDEC Standard JESD78
500
200
100
V
Latch−up
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour
cumulative during the useful life for reliability reasons.
2. LowqJA is obtained with 2S2P test board (2 signal − 2 plane). High qJA is obtained with double sideboard with minimum pad area and natural
convection. Refer to Jedec JESD51 for details.
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4
NCP1090, NCP1091, NCP1092
Recommended Operating Conditions
Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the
functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the
recommended operating conditions for extended periods of time may affect device reliability.
Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.)
Symbol
INPUT SUPPLY
VPORT
Parameter
Min
Typ
Max
Units
Conditions
Input supply voltage
0
57
V
VPORT = VPORTP –
VPORTN
SIGNATURE DETECTION
Offset_det1
Sleep_det1
Offset_det2
Sleep_det2
I
I
I
I
+ I
+ I
+ I
+ I
2
5
mA
mA
mA
mA
VPORTP = RTN = 1.9 V
(VPORTP)
(VPORTP)
(VPORTP)
(VPORTP)
(RTN)
Rdet = 24.9 KW
15
21
VPORTP = RTN = 9.8 V
Rdet = 24.9 KW
(RTN)
I
73
77
81
VPORTP = RTN = 1.9 V
Rdet = 24.9 KW
(RTN) + (DET)
I
390
400
412
VPORTP = RTN = 9.8 V
Rdet = 24.9 KW
(RTN) + (DET)
CLASSIFICATION
Vcl_on
Classification current turn−on lower
9.8
21
11.3
13
24
V
V
VPORTP rising
threshold
Vcl_off
Classification current turn−off upper
threshold
VPORTP rising
Vclass_reg
Icl_bias
Classification buffer output voltage
9.8
V
13 V < VPORTP < 21 V
I(vportp) quiescent current during
classification
600
mA
I(class) excluded
13 V < VPORTP < 21 V
Iclass0
Iclass1
Iclass2
Iclass3
Iclass4
Class 0: Rclass 4420 W (Note 3)
Class 1: Rclass 953 W (Note 3)
Class 2: Rclass 549 W (Note 3)
Class 3: Rclass 357 W (Note 3)
Class 4: Rclass 255 W (Note 3)
0
−
−
−
−
−
4
mA
mA
mA
mA
mA
13 V < VPORTP < 21 V
13 V < VPORTP < 21 V
13 V < VPORTP < 21 V
13 V < VPORTP < 21 V
13 V < VPORTP < 21 V
9
12
20
30
44
17
26
36
UVLO − INTERNAL SETTING − NCP1090/91/92
Vuvlo_on
Vuvlo_off
Vhyst_int
Uvlo_filter
Default turn on voltage
Default turn off voltage
UVLO internal hysteresis
UVLO On / Off filter time
−
29.6
−
37
31
6
40
−
V
V
VPORTP rising
VPORTP falling
−
V
−
100
−
mS
For information only
VPORTP rising
UVLO − EXTERNAL SETTING – NCP1091 ONLY
Vuvlo_pr
Vuvlo_on2
Vhyst_off2
Uvlo_ipd
UVLO external programming range
External UVLO turn on voltage
External UVLO turn off voltage
UVLO internal pull down current
25
1.14
0.95
−
−
1.2
1
50
1.26
1.05
−
V
V
V
2.5
mA
AUXILIARY SUPPLY SETTING – NCP1092 ONLY
Aux_h
Aux_l
AUX input high level voltage
AUX input low level voltage
AUX internal pull down resistor
3.1
−
−
−
−
V
V
0.6
Aux_pd
100
−
KW
For information only
3. A tolerance of 1% on the Rclass resistor is included in the min/max values.
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5
NCP1090, NCP1091, NCP1092
Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
PASS−SWITCH AND CURRENT LIMITING
Ron
I_inrush
I_ilim
Pass−switch Rds−on
−
0.5
120
500
1
W
Measured with I(RTN) =
200 mA
Inrush current with Rinrush = 178 kW
75
170
575
mA
mA
Measured at
RTN−VPORTN = 3 V
Operating current limit with Rinrush =
178 kW
425
Current limit threshold
POWER GOOD INDICATOR
Vds_pgood_on
Vds_pgood_off
Pgood_filter
RTN−VPORTN threshold voltage
0.8
9
1
1.2
11
V
V
RTN−VPORTN falling
RTN−VPORTN rising
required for power good status
RTN−VPORTN latchoff threshold
voltage
10
PGOOD filter time
100
mS
Rising and falling /
for information only
Ipgood
I(PGOOD) sinking current
PGOOD voltage output low
−
−
−
5
mA
V
Vpgood_low
0.2
0.5
Voltage with respect to RTN
VPORTP = 48 V
CURRENT CONSUMPTION
IvportP I(VPORTP) internal current
−
600
900
mA
consumption
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thermal hysteresis
150
−
−
−
°C Tj
°C Tj
Tj = junction temperature
Tj = junction temperature
Thyst
−
15
THERMAL RATINGS
Ta
Tj
Ambient temperature
Junction temperature
−40
−
−
85
°C
°C
−
125
3. A tolerance of 1% on the Rclass resistor is included in the min/max values.
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6
NCP1090, NCP1091, NCP1092
Under Voltage Lock Out (UVLO)
Description of Operation
The NCP1090/91/92 incorporate a fixed under voltage
lock out (ULVO) circuit which monitors the input voltage
and determines when to turn on the pass switch and charge
the dc−dc converter input capacitor before the power up of
the application.
The NCP1091 offers a fixed or adjustable Vuvlo_on
threshold depending if the UVLO pin is used or not. In
Figure 5, the UVLO pin is strapped to ground and the
Vuvlo_on threshold is defined by the internal level.
Powered Device Interface
The integrated PD interface supports the IEEE 802.3af
defined operating modes: detection signature, current
source classification, undervoltage lockout, inrush and
operating current limits. The following sections give an
overview of these previous processes.
Detection
During the detection phase, the incremental equivalent
resistance seen by the PSE through the cable must be in the
IEEE 802.3af standard specification range (23.70 kW to
26.30 kW) for a PSE voltage from 2.7 V to 10.1 V. In order
to compensate for the non−linear effect of the diode bridge
and satisfy the specification at low PSE voltage, the
NCP1090/91/92 present a suitable impedance in parallel
with the 24.9 kW Rdet external resistor. For some types of
diodes (especially Schottky diodes), it may be necessary to
adjust this external resistor.
The Rdet resistor has to be inserted between VPORTP and
DET pins. During the detection phase, the DET pin is pulled
to ground and goes in high impedance mode (open−drain)
once the device exit this mode, reducing thus the current
consumption on the cable.
VPORTP
UVLO
VPORT
VPORTN1,2
Figure 5. Default Internal UVLO Configuration
(NCP1091 only)
To define the UVLO threshold externally, the ULVO pin
must be connected to the center of an external resistor
divider between VPORTP and VPORTN as shown in
Figure 6.
In order to guarantee the detection signature, the
equivalent input resistor made of the Ruvlo1, Ruvlo2 and
Rdet should be equal to 24.9 kW.
Classification
Once the PSE device has detected the PD device, the
classification process begins. In classification, the PD
regulates a constant current source that is set by the external
resistor RCLASS value on the CLASS pin. Figure 4 shows
the schematic overview of the classification block. The
current source is defined as:
9.8 V
Iclass +
VPORTP
Rclass
Rdet
Ruvlo1
Class_enable
1.2 V
VPORTP
CLASS
DET
VPORT
VPORTP
UVLO
EN
Ruvlo2
VPORTN1,2
NCP1091
9.8 V
Figure 6. Default Internal UVLO Configuration
(NCP1091 only)
For a Vuvlo_on desired turn−on voltage threshold,
Ruvlo1 and Ruvlo2 can be calculated using the following
equations:
VPORTN
24.9 k @ Rdet
Rdet * 24.9 k
Ruvlo +
Figure 4. Classification Block Diagram
Power Mode
When the classification hand−shake is completed, the
PSE and PD devices move into the operating mode.
with
and
Ruvlo1 ) Ruvlo2 + Ruvlo
1.2
Ruvlo2 +
@ Ruvlo
Vuvlo_on
With:
Vuvlo_on: Desired Turn−On voltage threshold
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7
NCP1090, NCP1091, NCP1092
Example for a Targeted Uvlo_on of 35 V:
and the PD application against excessive transient current
and failure on the dc−dc converter output.
Let’s start with a Rdet of 30.1 kΩ. This gives a Ruvlo of
144 kΩ made with a Ruvlo2 of 4.99 kΩ and a Ruvlo1 of
140 kΩ (closest values from E96 series). Note that there is
a pull down current of 2.5 mA typ on the UVLO. Assuming
the previous example, this pull down current will create a
(non critical) systematic offset of 350 mV on the Uvlon_on
level of 35 V.
Once the input supply reached the Vulvo_on level, the
charge of Cpd capacitor starts with a current limitation set to
to the INRUSH level. When this capacitor is fully charged,
the current limit switches without any spikes from the inrush
current to the operational current level and the power good
indicator on PGOOD pin is turned on. The capacitor is
considered to be fully charged once the following conditions
are satisfied:
The external UVLO hysteresis on the NCP1091 is about
15 percent typical.
1. The drain−source voltage of the Pass Switch has
decreased below the Vds_pgood_on level (typical
1 V)
2. The gate−source voltage of the Pass Switch is
sufficiently high (above 2 V typical) which means
the current in the pass switch has decreased below
the current limit.
Inrush and Operational Current Limitations
Both inrush and operational current limit are defined by
an external Rinrush resistor connected between INRUSH
and VPORTN. The low inrush current limit allows smooth
charge of large dc−dc converter input capacitor by limiting
the power dissipation over the internal pass switch. In power
mode, the operational current limit protects the pass switch
This mechanism is depicted in the following Figure 7.
PGOOD
Pgood_on
Inrush current limit
0
1
Operational current limit
Pgood_on
Delay
100 mS
&
VDDA1
VDDA1
1 V / 10 V
detector
2 V
RTN
Vds_pgood comparator
VPORTNx
Vgs_pgood comparator
Sense Resistor
RTN
Pass Switch
Figure 7. Inrush and Operational Current Limitation Selection Mechanism
PGOOD Indicator
The operational current limit and the power good
indicator stays active as long as RTN voltage stays below the
vds_pgood_off threshold (10 V typical) and the input supply
stay above the Vulvo_off level. Therefore, fast and large
voltage step lower than 10 V are tolerated on the input
without interruption of the converter controller. Higher
input transient will not affect the behavior if RTN does not
exceed 10 V for more than 100 mS. Such input voltage steps
may be introduced by a PSE which is switched to a higher
power supply. In case RTN is still above 10 V after this delay,
the power good is turned off and the pass switch current limit
falls back to the inrush level.
The NCP1090/91/92 integrate a Power Good indicator
circuitry indicating the end of the dc−dc converter input
capacitor charge, and the enabling of the operational current
limit. This indicator is implemented on the PGOOD pin
which goes in open drain state when active and which is
pulled to ground during turn off.
A possible usage of this PGOOD pin is illustrated in
Figure 8. During the inrush phase, the converter controller
is forced in standby mode due to the PGOOD pin forcing low
the under voltage lock out pin of the controller. Once the Cpd
capacitor is fully charged, PGOOD goes in open drain state,
allowing the start up sequence of the converter controller.
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8
NCP1090, NCP1091, NCP1092
VPORTP
DET
VDD
Rdet
PGOOD
UVLO
NCP103x
DC−DC Converter
Controller
Rclass
Rinrush
Cpd
CLASS
OVLO
GATE
NCP1090
VSS
INRUSH
RTN
VPORTN
Figure 8. Power GOOD Implementation
Auxiliary Supply
To support application connected to non−PoE enabled
networks and minimize the bill of materials, the NCP1093
supports drawing power from an external supply and allows
simplified designs with PoE or auxiliary supply priorities.
In most of the cases, the auxiliary supply is connected
between VPORTP and RTN with a serial diode between
VPORTP and VAUX, as shown in Figure 9.
RJ−45
VAUX (+)
VPORTP
Data
Pairs
Rdet
DB1
DET
PGOOD
Rclass
To DC−DC
Converter
CLASS
NCP1092
Rinrush
INRUSH
AUX
RTN
DB2
Spare
Pairs
VPORTN
VAUX (−)
Figure 9. Auxiliary Supply Dominant PD Interface
The NCP1092 offers an AUX input pin which turns off the
pass switch when pulled high. This feature is useful for PD
applications where the auxiliary supply has to be dominant
over the PoE supply. When the auxiliary supply is inserted
and the application will remain supplied by the auxiliary
supply. The transition will happens without any power
conversion interruption since the PGOOD indicator stays
active (high impedance state).
on
a
POE powered application, the pass switch
Next Figure 10 depicts an other PD application where the
POE supply is dominant over the VAUX supply. A diode D1
has been added in order to not corrupt the PD detection
signature when the dc−dc converter is supplied by VAUX.
disconnection will move the current path from the PSE to the
rear auxiliary supply. Since the current delivered by the PSE
will goes below the DC MPS level (specified in IEEE
802.3 af/at standard), the PSE will disconnect the PoE−PD
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9
NCP1090, NCP1091, NCP1092
VAUX (+)
D1
RJ−45
VPORTP
Data
Pairs
Rdet
DET
DB1
PGOOD
Rclass
CLASS
To DC−DC
Converter
NCP1092
Rinrush
INRUSH
RTN
DB2
AUX
Spare
Pairs
VPORTN
VAUX (−)
Figure 10. PoE Supply Dominant PD Interface
Thermal Shutdown
Company or Product Inquiries
The NCP1090/91/92 include a thermal shutdown which
protect the device in case of high junction temperature. Once
the thermal shutdown (TSD) threshold is exceeded, the
classification block, the pass switch and the PGOOD
indicator are disabled. The NCP109X returns automatically
to normal operation once the die temperature has fallen
below the TSD low limit.
For more information about ON Semiconductor’s Power
over Ethernet products visit our Web site at
http://www.onsemi.com.
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10
NCP1090, NCP1091, NCP1092
PACKAGE DIMENSIONS
SOIC−8
CASE 751AZ−01
ISSUE O
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11
NCP1090, NCP1091, NCP1092
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE C
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.20 (0.008) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
8
5
4
2X L/2
B
−U−
J
J1
L
1
PIN 1
IDENT
K1
K
S
0.20 (0.008) T U
A
SECTION N−N
−V−
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
4.50
1.10
0.15
0.70
MAX
0.122
0.177
0.043
0.006
0.028
A
B
2.90
4.30
---
0.114
0.169
---
−W−
C
C
0.076 (0.003)
D
0.05
0.50
0.002
0.020
F
DETAIL E
SEATING
D
−T−
G
G
J
0.65 BSC
0.026 BSC
PLANE
0.09
0.09
0.19
0.19
0.20
0.16
0.30
0.25
0.004
0.004
0.007
0.007
0.008
0.006
0.012
0.010
J1
K
0.25 (0.010)
N
K1
L
6.40 BSC
0.252 BSC
0
M
M
0
8
8
_
_
_
_
N
F
DETAIL E
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