NCP1096 [ONSEMI]
PoE-PD Interface Controller, IEEE 802.3bt;
| 型号： | NCP1096 |
| 厂家： | 
ONSEMI |
| 描述： | PoE-PD Interface Controller, IEEE 802.3bt 光电二极管 |
| 文件： | 总17页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PoE-PD Interface
Controller, IEEE 802.3bt
NCP1096
Description
The NCP1096 is a member of the ON Semiconductor Power over
Ethernet Powered Device (PoE−PD) product family, and allows the
device containing the NCP1096 based PD to become an IEEE
802.3af/at and −3bt compliant powered equipment.
It incorporates all the required functions for operation within a PoE
system such as detection, classification and current limiting during the
inrush phase. The NCP1096 supports high-power applications (up to
90 W PoE) through an internal pass transistor. A power good pin
guarantees proper disabling/enabling of the adjacent main DC/DC
converter. The classification result pins allow for operation according
to the assigned power Class (up to Class 8).
The NCP1096 also offers Autoclass support and indicates when
a short Maintain Power Signature can be implemented. In addition an
auxiliary supply detection pin allows NCP1096 to be used in
applications where power can be supplied by either PoE or by a wall
adapter.
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RELATED STANDARDS
IEEE 802.3bt−2018
16
1
TSSOP−16 EP
CASE 948BV
MARKING DIAGRAM
Features
16
• Fully Supports IEEE 802.3af/at and −3bt Specifications
• Supports Up to 5-Event Physical Layer Classification
• Assigned Power Level Up to 90 W
• Supports Autoclass
• 110 mA Typical Inrush Current Limiting
• Internal 70 mW Pass-switch
• Open Drain Power Good Indicator
• Support for Short MPS
NCP1096
AL
YYWW
1
NCP1096 = Specific Device Code
A
L
YY
WW
= Assembly Location
= Wafer Lot
= Year
• Pass Switch Disabling Input for Rear Auxiliary Supply Operation
• Proprietary 100 W+ Applications
• Over Current Protection
= Work Week
• Over Temperature Protection
ORDERING INFORMATION
• Junction Temperature Range of −40°C to +125°C
• Available in 16-pin TSSOP EP
†
Device
Package
Shipping
• These Devices are Pb−Free and are RoHS Compliant
NCP1096PAR2G TSSOP−16 EP
(Pb−Free)
2500 /
Tape & Reel
96 / Tube
NCP1096PAG
TSSOP−16 EP
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
July, 2020 − Rev. 2
NCP1096/D
NCP1096
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VPP
CLA
NCL
NCM
PGO
LCF
CLB
AUX
COSC
ACS
DET
NCP1096
RTN
GBR
TST2
TST1
VPN
Figure 1. Pin-out NCP1096 in 16-pin TSSOP EP (Top View)
PIN DESCRIPTION
Signal Name
VPP
Pin No.
Type
Description
1
Power
Positive input power.
Connect to the positive terminal of the rectifier bridge
CLA
CLB
2
3
4
5
Output
Output
Input
Connect a class signature programming resistor to VPN.
See classification section for recommended values
AUX
Auxiliary supply detection input. Referenced to VPN
COSC
Analog
Connect a 1 nF capacitor between COSC and VPN.
This pin is pulled to VPP during the detection phase
ACS
DET
6
7
Input
Autoclass enable/disable input.
Pull to VPN to disable Autoclass; leave floating to enable Autoclass
Output
Connect a 26.1 kW detection resistor between DET and COSC.
This pin is pulled to VPN during the detection phase
VPN
8
9
Power,
Ground
Negative input power.
Connect to the negative terminal of the rectifier bridge
TST1
Input
Positive side of the internal sense resistor (and the source of the internal
pass transistor). Leave floating
TST2
GBR
10
11
Output
Gate of the internal pass transistor. Leave floating
Output,
Open Drain
Control output to disable the active rectifier bridge.
This pin is referenced to VPN
RTN
12
EP
13
14
Power
Return connection of the PGO, NCM, NCL and LCF outputs.
Connect to the DC/DC controller power return.
Power
Exposed pad (thermal contact). Drain of the internal pass transistor.
Connect to the DC/DC controller power return plane.
LCF
Output,
Open Drain
Long Classification Finger Indicator. This pin is referenced to RTN.
Connect with a pull-up resistor to the logic supply
PGO
Output,
Open Drain
Power Good Indicator. This pin is left floating when the power good signal is
active. Referenced to RTN. Must be used to enable/disable the main DC/DC
converter adjacent to NCP1096.
NCM
NCL
15
16
Output,
Class result MSB output. This pin is referenced to RTN.
Connect with a pull-up resistor to the logic supply
Open Drain
Output,
Open Drain
Class result LSB output. This pin is referenced to RTN.
Connect with a pull-up resistor to the logic supply
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2
NCP1096
VPP
1
DET
7
15
16
NCM
NCL
5
Assigned
Class
COSC
Oscillator
Detection
Indicator
2
CLA
CLB
ACS
13
11
14
3
6
LCF
Classification
Long Class
Finger
VPORT
monitor
GBR
PGO
IEEE Interface
Shutdown
(AUX supply prio)
Active Bridge
Control
4
AUX
Switch Control & Current
Limit
Power Good
indicator
NCP1096
EP
RTN RTN
8
9
10
12
VPN
TST1 TST2
Figure 2. NCP1096 Block Diagram
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3
NCP1096
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−40
−55
−0.3
Max
+150
+150
Unit
°C
°C
V
Conditions
T
J
Junction temperature
Storage temperature
Input Power Supply
T
S
VPP
72
(Note 1)
Voltage with respect to VPN
RTN
Pass switch drain connection, application
ground
−0.3
72
(Note 1)
V
Voltage with respect to VPN,
Pass switch in the off state
DET
PGO
Voltage on pin DET
−0.3
−0.3
3.6
72
V
V
Power Good output
Voltage with respect to RTN
NCM
Class result MSB output
Class result LSB output
Long Class Finger output
Voltage on AUTOCLASS pin
Voltage on CLASSA or CLASSB pins
Active bridge control output
Voltage on pin COSC
NCL
LCF
ACS
−0.3
72
V
Voltage with respect to VPN
CLA, CLB
GBR
COSC
AUX
Auxiliary supply detection input
Human Body Model
ESD−HBM
ESD−CDM
2
kV
V
Per EIA−JESD22−A114 standard
Per ESD−STM5.3.1 standard
Charged Device Model
500
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. NCP1096 tolerates transient overvoltages from the capacitor and/or TVS subjected to a surge according to IEC 61000−4−5.
For extremely high cable discharge and surge protection, contact ON Semiconductor.
THERMAL CHARACTERISTICS (Note 2)
Symbol
Characteristic
Thermal Resistance, Junction-to-Air
Typical Value
Unit
q
37.6
°C/W
JA
2. q is obtained with 1S2P test board (1 signal – 2 plane) and natural convection. Refer to JEDEC JESD51 for details.
JA
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
−40
0
Max
+125
57
Unit
°C
T
J
Junction Temperature
Input Power Supply (V
V
= V – V )
PN
V
PORT
PORT
PP
(Note 3)
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. Refer to ABSOLUTE MAXIMUM RATINGS for Safe Operating Area.
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4
NCP1096
ELECTRICAL CHARACTERISTICS
(All parameters are guaranteed for the recommended operating conditions unless otherwise noted)
Symbol
Parameter
Min
Typ
Max
Unit
Condition
DETECTION CHARACTERISTICS
Rdetect
Equivalent detection resistance
Detection offset voltage (IC part)
23.7
0
26.3
0.2
kW
R
= 26.1 kW 1%;
PORT
DET
1 V ≤ V
≤ 10.1 V
VoffsetIC
V
CLASISFICATION CHARACTERISTICS
Vcl_th
Class/Mark current switchover threshold
10.1
20.5
12.5
24.5
V
V
V
V
V
rising or falling
rising or falling
= 12.5 V
PORT
PORT
PORT
(Note 4)
Vcldis
Classification current disable threshold
(Note 4)
Iclsigq
Vcsr
Quiescent current during classification
207
8.5
327
484
9.7
mA
CLASS driver voltage (Note 4) during
class event
9.15
V
12.5 V ≤ V
≤ 20.5 V
PORT
Iclsig0
Iclsig1
Iclsig2
Iclsig3
Iclsig4
Imark
tfce
RclassA,B = 4.5 kW 1%
RclassA,B = 909 W 1%
1
9
4
mA
mA
mA
mA
mA
mA
ms
12.5 V ≤ V
12.5 V ≤ V
12.5 V ≤ V
12.5 V ≤ V
12.5 V ≤ V
≤ 20.5 V
≤ 20.5 V
≤ 20.5 V
≤ 20.5 V
≤ 20.5 V
PORT
PORT
PORT
PORT
PORT
12
20
30
44
4
RclassA,B = 511 W 1%
17
26
36
1
RclassA,B = 332 W 1%
RclassA,B = 232 W 1%
IPP during mark event range
Short/Long first class event threshold
2.3
4.9 V ≤ V
≤ 10.1 V
PORT
75
88
R
C
= 26.1 kW 1%;
= 1 nF 2%
DET
OSC
tacspd
Change to class signature ‘0’ current
timing
75.5
87.5
ms
Autoclass enabled
RC OSCILLATOR CHARACTERISTICS
fosc
duty
Frequency of the oscillator
Oscillator duty cycle
26.8
50
kHz
%
R
= 26.1 kW; C
= 1 nF
DET
OSC
PASS SWITCH CURRENT CONTROL STATE CHARACTERISTICS
Iinr
Inrush current
50
110
0.8
195
0.9
mA
V
Vdrain_pg
RTN PowerGood threshold voltage
(Note 4)
0.7
RTN–VPN falling
PGATE−VPN rising
Isink = 2 mA. Referenced to RTN
Vgate_pg
Vpgo_low
PGATE PowerGood threshold voltage
(Note 4)
6.9
8.5
10.0
0.50
V
V
PGO output low voltage
−
0.15
PASS SWITCH ON STATE CHARACTERISTICS
Ron
Idd_on
Ioc
On resistance
70
407
6.4
1.2
160
601
12.5
1.3
mW
mA
A
Operating current
257
3.1
1.1
V
= 57 V
PORT
Over current detection level
Voc
RTN overcurrent detection voltage
(Note 4)
V
RTN–VPN rising
UNDER-VOLTAGE LOCK-OUT CHARACTERISTICS
UVLO_H
UVLO_L
VPP UVLO threshold voltage (Note 4)
VPP UVLO threshold voltage (Note 4)
UVLO threshold hysteresis
33.0
30.0
2.4
35.1
32.3
2.8
37.5
34.5
3.3
V
V
V
V
V
rising
falling
PORT
PORT
UVLO_hyst
4. Voltage referenced to VPN.
5. E.g. after overcurrent timeout
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5
NCP1096
ELECTRICAL CHARACTERISTICS (continued)
(All parameters are guaranteed for the recommended operating conditions unless otherwise noted)
Symbol
Parameter
Min
Typ
Max
Unit
Condition
RESET CHARACTERISTICS
Vrst
VPP reset threshold voltage (Note 4)
2.81
3.85
4.9
V
V
PORT
falling
AUXILIARY SUPPLY DETECTION CHARACTERISTICS
AUX_H
AUX_L
AUX input high level voltage (Note 4)
AUX input low level voltage (Note 4)
AUX threshold hysteresis
1.7
0.5
1.0
180
2.15
0.75
1.4
2.6
1.05
2.0
V
V
AUX_hyst
AUX_pd
V
AUX internal pull down
265
380
kW
VAUX = 0.5 V
CLASSIFICATION RESULT INDICATOR CHARACTERISTICS
Vlow
NCL, NCM or LCF output low voltage
−
0.15
0.15
0.50
0.50
V
V
Isink = 2 mA. Referenced to RTN
Isink = 2 mA
GBR CHARACTERISTICS
Vgbr_low
GBR output low voltage (Note 4)
−
PASS SWITCH OFF STATE CHARACTERISTICS
Idd_off_err
Idd_off_aux
Poweroff current, error state (Note 5)
Poweroff current, aux mode
−
230
315
−
mA
mA
V
= 57 V, RTN = VPP
PORT
198
463
VPP−RTN = 57 V; AUX−VPN = 3.3 V
THERMAL PROTECTION CHARACTERISTICS
TSD Thermal shutdown threshold
150
−
−
°C
Junction temperature
4. Voltage referenced to VPN.
5. E.g. after overcurrent timeout
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
NCP1096
SIMPLIFIED APPLICATION SCHEMATIC
DATA +
BS termination
RJ45
DA+
1
2
3
4
5
6
U2
IN2
DA−
DB+
DC+
DC−
DB−
DD+
DD−
G2
OUTP
OUTN
FDMQ8205A
CPD
G1
G3
Vpd,A
U1
4
1
To DC/DC
Controller
VPP
DET
AUX
G4
7
5
IN1
IN2
14
RDET
PGO
COSC
15
16
COSC
U3
NCM
NCL
LCF
D1
C1
2
3
6
CLA
CLB
ACS
G2
OUTP
OUTN
RCLASSA
RCLASSB
Vport
FDMQ8205A
To μC
G1
G3
Vpd,B
13
11
7
G4
GBR
IN1
8
EP
8
12
Figure 3. General Application Schematic
TYPICAL BILL OF MATERIALS
Reference
Value
Designator
(Nominal)
Description
Tolerance
Manufacturer
ON Semiconductor
ON Semiconductor
Part Number
NCP1096
U
PoE Interface
NCP1096
1
U , U
GreenBridget
FDMQ8205A
FDMQ8205A
2
3
Rectifier
D1
C1
TVS Protection
58 V
100 nF/100 V
1 nF
Littelfuse
Walsin
SMBJ58A
VPP decoupling capacitor
Oscillator capacitor
10%
2%
0805B104K101CT
COSC
CPD
Murata
GRM1885C1H102GA01D
EEEFK1K100XP
ERJ3EKF2612V
VPP bulk capacitor
10 mF/80 V
26.1 kW
232 W
20%
1%
Panasonic
Panasonic
Panasonic
Panasonic
RDET
Detection resistor
RCLASSA
RCLASSB
Classification resistor A
Classification resistor B
1%
ERJ8ENF2320V
332 W
1%
ERJ6ENF3320V
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7
NCP1096
APPLICATION INFORMATION
Classification
The NCP1096 is a Power over Ethernet Powered Device
(PD) interface controller with an internal n-channel
MOSFET load switch.
A PD is characterized based upon the maximum power
level it requires at its power interface during operation. The
IEEE 802.3bt standard supports up to 71.3 W PDs and
defines 8 power Classes: Class 1 up to Class 8. The PD must
conform to a Class with a power level that is at or above the
maximum power the PD requires. Table 1 lists the different
Classes and the corresponding power level they stand for.
Based on the Class the PD conforms to, two resistance
values are listed. The R
CLA and VPN. Likewise, the R
between CLB and VPN. Eventually, when implementing
a Class 1, 2, 3 or 4 PD, the CLA and CLB pins can be shorted
together to the same single resistor.
Powered Device Interface
The NCP1096 is located at the interface of the PD and will
interact with the Power Sourcing Equipment (PSE) over the
Ethernet cable. NCP1096 allows the device to be powered
by an IEEE 802.3af/at or −3bt compliant PSE. It provides
a detection signature, classification handshaking, inrush
current limitation and operational overcurrent protection.
A block diagram is shown in Figure 2. Each section will be
explained in more detail below.
value must be inserted between
classA
value must be inserted
classB
Detection
During the detection phase, the PSE will check if a valid
or a non-valid detection signature is present. This will enable
the PSE to differentiate between equipment supporting PoE
requesting power and equipment either not supporting PoE
or not requesting power. In order to be able to present a valid
detection signature to the PSE, a 26.1 kW resistor must be
inserted between the COSC and DET pins of NCP1096.
During the detection phase all blocks of the chip are in
power-down except for an internal reference, a comparator
and two switches.
When the voltage at the PD power interface is within the
detection range, the COSC pin is pulled to VPP and the DET
pin is pulled to VPN, resulting in the PD presenting a valid
detection signature. The offset voltage of the input rectifier
bridge should be between 0 and 1.7 V in the detection range
Table 1. CLASSIFICATION RESISTOR VALUE
R
R
CLASSB
CLASSA
(Note 7)
4.5 kW
909 W
511 W
332 W
232 W
232 W
232 W
232 W
232 W
(Note 7)
4.5 kW
909 W
511 W
332 W
232 W
4.5 kW
909 W
511 W
332 W
PD Class
PD Power
13 W
0 (Note 6)
1
2
3
4
5
6
7
8
3.84 W
6.49 W
13 W
25.5 W
40.0 W
51.0 W
62.0 W
71.3…90 W
(2.7 V ≤ V ≤ 10.1 V).
PD
6. 3bt compliant PDs should use Class 1, 2 or 3 instead of Class 0.
7. All resistors must be 1% accurate.
When the PSE has detected a valid detection signature and
continues towards powering on the PD, the COSC and DET
switches are turned off in order to reduce the current
consumption of the PD.
Once the PSE device has detected the PD device, the
classification process begins. The NCP1096 is fully capable
of responding and completing classification with all PSE
types described in the 802.3af/at and −3bt PoE Standard.
The Class requested by NCP1096 during classification is
determined by the resistors connected to the CLA and CLB
pins. Depending on the power the PSE is able to deliver to
the PD, the PSE will generate a different number of
class-mark events. This will determine the amount of power
the PD is allowed to use. Next to that, the NCP1096 is able
to distinguish between a 3bt compliant PSE and a 3af/at
compliant PSE. Therefor a 1 nF capacitor must be inserted
between COSC and VPN. The classification results will be
written to the status outputs NCL, NCM and LCF. The offset
voltage of the input rectifier bridge should be between 0 and
VPP
COSC
RDET
DET
1,2 V
2 V in the detection range (14.5 V ≤ V ≤ 20.5 V).
PD
VPN
During a class event, the power dissipation in the R
class
2
resistor can be significant (V /R
) and its package size
csr
class
Figure 4. Detection Circuit
must be chosen properly. When the port voltage rises above
the class drivers will be disabled in order to limit the
V
cldis
power dissipation.
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8
NCP1096
Inrush Current Limiting
This PGO output MUST be used to hold off the adjacent
main DC/DC converter as well any significant load present
between VPP and RTN. This is important in order not to
further increase the already significant stress in the
pass-switch during inrush. Figure 5 shows how to hold off
a significant load and a DC/DC converter which has either
an /EN, EN or UVLO input.
When the PSE has successfully assigned the PD to
a specific Class in correspondence with the power the PSE
is able to deliver, the PSE will increase the voltage at its
power interface up to its internal power supply voltage.
NCP1096 will enter the inrush current control state once its
port voltage rises above the UVLO_H threshold.
In this state, NCP1096 will control the charging of its port
System Start-up
capacitance C
located between VPP and RTN by
PD
Once NCP1096 exits the inrush current control state, it
will make the PGO output floating, indicating the main
DC/DC converter − and eventually the system − is allowed
to start. This also indicates NCP1096 will no longer actively
limit the current and/or the power, as the pass switch is on
and will be left turned on.
PDs requesting Class 4 or higher need to take into account
that they can be underpowered and need to implement some
basic functionality with Class 3 power level. Also, the
microcontroller will only be able to read the classification
result after system startup. Therefore the main DC/DC
converter and the system must be able to start up with
Class 3 power (or lower for Class 1 and Class 2 PDs) and
turn on higher power loads only if this is allowed by the PSE
assigned Class.
operating the pass switch transistor in the active region. The
current through the pass switch is regulated by monitoring
the voltage over an internal sense resistor R
= 25 mW.
SNS
NCP1096 will limit the inrush current well below the PSE
inrush threshold while charging its port capacitance. The
nominal level of the inrush current is 110 mA typ. The
NCP1096 will exit the inrush current control state when the
voltage between RTN and VPN is smaller than 0.8 V and the
gate voltage rises above 8.5 V. At this stage, the port
capacitance can be considered to be fully charged, and
NCP1096 will enter the normal operation mode with the
pass switch completely turned on.
In case of an output short error condition, the inrush
current control state will be aborted to protect the
pass-switch. In order not to be considered as a short, the port
capacitance should be chosen not to have too high a value
(above 1 mF).
Even when being assigned to Class 4 or higher by the PSE,
the PD is only allowed to use this increased power level
80 ms after the UVLO_H threshold was crossed. The
nominal delay introduced to charge the port capacitance can
be calculated from the formula below.
Class 1 and 2 PDs should operate according to their power
Class 50 ms after the UVLO_H threshold was crossed.
Therefore it is recommended to limit the port capacitance to
59 mF for Class1 PDs and to 99 mF for Class2 PDs.
Cpd (mF) @ Vpd (V)
(eq. 1)
tcharge (ms) +
103
PGO Indicator
While in the inrush current control state, the PGO output
will be held low by NCP1096.
As an example, it typically takes 80 ms to charge a 165 mF
capacitor to 50 V. Depending mainly on the chosen port
capacitor value, this 80 ms delay may or may not yet have
passed when the NCP1096 exits the inrush current control
state.
VPP
VPP
VPP
VPP
Load
Load
RT1
RT1
EN
to DC/DC
14
14
Q1
PGO
Q1
PGO
D1
D1
RTN
RTN
NCP1096
NCP1096
EN
to DC/DC
VPP
VPP
Load
RT1
14
PGO
Q1
D1
RT2
RTN
NCP1096
UVLO
to DC/DC
CT
RB
Figure 5. PGO Interfacing
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9
NCP1096
NCM and NCL Indicators
LCF Indicator
The state of the NCM and NCL outputs provides
information about the power level that the PSE has assigned
to the PD during classification. These status outputs are
actually only relevant for PDs requesting Class 4 or higher
as those need to take into account that they can be
underpowered. See Table 2 to determine the assigned power
based on the NCM and NCL outputs and the requested Class.
An underpowered PD can eventually be assigned to Class 3,
4 or 6.
The state of the LCF output provides information
(retrieved during classification) about the type of PSE the
PD is connected to.
• LCF is left floating:
The PSE is categorized according to 802.3af/at
(PSE Type 1 or Type 2).
• LCF is low:
The PSE is categorized according to 802.3bt
(PSE Type 3 or Type 4).
Maintain Power Signature
Table 2. CLASSIFICATION RESULT OVERVIEW
There is a minimum amount of current a PD needs to draw
in order to allow the PSE to determine if the PD is still
connected. This is called the Maintain Power Signature
(MPS). If the PD no longer maintains this, the PSE may
disconnect the power.
Requested
Class
Assigned
Class
Assigned
Power
NCM
open
open
low
NCL
open
low
4
5
6
7
3
4
13 W
25.5 W
X
IPORT
open
open
low
open
low
3
4
5
3
4
6
3
4
6
7
3
4
6
8
13 W
25.5 W
40 W
7 ms
Short MPS
16 mA
10 mA
MPS
X
open
open
low
open
low
13 W
75 ms
250 ms
25.5 W
51 W
Figure 6. MPS
X
open
open
low
open
low
13 W
The current needs to be at or above a certain current
threshold (I ) during at least a certain amount of
25.5 W
51 W
Port_MPS,Min
open
low
time (T
). If this has been the case, the current
MPS_PD,Min
may fall below the threshold for at most a certain dropout
period (T ).
low
62 W
MPDO_PD,Max
8
open
open
low
open
low
13 W
Whether or not the lower power short MPS may be used
depends upon the state of the LCF output.
25.5 W
51 W
open
low
Table 3. MPS TIMING
low
71.3…90 W
LCF
open
low
T
T
MPDO_PD,Max
MPS_PD,Min
75 ms
250 ms
PDs assigned to Class 8 may consume greater than 71.3 W
as long as they guarantee not to exceed the 90 W power limit
at the PSE power interface. Operation beyond 71.3 W is,
however, only possible if additional information is available
to the PD regarding the actual link section DC resistance
between the PSE and the PD.
The application should always operate at or below the
assigned power limit. Failing to do so will result in the PSE
disconnecting the PD.
7 ms
310 ms
For PDs requesting Class 4 or less the MPS current
threshold will always be 10 mA.
For PDs requesting Class 5 or above the MPS current
threshold will depend upon the assigned Class (which in fact
can be determined by the state of the NCM output).
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10
NCP1096
Peak Power and Transients
Table 4. MPS CURRENT
Although the PoE standard allows the PD to draw slightly
higher peak power during a short time, making use of this is
not recommended. It is best to keep this additional margin
only to be able to withstand voltage transients on the PSE
side. The required recovery time for transients also limits the
amount of the port capacitance that can be used.
Assigned Class
I
Port_MPS,Min
≤ 4
≥ 5
10 mA
16 mA
An important remark is that the PD load current will be
low-pass filtered by its port capacitance and the actual
resistance of the cable. This should be taken into account
when generating current pulses for MPS.
The PD needs to maintain the MPS as soon as its port
voltage rises above the UVLO_H threshold. Depending on
the amount of port capacitance and the type of PSE it is
connected to, the time duration of the inrush current control
Under Voltage Lockout
If the port voltage falls below the UVLO_L threshold and
remains low for a sufficient amount of time, NCP1096 will
enter the poweroff state and turn off the pass switch.
Once the port voltage falls below the reset threshold V ,
rst
the NCP1096 will re−enter the idle state and can again be
detected as a PD requesting power.
state might or might not be enough (T
) to count
MPS_PD,Min
Operational Current Protection
as the first valid current pulse. In combination with 3bt PSEs
this will usually not be a problem as it typically takes 7 ms
to charge just a 14.4 mF cap to 50 V. In combination with
3af/at PSEs the situation is different as it typically takes
75 ms to charge a 176 mF cap to 44 V.
In the normal operation mode, NCP1096 will monitor the
current through the pass switch and provide protection
against soft and hard shorts.
Soft shorts are detected if the current is above the short
circuit threshold I (6.4 A typ) and a time out delay of
OC
960 ms is passed. After this time-out delay the pass switch is
disabled.
A hard short is detected if the voltage across the
Autoclass
802.3bt foresees an optional extension of classification
known as Autoclass. This allows a 3bt certified PSE to better
allocate its power among different PDs.
When the ACS pin is connected to VPN, Autoclass is
disabled.
When the ACS pin is left floating, Autoclass is enabled
and NCP1096 will request an Autoclass measurement to
a 3bt type of PSE during classification. If Autoclass is
enabled and the LCF output is low, the system must go to the
maximum power state according to its assigned Class no
later than 1.35 s after power has been applied, and keep the
maximum load active until at least 3.65 s after power has
been applied. During this period, the PSE will measure the
maximum power draw of the PD and allocate this amount of
power to the PD.
pass-switch and sense resistor is above V (1.2 V typ). The
OC
pass gate is switched off within 18 ms in this case.
Once an overcurrent condition is detected during the
normal operation mode, the NCP1096 will transition to the
offline state and remain there until the port voltage falls
below the reset threshold V .
rst
Thermal Shutdown
The NCP1096 includes a thermal shutdown which
protects the device in the case that the junction temperature
is too high. An on-chip sensor monitors the temperature.
Once the thermal shutdown threshold (TSD_H) is exceeded,
all functions are disabled and the device goes into the offline
state.
The device will remain in offline until the junction
temperature drops below TSD_L and the port voltage falls
below the reset threshold V .
rst
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11
NCP1096
Figure 7. Complete Start-up Diagram of a Class 8 PD with Autoclass
www.onsemi.com
12
NCP1096
PoE System Overview
The overall PoE standard distinguishes between four
Types of PSEs and four Types of PDs.
An important parameter is the cable DC resistance
(determined by cable type and length).
In general Cat 5 cabling is required when using a Type 3
or Type 4 PD or PSE in the system or when both PSE and PD
are of Type 2.
• Type 1 PSEs and PDs behave according to 802.3af/at
• Type 2 PSEs and PDs behave according to 802.3at
• Type 3 and 4 PSEs and PDs behave according to 802.3bt
Operation over 4-pair is reserved for Type 3 and 4 PSEs.
Table 5 gives an overview of the system parameters that
are allowed and required for operation at a certain power
level (assigned Class).
Table 5. SYSTEM PARAMETERS OVERVIEW
Minimum
Assigned
Number of
Powered Pairs
Requested
Class
Cabling
Type
Class
PSE Type
PD Type
Standard
1
2
3
1
2
Cat 3 (Note 8)
Cat 3
2p
1
1
802.3af/at
3, 4
1, 2
3
Cat 3
2p/4p
2p
3
1
3
802.3bt
802.3af/at
802.3bt
Cat 3
2
Cat 5 (Note 9)
Cat 5
2p/4p
4
1
Cat 3
2p
2p
1
1
2
1
2
3
4
2
3
4
3
3
4
4
4
0, 3
0, 3
4
802.3af
802.3at
1
Cat 3 (Note 10)
2
Cat 3
Cat 5
Cat 5
0, 3
4
802.3af/at
802.3at
3, 4
2p/4p
3, 4/5/6
7/8
4
802.3bt
4
2
2p
802.3at
802.3bt
3, 4
2p/4p
4/5/6
7/8
5
5
6
3, 4
3, 4
Cat 5
Cat 5
4p
4p
802.3bt
802.3bt
6
7, 8
7
7
8
4
4
Cat 5
Cat 5
4p
4p
802.3bt
802.3bt
8
8. Critical for: 44 V/4 W source connected to 3.84 W load over 20 W.
9. Critical for: 50 V/6.7 W source connected to 6.49 W load over 12.5 W.
10.Critical for: 44 V/15.4 W source connected to 13 W load over 20 W.
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13
NCP1096
Auxiliary Supply
Dual-signature PD
To support applications connected to non-PoE enabled
networks and to minimize the bill of materials, the NCP1096
supports drawing power from an alternate or local power
source and allows a simplified design with auxiliary supply
priority.
Up to now the description has been for a PD compliant to
IEEE 802.3af/at or a single-signature PD compliant to IEEE
802.3bt. The IEEE 802.3bt standard also introduces the
concept of a dual-signature PD. These have a separate input
bridge rectifier and PD controller for each alternative or
mode (A and B).
The maximum input average power is different for
a Class 5 dual-signature PD (35.6…45 W) compared to a
Class 5 single-signature PD. More general, a dual-signature
PD uses a different classB resistance value.
NCP1096 has a high voltage compliant AUX input pin. If
the AUX pin voltage rises above the AUX_H threshold and
remains high for a sufficient amount of time, the NCP1096
will turn off the pass switch and transition to the offline state
(indicated by NCM, NCL and LCF being left floating).
Disabling the pass switch based on the AUX input is useful
for PD applications where the auxiliary supply has to be
dominant over the PoE supply. When the auxiliary supply is
inserted into a PoE powered application, the pass switch
disconnection will move the current path from the PSE to the
rear auxiliary supply. Since the current delivered from the
PSE will go below the DC MPS level (as specified in the
IEEE 802.3af/at, −3bt standard) the PSE will disconnect the
PoE−PD. The auxiliary supply is connected between VPP
and RTN with a serial diode D1 between VPP and VAUX+,
as shown in Figure 8. It is recommended to use the circuit
with PNP transistor in combination with an auxiliary supply.
Table 6. CLASSIFICATION RESISTOR VALUE
R
R
CLASSB
CLASSA
(Note 11)
909 W
511 W
(Note 11)
4.5 kW
4.5 kW
4.5 kW
4.5 kW
332 W
PD Class
PD Power
3.84 W
1
2
3
4
5
6.49 W
332 W
232 W
232 W
13 W
25.5 W
35.6…45 W
11. All resistors must be 1% accurate.
VPP
VPP
The NCM, NCL and LCF outputs behave in a similar way.
D1
Q1
Table 7. CLASSIFICATION RESULT OVERVIEW
VAUX +
Requested
Class
Assigned
Class
Assigned
Power
Rt
NCM
open
open
low
NCL
open
low
X
NCP1096
4
4
3
4
13 W
AUX
8
Rbb
25.5 W
Cb
Rb
VAUX −
12, EP
5
open
open
low
open
low
X
3
4
5
13 W
25.5 W
VPN
RTN
35.6…45 W
Figure 8. AUX Pin Interfacing
It is necessary that the port voltage falls below the reset
The MPS timing is the same for dual-signature PDs and
can be retrieved from Table 3 based on the LCF output.
The MPS current threshold however is always 10 mA for
dual-signature PDs (on each pairset), even if assigned to
Class 5.
threshold V for the NCP1096 to re−enter the idle state in
rst
which it can again be detected as a PD requesting power.
If a too low aux (10.1 V…24.5 V) is inserted before the
UVLO threshold was crossed by the PSE, the class driver
could become unintentionally activated. The resulting large
additional current draw can be easily prevented if the
auxiliary supply is detected at a Vport voltage below 10.1 V.
This is accomplished by taking Rt = 33 kW and Rb = 15 kW.
Dual-signature PDs never have Autoclass implemented,
so ACS should be connected to VPN.
Reference
All information regarding Power over Ethernet over 4
Pairs can be found in document IEEE 802.3btt−2018
which is an amendment to IEEE Std 802.3t−2018.
GBR Output
If the AUX input pin of NCP1096 is pulled high, it will
immediately drive the GBR pin low. This allows the
GreenBridge input rectifiers to be disabled.
The GBR pin must be used to disable the GreenBridge
when a high voltage (> 30 V) auxiliary supply is used in
order to be sure the PD does not source power.
www.onsemi.com
14
NCP1096
SIMPLIFIED APPLICATION SCHEMATIC WITH AUXILIARY SUPPLY
VAUX(+)
Auxiliary
Supply
VAUX(−)
DATA +
BS termination
Rt
Q1
RJ45
DA+
Cb
Rb
1
2
3
4
5
6
7
8
Rbb
D2
U2
IN2
DA−
DB+
DC+
DC−
DB−
DD+
DD−
G2
OUTP
OUTN
FDMQ8205A
CPD
G1
G3
Vpd,A
U1
4
AUX
1
To DC/DC
Controller
VPP
DET
G4
RDET
7
5
IN1
IN2
14
PGO
COSC
15
16
COSC
RCLASSA
RCLASSB
NCM
NCL
LCF
U3
D1
C1
2
3
6
CLA
CLB
ACS
G2
OUTP
OUTN
Vport
To μC
FDMQ8205A
G1
G3
Vpd,B
13
11
G4
GBR
IN1
EP
D3
8
12
Figure 9. General Application Schematic with Auxiliary Supply
TYPICAL BILL OF MATERIALS
Reference
designator
Description
Value
(nominal)
Tolerance
Manufacturer
Part Number
U
PoE Interface
GreenBridge™ Rectifier
TVS Protection
NCP1096
FDMQ8205A
58 V
ON Semiconductor
ON Semiconductor
Littelfuse
NCP1096
FDMQ8205A
SMBJ58A
1
U , U
2
3
D1
C1
VPP decoupling
capacitor
100 nF / 100 V
10%
Walsin
0805B104K101CT
COSC
CPD
RDET
RCLASSA
RCLASSB
D2
Oscillator capacitor
VPP bulk capacitor
Detection resistor
Classification resistor A
Classification resistor B
Schottky Rectifier
Dual Diode
1 nF
10 μF / 80 V
26.1 kΩ
232 Ω
2%
20%
1%
Murata
Panasonic
GRM1885C1H102GA01D
EEEFK1K100XP
ERJ3EKF2612V
ERJ8ENF2320V
ERJ6ENF3320V
NRVTS860EMFS
BAV70LT1G
Panasonic
1%
Panasonic
332 Ω
1%
Panasonic
8 A / 60 V
100 V
ON Semiconductor
ON Semiconductor
Yageo
D3
Cb
AUX filter capacitor
AUX top resistor
47 pF
5%
1%
1%
1%
CC0603JRNPO8BN470
ERJ3EKF3302V
ERJ3EKF1502V
ERJ3EKF6202V
BC856BLT1G
Rt
33 kΩ
Panasonic
Rb
AUX bottom resistor
Base resistor
15 kΩ
Panasonic
Rbb
62 kΩ
Panasonic
Q1
PNP Transistor
80 V
ON Semiconductor
GreenBridge is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP16, 4.4x5 EXPOSED PAD
CASE 948BV
ISSUE O
DATE 22 JUN 2017
TOP VIEW
END VIEW
BOTTOM VIEW
SIDE VIEW
MIN
SYMBOL
NOM
MAX
A
A1
A2
b
c
D
1.10
0.15
0.95
0.30
0.20
5.10
6.50
4.50
0.05
0.85
0.19
0.13
4.90
6.30
4.30
E
E1
e
L
0.65 BSC
1.00 REF
L1
N
P
R
S
0.45
0.90
6.50
4.60
0.37
0.75
1.00
6.70
4.80
0.47
LAND PATTERN
0º
8º
θ
X
Y
Notes:
3.33 REF
2.76 REF
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153 variations ABT.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON65408G
TSSOP16, 4.4X5 EXPOSED PAD
PAGE 1 OF 1
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