NCP11184A100PG [ONSEMI]
mWSaver Integrated Power Switcher with 800 V SJ MOSFET for Offline SMPS;
| 型号： | NCP11184A100PG |
| 厂家： | 
ONSEMI |
| 描述： | mWSaver Integrated Power Switcher with 800 V SJ MOSFET for Offline SMPS |
| 文件： | 总25页 (文件大小：1275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
mWSaver) Integrated Power
Switcher with 800 V SJ
MOSFET for Offline SMPS
Product Preview
NCP11184, NCP11185,
NCP11187
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NCP1118x integrates a peak current mode PWM controller
employing mWSaver technology and a highly robust 800 V SJ
MOSFET providing especially enhanced performance in flyback
converters. The mWSaver technology reduces switching frequency
and operating current of the controller at light−load condition, which
helps avoid acoustic−noise problems and even meet international
®
power conservation standards, such as Energy Star .
PDIP−7
(PDIP−8 LESS PIN 6)
PDIP−7 GULLWING
(PDIP−7 GW)
Additionally, NCP1118x includes a high−voltage startup circuit,
frequency−hopping function, slope compensation, constant output
power limit, and highly reliable and various protections, which allows
easy design, less BOM counts, smaller PCB size and designing
cost−effective off−line power supply. The protections feature
a protection of a feedback pin open−loop, current−sense resistor short,
brown−out and line over−voltage using an line voltage sensing pin,
which operate with auto−recovery operation.
CASE 626A
CASE 707AA
MARKING DIAGRAMS
P1118XAFL
AWL
ONYYWWG
P1118XAFL
AWL
ON
YYWWG
Features
• Integrated 800 V Super Junction MOSFET
• Built−in High Voltage Start−up, Soft−Start, and Slope
Compensation
PDIP−7
PDIP−7 GULLWING
• mWSaver Technology Provides Industry’s Best−in−Class Standby
Power
X
A
= MOSFET Option
= Trimming Version
F
L
A
WL
YY
WW
G
= Frequency Version
= Lead Forming Version
= Plant Code
= Wafer Lot
= Year of Production
= Work Week
• Switching Frequency Option: 65/100/130 kHz
• Proprietary Asynchronous Frequency Hopping Technique for Low
EMI
• Programmable Constant Output Power Limit for Entire Input
Voltage Range
• Precise Brown−out Protection and Line Over−voltage Protection
(LOVP) with Hysteresis
= Pb−Free Package
• Current Sense Short Protection (CSSP) and Abnormal
Over−Current Protection (AOCP)
• Thermal Shutdown (TSD) with Hysteresis
ORDERING INFORMATION
See detailed ordering and shipping information on page 22 of
this data sheet.
• All Protections Operated by Auto−recovery: VCC Under−voltage
Lockout (UVLO), Feedback Open−Loop Protection (OLP),
VCC Over−Voltage Protection (OVP)
NOTE: NCP11184, NCP11185, 100 kHz, 130 kHz
frequency option and Gullwing Package
are not yet released. At the launching
moment of those products, related
parameters could be revised.
• These Devices are Pb−Free, Halogen Free/BFR Free and are
RoHS Compliant
Typical Applications
• Industrial Auxiliary Power Supplies, E−metering SMPS
• Power Supplies for White Good Applications and Consumer
Electronics
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
July, 2020 − Rev. P3
NCP11184/D
NCP11184, NCP11185, NCP11187
PRODUCTS INFORMATION & INDICATIVE MAXIMUM OUTPUT POWER
Output Power Table (W) (Note 2)
Open Frame
Switching
Frequency
R
(W)
DS(ON)
85 ~ 265 V
230 V
AC
(Note 1)
2.25
1.3
Part Number
NCP11184A065PG
NCP11185A065PG
NCP11187A065PG
NCP11184A100PG
NCP11187A100PG
NCP11184A130PG
NCP11185A130PG
NCP11184A065LPG
NCP11185A065LPG
NCP11187A065LPG
NCP11184A100LPG
Package
AC
PDIP7
65 kHz
35
40
50
33
45
30
37
35
40
50
33
45
55
65
40
60
36
52
45
55
65
40
0.87
2.25
0.87
2.25
1.3
100 kHz
130 kHz
65 kHz
LSOP−7
2.25
1.3
0.87
2.25
100 kHz
1. Typical at T = 25°C.
J
2. Estimated maximum output power rating at T = 50°C not exceeding T of 110°C assuming DRAIN pin surrounding with a thermal relief pad
A
C
2
150 mm in single layer PCB with 1oz. The actual output power could be varied depending on particular designs.
PIN CONFIGURATION
CS
DRAIN
DRAIN
VIN
GND
FB
VCC
(Top View)
PDIP−7 & PDIP−7 GW
Figure 1. Pin Configuration of PDIP & PDIP-7 GW
PIN FUNCTION DESCRIPTION
PIN #
Name
Description
1
CS
Sensing the drain current using a resistor. The sensed voltage is used for peak current mode control and
cycle−by−cycle current limit. This pin also connects to a source of the integrated MOSFET
2
VIN
Detecting line input voltage. The sensed line input voltage is used for brown−out protection with hysteresis.
Besides, constant output power limit is controlled with the sensed voltage. It is recommended to add
a low−pass filter with this pin in parallel to reject high frequency noise and line ripple on the bulk capacitor.
Pulling this pin up triggers auto−restart protection
3
4
GND
FB
Ground of the controller
Control compensation. The PWM duty cycle is determined in response of comparing the signal on this pin
and the sensed drain signal on the CS pin. Typically, an opto−coupler and capacitor are connected to this
pin
5
VCC
Power supply for the internal circuit operations
6, 7
DRAIN
This pin connects to an internal high voltage startup circuit and a drain of the integrated MOSFET. Typically,
this pin is directly connected to one of terminals of the transformer. At initial startup or restart mode,
operating voltage is powered through this pin
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2
NCP11184, NCP11185, NCP11187
TYPICAL APPLICATION
+
L
+
EMI
Vout
FILTER
N
2
VIN
7
6
D
D
5
VCC
NCP1118x
FB
4
GND CS 1
3
+
Figure 2. Typical Application (Detecting DC Voltage on Bulk−capacitor)
+
L
+
EMI
FILTER
Vout
N
2
VIN
7
6
D
D
5
VCC
NCP1118x
FB
4
GND CS 1
3
+
Figure 3. Typical Application (Detecting AC Input Voltage)
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3
NCP11184, NCP11185, NCP11187
BLOCK DIAGRAM
DRAIN
6
7
Reset
Latch
VCC−OVP
OLP
VIN−OVP
TSD
AOCP
CSSP
ISTA RT
DRAIN
Protection
DRAIN
800-V
MOSFET
Gate
Driver
VCC
5
Brown-out
Internal Bias
VPWM
VC C−ON
/VC C−OFF
/VC C−A R
Burst
S
R
Q
VC S-CSSP
CSSP
NC COVP
Counter
VCC−OVP
VR ESET
VC C−OVP
AOCP
VC S−AOC P
Reset
Latch
Frequency
Hopping
Soft−start
OSC
VC C−LR
tLEB
CS
1
VR ESET
VC S−LIMIT
Thermal
Shutdown
TSD
Green
Mode
PWM
Comparator
Slope
Compensation
VFB−C L
VIN−ON
/ VIN−OFF
Max.
Duty
tD−VINOF F
Brown-out
Burst
ZFB
Constant Output
Power Limit
VIN
VC S−LIM IT
2
FB
4
AV
OLP
Timer
OLP
NVINOVP
Counter
VIN−OVP
VIN−OVP
VFB−OLP
Burst
OLP
Comparator
VFB −B UR H/B UR L
3
GND
Figure 4. Simplified Internal Circuit Block Diagram
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4
NCP11184, NCP11185, NCP11187
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
V
VCC Supply Voltage
FB Pin Input Voltage
CS Pin Input Voltage
VIN Pin Input Voltage
DRAIN Pin Input Voltage
V
DD
−0.3 to 30
−0.3 to 5.5
−0.3 to 5.5
−0.5 to 5.5
−0.3 to 800
V
V
FB
CS
VIN
V
V
V
V
V
DRAIN
V
Pulsed Drain Current (Note 3)
NCP11184
I
A
DM
4.2
5.4
6.8
NCP11185
NCP11187
Power Dissipation (PDIP−7, PDIP−7 GW)
Junction Temperature (Note 4)
P
1.25
−40 to +150
−40 to +150
260
W
°C
°C
°C
kV
D
T
J
Storage Temperature
T
STG
Lead Temperature, Wave Soldering or IT, 10 seconds
T
L
ESD Capability HBM, JESD22−A114
All Pins Except DRAIN Pin
DRAIN Pin
4.0
2.0
ESD Capability CDM, JESD22−C101
1.0
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Repetitive rating. Pulse width is limited by maximum junction temperature. T = 25°C.
A
4. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Junction−to−Ambience Thermal Impedance
PDIP−7, PDIP−7 GW (Note 5)
PDIP−7, PDIP−7 GW (Note 6)
R
°C/W
θ
JA
100
70
Junction−to−Case (Top−side) Thermal Impedance
PDIP−7, PDIP−7 GW (Note 6)
R
°C/W
θ
JC
11
5. JEDEC recommended environment in JESD51−2 and test board with minimum land pad in JESD51−3.
2
6. Estimated in soldering a copper thermal relief pad with 200 mm (0.31 sq. inch) and 2 oz. to the drain pin.
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5
NCP11184, NCP11185, NCP11187
ELECTRICAL CHARACTERISTICS (T = −40°C to +125°C unless otherwise noted)
J
Parameter
MOSFET SECTION
Test Conditions
Symbol
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V
J
= 0 V, V = 0 V, I
= 1 mA,
BV
DSS
800
−
−
V
GS
CS
DRAIN
T = 25°C
Off−state Drain−to−Source Leakage
Current
V
V
J
≥ V
DRAIN
T = 25°C
, V = 0 V,
I
DSS
mA
CC
CC−OVP CS
= 800 V
−
−
2.05
4.57
25
250
T =125°C
J
Static Drain−to−Source On
V
= 15 V, T = 25°C
R
R
W
W
CC
J
DS(ON)
DS(ON)
Resistance (Note 7)
NCP11184, I
NCP11185, I
NCP11187, I
= 0.3 A
−
−
−
1.87
1.05
0.70
2.25
1.3
DRAIN
DRAIN
DRAIN
= 0.4 A
= 0.6 A
0.87
Static Drain−to−Source On
Resistance (Note 7)
V
= 15 V, T = 125°C
VCC J
NCP11184, I
NCP11185, I
NCP11187, I
= 0.3 A
= 0.4 A
= 0.6 A
−
−
−
3.74
2.10
1.40
4.5
2.6
1.74
DRAIN
DRAIN
DRAIN
Effective Output Capacitance
V
= 0 to 400 V, V = 0 V
C
pF
pF
ns
ns
DS
GS
OSS(tr)
Time−related
NCP11184
NCP11185
NCP11187
−
−
−
65
97
−
−
−
151
Effective Output Capacitance
Energy−related
V
DS
= 0 to 400 V, V = 0 V
C
GS
OSS(er)
NCP11184
NCP11185
NCP11187
−
−
−
14
20
30
−
−
−
Fall Time (Note 8)
Rise Time (Note 8)
V
CC
= 15 V, V = 400 V, falling 90³10%
t
f
DS
NCP11184
NCP11185
NCP11187
−
−
−
22
24
20
−
−
−
V
CC
= 15 V, V = 400 V, rising 10³90%
t
r
DS
NCP11184
NCP11185
NCP11187
−
−
−
25
16
20
−
−
−
HV STARTUP SECTION
VCC Threshold Voltage Switching
V
1.0
2.1
3.0
V
CC−SSC
Startup Current from I
to
START1
I
START2
Startup Charging Current
Startup Charging Current
V
V
> 40 V, V = 0 V
I
I
0.2
2.7
25
0.5
4.5
−
0.8
6.3
−
mA
mA
V
DRAIN
CC
START1
> 40 V, V = V
− 0.5 V
DRAIN
CC
CC−ON
START2
Minimum Required Drain Voltage for
Startup (Note 9)
V
D−STR
VCC SUPPLY SECTION
VCC Turn−on Threshold Voltage
VCC Turn−off Threshold Voltage
V
14
6.8
−
16
7.8
30
18
8.8
−
V
V
CC−ON
V
CC−OFF
CC−INIT
CC−OP1
Operating Current before V
Operating Supply Current
V
V
= V − 0.5 V
CC−ON
I
mA
mA
CC−ON
CC
= 15 V, V = 4.5 V,
I
CC
FB
Open DRAIN pin,
65−kHz Version
NCP11184
−
−
−
1.6
2.0
2.6
−
−
−
NCP11185
NCP11187
100−kHz Version
NCP11184
NCP11187
−
−
1.9
3.3
−
−
130−kHz Version
NCP11184
NCP11185
−
−
2.2
3.0
−
−
Operating Supply Current without
Switching
V
CC
= 15 V, V = 0 V
I
−
500
−
mA
FB
CC−OP2
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NCP11184, NCP11185, NCP11187
ELECTRICAL CHARACTERISTICS (T = −40°C to +125°C unless otherwise noted) (continued)
J
Parameter
VCC SUPPLY SECTION
Soft−start Time
Test Conditions
Symbol
Min
Typ
Max
Unit
V
FB
= V
t
SS
ms
FB−CL
65/130 kHz Version
100 kHz Version
4.0
5.2
5.5
7.15
7.0
9.1
V
Threshold Voltage Switching
V
9
10.2
11.4
V
CC
CC−SOP
Operating Current after Protection
Mode
Operating Current after Protection
V
+ 0.2 V
I
60
100
7.4
140
8.4
mA
CC−AR
CC−OP3
Protection Reset V Threshold
V
6.4
V
CC
CC−AR
Voltage
OSCILLATOR SECTION
Switching Frequency
V
V
= 4.5 V (V
), T = 25°C
f
OSC
kHz
FB
FB−OLP
J
65 kHz Version
100 kHz Version
130 kHz Version
62
95
65
100
130
68
105
136
124
Frequency Variation vs. Temperature
Deviation (Note 9)
= 4.5 V
f
DT
−
−
7.5
%
FB
T = T = −40 to 125°C
A
J
Frequency Modulation Range
V
FB
= 4.5 V (V
)
f
M
kHz
FB−OLP
65 kHz Version
100 kHz Version
130 kHz Version
5.1
8.1
9
6
9.2
10.4
6.9
10.3
11.8
Hopping Period
T = 25°C
J
t
7
14.5
22
ms
HOP
PWM CONTROL SECTION
Feedback(FB) Voltage Attenuation
(Note 9)
V
V
= 2~2.2 V
= 4 V
A
1/4.5
1/4.0
1/3.5
−
FB
V
FB Impedance
Z
FB
10.4
4.75
70
15.65
5.1
20.9
5.4
90
kW
V
FB
FB Clamp Voltage
FB Pin Open
V
FB−CL
Maximum Duty Cycle
Current Limit Threshold Voltage
D
80
%
V
MAX
CS−LIMIT
V
IN
V
IN
= 1 V
= 3 V
V
0.77
0.64
0.83
0.70
0.89
0.76
Current Limit Delay Time
T = 25°C
t
−
330
305
450
355
ns
ns
ms
J
CLD
Leading Edge Blanking Time (Note 9) Steady State
t
255
LEB
Slope Compensation Generation
Delay Time (Note 9)
65 kHz Version
100 kHz Version
130 kHz Version
t
−
−
−
6
4
2.99
−
−
−
D−SE
Slope Compensation (Note 9)
Normalized to CS Signal
65 kHz Version
S
E
mV/ms
−
−
−
30
46
60
−
−
−
100 kHz Version
130 kHz Version
GREEN/BURST MODE SECTION
Green−mode Start Threshold Voltage T = 25°C
V
V
−
−
3.0
2.4
−
−
V
V
J
FB−SG
Green−mode End Threshold Voltage
Green−mode Start Frequency
T = 25°C
J
FB−EG
V
FB
= 3 V
f
kHz
OSC−SG
65 kHz Version
100 kHz Version
130 kHz Version
−
−
−
58.5
90
117
−
−
−
Green−mode End Frequency
V
FB
= 2.4 V
f
kHz
OSC−EG
65 kHz Version
100 kHz Version
130 kHz Version
−
−
−
25.6
28
29
−
−
−
Burst−mode Start Threshold Voltage
Burst−mode End Voltage
V
1.3
1.5
1.6
1.8
1.9
2.1
V
V
FB−BURL
V
FB−BURH
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NCP11184, NCP11185, NCP11187
ELECTRICAL CHARACTERISTICS (T = −40°C to +125°C unless otherwise noted) (continued)
J
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
GREEN/BURST MODE SECTION
Burst−mode Hysteresis Voltage
Frequency Before Burst−mode
FB Impedance in Burst−mode
FB Impedance Switching Time from
V
V
V
− V
V
−
0.2
23
−
V
FB−BURH
FB−BURL
BUR−HYS
= V
< V
f
20
55
3.6
26
85
8.8
kHz
kW
ms
FB
FB
FB−BURL
OSC−BUR
, V > V
CC
Z
70
FB−BURL
CC−ZFB
FB−BUR
T = 25°C
J
t
6.2
ZFB
Z
to Z
FB−BUR
FB
V
Threshold Voltage to Force Z
V
FB
< V
, V Decrease
CC
V
9
10
11
V
CC
FB
FB−BURL
CC−ZFB
Reset
PROTECTION SECTION
V
Over−Voltage Protection (OVP)
V
N
24.5
26
27.5
V
CC
CC−OVP
V
CC
OVP Debounce Counting
65 kHz Version
100/130 kHz Version
5
11
6
12
−
−
pulse
VCCOVP
Number
Brown−in Threshold Voltage
Brown−out Threshold Voltage
Brown−out Debounce Time
V
= V
during HV start−up
V
0.85
0.66
0.9
0.95
0.74
V
V
CC
CC−ON
IN−ON
V
0.70
IN−OFF
V
FB
= V
T = 25°C
J
t
ms
FB−CL,
D−VINOFF
65/130 kHz Version
100 kHz Version
45.0
58.5
62.5
81.2
70.0
91.0
V
Over−voltage Protection (OVP)
V
3.65
3.85
4.05
V
IN
IN−OVP
Threshold Voltage
V
V
OVP Release Hysteresis
V
−
0.2
−
V
IN
IN
IN−OVPHYS
OVP Debounce Counting Number 65 kHz Version
100/130 kHz Version
N
5
11
6
12
−
−
pulse
VINOVP
FB−OLP
D−OLP
FB Open−loop Protection (OLP)
Threshold Voltage
V
t
4.1
4.5
4.9
V
FB OLP Debounce Time
V
FB
= V
, T = 25°C
ms
FB−CL
J
65/130 kHz Version
100 kHz Version
42.0
58.5
53.5
74.5
65.0
91.0
Abnormal Over−current Protection
Default: Enable after t
V
1.15
75
−
1.25
110
3
1.35
145
−
V
SS
CS−AOCP
(AOCP) Threshold Voltage
Abnormal Over−current Blanking Time
(Note 9)
t
ns
ON−AOCP
AOCP Debounce Counting Number
Counting GATE Pulses
N
Pulses
mV
AOCP
Current Sensing Short Protection
(CSSP) Threshold Voltage
V
IN
V
IN
= 1 V
= 3 V
V
70
145
95
175
120
205
CS−CSSP
PWM On−time to Trigger CSSP
65 kHz Version
100kHz Version
130kHz Version
t
4.05
2.35
2.0
4.6
3.0
2.3
5.15
3.65
2.6
ms
ON−CSSP
CSSP Debounce Counting Number
Counting GATE Pulses
N
−
2
−
Pulses
CSSP
Thermal Shutdown (TSD) Junction
Temperature (Note 9)
T
SD
130
140
150
°C
TSD Release Hysteresis (Note 9)
T
−
50
−
°C
SD−HYS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. The parameter, although guaranteed, is fully tested in wafer test process.
8. Evaluated in a typical flyback converter with T = 25°C.
A
9. This parameter is not tested in production, but verified by design or characterization.
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NCP11184, NCP11185, NCP11187
TYPICAL CHARACTERISTICS
Figure 5. VCC−ON vs. TJ
Figure 6. VCC−OFF vs. TJ
Figure 7. ISTART2 vs. TJ
Figure 8. ICC−OP1 vs. TJ
Figure 9. tSS vs. TJ
Figure 10. VCC−OVP vs. TJ
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NCP11184, NCP11185, NCP11187
TYPICAL CHARACTERISTICS (Continued)
Figure 11. fS vs. TJ
Figure 12. DMAX vs. TJ
Figure 14. VFB−BURH/L vs. TJ
Figure 16. tD−VINOFF vs. TJ
Figure 13. VLIMIT vs. TJ
Figure 15. VIN−ON/OFF vs. TJ
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NCP11184, NCP11185, NCP11187
TYPICAL CHARACTERISTICS (Continued)
Figure 17. VIN−OVP vs. TJ
Figure 18. VFB−OLP vs. TJ
Figure 19. tD−OLP vs. TJ
Figure 20. VCS−AOCP vs. TJ
Figure 21. VCS−CSSP vs. TJ
Figure 22. tON−CSSP vs. TJ
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NCP11184, NCP11185, NCP11187
TYPICAL CHARACTERISTICS (Continued)
Figure 23. Normalized BVDSS vs. TJ
Figure 24. RDS(ON) vs. TJ
Figure 25. Output Capacitance vs. VDS
Figure 26. Energy Loss in COSS vs. VDS
Figure 27. Safe Operating Area, NCP11184
Figure 28. Safe Operating Area, NCP11185
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NCP11184, NCP11185, NCP11187
TYPICAL CHARACTERISTICS (Continued)
Figure 29. Safe Operating Area, NCP11187
Figure 30. Allowable Power Dissipation vs. TA
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13
NCP11184, NCP11185, NCP11187
FUNCTIONAL DESCRIPTION
Startup & Soft−Start
immediately and V
starts decreasing by the internal
CC
At startup, an internal high−voltage(HV) startup circuit
connecting the DRAIN pin supplies a constant startup
current to internal circuits while charging the rest of current
operating current I
. Then, after V decreases lower
DD−OP2
CC
than V , V is discharged by I
CC−SOP CC
. As soon as
DD−OP3
V
CC
decreases to V
, all of protections is reset and the
CC−AR
the external capacitor C
as shown in Figure 31. While
IC restart up, which secure a long enough restart time after
a protection.
VCC
V
CC
is lower than V , the startup charging current is
CC−SSC
as small as ISTART1 to avoid NCP1118x damage when V
CC
is shorted to the ground. Whereas, once V
exceeds
VC C
CC
VCC−ON
V , the startup charging current becomes I
CC−SSC
,
START2
which allows being fast startup.
After V reaches V , the HV startup circuit is
deactivated and NCP1118x begins soft−startup with
increasing step−wise drain currents of the MOSFET to
minimize an inrush current and reduce an output voltage
VCC−SOP
VCC−AR
CC
CC−ON
overshoot during internal soft−start time t . Meanwhile,
during this time, NCP1118x operates by the only supply
IOP
SS
ICC−OP1
current from C
until the auxiliary winding of main
ICC−OP2
ICC−OP3
VCC
transformer provides sufficient operating current. Selecting
sufficient C is required. Otherwise, V could be
VCC
CC
t
decreased to V
and V
under−voltage lockout
CC−OFF
CC
Protection Reset
protection is triggered.
Protection Trigger
Figure 32. VCC Behavior in Auto Restart Mode
DRAIN
VCC
5
6
7
Latch Operation
CVC C
Protections with latch mode are available in latch−version
products optionally. When any protections is triggered in the
HV Startup
Vref
product, the switching is stopped immediately and V
CC
VC C Good
decreases. Once V
startup circuit restarts to supply operating current. However,
no switching operation will be taken place until V
touches V
, the internal HV
VC C−ON
/ VC C−OFF
/ VC C−AR
CC
CC−AR
Internal
Bias
CC
decreases to V
and a protection is reset. In addition,
in this V range. In the end,
DD−OP4 CC
CC−LR
VCC
ISTART1
V
CC
is discharged by I
this latch−protection reset can happen only when an input
voltage is disconnected and the HV startup circuit cannot
supply an operating current any longer. Next reconnection
of an input voltage can make IC restart.
ISTART2
VCC−ON
VCC−OFF
VCC
VCC−SSC
VCC−ON
IDRAIN
tSS
VCC−SOP
VCC−AR
VCC−LR
IDRAIN
t
Figure 31. HV Startup Circuit and Soft Start
Auto Restart Operation
NCP1118x offers auto restart mode for the protections
like feedback open−loop protection (OLP), VCC
over−voltage protection (VCC OVP), and thermal
shutdown (TSD) by over−temperature. Once one of the
protections is triggered, the IC stops switching operation
Protection Reset
Protection Trigger
AC Line Disconnection
AC Line Reconnection
Figure 33. VCC Behavior in Latch Mode
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14
NCP11184, NCP11185, NCP11187
DRAIN
Protection
Burst
VO
7
6
VFB−CL
Green Mode
+ OSC
Burst
AV
ZFB
FB
Gate
Driver
4
Q
S
R
FOD817
CFB
CS
tLEB
1
3
VCS
Slope
Comp.
DMAX
VFB−BURH/BURL
TL431
R
CS
VC S−LIMIT
VCS
GND
Burst
SG
SG
Figure 34. PWM Control Block
Switching
Frequency
PWM Control Operation
NPC1118x employs peak−current mode pulse width
modulation (PWM) control method to regulate output
voltage. As shown in Figure 34, an opto−coupler and shunt
regulator are typically used for the feedback network, which
2×fM
fOSC
controls a feedback voltage V . A sensing resistor is
FB
connected to CS pin and used to detect a drain current when
the integrated MOSFET turns on.
tHOP
Meanwhile, V is attenuated by the internal amplifier
FB
with a gain of A , that becomes (A × (V −V )) where V
t
V
V
FB
F
F
is forward voltage drop of an series−connected diode at FB
Figure 35. Frequency Hoping
Slope Compensation
pin inside node. Simply comparing the attenuated voltage
from the feedback voltage V with a sensed drain current
FB
V
CS
makes it possible to control the switching duty cycle.
A
slope compensation is employed to prevent
sub−harmonic oscillator and improve stability. A sawtooth
signal is generated and added V after pulse width of PWM
When V
reaches the attenuated voltage, the PWM
CS
comparator generates turn−off signal to the MOSFET
immediately. In case, an output voltage V increase makes
CS
O
signal exceeds t
which is around 40% of duty cycle to
D−SE
a current of the photo−diode increase, which leads V to
FB
an switching frequency f
. The amount of signals is
OSC
decrease and duty cycle is reduced as well. Accordingly, an
output power transferred to the secondary side is limited.
In addition, whenever the integrated MOSFET turns on,
compared with the internal feedback signal, which
determines PWM on time.
a leading edge current occurs on the sense resistor R
,
CS
which could lead premature termination of the gate turn−on
signal. To avoid it, a leading−edge blanking time t is
PWM
LEB
employed. During the t
blocked so that turn−on signal to the gate can be maintained.
, PWM comparator output is
LEB
t D−SE
Slope comp.
Frequency Hopping
Asynchronous frequency−hopping function built−in the
oscillator generates consistent jittering in switching
frequency. This frequency jittering prevents switching
noises from being concentrated in its switching frequency
band and distributes them to alleviate quasi−peak noises.
VCS
×
AV
VFB
+
The frequency is varied with period of t
and amplitude
HOP
of double of f as can be seen in Figure 35.
VCS
M
Slope comp.
Figure 36. Slope Compensation
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15
NCP11184, NCP11185, NCP11187
Slope of the sawtooth signal and t
are 30 mV/ms &
After V is lower than V
, the switching frequency
D−SE
FB
FB−SG
is steeply decreased from the green−mode start frequency
6 ms for 65 kHz of f , 46 mV/ms & 3.9 ms for 100 kHz of
OSC
f
to the green−mode end frequency f
until
f
and 60 mV/ms & 3 ms for 130 kHz of f . The delay
OSC−SG
OSC−EG
OSC
OSC
V
FB
touches the green−mode end level V . When V
FB−EG FB
time t
is 6 ms for 65−kHz version, 3.9 ms for 100−kHz
D−SE
is lower than the burst−mode start level V , the
FB−BURL
version, and 3 ms for 130−kHz version, respectively.
PWM controller is halted and starts entering the burst−mode
operation. In this mode, the most of internal circuits are
disabled so that internal operating current consumption is
drastically decreased, thereby standby power figure can be
improved as well. Meanwhile, all of internal circuits is
Constant Over−power Limit
For constant output power limit at the entire input voltage
range, a peak current limit threshold level V
controlled by the voltage of VIN pin V . As can be seen in
is
LIMIT
IN
Figure 37, V
is decreased as V increases and
LIMIT
IN
enabled and the PWM switching is resumed as soon as V
FB
maximum output power is limited automatically.
VIN pin is typically connected to the rectified AC line
input voltage through the resistors divider.
is higher than the burst−mode end level V
.
FB−BURH
Feedback Impedance Switching in Burst−mode
To minimize power consumption in no−load condition
especially, a method to switch FB−pin impedance Z in
VLIMIT
FB
VIN−ON
VIN−OVP
burst−mode is implemented. Figure 39 illustrates Z
FB
variation depending on V . By increasing Z , amount of
FB
FB
0.86
0.83
current consumed by the feedback network including the
opto−coupler can be reduced. When touches
, Z is switched from 15 kW to Z
V
FB
FB−BUR
V
of
FB−BURL
FB
typical 70 kW immediately. Whereas, when V increases
FB
0.7
and gets higher than V , Z decreases stepwise and
FB−BURH FB
is back to normal Z of 15 kW.
FB
0.635
fOSC
ZFB (kW)
15
20
75
VIN
3
1
25
Figure 37. VIN vs. VLIMIT
Green−mode & Burst−mode Operation
60
65
To improve efficiency while reducing power dissipation,
the proprietary green−mode function reduces switching
frequency as load is decreased and forces PWM operation to
stop at light load condition. The switching frequency
75
70
fOSC−BUR
depends on V as illustrated in Figure 38.
FB
fs
VFB
VFB−BURL
VFB−BURH
fOSC
Figure 39. ZFB Switching
fOSC−SG
Meanwhile, when V decreases to V
while Z
FB
CC
CC−ZFB
switches to Z
, the Z of 70 kW is forced to back to
FB−BUR
FB
CC−UVLO
normal Z to prevent V
by touching V
.
FB
CC−OFF
VCC Over−Voltage Protection (VCC−OVP
To prevent damage from over−voltage to V pin, VCC
over−voltage protection (OVP) is included. Once V is
over the over−voltage protection voltage V
)
fOSC−EG
CC
fOSC−BUR
CC
, which
VFB
CC−OVP
VFB−BURL VFB−EG VFB−SG
VFB−BURH
VFB−OLP
lasts for fixed time duration corresponding to the V OVP
CC
debounce counting number N , the PWM will be
VCCOVP
disabled immediately. This protection can be reset only
when V is lower than V in the auto−restart mode.
Figure 38. PWM Frequency vs. VFB
CC
CC−AR
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16
NCP11184, NCP11185, NCP11187
FB Open Loop Protection (OLP)
When the output voltage drops below a regulation voltage
or FB pin is open circuit, FB Voltage V will settle
voltage. Meanwhile, V
is varied depending on VIN
CS−CSSP
level to avoid abnormal detection of CSSP at low input
voltage. N is different in either of startup or normal
FB
CSSP
V , because a shunt regulator such as NCP431 no
FB−OLP
operation as well.
longer draws the opto−coupler current down. This is
regarded as FB OL situation. If it lasts longer than t
,
D−OLP
CSSP trigger
VFB
CS short at this point
FB OLP is triggered and PWM operation is stopped
immediately. This protection can be reset when V is
CC
below than V
.
V
CS−CSSP@VVIN=3
CC−OFF
VC S
VCS−CSSP@VVIN=1
Abnormal Over−current Protection (AOCP)
tON−C SSP
The AOCP stops PWM switching to prevent any damage
of NCP1118x from excessive drain current caused by either
of the secondary−side rectifier diode or the transformer is
PWM
Figure 42. CSSP Waveform
shorted. It has blanking time t
and doubouncing
ON−AOCP
Brown−out/Line Over−voltage Protection (Line OVP)
Brown−out and Line−OVP are performed by detecting
line input voltage through VIN pin. VIN pin is typically
connected to a resistive divider. They can connect to either
of the ac rectifier or dc−link capacitor as can be seen in
Figure 2 and Figure 3.
counting number N
to prevent AOCP activation
AOCP
prematurely from a leading edge current at an instance of
turn−on of the main MOSFET in normal operation. When
extreme current flows above the abnormal over−current
threshold level V , which lasts over t
CS−AOCP
in
ON−AOCP
abnormal conditions, the main MOSFET turns off
immediately and the internal counter counts up the number
of occurrence. Once this situation occurs the number of
As for Brown−in operation, if a sensed V is above
IN
V
IN−ON
and V is higher than V
, then NCP1118x
CC
CC−ON
starts up and operates. Whereas, Brown−out is triggered
when V is kept less than V for a debounce time
N
AOCP
consecutively, then AOCP is triggered and PWM
switching stops immediately until V
decreases to
IN
IN−OFF
CC
t , the PWM switching stop. The protection is not
V
CC−LR
.
D−VINOFF
released until V is higher than V
.
IN
IN−ON
Meanwhile, when V is higher than V
and the
IN
IN−OVP
OSC
number of PWM switching last longer than Line−OVP
debouncing counting number N , Line−OVP is
S
Q
PWM
VFB
tLEB
VINOVP
R
triggered and PWM switching stops. Whereas, this
protection can be released and allows NCP1118x to restart
CS
with soft−start when V decreases by V
lower
IN
IN−OVPHYS
NAOCP
counter
and V is higher than V
.
CC
CC−ON
tON−AOCP
AOCP
An ac input voltage for brown−out and Line−OVP can be
VCS−AOCP
simply set up by equations shown in Figure 43. Since it,
Figure 40. AOCP Logic
a brown−in level is naturally determined by V
.
IN−ON
Additionally, it is recommended to add a capacitor of tens
nano−farad to decouple switching noise and sense a voltage
stably.
tLEB
tON−AOCP
VIN
VCS−AOCP
VCS−LIMIT
tD−VINOFF
VIN−OVP
No
switching
VCS
VIN−OVPHYS
t
VIN−ON
Figure 41. AOCP Operation
VIN−OFF
Current−Sense Short Protection
When CS pin is shorted to GND pin due to soldering
defect or some dust, a drain current− cannot be sensed
properly. It causes excessive drain current and ends up the
VCC
VCC−ON
VCC−OFF
VCC−AR
switcher damage. If PWM on−time is longer than t
ON−CSSP
IDRAIN
while V is less than V
, the CSSP circuit regards as
CS−CSSP
CS
a situation of CS pin short and turns off PWM switching
immediately. If this state persists consecutively NCSSP
times, then PWM switching operation stops permanently.
This protection cannot be reset until unplugging the input
Figure 43. Brown−in/out & Line−OVP
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17
NCP11184, NCP11185, NCP11187
VD C
Ǹ
RUP
RLO
VAC*BO
@
2 ) VIN*OFF
RUP
+
VIN*OFF
VIN
CF
RLO
R
UP ) RLO VIN*OVP
VAC*OVP
+
@
Ǹ
RLO
2
Figure 44. Line Voltage Detection
Thermal Shutdown (TSD)
TSD limits total power dissipation of NCP1118x by
detecting temperature. When the junction temperature T
J
exceeds T , this switcher shuts down immediately. It can
SD
be recovery when T reduces by below T
. During
TSD−HYS
J
this TSD status, HV startup circuit performs on and off
repeatedly.
T
J
TSD
TSD−HYS
VCC
VCC−ON
VCC−AR
IDRAIN
Figure 45. Thermal Shutdown
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NCP11184, NCP11185, NCP11187
PCB LAYOUT RECOMMENDATIONS
This section introduces some PCB design tips for
• GND: There are two kinds of GND in power conversion
board and should be separated for avoiding interference
and better performance.
• Generally, lightning surge could pass through stray
capacitance of the transformer from the primary side to
the secondary side or vice−versa. Regard with that, some
points should be taken into account when designing PCB,
such as placing control circuit parts, EMI filters and an
Y−capacitor.
designers to minimize EMI (Electromagnetic Interference)
and make robust switched mode power supplies using
NCP1118x.
• High−frequency switching current/voltage makes PCB
layout a very important design issue. Good PCB layout
minimizes excessive EMI and helps the power supply
survive during surge/ESD (Electro Static Discharge)
tests.
• To improve EMI performance and reduce line frequency
ripples, the output of the bridge rectifier should connect
to bulk capacitor as close as possible.
• 3 could be a point−discharger route to bypass the static
electricity energy. It is suggested to map out this discharge
route and not to place any low voltage components on the
route.
• Should a Y−cap be required between primary and
secondary, connect this Y−cap to the positive terminal of
bulk capacitor. If this Y−cap is connected to primary
GND, it should be connected to the negative terminal of
bulk capacitor (GND) directly. Point discharge of this
Y−cap helps for ESD; however, the creepage between
these two pointed ends should be at least 5 mm according
to safety requirements.
• As indicated by 1 in Figure 46, the high−frequency
current loop is formed by beginning of the bridge rectifier,
bulk capacitor, a power transformer to return to bulk
capacitor. The area enclosed by this current loop should
be designed as small as possible to reduce conduction and
radiation noise. Keep the traces short, direct, and wide.
High−voltage traces related the drain of MOSFET and
RCD snubber should be kept far away from control
circuits to prevent noise interference affecting low
voltage signal paths at the control part.
• Thermal Considerations:
• As indicated by 2, the ground of control circuits should be
connected first, then to other circuitry.
Power MOSFET dissipates heats during switching
operation. If chip temperature exceeds TSD, thermal
shutdown would be triggered and NCP1118x stops
operating to protect itself from damage. The path of
lowest thermal impedance from NCP1118x chip to
externals is from DRAIN pin. It is recommended to
increase area of connected copper to DRAIN pin as much
as possible.
• Place C
as close to VCC pin of the NCP1118x as
VCC
possible for good decoupling. It is recommended to use
a few of micro−farad capacitor and 100 nF ceramic
capacitor for high frequency noise decoupling as well.
C
VIN
pin and C pin capacitor are also recommended to
FB
place as close as possible to VIN and FB pin.
There are some suggestions for grounding connection.
Enlarge DRAIN−pin pattern for
GND pin
better heat emission
YCap
1
Power GND
Bigger pattern
3
Signal GND
Smaller pattern
Separate signal and power ground
CS
C9
DRAI N
VI N
GND
FB
VCC
C13
FB
C9: VIN−pin capacitor
C13: FB−pin capacitor
C17: VCC−pin small capacitor
Each capacitor should be placed
close to pins
C17
2
Figure 46. Layout Considerations
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19
NCP11184, NCP11185, NCP11187
DESIGN EXAMPLE
This is a design example of 45 W isolated flyback converter using NCP1118765. For further detail information, go to the
webpage of NCP1118x.
EVB No: NCP11187A65F45GEVB
Devices
Applications
Topology
Output Power
NCP11187A65
White Goods and Industrial
Power Supplies
Isolated Flyback
45 W
Input Voltage
Output Spec.
Efficiency
Standby Power
85–265 Vac
12 V/3.5 A &
16 V/0.2 A
> 88%
@ Full−load
< 50 mW
@ 230 Vac
Package Temperature
Operating Temperature
Cooling Method
Board Size
90°C @ T = 50°C
0~50°C
Natural Convection
In Open Frame
145 x 60 x 30 mm
A
3
2.83 W/inch
CY101
4.7nF
R201/130
C201/100pF
12V
T201
940uH
L201
1.5uH/6A
R202/130
C204
47uF
35V
R104
NC
C202
2200uF
16V
C203
2200uF
16V
BD101
GBU6J
D201
MBR20200CT
R101
10MW
ZD101
P6KE220A
C102
C101
100uF
450V
CN201
R105
NC
NC
R102
10MW
D101
MURS160T3G
R203/82
C205/470pF
16V
L202
1.5uH/0.92A
R112
10MW
R204/82
C207
47uF
35V
VIN
C206
680uF
25V
D202
FSV10150
C106
2nF/10V
R103
270kW
CX102
150nF/275Vac
U101
NCP11187
R106 2.7W
R107 2.7W
R108 2.7W
R109 2.2W
R110 2.2W
R111
0
DRAIN
LF101
40mH/1.3A
CS
VIN
DRAIN
D102
MURS160T3G
VIN
12V
12V
16V
GND
FB
CX101
680nF/275Vac
VDD
C104
100nF/50V
C103
1nF/10V
C105
47uF/35V
R209
1.2MW
R205
750W
R208
160kW
R206
1.2kW
R210
680kW
F101
250Vac/2A
R207
56kW
C208
27nF/25V
U201
FOD817A
U202
NCP431BC
R211
36kW
CN101
R212
1.8kW
L
N
Figure 47. NCP11187 EVB Schematic
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20
NCP11184, NCP11185, NCP11187
REFERENCES
For more specific designs, refer to the links below:
• AN−4148 Audible Noise Reduction Technique for FPS Applications
https://www.onsemi.com/pub/Collateral/AN−4148.pdf
• AN−4137 Design Guidelines for Off−line Flyback Converters Using Power Switch
https://www.onsemi.com/pub/Collateral/AN−4137.pdf
• AN−4140 Transformer Design Consideration for Offline Flyback Converters Using Power Switch
https://www.onsemi.com/pub/Collateral/AN−4140.pdf
• NCP1118x Family Simplis Behavior Model
• NCP1118x Family Excel−based Design Tool
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21
NCP11184, NCP11185, NCP11187
ORDERING INFORMATION
ORDERING INFORMATION
Device
R
(W)
f
(kHz)
OSC
Package
Shipping
DS(ON)
NCP11184A065PG
NCP11185A065PG
NCP11187A065PG
NCP11184A100PG
NCP11187A100PG
NCP11184A130PG
NCP11185A130PG
NCP11184A065PLR2G
NCP11185A065PLR2G
NCP11187A065PLR2G
NCP11184A100PLR2G
2.25
65
PDIP−7
50 Units / Rail
(Pb−Free)
1.3
0.87
2.25
0.87
2.25
1.3
65
65
100
100
130
130
65
2.25
1.3
PDIP−7 GW
(Pb−Free)
50 Units / Rail
65
0.87
2.25
65
100
mWSaver is a registered trademark of Semiconductor Components Industries, LLC.
Energy Star is a registered trademark of the U.S. Environmental Protection Agency
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22
NCP11184, NCP11185, NCP11187
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 6)
CASE 626A
ISSUE C
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
H
8
5
4
E1
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
1
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 8
c
b2
B
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
TOP VIEW
INCHES
DIM MIN MAX
−−−−
A1 0.015
MILLIMETERS
A2
A
MIN
−−−
0.38
2.92
0.35
MAX
5.33
−−−
4.95
0.56
e/2
A
0.210
−−−−
NOTE 3
A2 0.115 0.195
L
b
b2
C
0.014 0.022
0.060 TYP
0.008 0.014
1.52 TYP
0.20
9.02
0.13
7.62
6.10
0.36
10.16
−−−
8.26
7.11
D
0.355 0.400
SEATING
PLANE
D1 0.005
0.300 0.325
E1 0.240 0.280
−−−−
A1
D1
E
C
M
e
eB
L
0.100 BSC
−−−− 0.430
0.115 0.150
−−−− 10°
2.54 BSC
−−−
2.92
−−−
10.92
3.81
10°
e
eB
8X
b
END VIEW
M
NOTE 6
M
M
M
0.010
C A
B
SIDE VIEW
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NCP11184, NCP11185, NCP11187
PACKAGE DIMENSIONS
PDIP7 MINUS PIN 6 GW
CASE 707AA
ISSUE O
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24
NCP11184, NCP11185, NCP11187
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
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