NCP1207-D [ONSEMI]
PWM Current-Mode Controller for Free Running Quasi-Resonant Operation; PWM电流模式控制器自由运行准谐振操作
| 型号： | NCP1207-D |
| 厂家： | 
ONSEMI |
| 描述： | PWM Current-Mode Controller for Free Running Quasi-Resonant Operation |
| 文件： | 总18页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1207
PWM Current−Mode
Controller for Free Running
Quasi−Resonant Operation
The NCP1207 combines a true current mode modulator and a
demagnetization detector to ensure full borderline/critical
Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi−Resonant operation). Due to its inherent
skip cycle capability, the controller enters burst mode as soon as the
power demand falls below a predetermined level. As this happens at
low peak current, no audible noise can be heard. An internal 8.0 ms
timer prevents the free−run frequency to exceed 100 kHz (therefore
below the 150 kHz CISPR−22 EMI starting limit), while the skip
adjustment capability lets the user select the frequency at which the
burst foldback takes place.
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MARKING
DIAGRAMS
8
SOIC−8
D1, D2 SUFFIX
CASE 751
1207
ALYW
8
1
1
The Dynamic Self−Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1207. This feature is particularly useful in applications
where the output voltage varies during operation (e.g. battery
chargers). Due to its high−voltage technology, the IC is directly
connected to the high−voltage DC rail. As a result, the short−circuit
8
PDIP−8
N SUFFIX
CASE 626
1207P
AWL
YYWW
8
1
1
trip point is not dependent upon any V auxiliary level.
CC
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin, also enables fast
Overvoltage Protection (OVP). Once an OVP has been detected, the
IC permanently latches−off.
Finally, the continuous feedback signal monitoring implemented
with an overcurrent fault protection circuitry (OCP) makes the final
design rugged and reliable.
1207/P = Device Code
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
Features
• Free−Running Borderline/Critical Mode Quasi−Resonant Operation
• Current−Mode with Adjustable Skip−Cycle Capability
DMG
FB
1
2
3
4
8
7
6
5
HV
NC
V
• No Auxiliary Winding V Operation
CC
CS
CC
• Auto−Recovery Overcurrent Protection
• Latching Overvoltage Protection
GND
Drv
• External Latch Triggering, e.g. Via Overtemperature Signal
• 500 mA Peak Current Source/Sink Capability
• Internal 1.0 ms Soft−Start
(Top View)
ORDERING INFORMATION
• Internal 8.0 ms Minimum T
†
OFF
Device
Package
Shipping
• Adjustable Skip Level
NCP1207DR2
NCP1207DR2G
SOIC−8
2500/Tape & Reel
2500/Tape & Reel
• Internal Temperature Shutdown
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient Analysis
• Pb−Free Package is Available
SOIC−8
(Pb−Free)
NCP1207P
PDIP−8
50 Units/Tube
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Typical Applications
• AC/DC Adapters for Notebooks, etc.
• Offline Battery Chargers
• Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
June, 2004 − Rev. 6
NCP1207/D
NCP1207
V
out
+
+
OVP and
Demag
NCP1207
1
2
3
4
8
7
6
5
*
GND
Universal Network
+
*Please refer to the application information section
Figure 1. Typical Application
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
Demag
Core reset detection and OVP
The auxiliary FLYBACK signal ensures discontinuous operation and
offers a fixed overvoltage detection level of 7.2 V.
2
3
FB
CS
Sets the peak current setpoint
By connecting an Optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand. By bringing this pin
below the internal skip level, device shuts off.
Current sense input and
skip cycle level selection
This pin senses the primary current and routes it to the internal
comparator via an L.E.B. By inserting a resistor in series with the pin, you
control the level at which the skip operation takes place.
4
5
6
7
8
GND
Drv
The IC ground
Driving pulses
Supplies the IC
−
−
The driver’s output to an external MOSFET.
V
CC
This pin is connected to an external bulk capacitor of typically 10 mF.
This unconnected pin ensures adequate creepage distance.
Connected to the high−voltage rail, this pin injects a constant current into
NC
HV
High−voltage pin
the V bulk capacitor.
CC
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2
NCP1207
4.5 ms
Delay
R
esd
Demag
−
+
Demag
HV
OVP
+
R
int
7.0
mA
8.0 ms
Blanking
10 V
PON
+
/1.44
50 mV
5.0 V
S
+
−
Q
Driver: src = 20
sink = 10
+
V
CC
S*
Q
−
+
R*
R
V
12 V, 10 V,
5.3 V (fault)
CC
Drv
FB
4.2 V
To Internal
Supply
Fault
Mngt.
Soft−Start = 1 ms
1.0 V
/3
+
−
GND
200 mA
when Drv
is OFF
Overload?
380 ns
L.E.B.
Timeout
Reset
CS
5.0 ms
Timeout
Demag
*S and R are level triggered whereas S is edge
triggered. R has priority over the other inputs.
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating
Symbol
, Drv
Value
16
Units
Power Supply Voltage
V
V
V
CC
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (V ) Pin 5 (Drv) and
−
−0.3 to 10
CC
Pin 1 (Demag)
Maximum Current into all pins except V (6), HV (8) and Demag (1) when 10 V
−
5.0
mA
CC
ESD diodes are activated
Maximum Current in Pin 1
Idem
R
+3.0/−2.0
mA
°C/W
°C/W
°C/W
°C
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Air, SOIC version
Thermal Resistance, Junction−to−Air, PDIP version
Maximum Junction Temperature
Temperature Shutdown
57
178
q
q
q
JC
JA
JA
R
R
100
TJ
150
MAX
−
155
°C
Hysteresis in Shutdown
−
−
−
−
30
°C
Storage Temperature Range
−60 to +150
2.0
°C
ESD Capability, HBM Model (All pins except HV)
ESD Capability, Machine Model
kV
200
V
Maximum Voltage on Pin 8 (HV), Pin 6 (V ) decoupled to ground with 10 mF
V
500
V
CC
HVMAX
Minimum Voltage on Pin 8 (HV), Pin 6 (V ) decoupled to ground with 10 mF
V
HVMIN
40
V
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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3
NCP1207
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = 0°C to +125°C, Max T = 150°C,
J
J
J
V
CC
= 11 V unless otherwise noted)
Rating
Pin
Symbol
Min
Typ
Max
Unit
DYNAMIC SELF−SUPPLY
V
V
V
Increasing Level at which the Current Source Turns−off
6
6
6
6
VCC
10.8
9.1
−
12
10
12.9
10.6
−
V
V
CC
CC
CC
OFF
Decreasing Level at which the Current Source Turns−on
Decreasing Level at which the Latch−off Phase Ends
VCC
ON
VCC
5.3
1.0
V
latch
Internal IC Consumption, No Output Load on Pin 5,
= 60 kHz
I
I
I
−
1.3
(Note 1)
mA
CC1
F
SW
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
= 60 kHz
6
6
−
−
1.6
2.0
(Note 1)
mA
CC2
CC3
F
SW
Internal IC Consumption in Latch−off Phase
330
−
mA
INTERNAL STARTUP CURRENT SOURCE (T u 0°C)
J
High−voltage Current Source, V = 10 V
8
8
I
I
4.3
−
7.0
8.0
9.6
−
mA
mA
CC
C1
High−voltage Current Source, V = 0
CC
C2
DRIVE OUTPUT
Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of Output
Signal
5
5
T
−
−
40
20
−
−
ns
ns
r
Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of Output
Signal
T
f
Source Resistance
5
5
R
12
20
10
36
19
W
W
OH
Sink Resistance
R
5.0
OL
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint
3
3
3
3
3
I
−
0.92
−
0.02
1.0
−
1.12
160
−
mA
V
IB
I
Limit
Propagation Delay from Current Detection to Gate OFF State
Leading Edge Blanking Duration
T
DEL
T
LEB
skip
100
380
200
ns
ns
mA
−
Internal Current Offset Injected on the CS Pin during OFF Time
I
−
−
OVERVOLTAGE SECTION (V = 11 V)
CC
Sampling Delay after ON Time
OVP Internal Reference Level
1
1
T
−
4.5
7.2
−
ms
sample
V
ref
6.4
8.0
V
FEEDBACK SECTION (V = 11 V, Pin 5 Loaded by 1.0 kW)
CC
Internal Pull−up Resistor
2
−
−
Rup
Iratio
Tss
−
−
−
20
3.3
1.0
−
−
−
kW
−
Pin 3 to Current Setpoint Division Ratio
Internal Soft−start
ms
DEMAGNETIZATION DETECTION BLOCK
Input Threshold Voltage (V
Decreasing)
1
1
V
35
−
50
20
90
−
mV
mV
pin1
TH
Hysteresis (V
Decreasing)
V
H
pin1
Input Clamp Voltage
High State (I 1 = 3.0 mA)
1
1
VC
8.0
10
12
V
V
pin
H
Low State (I 1 = −2.0 mA)
pin
VC
−0.9
−0.7
−0.5
L
Demag Propagation Delay
1
1
1
1
1
T
−
−
−
−
−
210
10
−
−
−
−
−
ns
pF
ms
dem
Internal Input Capacitance at V
= 1.0 V
C
par
pin1
Minimum T
(Internal Blanking Delay after T
)
T
blank
8.0
5.0
28
OFF
ON
Timeout After Last Demag Transition
Pin 1 Internal Impedance
T
ms
out
R
kW
int
1. Max value at T = 0°C.
J
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4
NCP1207
TYPICAL CHARACTERISTICS
(T = −40°C to 125°C)
J
13.2
12.8
12.4
12.0
11.2
10.8
7
10.4
10.0
11.6
9.6
9.2
8.8
11.2
10.8
10.4
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. VCC Increasing Level at which the
Current Source Turns−off versus Temperature
Figure 4. VCC Decreasing Level at which the
Current Source Turns−on versus Temperature
2.30
1.60
1.40
2.10
1.90
1.70
1.20
1.00
0.80
0.60
1.50
1.30
1.10
0.40
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Internal IC Consumption, No Output
Load on Pin 5 versus Temperature
Figure 6. Internal IC Consumption, Output
Load on Pin 5 versus Temperature
12
11
10
9
1.20
1.15
1.10
1.05
1.00
0.95
0.90
8
7
6
5
4
3
2
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Internal Startup Current Source,
VCC = 10 V versus Temperature
Figure 8. Maximum Internal Current Setpoint
versus Temperature
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5
NCP1207
TYPICAL CHARACTERISTICS
(T = −40°C to 125°C)
J
40
35
30
25
20
15
10
20
18
16
14
12
10
8
6
4
5
0
2
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Source Resistance versus
Temperature
Figure 10. Sink Resistance versus
Temperature
8.0
7.5
7.0
6.5
6.0
120
100
80
60
40
20
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Input Voltage (Vpin1 Decreasing)
versus Temperature
Figure 12. OVP Internal Reference Level
versus Temperature
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6
NCP1207
TYPICAL CHARACTERISTICS
(T = −50°C to 125°C)
J
10
9.5
9.0
8.5
8.0
7.5
1.5
1.4
1.3
1.2
1.1
1
7.0
6.5
0.9
0.8
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
−50
−25
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Minimum Toff versus Temperature
Figure 14. Internal Soft−start versus
Temperature
50
40
30
20
10
0
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 15. DMG Pin Internal Resistance versus
Temperature
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7
NCP1207
Application Information
Introduction
occurs at low peak current. This point guarantees a
noise−free operation with cheap transformer. This
option also offers the ability to fix the maximum
switching frequency when entering light load
conditions.
The NCP1207 implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint whereas the core reset detection
triggers the turn−on event. This component represents the
ideal candidate where low part−count is the key parameter,
particularly in low−cost AC/DC adapters, consumer
electronics, auxiliary supplies, etc. Thanks to its
high−performance High−Voltage technology, the NCP1207
incorporates all the necessary components / features needed
to build a rugged and reliable Switch−Mode Power Supply
(SMPS):
• Overcurrent Protection (OCP): by continuously
monitoring the FB line activity, NCP1207 enters burst
mode as soon as the power supply undergoes an
overload. The device enters a safe low power operation
which prevents from any lethal thermal runaway. As
soon as the default disappears, the power supply
resumes operation. Unlike other controllers, overload
detection is performed independently of any auxiliary
winding level. In presence of a bad coupling between
both power and auxiliary windings, the short circuit
detection can be severely affected. The DSS naturally
shields you against these troubles.
• Transformer core reset detection: borderline / critical
operation is ensured whatever the operating conditions
are. As a result, there are virtually no primary switch
turn−on losses and no secondary diode recovery losses.
The converter also stays a first−order system and
accordingly eases the feedback loop design.
Dynamic Self−Supply
• Quasi−resonant operation: by delaying the turn−on
event, it is possible to re−start the MOSFET in the
minimum of the drain−source wave, ensuring reduced
EMI / video noise perturbations. In nominal power
conditions, the NCP1207 operates in Borderline
Conduction Mode (BCM) also called Critical
Conduction Mode.
The DSS principle is based on the charge/discharge of the
V
bulk capacitor from a low level up to a higher level. We
CC
can easily describe the current source operation with some
simple logical equations:
POWER−ON:IF V < VCC
THEN Current Source
CC
OFF
is ON, no output pulses
IF V decreasing > VCC THEN Current Source is
CC
ON
• Dynamic Self−Supply (DSS): due to its Very High
Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductor’s NCP1207 allows for a direct pin
connection to the high−voltage DC rail. A dynamic
current source charges up a capacitor and thus provides
OFF, output is pulsing
IF V increasing < VCC
THEN Current Source is
CC
OFF
ON, output is pulsing
Typical values are: VCC
= 12 V, VCC = 10 V
ON
OFF
a fully independent V level to the NCP1207. As a
CC
To better understand the operational principle, Figure 16’s
sketch offers the necessary light.
result, there is no need for an auxiliary winding whose
management is always a problem in variable output
voltage designs (e.g. battery chargers).
V
= 2 V
RIPPLE
• Overvoltage Protection (OVP): by sampling the plateau
voltage on the demagnetization winding, the NCP1207
goes into latched fault condition whenever an
VCC
= 12 V
OFF
VCC = 10 V
ON
overvoltage condition is detected. The controller stays
fully latched in this position until the V is cycled
CC
down 4.0 V, e.g. when the user un−plugs the power
supply from the mains outlet and re−plugs it.
ON
• External latch trip point: by externally forcing a level
on the OVP greater than the internal setpoint, it is
possible to latch−off the IC, e.g. with a signal coming
from a temperature sensor.
OFF
Output Pulses
• Adjustable skip cycle level: by offering the ability to
tailor the level at which the skip cycle takes place, the
designer can make sure that the skip operation only
Figure 16. The Charge/Discharge Cycle Over a 10 mF
CC Capacitor
V
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8
NCP1207
The DSS behavior actually depends on the internal IC
When using Figure17 option, it is important to check
the absence of any negative ringing that could occur
on pin 8. The resistor in series should help to damp
any parasitic LC network that would ring when
suddenly applying the power to the IC. Also, since
the power disappears during 10 ms (half−wave
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg equals 22 nC
(max). With a maximum switching frequency selected at
75 kHz, the average power necessary to drive the MOSFET
(excluding the driver efficiency and neglecting various
voltage drops) is:
rectification), CV should be calculated to supply
CC
the IC during these holes in the supply
Fsw Qg V with:
CC
3. Permanently force the V level above V
with
CCH
CC
Fsw = maximum switching frequency
Qg = MOSFET’s gate charge
an auxiliary winding. It will automatically
disconnect the internal startup source and the IC will
be fully self−supplied from this winding. Again, the
total power drawn from the mains will significantly
decrease. Make sure the auxiliary voltage never
exceeds the 16 V limit.
V
CC
= V level applied to the gate
GS
To obtain the output current, simply divide this result by
: I = F Qg = 1.6 mA. The total standby power
V
CC driver
SW
consumption at no−load will therefore heavily rely on the
internal IC consumption plus the above driving current
(altered by the driver’s efficiency). Suppose that the IC is
supplied from a 350 VDC line. The current flowing through
pin 8 is a direct image of the NCP1207 consumption
(neglecting the switching losses of the HV current source).
Skipping Cycle Mode
The NCP1207 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18) and
follows the following formula:
If I
equals 2.3 mA @ T = 60°C, then the power
CC2
J
dissipated (lost) by the IC is simply: 350 V x 2.3 mA =
805 mW. For design and reliability reasons, it would be
interested to reduce this source of wasted power that
increase the die temperature. This can be achieved by using
different methods:
1. Use a MOSFET with lower gate charge Qg.
2. Connect pin 8 through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
1
2
@ Lp @ Ip2 @ Fsw @ D
with:
V
mainsPEAK @ 2
burst
becomes
. Our power contribution
p
example drops to: 223 V x 2.3 mA = 512 mW. If a
resistor is installed between the mains and the diode,
you further force the dissipation to migrate from the
package to the resistor. The resistor value should
account for low−line startups.
Lp = primary inductance
Fsw = switching frequency within the burst
Ip = peak current at which skip cycle occurs
D
burst
= burst width / burst recurrence
HV
1N4007
MAX PEAK
CURRENT
NORMAL CURRENT
MODE OPERATION
300
200
100
0
5
1
2
C
bulk
1
2
3
4
8
MAINS
6
SKIP CYCLE
CURRENT LIMIT
7
6
5
Figure 17. A simple diode naturally reduces the
average voltage on pin 8
WIDTH
RECURRENCE
Figure 18. The skip cycle takes place at low peak
currents which guaranties noise free operation
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9
NCP1207
DRIVER
current sense comparator permanently resets the latch and the
next clock cycle (given by the demagnetization detection) is
ignored: we are skipping cycles as shown by Figure 20. As
soon as the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1207. To the opposite, in low output power conditions, no
more ringing waves are present on the drain and the toggling
of the current sense comparator together with the internal 5 ms
timeout initiates a new cycle start. In normal operating
conditions, e.g. when the drain oscillations are generous, the
demagnetization comparator can detect the 50 mV crossing
and gives the “green light”, alone, to re−active the power
switch. However, when skip cycle takes place (e.g. at low
output power demands), the re−start event slides along the
drain ringing waveforms (actually the valley locations) which
decays more or less quickly, depending on the
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 mA
R
skip
3
2
−
+
RESET
R
sense
+
Figure 19. A patented method allows for skip level
selection via a series resistor inserted in series
with the current
The skip level selection is done through a simple resistor
inserted between the current sense input and the sense element.
Every time the NCP1207 output driver goes low, a 200 mA
source forces a current to flow through the sense pin
(Figure 19): when the driver is high, the current source is off
and the current sense information is normally processed. As
soon as the driver goes low, the current source delivers 200 mA
L
−C
network damping factor. The situation can
primary parasitic
thus quickly occur where the ringing becomes too weak to be
detected by the demagnetization comparator: it then
permanently stays locked in a given position and can no longer
deliver the “green light” to the controller. To help in this
situation, the NCP1207 implements a 5 ms timeout generator:
each time the 50 mV crossing occurs, the timeout is reset. So,
as long as the ringing becomes too low, the timeout generator
starts to count and after 5 ms, it delivers its “green light”. If the
skip signal is already present then the controller re−starts;
otherwise the logic waits for it to set the drive output high.
Figure 20 depicts these two different situations:
and develops a ground referenced voltage across R . If this
skip
voltage is below the feedback voltage, the current sense
comparator stays in the high state and the internal latch can be
triggered by the next clock cycle. Now, if because of a low load
mode the feedback voltage is below R
level, then the
skip
Drain
Signal
Timeout
Signal
Demag Re−start
Current Sense and Timeout Re−start
Drain
Signal
Timeout
Signal
5 ms
5 ms
Figure 20. When the primary natural ringing becomes too low, the internal timeout together with the sense
comparator initiates a new cycle when FB passes the skip level.
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10
NCP1207
Demagnetization Detection
400
300
200
100
0
The core reset detection is done by monitoring the voltage
activity on the auxiliary winding. This voltage features a
FLYBACK polarity. The typical detection level is fixed at
50 mV as exemplified by Figure 21.
7.0
POSSIBLE
5.0
RE−STARTS
3.0
Figure 23. The NCP1207 Operates in
Borderline / Critical Operation
1.0
50 mV
0 V
−1.0
Overvoltage Protection
The overvoltage protection works by sampling the plateau
voltage 4.5 ms after the turn−off sequence. This delay
guarantees a clean plateau, providing that the leakage
inductance ringing has been fully damped. If this would not
be the case, the designer should install a small RC damper
across the transformer primary inductance connections.
Figure 24 shows where the sampling occurs on the auxiliary
winding.
Figure 21. Core reset detection is done through a
dedicated auxiliary winding monitoring
TO INTERNAL
COMPARATOR
R
R
dem
esd
1
2
1
5
4
R
ESD2
ESD1
4
int
Aux
3
SAMPLING HERE
8.0
R
+ R = 28 k
int
esd
Figure 22. Internal Pad Implementation
6.0
4.0
An internal timer prevents any re−start within 8.0 ms
further to the driver going−low transition. This prevents the
switching frequency to exceed (1 / (T + 8.0 ms)) but also
ON
avoid false leakage inductance tripping at turn−off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.
2.0
4.5 ms
The 1207 demagnetization detection pad features a
specific component arrangement as detailed by Figure 22. In
this picture, the zener diodes network protect the IC against
any potential ESD discharge that could appear on the pins.
The first ESD diode connected to the pad, exhibits a parasitic
capacitance. When this parasitic capacitance (10 pF
0
Figure 24. A voltage sample is taken 4.5 ms after
the turn−off sequence
When an OVP condition has been detected, the NCP1207
enters a latch−off phase and stops all switching operations.
The controller stays fully latched in this position and the
DSS is still active, keeping the V between 5.3 V/12 V as
in normal operations. This state lasts until the V is cycled
down 4 V, e.g. when the user unplugs the power supply from
the mains outlet.
By default, the OVP comparator is biased to a 5 V
reference level and pin 1 is routed via a divide by 1.44
typically) is combined with R , a re−start delay is created
dem
and the possibility to switch right in the drain−source wave
exists. This guarantees QR operation with all the associated
CC
benefits (low EMI, no turn−on losses etc.). R
should be
dem
CC
calculated to limit the maximum current flowing through
pin 1 to less than +3 mA/−2 mA. If during turn−on, the
auxiliary winding delivers 30 V (at the highest line level),
then the minimum R
value is defined by:
dem
(30 V + 0.7 V) / 2 mA = 14.6 kW.
network. As a result, when V
reaches 7.2 V, the OVP
pin1
This value will be further increased to introduce a re−start
delay and also a slight filtering in case of high leakage
energy.
comparator is triggered. The threshold can thus be adjusted
by either modifying the power winding to auxiliary winding
turn ratios to match this 7.2 V level, or insert a resistor from
pin1 to ground to cope with your design requirement.
Figure 23 portrays a typical V shot at nominal output
DS
power.
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11
NCP1207
Latching Off the NCP1207
Power Dissipation
In certain cases, it can be very convenient to externally
shut down permanently the NCP1207 via a dedicated signal,
e.g. coming from a temperature sensor. The reset occurs
when the user unplugs the power supply from the mains
outlet. To trigger the latch−off, a CTN (Figure 25) or a
simple NPN transistor (Figure 26) can do the work.
The NCP1207 is directly supplied from the DC rail
through the internal DSS circuitry. The DSS being an
auto−adaptive circuit (e.g. the ON/OFF duty−cycle adjusts
itself depending on the current demand), the current flowing
through the DSS is therefore the direct image of the
NCP1207 current consumption. The total power dissipation
can be evaluated using: (V
* 11 V) @ I . If we
HVDC
CC2
CTN
operate the device on a 250 Vac rail, the maximum rectified
voltage can go up to 350 Vdc. As a result, the worse case
dissipation occurs at the maximum switching frequency and
the highest line. The dissipation is actually given by the
internal consumption of the NCP1207 when driving the
selected MOSFET. The best method to evaluate this total
consumption is probably to run the final circuit from a
50 Vdc source applied to pin 8 and measure the average
current flowing into this pin. Suppose that we find 2.0 mA,
meaning that the DSS duty−cycle will be 2.0/7.0 = 28.6%.
From the 350 Vdc rail, the part will dissipate:
350 V @ 2.0 mA + 700 mW (however this 2.0 mA number
will drop at higher operating junction temperatures).
A DIP8 package offers a junction−to−ambient thermal
NCP1207
Aux
1
2
3
4
8
7
6
5
Figure 25. A simple CTN triggers the latch−off as
soon as the temperature exceeds a given setpoint
resistance R
of 100°C/W. The maximum power
qJA
dissipation can thus be computed knowing the maximum
operating ambient temperature (e.g. 70°C) together with
the maximum allowable junction temperature (125°C):
NCP1207
Aux
1
2
3
4
8
7
6
5
T
* T
Amax
Jmax
P
+
t 550 mW. As we can see, we
max
R
qJA
ON/OFF
do not reach the worse consumption budget imposed by the
operating conditions. Several solutions exist to cure this
trouble:
• The first one consists in adding some copper area around
the NCP1207 DIP8 footprint. By adding a min pad area
Figure 26. A simple transistor arrangement allows
to trigger the latch−off by an external signal
2
of 80 mm of 35 mm copper (1 oz.) R
drops to about
qJA
75°C/W. Maximum power then grows up to 730 mW.
• A resistor Rdrop needs to be inserted with pin 8 to
a) avoid negative spikes at turn−off (see below)
Shutting Off the NCP1207
Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 27. When OFF,
Q1 is transparent to the operation. When forward biased, the
transistor pulls the FB pin to ground (V
permanently disables the IC. A small time constant on the
transistor base will avoid false triggering (Figure 27).
b) split the power budget between this resistor and the
package. The resistor is calculated by leaving at least 50 V
on pin 8 at minimum input voltage (suppose 100 Vdc in
≈ 200 mV) and
CE(sat)
V
* 50 V
7.0 mA
bulkmin
our case): R
v
t 7.1 kW. The
drop
power dissipated by the resistor is thus:
NCP1207
P
+ V
2ńR
drop
dropRMS
drop
2
1
2
3
4
8
7
6
5
Ǹ
DSS
ǒI
duty * cycleǓ
@ R
@
DSS
drop
+
10 k
1
R
drop
Ǹ
Q1
ON/OFF
ǒ7.0 mA @ 7.1 kW @ 0.286Ǔ2
3
2
+
+ 99.5 mW
10 nF
7.1 kW
Please refer to the application note AND8069 available
from www.onsemi.com/pub/ncp1200.
Figure 27. A simple bipolar transistor totally
disables the IC
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12
NCP1207
hosts a dedicated overload detection circuitry. Once
• If the power consumption budget is really too high for the
activated, this circuitry imposes to deliver pulses in a burst
manner with a low duty−cycle. The system recovers when
the fault condition disappears.
DSS alone, connect a diode between the auxiliary
winding and the V pin which will disable the DSS
CC
operation (V u 10 V).
CC
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time−out used by this IC
The SOIC package offers a 178°C/W thermal resistor.
Again, adding some copper area around the PCB footprint
will help decrease this number: 12 mm 12 mm to drop
R
qJA
down to 100°C/W with 35 mm copper thickness (1 oz.)
or 6.5 mm 6.5 mm with 70 mm copper thickness (2 oz.).
As one can see, we do not recommend using the SO−8
package and the DSS if the part operates at high switching
frequencies. In that case, an auxiliary winding is the best
solution.
works with the V decoupling capacitor: as soon as the
CC
V
CC
decreases from the VCC
level (typically 12 V) the
OFF
device internally watches for an overload current situation.
If this condition is still present when the VCC level is
ON
reached, the controller stops the driving pulses, prevents the
self−supply current source to restart and puts all the circuitry
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short−circuit protection. A
short−circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken Optocoupler. To account for this situation, NCP1207
in standby, consuming as little as 330 mA typical (I
CC3
parameter). As a result, the V level slowly discharges
CC
toward 0. When this level crosses 5.3 V typical, the
controller enters a new startup phase by turning the current
source on: V rises toward 12 V and again delivers output
CC
pulses at the VCC
crossing point. If the fault condition
OFF
has been removed before VCC approaches, then the IC
ON
continues its normal operation. Otherwise, a new fault cycle
takes place. Figure 28 shows the evolution of the signals in
presence of a fault.
V
CC
REGULATION
OCCURS HERE
12 V
LATCH−OFF
PHASE
10 V
5.3 V
TIME
If the fault is relaxed during the V
CC
DRV
natural fall down sequence, the IC
automatically resumes.
If the fault still persists when V
DRIVER
PULSES
CC
reached VCC , then the controller
ON
cuts everything off until recovery.
TIME
TIME
INTERNAL
FAULT FLAG
FAULT IS
RELAXED
STARTUP PHASE
FAULT OCCURS HERE
Figure 28.
Soft−Start
1.0 V). The soft−start is also activated during the
overcurrent burst (OCP) sequence. Every restart attempt is
followed by a soft−start activation. Generally speaking, the
The NCP1207 features an internal 1 ms soft−start to soften
the constraints occurring in the power supply during startup.
It is activated during the power on sequence. As soon as V
soft−start will be activated when V ramps up either from
CC
CC
reaches VCC
, the peak current is gradually increased
zero (fresh power−on sequence) or 5.3 V, the latch−off
voltage occurring during OCP.
OFF
from nearly zero up to the maximum clamping level (e.g.
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13
NCP1207
HV
Calculating the V Capacitor
CC
As the above section describes, the fall down sequence
depends upon the V level: how long does it take for the
NCP1207
CC
V
line to go from 12 V to 10 V? The required time depends
1
2
3
4
8
CC
D1
1N4007
+
on the startup sequence of your system, i.e. when you first
apply the power to the IC. The corresponding transient fault
duration due to the output capacitor charging must be less
than the time needed to discharge from 12 V to 10 V,
otherwise the supply will not properly start. The test consists
in either simulating or measuring in the lab how much time
the system takes to reach the regulation at full load. Let’s
suppose that this time corresponds to 6.0 ms. Therefore a
Cbulk
7
6
5
+
V
fall time of 10 ms could be well appropriated in order
CC
Figure 29.
to not trigger the overload detection circuitry. If the
corresponding IC consumption, including the MOSFET
drive, establishes at 1.8 mA (e.g. with an 11 nC MOSFET),
we can calculate the required capacitor using the following
DV @ C
Operation Shots
Below are some oscilloscope shots captured at
= 120 VDC with a transformer featuring a 800 mH
V
formula: Dt +
, with DV = 2.0 V. Then for a wanted
in
i
primary inductance.
Dt of 10 ms, C equals 9.0 mF or 22 mF for a standard value.
When an overload condition occurs, the IC blocks its
internal circuitry and its consumption drops to 330 mA
typical. This happens at V = 10 V and it remains stuck
CC
until V reaches 5.3 V: we are in latch−off phase. Again,
CC
using the calculated 22 mF and 330 mA current consumption,
this latch−off phase lasts: 313 ms.
HV Pin Recommended Protection
When the user unplugs a power supply built with a QR
controller such as the NCP1207, two phenomena can
appear:
1. A negative ringing can take place on pin8 due to a
resonance between the primary inductance and
the bulk capacitor. As any CMOS device, the
NCP1207 is sensitive to negative voltages that
could appear on it’s pins and could create an
internal latch−up condition.
Figure 30.
2. When the bulk capacitor discharges, the internal
latch is reset by the voltage developed over the
sense resistor and the ON time expands as less
voltage is available. When the high−voltage rail
becomes too low, the gate drives permanently
stays high since no reset occurs. This situation is
not desirable in many applications.
This plot gathers waveforms captured at three different
operating points:
st
1
upper plot: free run, valley switching operation,
= 26 W
P
out
nd
2
middle plot: min T clamps the switching frequency
off
and selects the second valley
For the above reasons, we strongly recommend to add a
high−voltage diode like a 1N4007 between the bulk
rd
3
lowest plot: the skip slices the second valley pattern
and will further expand the burst as P goes low
out
capacitor and the V pin. When the bulk level collapses, it
CC
naturally shuts the controller down and eradicates the two
above problems.
http://onsemi.com
14
NCP1207
V
CC
(5 V/div)
V
GATE
(5 V/div)
V
(200 mV/div)
Rsense
200 mA X R
SKIP
V
GATE
(5 V/div)
Current Sense Pin (200 mV/div)
Figure 32.
Figure 31.
The short−circuit protection forces the IC to enter burst in
presence of a secondary overload.
This picture explains how the 200 mA internal offset
current creates the skip cycle level.
http://onsemi.com
15
NCP1207
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
8
5
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B−
1
4
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
MILLIMETERS
INCHES
MIN
0.370
F
DIM MIN
MAX
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
10.16
−A−
NOTE 2
6.60 0.240
4.45 0.155
0.51 0.015
1.78 0.040
L
G
H
J
2.54 BSC
0.100 BSC
C
0.76
0.20
2.92
1.27 0.030
0.30 0.008
0.050
0.012
0.135
K
L
3.43
0.115
J
−T−
SEATING
PLANE
7.62 BSC
0.300 BSC
N
M
N
−−−
0.76
10
−−−
1.01 0.030
10
_
0.040
_
M
D
K
G
H
M
M
M
B
0.13 (0.005)
T
A
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16
NCP1207
PACKAGE DIMENSIONS
SOIC−8
D1, D2 SUFFIX
CASE 751−07
ISSUE AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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17
NCP1207
The product described herein (NCP1207), may be covered by one or more of the following U.S. patents: 6,362,067, 6,385,060, 6,385,061, 6,429,709,
6,587,357, 6,633,193. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 81−3−5773−3850
For additional information, please contact your
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NCP1207/D
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