NCP1219BD100R2G [ONSEMI]
PWM Controller with Adjustable Skip Level and External Latch Input; PWM控制器，可调节跳过级和外部锁存输入
| 型号： | NCP1219BD100R2G |
| 厂家： | 
ONSEMI |
| 描述： | PWM Controller with Adjustable Skip Level and External Latch Input |
| 文件： | 总20页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1219
PWM Controller with
Adjustable Skip Level and
External Latch Input
The NCP1219 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The
controller allows for excellent standby power consumption by use of
its adjustable skip mode and integrated high voltage startup FET.
Internal frequency jittering, ramp compensation, timer−based fault
detection and a latch input make this controller an excellent
candidate for converters where ruggedness and component cost are
the key constraints.
http://onsemi.com
SOIC−7
D SUFFIX
CASE 751U
The Dynamic Self Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1219. This feature is particularly useful in
applications where the output voltage varies during operation (e.g.
battery chargers). Due to its high voltage technology, the IC can be
directly connected to the high voltage dc rail.
MARKING DIAGRAM
8
1219XZ
ALYW
G
1
Features
• Fixed−Frequency Current−Mode Operation with Ramp
Compensation (65 kHz and 100 kHz Options)
• Dynamic Self Supply Eliminates the Need for an Auxiliary Winding
• Timer−Based Fault Protection for Improved Overload Detection
• Cycle Skip Reduces Input Power in Standby Mode
• Latch and Auto−Recovery Overload Protection Options
• Internal High Voltage Startup Circuit
1219 = Specific Device Code
X
= Overcurrent
= (A = latch, B = auto−retry)
Z
= Frequency
= (6 = 65 kHz, 1 = 100 kHz)
= Assembly Location
= Wafer Lot
A
L
Y
W
G
= Year
= Work Week
= Pb−Free Package
• Accurate Current Limit Detector ( 5%)
• Adjustable Skip Level
• Latch Input for Easy Implementation of Overvoltage and
PIN CONNECTIONS
Overtemperature Protection
1
Skip/latch
FB
HV
• Frequency Modulation for Softened EMI Signature
• 500 mA/800 mA Peak Source/Sink Current Drive Capability
• Pin to Pin Compatible with the Existing NCP12XX Series
• These Devices are Pb−Free and Halogen Free/BFR Free*
V
CC
CS
Drv
GND
(Top View)
Typical Applications
• AC−DC Adapters for Notebooks, LCD Monitors
• Offline Battery Chargers
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
• Consumer Electronic Appliances STB, DVD, DVDR
*For additional information on our Pb−Free strategy and soldering details, please
downloadthe ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
October, 2009 − Rev. 3
NCP1219/D
NCP1219
+
EMI
Filter
Output
Voltage
AC
Input
−
latch input*
HV
Skip/latch
FB
CS
V
CC
GND
* Optional
DRV
NCP1219
R
ramp
*
Figure 1. Typical Application Circuit
http://onsemi.com
2
NCP1219
Latched overload
I
I
when V > V
CC inhibit
start
2 V
(Option A)
when V < V
inhibit
CC
inhibit
R
42.0k*
latch−off, reset when
upper
V
latch
V
< V
CC
CC(reset)
R
S
HV
Skip/latch
*
-
50 ms
filter
R
+
Q
Q
S
R
lower
R
skip
51.3k*
(Option A)
+
-
V
Skip
V
Skip(max)
Skip
Comparator
V
CC(on)
V
V
FB(open)
Skip/latch
-
TSD
+
-
+
16.7k*
V
FB
FB
Normal = V
CC(min)
75 ms*
filter
soft−
start
set
Fault = V
CC(hiccup)
Soft−Start/PWM Clamp
V
FB
/ 3
−
V
ILIM
+
time
t
SSTART
V
CC(reset)
clamp
detect
tOVLD
timer
UVLO
V
CC
reset
+
-
V
DD
I
ramp(peak)
PWM
-
0
Fault
+
CS
I
Management
ramp
Double Hiccup
Counter
R
ramp
V
CS
LEB
CS
disable
internal
bias
R
CS
Maximum
Duty Ratio
detect
V
CC
DRV
Q
R
Oscillator
S
GND
7.5%* Jittering
* Typical values are shown
Figure 2. Functional Block Diagram
http://onsemi.com
3
NCP1219
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Description
1
Skip/latch
This pin provides a latch input to permanently disable the device under a fault condition. It also allows the user to
adjust the skip threshold. A resistor between this pin and GND provides noise immunity to the latch input and sets
the skip threshold. The voltage on this pin is determined by the combination of the internal voltage divider and the
external resistor to ground. The default skip threshold is 1.1 V (typical) if no external resistor is used. An internal
clamp prevents the skip level from increasing above 1.3 V if the Skip/latch pin is pulled high to latch the controller.
2
3
FB
CS
The voltage on this pin is proportional to the output load on the converter. An internal resistor divider sets the
voltage on this pin above the regulation threshold (3 V) and an external optocoupler pulls the pin low to achieve
regulation. While the FB voltage is above its regulation threshold, the overload timer is enabled. If the overload
timer expires, the controller enters a double hiccup mode (option B) or is latched (option A) depending on the ver-
sion of the device. The converter enters skip mode if the FB voltage is below the skip threshold.
A voltage ramp proportional to the primary current is applied to this pin. The maximum current is reached once the
ramp voltage reaches 1 V (typical). A 100 mA (typical) current source provides ramp compensation. The amount of
ramp compensation is adjusted with a series resistor between the CS pin and the current sense resistor.
4
5
GND
DRV
Analog ground.
Main output of the PWM Controller. DRV has a source resistance of 12.6 W (typical) and a sink resistance of 6.7 W
(typical).
6
VCC
Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source
supplies current from the HV pin to this pin. Once the V voltage reaches V
(12.7 V typical), the current
CC
CC(on)
CC
source turns off and the DRV is enabled. The current source turns on once V falls to V
(9.9 V typical).
CC(min)
This mode of operation is known as dynamic self supply (DSS).
If the bias current consumption exceeds the startup current, and V drops 0.5 V (typical) below V
the con-
CC
CC(min)
verter turns off and enters a double hiccup mode. If the V voltage is below 0.67 V (typical) the startup current is
CC
reduced to 200 mA (typical), reducing power dissipation.
8
HV
This is the input of the high voltage startup regulator and connects directly to the bulk voltage. A controlled current
source supplies current from this pin to the V capacitor, eliminating the need for an external startup resistor. The
CC
charge current is 12.8 mA (typical).
http://onsemi.com
4
NCP1219
Table 2. MAXIMUM RATINGS (Notes 1 − 4)
Rating
Symbol
Value
−0.3 to 500
100
Unit
V
HV Voltage
V
HV
HV
HV Current
I
mA
V
Supply Voltage
V
−0.3 to 20
100
CC
CC
Supply Current
I
mA
V
Skip/latch Voltage
Skip/latch Current
FB Voltage
V
−0.3 to 9.5
100
Skip/latch
Skip/latch
I
mA
V
V
−0.3 to 5.0
100
FB
FB
FB Current
I
mA
V
CS Voltage
V
−0.3 to 5.0
100
CS
CS
CS Current
I
mA
V
DRV Voltage
V
−0.3 to 20
−500 to 800
–40 to 150
–60 to 150
DRV
DRV
DRV Current
I
mA
°C
°C
W
Operating Junction Temperature
Storage Temperature Range
T
J
T
stg
Power Dissipation (T = 25°C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad)
P
D
A
D Suffix, Plastic Package Case 751U (SOIC−7) (Note 4)
0.92
Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad)
D Suffix, Plastic Package Case 751U (SOIC−7)
°C/W
Junction to Air, Low conductivity PCB (Note 3)
Junction to Lead, Low conductivity PCB (Note 3)
Junction to Air, High conductivity PCB (Note 4)
R
R
177
75
136
69
θ
JA
θ
JL
R
θ
JA
Junction to Lead, High conductivity PCB (Note 4)
R
θ
JL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1– 6: Human Body Model 3000 V per JEDEC JESD22−A114−F.
Pins 1– 6: Machine Model Method 300 V per JEDEC JESD22−A115−A.
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.
2. This device contains Latch−Up protection and exceeds 100 mA per JEDEC Standard JESD78.
2
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
2
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
http://onsemi.com
5
NCP1219
Table 3. ELECTRICAL CHARACTERISTICS (V = 60 V, V = 11.3 V, V = 2 V, V
= 0 V, V = 0 V, V
= open, C
=
HV
CC
FB
Skip/latch
CS
DRV
CC
0.1 mF, for typical values T = 25°C, for min/max values, T is –40°C to 125°C, unless otherwise noted)
J
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
V
Startup Threshold
V
Increasing
Decreasing
Decreasing
Decreasing
Decreasing
V
11.2
9.0
8.4
4.9
–
12.7
9.9
9.4
5.7
4.0
13.8
10.8
10.6
6.3
CC
CC(on)
Minimum Operating Voltage
Undervoltage Lockout
Double Hiccup Threshold
Logic Reset Voltage
V
CC
V
CC
V
CC
V
CC
V
CC(MIN)
UVLO
V
CC(hiccup)
V
–
CC(reset)
UVLO Filter Delay
t
–
0.35
100
–
50
0.67
200
20
–
ms
V
UVLO(delay)
Inhibit Threshold Voltage
Inhibit Bias Current
I
= 500 mA
V
0.90
350
28
inhibit
inhibit
inhibit
V
= 0 V
I
mA
V
CC
Minimum Startup Voltage
Startup Current
I
= 0.5 mA, V = V
– 0.5 V
V
start(min)
start
CC
CC(on)
V
= V
– 0.5 V
I
5.5
–
12.8
–
18.5
100
50
mA
mA
mA
V
CC
CC (on)
start
I
HV(reverse)
Startup Circuit Reverse Current
Off−State Leakage Current
Breakdown Voltage (Note 5)
V
= 0 V, V = 14 V
HV
CC
V
HV
= 500 V, V = 14 V
I
HV(off)
–
12
CC
I
= 50 mA
V
500
–
–
HV
BR(DS)
Supply Current
mA
Device Disabled/Fault
V
V
= 5.2 V, V = open
I
I
–
–
–
–
0.6
1.4
2.2
2.4
0.8
2.1
2.7
3.2
Skip/latch
FB
CC1
Device Enabled/No Switching
Device Switching (65 kHz)
Device Switching (100 kHz)
= open, V = 0 V
Skip/latch FB
CC2
V
V
= open, C
= 1000 pF
I
Skip/latch
DRV
CC3A
CC3B
= open, C
= 1000 pF
I
Skip/latch
DRV
CURRENT SENSE
Current Sense Voltage Threshold
Leading Edge Blanking Duration
Propagation Delay
Apply voltage step on CS pin
V
0.95
100
–
1.0
184
59
1.05
330
150
V
ILIM
t
ns
ns
LEB
V
> V
to 50% DRV turns off,
= 1000 pF
t
delay
CS
ILIM
C
DRV
Ramp Compensation Peak Current
Ramp Compensation Valley Current
FEEDBACK INPUT
I
–
–
100
0
–
–
mA
mA
ramp(peak)
I
ramp(valley)
Open Feedback Voltage
Internal Pull−up Resistance
Feedback Pull−up Current
Feedback to Current Set Point Ratio
SOFT−START
V
3.2
–
3.6
16.7
280
3.0
3.9
–
V
FB(open)
R
FB
kW
mA
V
FB
= 0 V
I
FB
141
–
392
–
I
ratio
Soft−Start Period
Measured at 0.9 V
t
–
4.8
–
ms
ILIM
SSTART
OSCILLATOR
Oscillator Frequency
65 kHz Option
f
kHz
OSC
T = 25_C
61.75
58
55
95
89
65
–
–
100
–
–
68.25
71
71
105
107
107
J
T = −40_C to 85_C
J
T = −40_C to 125_C
J
100 kHz Option
T = 25_C
J
T = −40_C to 85_C
J
T = −40_C to 125_C
85
J
Frequency Modulation in
–
7.5
–
%
Percentage of f
OSC
Frequency Modulation Period
Maximum Duty Ratio
–
6.0
80
–
ms
%
D
75
85
5. Guaranteed by the I
test.
HV(off)
6. Guaranteed by design only.
http://onsemi.com
6
NCP1219
Table 3. ELECTRICAL CHARACTERISTICS (V = 60 V, V = 11.3 V, V = 2 V, V
= 0 V, V = 0 V, V
= open, C
=
HV
CC
FB
Skip/latch
CS
DRV
CC
0.1 mF, for typical values T = 25°C, for min/max values, T is –40°C to 125°C, unless otherwise noted)
J
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
GATE DRIVE
Drive Resistance
DRV Sink
DRV Source
W
V
= 0 V, V
= 1 V
R
R
2.0
6.0
6.7
12.6
13
25
FB
V
DRV
SNK
= V – 1 V
DRV
CC
SRC
Rise Time (10% to 90%)
Fall Time (90% to 10%)
LATCH INPUT
C
C
= 1000 pF (10% to 90%)
= 1000 pF (90% to 10%)
t
t
–
–
30
20
–
–
ns
ns
DRV
r
DRV
f
Latch Voltage Threshold
Latch Filter Delay
V
3.4
–
3.9
50
4.6
–
V
latch
V
= 5.2 V, apply voltage step
on Skip/latch pin
t
ms
Skip/latch
latch(delay)
CYCLE SKIP
Default Skip Threshold
Skip Clamp Voltage
Skip Comparator Hysteresis
V
increasing, V
increasing, V
= Open
= 2.0 V
= 0.5 V
= 2.0 V
V
skip
0.9
1.1
–
1.1
1.3
75
1.3
1.5
–
V
V
FB
Skip/latch
V
V
FB
Skip/latch
skip(MAX)
skip(HYS1)
skip(HYS2)
V
FB
V
FB
decreasing, V
decreasing, V
V
V
mV
mV
Skip/latch
Skip Clamp Comparator
Hysteresis
–
75
–
Skip/latch
Skip Current
V
= 0 V
I
30
47
56
mA
Skip/latch
skip
FAULTS PROTECTION
Thermal Shutdown (Note 6)
Thermal Shutdown Hysteresis
Thermal Shutdown Delay
Overload Timer
Temperature Increasing
Temperature Decreasing
T
–
–
–
–
155
40
–
–
–
–
°C
°C
ms
SHDN
T
SHDN(HYS)
SHDN(delay)
T
75
Apply voltage step on FB pin
t
118
ms
OVLD
5. Guaranteed by the I
test.
HV(off)
6. Guaranteed by design only.
http://onsemi.com
7
NCP1219
TYPICAL CHARACTERISTICS
15
14
13
1.40
1.26
1.12
0.98
0.84
0.70
0.56
0.42
0.28
I
= 500 mA
inhibit
V
12
11
10
9
CC(on)
V
CC(MIN)
UVLO
8
7
V
CC(reset)
0.14
0
6
5
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. Supply Voltage Thresholds vs.
Junction Temperature
Figure 4. Inhibit Threshold Voltage vs.
Junction Temperature
300
280
260
240
220
200
180
160
140
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
V
= V
= 60 V
HV
V
CC
= 0 V
V
CC
− 0.5 V
CC(on)
120
100
10.5
10.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. Inhibit Current vs. Junction
Temperature
Figure 6. Startup Current vs. Junction
Temperature
30
16
14
12
10
8
V
HV
= 60 V
V
HV
V
CC
= 60 V
= 14 V
27
24
21
18
15
12
9
6
4
6
2
0
3
0
0
2
4
6
8
10 12 14
16 18 20
−50 −25
0
25
50
75
100 125 150
V , SUPPLY VOLTAGE (V)
CC
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Startup Current vs. Supply Voltage
Figure 8. Startup Circuit Leakage Current vs.
Junction Temperature
http://onsemi.com
8
NCP1219
TYPICAL CHARACTERISTICS
3.0
50
45
40
35
30
25
20
15
10
I
(f
~ 100 kHz)
~ 65 kHz)
CC3 OSC
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0.0
V
= 14 V
CC
I
(f
CC3 OSC
I
CC2
T = −40°C
J
I
CC1
T = 125°C
J
5
0
0
75
150
225
300
375
450
525
−50
−25
0
25
50
75
100 125 150
V , HV VOLTAGE (V)
HV
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Startup Circuit Leakage Current vs.
HV Voltage
Figure 10. Supply Current vs. Junction
Temperature
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
4.0
3.5
3.0
2.5
2.0
1.5
1.0
T = 25°C
J
f
= 100 kHz
OSC
f
= 65 kHz
OSC
0.5
0
9
10 11 12 13 14 15 16 17 18 19 20 21
, SUPPLY VOLTAGE (V)
−50 −25
0
25
50
75
100 125 150
V
CC
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Operating Supply Current vs.
Supply Voltage
Figure 12. Current Sense Voltage Threshold
vs. Junction Temperature
300
280
260
240
220
200
180
160
140
125
115
105
95
85
75
65
55
45
120
100
35
25
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. Leading Edge Blanking Time vs.
Junction Temperature
Figure 14. Current Sense Propagation Delay
vs. Junction Temperature
http://onsemi.com
9
NCP1219
TYPICAL CHARACTERISTICS
120
110
100
90
85
84
83
82
81
80
79
100 kHz Option
80
65 kHz Option
70
78
77
76
75
60
50
40
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. Oscillator Frequency vs. Junction
Temperature
Figure 16. Maximum Duty Ratio vs. Junction
Temperature
20
18
5.0
V
CC
= 11.3 V
4.8
4.6
4.4
4.2
4.0
16
14
12
10
8
Source, V
= V − 1 V
CC
DRV
3.8
3.6
3.4
6
4
Sink, V
= 1 V
DRV
2
0
3.2
3.0
−50 −25
0
25
50
75
100 125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 17. Drive Sink and Source Resistances
vs. Junction Temperature
Figure 18. Latch Voltage Threshold vs.
Junction Temperature
1.55
1.50
1.30
1.25
1.20
1.15
1.10
1.05
1.00
V
= open
Skip/latch
V
= 2 V
Skip/latch
1.45
1.40
1.35
1.30
1.25
0.95
0.90
0.85
1.20
1.15
1.10
1.05
0.80
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 19. Default Skip Threshold vs. Junction
Temperature
Figure 20. Skip Clamp Voltage vs. Junction
Temperature
http://onsemi.com
10
NCP1219
TYPICAL CHARACTERISTICS
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
1.2
R
skip
= 48.7 kW
1.0
0.8
0.6
0.4
0.2
0
0.3
0.2
−50 −25
0
25
50
75
100
125 150
1
10
, EXTERNAL SKIP RESISTOR (kW)
Skip
100
1000
10000
T , JUNCTION TEMPERATURE (°C)
J
R
Figure 21. Adjustable Skip Threshold vs.
Junction Temperature
Figure 22. Skip Threshold vs. Skip Resistor
140
135
10
9
130
125
120
115
110
8
7
6
5
4
105
3
100
95
2
1
0
90
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 23. Soft−Start Period vs. Junction
Figure 24. Overload Timer Period vs. Junction
Temperature
Temperature
http://onsemi.com
11
NCP1219
DETAILED OPERATING DESCRIPTION
The NCP1219 is part of a product family of current mode
supply current consumption exceeds the startup current,
V will decay below V . The NCP1219 has an
CC
controllers designed for ac−dc applications requiring low
standby power. The controller operates in skip or burst
mode at light load. Its high integration reduces component
count resulting in a more compact and lower cost power
supply. This device family has 2 options, A and B. Option
A latches where as option B auto restarts after an overload
fault.
CC(MIN)
undervoltage lockout (UVLO) to prevent operation at low
levels. The UVLO threshold is typically 9.4 V. The
V
CC
DRV signal is immediately disabled upon reaching UVLO.
It is re−enabled if V increases above UVLO before the
CC
50 ms (typical) timer expires. Otherwise, the controller
enters double hiccup mode.
The internal high voltage startup circuit with dynamic
self supply (DSS) allows the controller to operate without
an auxiliary supply, simplifying the transformer design.
This feature is particularly useful in applications where the
output voltage varies during operation (e.g. printer
adapters).
Other features found in the NCP1219 are frequency
jittering, adjustable ramp compensation, timer based fault
detection and a dedicated latch input.
The controller enters a double hiccup mode if an
overload (option B), thermal shutdown, UVLO or latch
fault is detected. A double hiccup fault disables the DRV
signal, sets the controller in a low current mode and allows
V
CC
to discharge to V , typically 5.7 V. This cycle
CC(hiccup)
is repeated twice to minimize power dissipation in external
components during a fault event. Figures 25 and 26 show
double hiccup mode operation with a fault occurring while
the startup circuit is disabled and enabled, respectively. A
soft−start sequence is initiated the second time V reaches
CC
High Voltage Startup Circuit
V . If the fault is present or the controller is latched
CC(on)
The NCP1219 internal high voltage startup circuit
eliminates the need for external startup components and
provides a faster startup time compared to an external
startup resistor. The startup circuit consists of a constant
current source that supplies current from the HV pin to the
upon reaching V , the controller stays in hiccup mode.
CC(on)
During this mode, V
never drops below 4 V, the
CC
controller logic reset level. This prevents latched faults
from being cleared unless power to the controller is
completely removed (i.e. unplugging the supply from the
AC line). There are two options available in the NCP1219,
options A and B. Option A latches off after the overload
timer expires if an overload fault is detected. In this case,
supply capacitor on the V pin (C ). The HV pin is rated
CC
CC
at 500 V allowing direct connection to the bulk capacitor.
The start−up current (I ) is typically 12.8 mA.
start
The startup current source is disabled once the V
CC
V
CC
cycles between V
and V
without
CC(on)
CC(hiccup)
voltage reaches V , typically 12.7 V. The controller is
CC(on)
enabling the DRV signal until the power to the controller
is reset. On the other hand, option B has auto−retry circuitry
allowing the DRV signal to restart after a double hiccup
sequence triggered by an overload condition.
then biased by the V capacitor. The current source is
CC
enabled once the V
voltage decays to its minimum
CC
operating threshold (V
) typically 9.9 V. If the
CC(MIN)
V
CC(on)
V
CC(MIN)
UVLO
V
CC(hiccup)
V
CC(reset)
Fault1
Fault
DRV
ON
OFF
ON
Figure 25. VCC Double Hiccup Operation with a Fault Occurring While the Startup Circuit is Disabled.
http://onsemi.com
12
NCP1219
V
CC(on)
V
CC(MIN)
UVLO
V
CC(hiccup)
V
CC(reset)
Fault2
Fault
ON
OFF
ON
DRV
Figure 26. VCC Double Hiccup Operation with a Fault Occurring While the Startup Circuit is Enabled
An internal supervisory circuit monitors the V voltage
to prevent the controller from dissipating excessive power
In comparison, the power dissipation when the startup
circuit is disabled and V is being supplied by the
CC
CC
if the V
pin is accidentally grounded. A lower level
auxiliary winding is a function of the V voltage. This is
CC
CC
current source (I
) charges C from 0 V to V ,
shown in Equation 2.
inhibit
CC
inhibit
typically 0.67 V. Once V exceeds V
current source is enabled. This behavior is illustrated in
Figure 27. This slightly increases the total time to charge
, the startup
CC
inhibit
PAUX + ICC3 @ VCC
(eq. 2)
It is recommended that an external filter capacitor be
placed as close as possible to the V pin to improve the
CC
V , but it is generally not noticeable.
CC
noise immunity.
Startup Current
Soft−Start Operation
Figures 28 and 29 show how the soft−start feature is
included in the pulse−width modulation (PWM)
comparator. When the NCP1219 starts up, a soft−start
I
start
voltage V
begins at 0 V. V
increases
SSTART
SSTART
gradually from 0 V to 1.0 V in 4.8 ms and stays at 1.0 V
afterward. V is compared with the divided by 3
SSTART
feedback pin voltage (V /3). The lesser of V
and
FB
SSTART
(V /3) becomes the modulation voltage, V
, in the
PWM
V
CC
I
FB
inhibit
PWM duty ratio generation. Initially, (V /3) is above
FB
FB(open)
V
V
V
CC(on)
inhibit
CC(MIN)
1.0 V because the FB pin is brought to V
, typically
is
3.6 V, by the internal pullup resistor. As a result, V
PWM
Figure 27. Startup Current at Various VCC Levels
limited by the soft−start function and slowly ramps up the
duty ratio (and therefore the primary current) for the initial
4.8 ms. This provides a greatly reduced stress on the power
devices during startup.
The start−up circuit is rated at a maximum voltage of
500 V. If the device operates in the DSS mode, power
dissipation should be controlled to avoid exceeding the
maximum power dissipation of the controller. If dissipation
on the controller is excessive, a resistor can be placed in
series with the HV pin. This will reduce power dissipation
on the controller and transfer it to the series resistor.
Standby mode losses and normal mode power dissipation
can be reduced by biasing the controller with an auxiliary
V
−
)
SSTART
V /3
FB
0
1
winding. The auxiliary winding needs to maintain V
CC
above V
once the startup circuit is disabled.
V
PWM
CC(MIN)
The power dissipation of the controller when operated in
DSS mode, P , can be calculated using equation 1, where
Figure 28. VPWM is the lesser of VSSTART and (VFB/3)
DSS
I
is the operating current of the NCP1219 during
CC3
switching and V is the voltage at the HV pin. The HV pin
HV
is most often connected to the bulk capacitor.
PDSS + ICC3 @ (VHV * VCC
)
(eq. 1)
http://onsemi.com
13
NCP1219
Soft−start voltage, V
V
bulk
SSTART
I
ramp(peak)
I
ramp
1 V
V
CS
+
180 ns
LEB
time
PWM
Output
−
R
S
Q
t
CS
I
D
SSTART
80%
V
PWM
max duty
Feedback pin voltage divided by 3, V /3
(1 V max. signal)
FB
Clock
R
CS
1 V
Figure 30. Current−Mode Implementation
Figure 31 shows the timing diagram for the
current−mode pulse width modulation operation. An
internal clock sets the output RS latch, pulling the DRV pin
high. The latch is then reset when the voltage on the CS pin
time
time must be less than t
OVLD
to prevent fault condition
Pulse Width Modulation voltage, V
PWM
intersects the modulation voltage, V . This generates
PWM
the duty ratio of the DRV pulse. The maximum duty ratio
is internally limited to 80% (typical) by the output RS latch.
1 V
PWM
Output
time
t
SSTART
Drain Current, I
D
V
PWM
time
V
CS
t
SSTART
Figure 29. Soft−Start (Time = 0 at VCC = VCC(on)
)
clock
Current−Mode Pulse Width Modulation
The NCP1219 is a current−mode, fixed frequency pulse
width modulation controller with ramp compensation. The
PWM block of the NCP1219 is shown in Figure 30. The
DRV signal is enabled by a clock pulse. At this time,
current begins to flow in the power MOSFET and the sense
resistor. A corresponding voltage is generated on the CS
pin of the device, ranging from very low to as high as the
Figure 31. Current−Mode Timing Diagram
The V
voltage is the scaled representation of the FB
PWM
pin voltage. The scale factor, I , is 3. The FB pin voltage
ratio
is provided by an external error amplifier, whose output is
a function of the power supply output. An FB signal
between V
and 3 V determines the duty ratio of the
skip
controller output. The FB voltage operates in a closed loop
with the output voltage to regulate the power supply.
It is recommended that an external filter capacitor be
placed as close to the FB pin as possible to improve the
noise immunity.
maximum modulation voltage, V
(maximum of 1 V).
PWM
This sets the primary current on a cycle−by−cycle basis.
Equation 3 gives the maximum drain current, I
,
D(MAX)
where R is the current sense resistor value and V
is
CS
ILIM
the current sense voltage threshold.
VILIM
RCS
ID(MAX)
+
(eq. 3)
http://onsemi.com
14
NCP1219
Ramp Compensation
ǒ
Ǔ@ %slope
Soff,primary RCS
Ramp compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
continuous conduction mode (CCM) with a duty ratio
greater than 50%. To lower the current loop gain, one
usually injects 50 to 75% of the inductor current down
slope. The NCP1219 generates an internal current ramp
that is synchronized with the clock. This current ramp is
then routed to the CS pin. Figures 32 and 33 depict how the
ramp is generated and utilized. Ramp compensation is
Rramp
+
(eq. 5)
I
f
ramp(peak) OSC
D
ǒ
Ǔ
where R is the current sense resistor and %slope is the
percentage of the current downslope to be used for ramp
compensation.
The NCP1219 has a peak ramp compensation current of
100 mA. A frequency of 65 kHz with an 80% maximum
duty ratio corresponds to an 8.1 mA/ms ramp. For a typical
flyback design, let’s assume that the primary inductance is
CS
simply formed by placing a resistor, R
, between the CS
ramp
350 mH, the converter output is 19 V, the V of the output
pin and the sense resistor.
f
diode is 1 V and the N :N ratio is 10:1. The off time
primary current slope is given by Equation 6.
P
S
Ramp current, I
ramp
N
P
) V )ǒ Ǔ
(Vout
I
f
ramp(peak)
N
S
mA
+ 571
(eq. 6)
ms
LP
When projected over an R of 0.1 W (for example), this
CS
becomes 57 mV/ms. If we select 50% of the downslope as
the required amount of ramp compensation, then we shall
time
0
80% of period
100% of period
inject 28.5 mV/ms. Therefore, R
is simply equal to
ramp
Equation 7.
Figure 32. Internal Ramp Compensation Current
Source
mV
28.5
ms
Rramp
+
+ 3.5 kW
(eq. 7)
mA
8.1
ms
Ramp compensation greater than 50% of the inductor
down slope can be used if necessary; however,
overcompensating will degrade the transient response of
the system. The addition of ramp compensation also
reduces the total available output power of the system.
DRV
Clock
I
ramp(peak)
Internal Oscillator
Current
Ramp
R
ramp
The internal oscillator of the NCP1219 provides the
clock signal that sets the DRV signal high and limits the
duty ratio to 80% (typical). The oscillator has a fixed
frequency of 65 kHz or 100 kHz. The NCP1219 employs
frequency jittering to smooth the EMI signature of the
system by spreading the energy of the main switching
component across a range of frequencies. An internal low
frequency oscillator continuously varies the switching
frequency of the controller by 7.5%. The period of
modulation is 6 ms, typical. Figure 34 illustrates the
oscillator frequency modulation.
CS
Oscillator
R
CS
Figure 33. Inserting a Resistor in Series with the
Current Sense Information Provides Ramp
Compensation
In order to calculate the value of the ramp compensation
resistor, R
, the off time primary current slope,
must be calculated using Equation 4,
ramp
S
off,primary
N
P
) V ) @ ǒ Ǔ
(Vout
f
N
S
Soff,primary
+
(eq. 4)
LP
where V is the converter output voltage, V is the forward
out
f
diode drop of the secondary diode, N /N is the primary to
P
S
secondary turns ratio, and L is the primary inductance of
P
the transformer. The value of R
Equation 5,
can be calculated using
ramp
http://onsemi.com
15
NCP1219
Oscillator Frequency
Startup current source is
is V
Startup current source is
charging the V capacitor
off when V
CC
CC
CC(on)
VCC(on)
FOSC + 7.5%
FOSC
FOSC − 7.5%
VCC(hiccup)
time
6 ms
Startup current source turns
on when V reaches V
CC
CC(hiccup)
time
Figure 35. Latch−off VCC Timing Diagram
The external latch feature allows the circuit designers to
implement different kinds of latching protection. Figure 36
shows an example circuit in which a bipolar transistor is
used to pull the Skip/latch pin above the latch threshold.
Figure 34. Oscillator Frequency Modulation
Gate Drive
The output drive of the NCP1219 is designed to directly
drive the gate of an n−channel power MOSFET. The DRV
pin is capable of sourcing 500 mA and sinking 800 mA of
drive current. It has typical rise and fall times of 30 ns and
20 ns, respectively, driving a 1 nF capacitive load.
The power dissipation of the output stage while driving
the capacitance of the power MOSFET must be considered
when calculating the NCP1219 power dissipation. The
driver power dissipation can be calculated using
Equation 8,
The R
value is chosen to prevent the Skip/latch pin from
LIM
exceeding the maximum rated voltage. The NCP1219
applications note (AND8393/D) details several simple
circuits to implement overtemperature protection (OTP)
and overvoltage protection (OVP).
V
CC
R
LIM
PDRV + fOSC @ QG @ VCC
(eq. 8)
Fault
output
where Q is the gate charge of the power MOSFET.
G
Skip/latch
FB
External Latch Input
HV
Board level protection functionality is often
incorporated using external circuits to suit a specific
application. An external fault condition can be used to
disable the controller by bringing the voltage on the
Skip/latch pin above the latch threshold, V
typical). When an external fault condition is detected, the
DRV signal is stopped, and the controller enters low current
C
skip
R
skip
CS
VCC
DRV
(3.9 V
latch
GND
NCP1219
operation mode. The external capacitor C
discharges
CC
Figure 36. Circuit Example of an External
and V
drops until V
is reached. The high
CC
CC(hiccup)
Latch−off Circuit
voltage startup circuit turns on and I
charges C until
CC
start
An internal blanking filter prevents fast voltage spikes
caused by noise from latching the part. However, it is
recommended that an external filter capacitor be placed as
close as possible to the Skip/latch pin to further improve the
noise immunity.
V
V
is reached. V
cycles between V
and
CC(on)
CC
CC(on)
until V reaches V . Voltage must be
CC(hiccup)
CC
CC(reset)
removed from the HV pin, disabling the startup current and
allowing C to discharge to V . Therefore, the
CC
CC(reset)
controller is reset by unplugging the power supply from the
wall to allow V to discharge. Figure 35 illustrates the
bulk
timing diagram of V in the latch−off condition.
CC
http://onsemi.com
16
NCP1219
Skip Cycle Operation
Skip peak current, %I , is the percentage of the
CSSKIP
During standby or light load operation the duty ratio on
the controller becomes very small. At this point, a
significant portion of the power dissipation is related to the
power MOSFET switching on and off. To reduce this power
dissipation, the NCP1219 “skips” pulses when the FB level
drops below the skip threshold. The level at which this
occurs is completely adjustable by setting a resistor on the
Skip/latch pin.
maximum peak current at which the controller enters skip
mode. %I can be any value from 0 to 43% as defined
CSSKIP
by Equation 9. However, the higher %I
is, the greater
CSSKIP
the drain current when skip is entered. This increases
acoustic noise. Conversely, the lower %I is, the
CSSKIP
larger the percentage of energy is expended turning the
switch on and off. Therefore, it is important to adjust
%I
to the optimal level for a given application.
CSSKIP
By discontinuing pulses, the output voltage slowly drops
and the FB voltage rises. When the FB voltage rises above
V
skip
%ICSSKIP
+
@ 100
(eq. 9)
3 V
the V
level, DRV is turned back on. This feature
skip
Figure 38 shows the details of the Skip/latch pin
circuitry. The voltage on the Skip/latch pin determines the
voltage required on the FB pin to place the controller into
skip mode. If the pin is left open, the default skip threshold
produces the timing diagram shown in Figure 37.
V
skip
V
FB
is 1.1 V. This corresponds to a 37% %I
(%I
=
CSSKIP
CSSKIP
Skip
1.1 V / 3.0 V * 100% = 37%). Therefore, the controller will
enter skip mode when the peak current is less than 37% of
the maximum peak current.
I
D
Figure 37. Skip Operation
latch-off, reset
< V
2 V
when V
CC
CC(reset)
R
Vlatch
upper
42.0 k
Skip/latch
-
50 us
filter
S
+
+
R Q
R
lower
51.3 k
V
R
skip
C
skip
Skip/latch
VSkip
-
Vskip(MAX)
Vskip/Latch
+
V
-
FB
Skip
Comparator
To DRV
latch
reset
Figure 38. Skip Adjust Circuit
The skip level is reduced by placing an external resistor,
, between the Skip/latch and GND pins. Figure 39
R
skip
summarizes the operating voltage regions of the Skip/latch
pin.
http://onsemi.com
17
NCP1219
V
skip/latch
Within the adjustable V
range, the skip level changes
skip
according to Equation 10.
9.5 V (maximum pin voltage)
2 V @ (Rlower ø Rskip
)
Vskip
+
(eq. 10)
(Rlower ø Rskip) ) Rupper
Controller is latched
An internal clamp limits the skip threshold (V
)
skip(MAX)
to 1.3 V. Increasing the voltage on the Skip/latch pin
beyond the value of the internal clamp will induce no
further change in the skip level. This prevents the act of
disabling the controller in the presence of an external latch
event from causing it to enter skip mode. The relationship
V
latch
Skip threshold clamped to Vskip(MAX)
Vskip(MAX)(maximum skip threshold)
Adjustable Vskip range.
0 V (no skip)
between %I
,
V
,
V
,
and
R
skip
is
CSSKIP
Skip/latch
skip
summarized in Table 4.
Figure 39. NCP1219 VSkip/latch Pin Operating
Regions
Table 4. %ICSskip and Skip Threshold Relationship with Rskip
%ICS
V
V
skip
R
skip
Comment
skip
Skip/latch
0%
12%
25%
37%
43%
43 %
0 V
0 V
0 W
11.8 kW
52.3 kW
Open
–
Never skips
0.36 V
0.75 V
1.10 V
2.00 V
3.00 V
0.36 V
0.75 V
1.10 V
1.30 V
1.30 V
–
–
Default Skip Threshold
No further increase in Skip threshold
No further increase in Skip threshold
–
External Non−Latched Shutdown
Figure 40 summarizes the operating regions of the FB
pin. An external non−latched shutdown can be easily
implemented by simply pulling FB below the skip level.
This is an inherent feature of the standby skip operation,
allowing additional flexibility in the SMPS design.
Skip/latch
HV
FB
VCC
DRV
CS
OFF
GND
NCP1219
opto
coupler
V
FB
Fault operation when staying
in this region longer than 118 ms
3 V
Figure 41. Example Circuit for Non−Latched
Shutdown
PWM operation
Overload Protection
Figure 42 details the timer based fault detection circuitry.
When an overload (or short circuit) event occurs, the output
voltage collapses and the optocoupler does not conduct
V
skip
0 V
No DRV pulses
current. This opens the FB pin and V is internally pulled
FB
higher than 3.0 V. Since V /3 is greater than 1 V, the
FB
Figure 40. NCP1219 Operation Threshold
Figure 41 shows an example implementation of a
non−latched shutdown circuit using a bipolar transistor to
pull the FB pin low.
controller activates an error flag and starts a timer, t
OVLD
(118 ms typical). If the output recovers during this time, the
timer is reset and the device continues to operate normally.
http://onsemi.com
18
NCP1219
However, if the fault lasts for more than 118 ms, then the
The NCP1219 also has an internal temperature shutdown
circuit. If the junction temperature of the controller reaches
155°C (typical), the driver turns off and the controller
enters double hiccup mode.
driver turns off and the device enters the V double hiccup
CC
mode described earlier.
4.8 V
Latched and Auto−Retry Options
The NCP1219A offers a latched fault circuitry. An
overload fault condition detected by the controller results
in a latch−off shutdown, requiring the controller to be reset
V
FB
FB
by cycling V (removing the ac line input). NCP1219B
CC
V
FB
3
provides an auto−retry circuit. All fault conditions except
the external latch fault result in the controller entering
double hiccup mode, attempting to restart the controller
Fault
+
−
118 ms
delay
disable Drv
V
SS
Soft−start
1 V max
every other V cycle, as mentioned earlier.
CC
Figure 42. Block Diagram of Timer−Based Fault
Detection
Table 5. ORDERING INFORMATION
†
Device
Overcurrent
Frequency
Package
Shipping
NCP1219AD65R2G
NCP1219BD65R2G
NCP1219AD100R2G
NCP1219BD100R2G
Latch
65 kHz
65 kHz
Auto−Recovery
Latch
SOIC−7 (Pb−Free)
2500 / Tape & Reel
100 kHz
100 kHz
Auto−Recovery
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
19
NCP1219
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE D
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
S
M
M
B
−B−
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
C
R X 45
_
1.27 BSC
J
0.10
0.19
0.40
0
−T−
SEATING
PLANE
K
8
0
8
_
_
_
_
M
H
D 7 PL
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
M
S
S
0.25 (0.010)
T
B
A
The products described herein (NCP1219) may be covered by one or more of the following U.S. patents: 6,271,735, 6,362,067, 6,385,060,
6,597,221, 6,633,193, 6,587,351, 6,940,320. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your loca
Sales Representative
NCP1219/D
相关型号：
©2020 ICPDF网 联系我们和版权申明