NCP1230P100G [ONSEMI]
Low−Standby Power High Performance PWM Controller; 低待机功耗高性能PWM控制器
| 型号： | NCP1230P100G |
| 厂家： | 
ONSEMI |
| 描述： | Low−Standby Power High Performance PWM Controller |
| 文件： | 总21页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1230
Low−Standby Power High
Performance PWM
Controller
The NCP1230 represents a major leap towards achieving low
standby power in medium−to−high power Switched−Mode Power
Supplies such as notebook adapters, off−line battery chargers and
consumer electronics equipment. Housed in a compact 8−pin package
(SOIC−8, SOIC−7, or PDIP−7), the NCP1230 contains all needed
control functionality to build a rugged and efficient power supply. The
NCP1230 is a current mode controller with internal ramp
compensation. Among the unique features offered by the NCP1230 is
an event management scheme that can disable the front−end PFC
circuit during standby, thus reducing the no load power consumption.
The NCP1230 itself goes into cycle skipping at light loads while
limiting peak current (to 25% of nominal peak) so that no acoustic
noise is generated. The NCP1230 has a high−voltage startup circuit
that eliminates external components and reduces power consumption.
The NCP1230 also features an internal latching function that can be
used for OVP protection. This latch is triggered by pulling the CS pin
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MARKING
DIAGRAM
8
SOIC−8 VHVIC
D SUFFIX
CASE 751
230Dy
ALYWy
G
8
1
1
8
1
SOIC−7
D1 SUFFIX
CASE 751U
8
30D16
ALYWG
G
1
above 3.0 V and can only be reset by pulling V to ground. True
CC
overload protection, internal 2.5 ms soft−start, internal leading edge
blanking, internal frequency dithering for low EMI are some of the
other important features offered by the NCP1230.
1230Pxxx
AWL
YYWWG
PDIP−7 VHVIC
P SUFFIX
CASE 626B
Features
8
1
• Current−Mode Operation with Internal Ramp Compensation
• Internal High−Voltage Startup Current Source for Loss−Less Startup
• Extremely Low No−Load Standby Power
• Skip−Cycle Capability at Low Peak Currents
• Direct Connection to PFC Controller for Improved No−Load Standby
Power
1
xxx
y
y
A
L
= Device Code: 65, 100, 133
= Device Code: 6, 1, 1
= Device Code: 5, 0, 3
= Assembly Location
= Wafer Lot
Y, YY
= Year
• Internal 2.5 ms Soft−Start
• Internal Leading Edge Blanking
W, WW = Work Week
G
= Pb−Free Package
= Pb−Free Package
G
• Latched Primary Overcurrent and Overvoltage Protection
• Short−Circuit Protection Independent of Auxiliary Level
• Internal Frequency Jittering for Improved EMI Signature
• +500 mA/−800 mA Peak Current Drive Capability
• Available in Three Frequency Options: 65 kHz, 100 kHz, and 133 kHz
• Direct Optocoupler Connection
(Note: Microdot may be in either location)
PIN CONNECTIONS
1
8
PFC Vcc
FB
HV
• SPICE Models Available for TRANsient and AC Analysis
• Pb−Free Packages are Available
CS
GND
V
CC
DRV
Typical Applications
• High Power AC−DC Adapters for Notebooks, etc.
• Offline Battery Chargers
• Set−Top Boxes Power Supplies, TV, Monitors, etc.
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 8
NCP1230/D
NCP1230
HV
+
V
out
PFC_V
CC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
OVP
OVP
GN-
D
+
CBulk
NCP1230
MC33262/33260
Ramp Comp
10 k
Rsense
V
CC
Cap
GND
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Pin Description
This pin is a direct connection to the V pin (Pin 6) via a low impedance switch. In
1
PFC V
This pin provides
the bias voltage to
CC
CC
standby and during the startup sequence, the switch is open and the PFC V is
CC
the PFC controller. shut down. As soon as the aux. winding is stabilized, Pin 1 connects to the V pin
CC
and provides bias to the PFC controller. It goes down in standby and fault conditions.
2
3
FB
Feedback Signal
Current Sense
An optocoupler collector pulls this pin low to regulate. When the current setpoint
reaches 25% of the maximum peak, the controller skips cycles.
CS/OVP
This pin incorporates three different functions: the current sense function, an internal
ramp compensation signal and a 3.0 V latch−off level which latches the output off
until V is recycled.
CC
4
5
GND
DRV
IC Ground
−
Driver Output
With a drive capability of +500 mA / −800 mA, the NCP1230 can drive large Qg
MOSFETs.
6
V
CC
V
CC
Input
The controller accepts voltages up to 18 V and features a UVLO turn−off threshold of
7.7 V typical.
7
8
NC
HV
−
−
High−Voltage
This pin connects to the bulk voltage and offers a lossless startup sequence. The
charging current is high enough to support the bias needs of a PWM controller
through Pin 1.
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2
NCP1230
+
+
+
+
+
+
Figure 2. Internal Circuit Architecture
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3
NCP1230
MAXIMUM RATINGS (Notes 1 and 2)
Rating
Symbol
Value
Unit
Maximum Voltage on Pin 8
Maximum Current
V
−0.3 to 500
V
mA
DS
C2
I
100
Power Supply Voltage, Pin 6
Current
V
CC2
−0.3 to 18
V
mA
CC
I
100
Drive Output Voltage, Pin 5
Drive Current
V
V
18
V
A
DV
o
I
1.0
Voltage Current Sense Pin, Pin 3
Current
10
100
V
mA
cs
cs
I
Voltage Feedback, Pin 2
Current
V
fb
10
100
V
mA
fb
I
Voltage, Pin 1
V
18
35
V
PFC
PFC
Maximum Continuous Current Flowing from Pin 1
Thermal Resistance, Junction−to−Air, PDIP Version
Thermal Resistance, Junction−to−Air, SOIC Version
I
mA
R
R
100
178
°C/W
°C/W
W
ꢀ
ꢀ
JA
JA
Maximum Power Dissipation @ T = 25°C
PDIP
SOIC
P
1.25
0.702
A
max
Maximum Junction Temperature
Storage Temperature Range
T
150
°C
°C
J
T
stg
−60 to +150
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−6: Human Body Model 2000 V per Mil−Std−883, Method 3015.
Machine Model Method 200 V
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
ORDERING INFORMATION
†
Device
Package
Shipping
NCP1230D165R2G
SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1230D65R2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
NCP1230D65R2G
SOIC−8
(Pb−Free)
NCP1230D100R2
NCP1230D100R2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
NCP1230D133R2
NCP1230D133R2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
NCP1230P65
PDIP−7
50 Units/ Rail
50 Units/ Rail
NCP1230P65G
PDIP−7
(Pb−Free)
NCP1230P100
PDIP−7
50 Units/ Rail
50 Units/ Rail
NCP1230P100G
PDIP−7
(Pb−Free)
NCP1230P133
PDIP−7
50 Units/ Rail
50 Units/ Rail
NCP1230P133G
PDIP−7
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NCP1230
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C,
J
J
J
V
CC
= 13 V, V
= 30 V unless otherwise noted.)
PIN8
Characteristic
Symbol
Pin
Min
Typ
Max
Unit
Supply Section (All frequency versions, otherwise noted)
Turn−On Threshold Level, V Going Up (V = 2.0 V)
V
6
6
6
6
6
6
11.6
7.0
5.0
−
12.6
7.7
5.6
4.0
1.1
1.8
13.6
8.4
6.2
−
V
V
CC
fb
CCOFF
V
CC(min)
Minimum Operating Voltage after Turn−On
V
CC
V
CC
Decreasing Level at which the Latch−Off Phase Ends (V = 3.5 V)
V
V
fb
CClatch
CCreset
Level at which the Internal Logic gets Reset
V
V
Internal IC Consumption, No Output Load on Pin 6 (V = 2.5 V)
I
I
0.6
1.3
1.8
2.5
mA
mA
fb
CC1
Internal IC Consumption, 1.0 nF Output Load on Pin 6, F
= 65 kHz
SW
CC2
(V = 2.5 V)
fb
Internal IC Consumption, 1.0 nF Output Load on Pin 6, F
Internal IC Consumption, 1.0 nF Output Load on Pin 6, F
Internal IC Consumption, Latch−Off Phase
= 100 kHz
= 133 kHz
I
I
I
6
6
6
1.3
1.3
400
2.2
2.8
3.0
3.3
mA
mA
ꢁ A
SW
CC2
CC2
CC3
SW
680
1000
Internal Startup Current Source
High−Voltage Current Source, 1.0 nF Load
I
I
8
1.8
3.2
4.2
mA
C1
(V
CCOFF
−0.2 V, V = 2.5 V, V
= 30 V)
fb
PIN8
High−Voltage Current Source (V = 0 V)
8
8
8
1.8
−
4.4
20
30
5.6
23
80
mA
V
CC
C2
Minimum Startup Voltage (I = 0.5 mA, V
−0.2 V, V = 2.5 V)
V
HVmin
c
CCOFF
fb
Startup Leakage (V
= 500 V)
I
10
ꢁ
A
PIN8
HVLeak
Drive Output
Output Voltage Rise−Time @ C = 1.0 nF, 10−90% of Output Signal
T
5
5
5
5
1
−
40
15
−
ns
ns
ꢂ
L
r
Output Voltage Fall−Time @ C = 1.0 nF, 10−90% of Output Signal
T
−
−
L
f
Source Resistance, R
300 ꢂ (V = 2.5 V)
R
OH
6.0
3.0
6.0
12.3
7.5
25
18
23
Load
fb
Sink Resistance, at 1.0 V on Pin 5 (V = 3.5 V)
R
ꢂ
fb
OL
Pin 1 Output Impedance (or R
between Pin 1 and Pin 6 when SW1
RPFC
11.7
ꢂ
dson
is closed) R
on Pin 1 = 680 ꢂ
load
Current Comparator and Thermal Shutdown
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint
I
3
3
−
0.02
−
ꢁ
A
IB
Tj = 25°C
Tj = −40°C to +125°C
I
1.010
0.979
1.063
−
1.116
1.127
V
Limit
Default Internal Setpoint for Skip Cycle Operation and Standby
Detection
V
skip
3
600
750
900
mV
Default Internal Setpoint to Leave Standby
V
−
1.0
1.25
90
1.5
V
stby−out
Propagation Delay from CS Detected to Gate Turned Off (V
(Pin 5 Loaded by 1.0 nF)
= 10 V)
T
3
−
180
ns
Gate
DEL CS
Leading Edge Blanking Duration
Soft−Start Period (Note 3)
T
3
−
−
−
100
−
200
2.5
165
25
350
−
ns
ms
°C
°C
LEB
SS
Temperature Shutdown, Maximum Value (Note 3)
Hysteresis while in Temperature Shutdown (Note 3)
3. Verified by Design.
T
150
−
−
SD
T
hyste
−
SD
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5
NCP1230
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C,
J
J
J
V
CC
= 13 V, V
= 30 V unless otherwise noted.)
PIN8
Characteristic
Symbol
Pin
Min
Typ
Max
Unit
Internal Oscillator
Oscillation Frequency, 65 kHz Version (V = 2.5 V)
Tj = 25°C
Tj = 0°C to +125°C
Tj = −40°C to +125°C
f
f
f
−
−
−
60
58
55
65
−
−
70
72
72
kHz
fb
OSC
OSC
OSC
Oscillation Frequency, 100 kHz Version
Oscillation Frequency, 133 kHz Version
Tj = 25°C
Tj = 0°C to +125°C
Tj = −40°C to +125°C
93
90
85
100
−
−
107
110
110
kHz
kHz
Tj = 25°C
Tj = 0°C to +125°C
Tj = −40°C to +125°C
123
120
113
133
−
−
143
146
146
Internal Modulation Swing, in Percentage of F (V = 2.5 V) (Note 4)
−
−
−
−
−
−
−
"6.4
5.0
−
−
%
ms
%
sw
fb
Internal Swing Period (Note 4)
Maximum Duty−Cycle (CS = 0, V = 2.5 V)
D
75
80
85
fb
max
Internal Ramp Compensation
Internal Resistor (Note 4)
R
3
3
9.0
18
36
kꢂ
up
Ramp Compensation Sawtooth Amplitude
Feedback Section
−
−
2.3
−
Vpp
Opto Current Source (V = 0.75 V)
−
2
200
235
2.8
270
ꢁ
A
fb
Pin 3 to Current Setpoint Division Ratio (Note 4)
I
−
−
−
−
ratio
Protection
Timeout before Validating Short−Circuit or PFC V (Note 4)
T
−
−
125
3.0
−
ms
V
CC
DEL
Latch−Off Level
V
latch
3
2.7
3.3
4. Verified by Design.
TYPICAL PERFORMANCE CHARACTERISTICS
8.0
13.0
12.8
12.6
V
CC
= 0 V
V
PIN8
= 30 V
V
PIN8
= 30 V
7.8
7.6
7.4
12.4
12.2
12.0
7.2
7.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. VCC(OFF) Threshold vs. Temperature
Figure 4. VCC(min) Threshold vs. Temperature
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6
NCP1230
TYPICAL PERFORMANCE CHARACTERISTICS
6.0
5.8
5.6
5.4
1.6
V
PIN8
= 30 V
V
CC
= 13 V
1.35
1.1
0.85
0.6
5.2
5.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. VCC Latch Threshold vs. Temperature
Figure 6. ICC1 Internal Current Consumption, No Load
vs. Temperature
800
700
600
3.1
2.7
2.3
V
= 13 V
CC
133 kHz
100 kHz
65 kHz
1.9
1.5
500
400
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. ICC2 Internal Current Consumption,
1.0 nF Load vs. Temperature
Figure 8. ICC3 Internal Consumption,
Latch−Off Phase vs. Temperature
4.0
3.5
3.0
5.0
4.5
4.0
V
CC
= V − 0.2 V
V
PIN8
= 30 V
V
CC
= 0 V
V
PIN8
= 30 V
CC
2.5
2.0
3.5
3.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. IC1 Startup Current vs. Temperature
Figure 10. IC2 Startup Current vs. Temperature
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7
NCP1230
TYPICAL PERFORMANCE CHARACTERISTICS
22.0
21.5
21.0
100
V
CC
= 13 V
V
CC
= V
− 0.2 V
CC(off)
75
50
T = −40 °C
J
20.5
20.0
T = +25 °C
J
25
0
19.5
19.0
T = +125 °C
J
−50 −25
0
25
50
75
100
125 150
1
10
50
200 400 600 800 850 950
T , JUNCTION TEMPERATURE (°C)
J
V
DRAIN
, VOLTAGE (V)
Figure 11. Minimum Startup Voltage vs. Temperature
Figure 12. Leakage Current vs. Temperature
18
15
14
13
12
11
V
CC
= 13 V
V
CC
= 13 V
16
14
10
9.0
12
8.0
7.0
10
6.0
5.0
−50 −25
8.0
−50 −25
0
25
50
75
100
125 150
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. Drive Source Resistance vs. Temperature
Figure 14. Drive Sink Resistance vs. Temperature
18
17
1.20
V
CC
= 13 V
V
CC
= 13 V
1.15
1.10
16
15
14
max
1.05
1.00
0.95
0.90
13
12
typ
11
10
min
9.0
8.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. RPFC vs. Temperature
Figure 16. ILimit vs. Temperature
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8
NCP1230
TYPICAL PERFORMANCE CHARACTERISTICS
800
775
750
1.40
V
CC
= 13 V
V
CC
= 13 V
1.35
1.30
1.25
1.20
725
700
1.15
1.10
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 17. Vskip vs. Temperature
Figure 18. Vstby−out vs. Temperature
80
75
70
4.0
3.5
3.0
2.5
2.0
1.5
V
CC
= 13 V
65
60
55
50
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 19. Soft−Start vs. Temperature
Figure 20. Frequency (65 kHz) vs. Temperature
110
106
102
98
145
141
137
133
129
125
V
CC
= 13 V
V
= 13 V
CC
94
90
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 21. Frequency (100 kHz) vs. Temperature
Figure 22. Frequency (133 kHz) vs. Temperature
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NCP1230
TYPICAL PERFORMANCE CHARACTERISTICS
10.0
9.0
81.0
V
CC
= 13 V
f
= 65 kHz
osc
V
CC
= 13 V
80.5
80.0
8.0
7.0
6.0
5.0
4.0
79.5
79.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 23. Internal Modulation Swing
vs. Temperature
Figure 24. Maximum Duty Cycle
vs. Temperature
280
270
260
24
V
= 0.75 V
fb
V
CC
= 13 V
22
20
18
16
14
250
240
230
220
210
200
12
10
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 25. Iopto vs. Temperature
Figure 26. Internal Ramp Compensation Resistor
vs. Temperature
150
140
3.50
3.25
3.00
130
120
2.75
2.50
110
100
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 27. Fault Time Delay vs. Temperature
Figure 28. Vlatch vs. Temperature
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NCP1230
OPERATING DESCRIPTION
PFC_VCC
Introduction
The NCP1230 is a current mode controller which provides
a high level of integration by providing all the required
control logic, protection, and a PWM Drive Output into a
single chip which is ideal for low cost, medium to high
power off−line application, such as notebook adapters,
battery chargers, set−boxes, TV, and computer monitors.
The NCP1230 can be connected directly to a high voltage
source providing lossless startup, and eliminating external
As shown on the internal NCP1230 diagram, an internal
low impedance switch SW1 routes Pin 6 (V ) to Pin 1
CC
when the power supply is operating under nominal load
conditions. The PFC_V signal is capable of delivering up
CC
to 35 mA of continuous current for a PFC Controller, or
other logic.
Connecting the NCP1230 PFC_V
output to a PFC
CC
Controller chip is very straight forward, refer to the “Typical
Application Example” all that is generally required is a
small decoupling capacitor (0.1 ꢁ F).
startup circuitry. In addition, the NCP1230 has a PFC_V
CC
output pin which provides the bias supply power for a Power
Factor Correction controller, or other logic. The NCP1230
has an event management scheme which disables the
PFC_V output during standby, and overload conditions.
CC
High Voltage
+
V
out
PFC_V
CC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
GND
NCP1230
MC33262/33260
Rsense
V
CC
Cap
GND
Figure 29. Typical Application Example
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11
NCP1230
Feedback
0.75
s
I
+
pk
R @ 3
The feedback pin has been designed to be connected
directly to the open−collector output of an optocoupler. The
pin is pulled−up through a 20 kꢂ resistor to the internal Vdd
supply (6.5 volts nominal). The feedback input signal is
divided down, by a factor of three, and connected to the
negative (−) input of the PWM comparator. The positive (+)
input to the PWM comparator is the current sense signal
(Figure 30).
where:
I
@ R + 1V
s
pk
2 @ P
in
I
+
ǸL @ f
pk
p
where:
P = is the power level where the NCP1230 will go into
the skip mode
The NCP1230 is a peak current mode controller, where
the feedback signal is proportional to the output power. At
the beginning of the cycle, the power switch is turns−on and
the current begins to increase in the primary of the
transformer, when the peak current crosses the feedback
voltage level, the PWM comparators switches from a logic
level low, to a logic level high, resetting the PWM latching
Flip−Flop, turning off the power switch until the next
oscillator clock cycle begins.
in
L = Primary inductance
p
f = NCP1230 controller frequency
2
L @ f @ I
p
pk
P
+
in
2
P
out
+
P
in
Eff
where:
Eff = the power supply efficiency
Vdd
20k
2
E
out
+
R
out
P
out
55k
FB
−
PWM
2
S is rising edge triggered
R is falling edge triggered
+
10 V
25k
Vskip
/ Vstby−out
1.25 V
125 ms
+
2.3 Vpp
Ramp
+
S
R
−
18k
LEB
3
Vdd
Figure 30.
PFC_V
CC
−
FB
The feedback pin input is clamped to a nominal 10 volt for
ESD protection.
Latch
Reset
+
+
Vskip
0.75 V
Skip Mode
CS Cmp
The feedback input is connected in parallel with the skip
cycle logic (Figure 31). When the feedback voltage drops
below 25% of the maximum peak current (1.0 V/Rsense) the
IC prevents the current from decreasing any further and
starts to blank the output pulses. This is called the skip cycle
mode. While the controller is in the burst mode the power
transfer now depends upon the duty cycle of the pulse burst
width which reduces the average input power demand.
Figure 31.
During the skip mode the PFC_Vcc signal (pin 1) is
asserted into a high impedance state when a light load
condition is detected and confirmed, Figure 32 shows
typical waveforms. The first section of the waveform shows
a normal startup condition, where the output voltage is low,
as a result the feedback signal will be high asking the
controller to provide the maximum power to the output. The
second phase is under normal loading, and the output is in
regulation. The third phase is when the output power drops
below the 25% threshold (the feedback voltage drops to 0.75
volts). When this occurs, the 125 msec timer starts, and if the
conditions is still present after the time output period, the
V + I @ R @ 3
pk
c
s
where:
V = control voltage (Feedback pin input),
c
I
= Peak primary current,
pk
R = Current sense resistor,
s
3 = Feedback divider ratio.
SkipLevel + 3V @ 25% + 0.75V
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NCP1230
Ramp Compensation
NCP1230 confirms that the low output power condition is
present, and the internal SW1 opens, and the PFC_Vcc
signal output is shuts down. While the NCP1230 is in the
skip mode the FB pin will move around the 750 mV
threshold level, with approximately 100 mVp−p of
hysteresis on the skip comparator, at a period which depends
upon the (light) loading of the power supply and its various
time constants. Since this ripple amplitude superimposed
over the FB pin is lower than the second threshold (1.25
volt), the PFC_Vcc comparator output stays high (PFC_Vcc
output Pin 1 is low).
In Switch Mode Power Supplies operating in Continuous
Conduction Mode (CCM) with a duty−cycle greater than
50%, oscillation will take place at half the switching
frequency. To eliminate this condition, Ramp Compensation
can be added to the current sense signal to cure sub harmonic
oscillations. To lower the current loop gain one typically
injects between 50 and 100% of the inductor down slope.
The NCP1230 provides an internal 2.3 Vpp ramp which
is summed internally through a 18 kꢂ resistor to the current
sense pin. To implement ramp compensation a resistor needs
to be connected from the current sense resistor, to the current
sense pin 3.
In Phase four, the output power demands have increases
and the feedback voltage rises above the 1.25 volts
threshold, the NCP1230 exits the skip mode, and returns to
normal operation.
Example:
If we assume we are using the 65 kHz version of the
NCP1230, at 65 kHz the dv/dt of the ramp is 130 mV/ꢁ s.
Assuming we are designing a FLYBACK converter which
has a primary inductance, Lp, of 350 ꢁ H, and the SMPS has
a +12 V output with a Np:Ns ratio of 1:0.1. The OFF time
primary current slope is given by:
Max I
P
Regulation
Skip + 60%
Ns
V
(V
) V @
out f)
Np
FB
= 371 mA/ꢁ s or 37 mV/ꢁ s
L
p
1.25 V
0.75 V
when imposed on a current sense resistor (Rsense) of 0.1 ꢂ.
If we select 75% of the inductor current downslope as our
required amount of ramp compensation, then we shall inject
27 mV/ꢁ s.
With our internal compensation being of 130 mV, the
divider ratio (divratio) between Rcomp and the 18 kꢂ is
0.207. Therefore:
PFC is Off
PFC is Off
No Delay
125 ms
Delay
PFC is On
PFC is On
Figure 32.
18k @ divratio
(1 * divratio)
= 4.69 kꢂ
R
+
comp
Leaving Standby (Skip Mode)
2.3 V
0V
When the feedback voltage rises above the 1.25 volts
reference (leaving standby) the skip cycle activity stops and
SW1 immediately closes and restarts the PFC, there is no
delay in turning on SW1 under these conditions, refer to
Figure 32.
18 k
CS
Current Sense
Rcomp
+
The NCP1230 is a peak current mode controller, where
the current sense input is internally clamped to 1.0 V, so the
sense resister is determined by Rsense = 1.0 V /Ipk
maximum.
LEB
−
Rsense
There is a 18k resistor connected to the CS pin, the other
end of the 18k resistor is connect to the output of the internal
oscillator for ramp compensation (refer to Figure 33).
Fb/3
Figure 33.
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NCP1230
Leading Edge Blanking
isolated secondary output and on the auxiliary winding.
Because the auxiliary winding and diode form a peak
rectifier, the auxiliary Vcc capacitor voltage can be charged
up to the peak value rather than the true plateau which is
proportional to the output level.
In Switch Mode Power Supplies (SMPS) there can be a
large current spike at the beginning of the current ramp due
to the Power Switch gate to source capacitance, transformer
interwinding capacitance, and output rectifier recovery
time. To prevent prematurely turning off the PWM drive
output, a Leading Edges Blanking (LEB) (Figure 34) circuit
is place is series with the current sense input, and PWM
comparator. The LEB circuit masks the first 250 ns of the
current sense signal.
To resolve these issues the NCP1230 monitors the 1.0 V
error flag. As soon as the internal 1.0 V error flag is asserted
high, a 125 ms timer starts. If at the end of the 125 ms timeout
period, the error flag is still asserted then the controller
determines that there is a true fault condition and stops the
PWM drive output, refer to Figure 35. When this occurs,
Vcc starts to decrease because the power supply is locked
out. When Vcc drops below UVLOlow (7.7 V typical), it
enters a latch−off phase where the internal consumption is
reduced down to 680 ꢁ A (typical). The voltage on the Vcc
capacitor continues to drop, but at a lower rate. When Vcc
reaches the latch−off level (5.6 V), the current source is
turned on and pulls Vcc above UVLOhigh. To limit the fault
output power, a divide−by−two circuit is connected to the
Vcc pin that requires two startup sequences before
attempting to restart the power supply. If the fault has gone
and the error flag is low, the controller resumes normal
operations.
Thermal Shutdown
Skip
125 msec Timer
2.3 Vpp
Ramp
PWM Comparator
FB/3
−
+
Vccreset
R Q
18 k
LEB
CS
+
−
3
S
250 ns
10 V
Latch−Off
3 V
Figure 34.
Under transient load conditions, if the error flag is
asserted, the error flag will normally drop prior to the 125 ms
timeout period and the controller continues to operate
normally.
If the 125 msec timer expires while the NCP1230 is in the
Skip Mode, SW1 opens and the PFC_Vcc output will shut
down and will not be activated until the fault goes away and
the power supply resumes normal operations.
Short−Circuit Condition
The NCP1230 is different from other controllers which
use an auxiliary windings to detect events on the isolated
secondary output. There maybe some conditions (for
example when the leakage inductance is high) where it can
be extremely difficult to implement short−circuit and
overload protection. This occurs because when the power
switch opens, the leakage inductance superimposes a large
spike on the switch drain voltage. This spike is seen on the
While in the Skip Mode, to avoid any thermal runaway it
is desirable for the Burst duty cycle to be kept below
20%(the burst duty−cycle is defined as Tpulse / Tfault).
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NCP1230
12.6V
7.7V
125ms
125ms
125ms
125ms
Figure 35.
The latch−off phase can also be initiated, more classically,
when Vcc drops below UVLO (7.7 V typical). During this
fault detection method, the controller will not wait for the
125 ms time−out, or the error flag before it goes into the
latch−off phase, operating in the skip mode under these
conditions, refer to Figure 36.
Regulation
Fault
Regulation
12.6 V
V
PWM
7.7 V
CC
5.6 V
Timer
125 ms
125 ms
2.5 ms
SS
1 V
Flag
Pin 1
PFC
V
CC
Figure 36.
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NCP1230
Current Sense Input Pin Latch−Off
Vccoff (12.6 V typically), the current source is turned off
reducing the amount of power being dissipated in the chip.
The NCP1230 then turns on the drive output to the external
MOSFET in an attempt to increase the output voltage and
charge up the Vcc capacitor through the Vaux winding in the
transformer.
The NCP1230 features a fast comparator (Figure 34) that
monitors the current sense pin during the controller off time.
If for any reason the voltage on pin 3 increases above 3.0 V,
the NCP1230 immediately stops the PWM drive pulses and
permanently stays latched off until the bias supply to the
NCP1230 is cycled down (Vcc must drop below 4.0 V, e.g.
when the user unplugs the converter from the mains). This
offers the designer the flexibility to implement an externally
shutdown circuit (for example for overvoltage or
overtemperature conditions). When the controller is latched
off through pin 3 (current sense), SW1 opens and shuts off
PFC_Vcc output.
Figure 37 shows how to implement the external latch via
a Zener diode and a simple PNP transistor. The PNP actually
samples the Zener voltage during the OFF time only, hence
leaving the CS information un−altered during the ON time.
Various component arrangements can be made, e.g. adding
a NTC device for the Over Temperature Protection (OTP).
During the startup sequence, the controller pushes for the
maximum peak current, which is reached after the 2.5 ms
soft−start period. As soon as the maximum peak set point is
reached, the internal 1.0 V Zener diode actively limits the
current amplitude to 1.0 V/Rsense and asserts an error flag
indicating that a maximum current condition is being
observed. In this mode, the controller must determine if it is
a normal startup period (or transient load) or is the controller
is facing a fault condition. To determine the difference
between a normal startup sequence, and a fault condition, the
error flag is asserted, and the 125 ms timer starts to count
down. If the error flag drops prior to the 125 ms time−out
period, the controller resets the timer and determines that it
was a normal startup sequence and enables the low
impedance switch (SW1), enabling the PFC_Vcc output.
If at the end of the 125 ms period the error flag is still
asserted, then the controller assumes that it is a fault
condition and the PWM controller enters the skip mode and
does not enable the PFC_Vcc output.
HV
Vz
1
2
3
4
8
7
6
5
8
HV
12.6 V/
5.6 V
+
−
3.2 mA or 0
6
1k
Ramp
CVcc
Aux
CVcc
4
Figure 38.
ON Semiconductor recommends that the Vcc capacitor be at
least 47 ꢁ F to be sure that the Vcc supply voltage does not drop
below Vccmin (7.7 V typical) during standby power mode and
unusual fault conditions.
Figure 37.
Connecting the PNP to the drive only activates the offset
generation during Toff. Here is a solution monitoring the
auziliary Vcc rail.
Soft−Start
Drive Output
The NCP1230 features an internal 2.5 ms soft−start
circuit. As soon as Vcc reaches a nominal 12.6 V, the
soft−start circuit is activated. The soft−start circuit output
controls a reference on the minus (−) input to an amplifier
(refer to Figure 39), the positive (+) input to the amplifier is
the feedback input (divided by 3). The output of the
amplifier drives a FET which clamps the feedback signal. As
the soft−start circuit output ramps up, it allow the feedback
pin input to the PWM comparator to gradually increased
from near zero up to the maximum clamping level of 1.0
V/Rsense. This occurs over the entire 2.5 ms soft−start
period until the supply enters regulation. The soft−start is
also activated every time a restart is attempted. Figure 40
shows a typical soft−start up sequence.
The NCP1230 provides a Drive Output which can be
connected through a current limiting resistor to the gate of
a MOSFET. The Driver output is capable of delivering drive
pulses with a rise time of 40 ns, and a fall time of 15 ns
through its internal source and sink resistance of 12.3 ohms
(typical), measured with a 1.0 nF capacitive load.
Startup Sequence
The NCP1230 has an internal High Voltage Startup
Circuit (Pin 8) which is connected to the high voltage DC
bus (Refer to Figure 36). When power is applied to the bus,
the NCP1230 internal current source (typically 3.2 mA) is
biased and charges up the external Vcc capacitor on pin 6,
refer to Figure 38. When the voltage on pin 6 (Vcc) reaches
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NCP1230
Vdd
Vdd
20k
Error
Skip
Comparators
55k
FB
2
PWM
−
+
10V 25k
CS
+
−
2.5 msec
SS Timer
OSC
Soft−Start
Ramp (1V max)
Figure 39.
V
CC
12.6 V
0 V (Fresh PON)
or
6 V (OCP)
Current
Sense
Max I
P
2.5 ms
Figure 40. Soft−Start is Activated during a Startup
Sequence or an OCP Condition
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NCP1230
Frequency Jittering
NCP1230 offers a nominal ±6.4% deviation of the nominal
switching frequency. The sweep sawtooth is internally
generated and modulates the clock up and down with a 5 ms
period. Figure 41 illustrates the NCP1230 behavior:
Frequency jittering is a method used to soften the EMI
signature by spreading out the average switching energy
around the controller operating switching frequency. The
Internal Ramp
62.4 kHz
65 kHz
Internal Sawtooth
67.6 kHz
5 ms
Figure 41. An Internal Ramp is used to Introduce Frequency Jittering on the Oscillator Saw Tooth
Thermal Protection
drops below 4.0 volts and the Vccreset circuit is activated,
the controller will restart. If the user is using a fixed bias
supply (the bias supply is provided from a source other than
from an auxiliary winding, refer to the typical application )
and Vcc is not allow to drop below 4.0 volts under a thermal
shutdown condition, the NCP1230 will not restart. This
feature is provided to prevent catastrophic failure from
accidentally overheating the device.
An internal Thermal Shutdown is provided to protect the
integrated circuit in the event that the maximum junction
temperature is exceeded. When activated (165°C typically)
the controller turns off the PWM Drive Output. When this
occurs, Vcc will drop (the rate is dependent on the NCP1230
loading and the size of the Vcc capacitor) because the
controller is no longer delivering drive pulses to the
auxiliary winding charging up the Vcc capacitor. When Vcc
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NCP1230
PACKAGE DIMENSIONS
SOIC−7
D1 SUFFIX
CASE 751U−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
−A−
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
S
M
M
B
−B−
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
G
1.27 BSC
0.10
0.19
0.40
0
C
R X 45
_
J
8
0
8
_
_
_
_
−T−
SEATING
PLANE
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
K
M
H
D 7 PL
M
S
S
0.25 (0.010)
T
B
A
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NCP1230
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AG
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
0.10 (0.004)
1.27 BSC
0.050 BSC
M
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)
Z
Y
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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20
NCP1230
PACKAGE DIMENSIONS
7−LEAD PDIP
P SUFFIX
CASE 626B−01
ISSUE A
NOTES:
J
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION L TO CENTER OF LEAD
WHEN FORMED PARALLEL.
8
5
M
4. PACKAGE CONTOUR OPTIONAL
(ROUND OR SQUARE CORNERS).
5. DIMENSIONS A AND B ARE DATUMS.
B
L
1
4
MILLIMETERS
DIM MIN
MAX
A
B
C
D
F
G
H
J
9.40 10.16
F
6.10
3.94
0.38
1.02
6.60
4.45
0.51
1.78
A
NOTE 2
2.54 BSC
0.76
0.20
2.92
1.27
0.30
3.43
C
K
L
7.62 BSC
M
N
−−−
0.76
10 °
1.01
−T−
N
SEATING
PLANE
H
D
K
G
M
M
M
B
0.13 (0.005)
T A
The product described herein (NCP1230), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,221. There may be other
patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP1230/D
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