NCP1231P100G [ONSEMI]
Low−Standby Power High Performance PWM Controller; 低待机功耗高性能PWM控制器
| 型号： | NCP1231P100G |
| 厂家： | 
ONSEMI |
| 描述： | Low−Standby Power High Performance PWM Controller |
| 文件： | 总21页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1231
Low−Standby Power High
Performance PWM
Controller
The NCP1231 represents a major leap towards achieving low
standby power in medium−to−high power Switched−Mode Power
Supplies such as notebook adapters, off−line battery chargers and
consumer electronics equipment. Housed in SOIC−8 or PDIP−8, the
NCP1231 contains all needed control functionality to build a rugged
and efficient power supply. Among the unique features offered by the
NCP1231 is an event management scheme that can disable the
front−end PFC circuit during standby, thus reducing the no load power
consumption. The NCP1231 itself goes into cycle skipping at light
loads while limiting peak current (to 25% of nominal peak) so that no
acoustic noise is generated and while in the skip cycle mode.
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MARKING
DIAGRAMS
8
231Dx
y
ALYW
G
SOIC−8
D SUFFIX
CASE 751
1
1
The NCP1231 also features an internal latching function that can be
used for Overvoltage Protection (OVP). The latch is triggered when
the voltage on Pin 8 rises above 4.0 V. During an OVP condition, the
output drive pulses are immediately stopped and the NCP1231 stays in
8
1
1231Pzz
AWL
YYWWG
PDIP−8
P SUFFIX
CASE 626
the latched off condition until V drops below 4.0 V (V
). In
CCreset
CC
addition, Pin 8 also serves as a Brown−Out input which provides the
necessary safety feature when the SMPS faces low mains situations.
1
Features
• Current−Mode Operation with Internal Ramp Compensation
• Extremely Low Startup Current of 30 ꢀ A Typical
• Skip−Cycle Capability at Low Peak Currents
• Adjustable Soft−Start
231Dxy = Device Code
x = 1 or 6
y = 0 or 3
1231Pzz = Device Code
zz = 65, 100 or 133
= Assembly Location
A
• Overvoltage and Brown−Out Protection
L, WL
Y, YY
= Wafer Lot
= Year
• Short−Circuit Protection Independent of Auxiliary Level
• Internal Frequency Dithering for Improved EMI Signature
• Go−To−Standby Signal for PFC Front Stage
• Extremely Low No−Load, Noiseless, Standby Power
• Internal Leading Edge Blanking
W, WW = Work Week
G or G
= Pb−Free Package
PIN CONNECTIONS
• +500 mA/−800 mA Peak Current Drive Capability
• Available in Three Frequency Options: 65 kHz, 100 kHz, and 133 kHz
• Direct Optocoupler Connection
• SPICE Models Available for TRANsient and AC Analysis
• Pb−Free Packages are Available
1
8
PFC_V
BO/OVP
SS
CC
FB
CS
GND
V
CC
DRV
Typical Applications
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
• High Power AC−DC Adapters for Notebooks, etc.
• Offline Battery Chargers
• Set−Top Boxes Power Supplies, TV, Monitors, etc.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 4
NCP1231/D
NCP1231
HV
OVP
+
V
out
BO/OVP
to PFC’s V
1
2
3
4
8
7
6
5
CC
SS
GND
+
NCP1231
Ramp
GND
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Pin Description
1
PFC V
Directly powers the PFC This pin is a direct connection to the V pin (Pin 6) via a low impedance switch.
CC
CC
front−end stage
In standby and during the startup sequence, the switch is open and the PFC V
is shutdown. As soon as the aux. winding is stabilized, Pin 1 connects to the V
pin and provides bias to the PFC controller. It goes down in standby and fault
conditions.
CC
CC
2
3
FB
CS
Feedback Signal
Current Sense
An optocoupler collector pulls this pin low to regulate. When the current setpoint
falls below 25% of the maximum peak, the controller skips cycles.
This pin incorporates two different functions: the standard sense function and an
internal ramp compensation signal.
4
5
GND
DRV
IC Ground
−
Driver Output
With a drive capability of +500 mA / −800 mA, the NCP1231 can drive large Qg
MOSFETs.
6
7
V
V
Input
The controller accepts voltages up to 18 V and features a UVLO of 7.7 V typical.
CC
CC
SS
To provide an internal
This pin provides three different functions, via a capacitor to ground, saw tooth
signal whose function is to create a soft−start, frequency dithering and 100 msec
fault timer.
(Soft−Start) ramp timing for different
usages
8
BO/OVP
Brown−Out and OVP
By connecting this pin to a resistive divider, the controller ensures operation at a
safe mains level. If an external event brings this pin above 4 V, the controller is
permanently latched−off.
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2
NCP1231
+
+
+
+
+
+
+
+
+
Figure 2. Internal Circuit Architecture
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3
NCP1231
MAXIMUM RATINGS (Notes 1 and 2)
Rating
Symbol
Value
Unit
Voltage BO/OVP Pin 8
Current
BO/OVP
10
100
V
mA
Voltage Pin 7
Current
SS
10
100
V
mA
Power Supply Voltage, Pin 6
Maximum Current
V
V
V
−0.3 to 18
V
CC
100
mA
I
C
Drive Output Voltage, Pin 5
Drive Current
18
1.0
V
A
DV
I
o
Voltage Current Sense Pin, Pin 3
Current
10
100
V
mA
cs
cs
I
Voltage Feedback, Pin 2
Current
V
10
100
V
mA
fb
I
fb
Voltage, Pin 1
Maximum Continuous Current Flowing from Pin 1
V
18
35
V
mA
PFC
I
PFC
Thermal Resistance, Junction−to−Air, PDIP Version
Thermal Resistance, Junction−to−Air, SOIC Version
R
R
100
178
°C/W
°C/W
W
ꢁ
ꢁ
JA
JA
Maximum Power Dissipation @ T = 25°C
PDIP
SOIC
P
max
1.25
0.702
A
Maximum Junction Temperature
Storage Temperature Range
T
150
°C
°C
J
T
stg
−60 to +150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−6: Human Body Model 2000 V per Mil−Std−883, Method 3015.
Machine Model Method 200 V
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1231
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C,
J
J
J
V
CC
= 13 V, unless otherwise noted.)
Rating
Supply Section (All frequency versions, otherwise noted)
Symbol
Pin
Min
Typ
Max
Unit
Turn−On Threshold Level, V going up (V = 2.0 V)
V
CCON
6
6
6
6
6
6
6
6
6
11.3
7.0
−
12.6
7.7
4.0
30
13.8
8.4
−
V
CC
fb
Minimum Operating Voltage after Turn−On
V
V
V
CC(min)
CCreset
V
CC
Level at which the Internal Logic gets Reset (Note 4)
V
Startup Current (V
−0.2 V)
I
−
50
ꢀ A
mA
mA
mA
mA
ꢀ A
CCON
startup
Internal IC Consumption, No Output Load on Pin 6 (V = 2.5 V)
I
I
I
I
I
0.75
1.4
1.4
1.4
300
1.3
2.0
2.4
2.9
500
2.0
2.6
3.1
3.7
800
fb
CC1
CC2
CC2
CC2
CC3
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
Internal IC Consumption, Latch−Off Phase
Drive Output
= 65 kHz
= 100 kHz
= 133 kHz
SW
SW
SW
Output Voltage Rise−Time @ C = 1.0 nF, 10−90% of Output Signal (Note 4)
T
5
5
5
5
1
−
40
15
−
ns
ns
ꢂ
L
r
Output Voltage Fall−Time @ C = 1.0 nF, 10−90% of Output Signal (Note 4)
T
−
−
L
f
Source Resistance (R
= 300 ꢂ, V = 2.5 V)
R
6.0
3.0
6.0
12.3
7.5
25
18
23
Load
fb
OH
Sink Resistance, at 1.0 V on Pin 5 (V = 3.5 V)
R
ꢂ
fb
OL
Pin1 Output Impedance (or R
load
between Pin 1 and Pin 6 when SW1 is closed)
RPFC
11.7
ꢂ
dson
R
on Pin 1= 680 ꢂ
Current Comparator (Pin 5 unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Set Point
I
3
3
−
0.02
−
ꢀ
A
IB
T = +25°C
I
0.95
0.93
1.00
−
1.05
1.07
V
J
Limit
T = −40°C to +125°C
J
Default Internal Set Point for Skip Cycle Operation and Standby Detection
Default Internal Set Point to Leave Standby
V
3
−
3
3
600
1.0
−
750
1.25
90
900
1.5
mV
V
skip
V
stby−out
Propagation Delay from CS Detected to Gate Turned Off (Pin 5 Loaded by 1.0 nF)
Leading Edge Blanking Duration
T
200
350
ns
ns
DEL CS
T
LEB
100
250
Internal Oscillator
Oscillation Frequency, 65 kHz version (V = 2.5 V)
f
f
f
−
−
−
−
−
−
7
7
7
7
7
56
88
118
−
65
100
133
±4.0
5.0
80
69
108
140
−
kHz
kHz
kHz
%
fb
OSC
Oscillation Frequency, 100 kHz version (V = 2.5 V)
fb
OSC
Oscillation Frequency, 133 kHz version (V = 2.5 V)
fb
OSC
Internal Modulation Swing, in Percentage of Fsw) (Typical) (Note 4)
Internal Swing Period with a 82 nF Capacitor to Pin 7) (Typical) (Note 4)
Maximum Duty−Cycle
−
−
−
−
ms
%
D
75
−
85
−
max
Typical Soft−Start Period with a 82 nF to Pin 7 (Note 4)
SS Charging/Discharging Current
SS
−
5.0
60
ms
ꢀ A
ꢀ A
V
35
−
75
−
Timer Charging Current (Typical) (Note 4)
Timer Peak Voltage
−
1.36
4.0
2.2
−
3.5
1.9
4.5
2.6
Timer Valley Voltage
−
V
Feedback Section (V = 13 V)
CC
Opto Current Source (V = 0.75 V)
−
2
190
235
3.0
270
ꢀ
A
fb
Pin 3 to Current Setpoint Division Ratio (Note 3)
I
−
−
−
−
ratio
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5
NCP1231
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C,
J
J
J
V
CC
= 13 V, unless otherwise noted.)
Rating
Symbol
Pin
Min
Typ
Max
Unit
Internal Ramp Compensation (V = 13 V)
CC
Internal Resistor (Note 3)
R
3
3
9.0
18
36
kꢂ
up
Internal Sawtooth Amplitude (Note 4)
−
−
2.3
−
Vpp
Protection (V = 13 V)
CC
Timeout before Validating Short−Circuit or PFC V with an 82 nF cap. to Pin 7
T
delay
−
−
110
−
ms
CC
(Note 4)
Latch−Off Level
V
8
−
8
8
−
−
3.7
−
4.2
100
0.50
4.5
−
V
ns
V
latch
Propagation Delay from Latch Detected to Gate Turned Off (Pin 5 Loaded by 1.0 nF)
Brown−Out Level High
T
DEL LATCH
V
0.40
0.55
BOhigh
Brown−Out Level Low
V
BOlow
0.180 0.230 0.285
V
Temperature Shutdown, Maximum Value (Note 4)
Hysteresis while in Temperature Shutdown (Note 4)
T
−
−
160
30
−
−
°C
°C
SD
SD hyste
T
3. Guaranteed by Design.
4. Verified by Design.
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6
NCP1231
TYPICAL PERFORMANCE CHARACTERISTICS
8.0
13.0
12.8
12.6
12.4
V
PIN8
= 30 V
7.8
7.6
7.4
12.2
12.0
7.2
7.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. VCC(on) Threshold vs. Temperature
Figure 4. VCC(min) Threshold vs. Temperature
35
33
31
29
27
25
23
21
19
1.75
1.50
1.25
V
= 13 V
CC
F
= 65 kHz
OSC
1.00
0.75
17
15
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. Istartup vs. Temperature
Figure 6. ICC1 Internal Current Consumption,
No Load vs. Temperature
3.5
3.0
2.5
600
550
500
V
CC
= 13 V
V
CC
= 13 V
133 kHz
100 kHz
65 kHz
2.0
1.5
450
400
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. ICC2 Internal Current Consumption,
1.0 nF Load vs. Temperature
Figure 8. ICC3 Internal Consumption,
Latch−Off Phase vs. Temperature
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NCP1231
TYPICAL PERFORMANCE CHARACTERISTICS
18
16
14
15
V
CC
= 13 V
V
CC
= 13 V
14
13
12
11
10
9.0
12
8.0
7.0
10
6.0
5.0
−50 −25
8.0
−50 −25
0
25
50
75
100
125 150
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Drive Source Resistance vs. Temperature
Figure 10. Drive Sink Resistance vs. Temperature
18
1010
1000
V
CC
= 13 V
V
CC
= 13 V
17
16
15
14
990
980
970
960
13
12
11
10
9.0
8.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. RPFC vs. Temperature
Figure 12. ILimit vs. Temperature
800
780
760
740
1.40
V
CC
= 13 V
V
CC
= 13 V
1.35
1.30
1.25
1.20
1.15
1.10
720
700
1.05
1.00
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. VSkip vs. Temperature
Figure 14. Vstandby−out vs. Temperature
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NCP1231
TYPICAL PERFORMANCE CHARACTERISTICS
110
68
66
V
CC
= 13 V
V
CC
= 13 V
105
100
64
62
60
58
95
90
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. Frequency (65 kHz) vs. Temperature
Figure 16. Frequency (100 kHz) vs. Temperature
140
135
130
125
120
115
110
9.0
8.5
V
CC
= 13 V
V
= 13 V
f
= 62.5 kHz
CC
osc
8.0
7.5
7.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 17. Frequency (133 kHz) vs. Temperature
Figure 18. Internal Modulation Swing
vs. Temperature
6.0
5.5
81.0
80.5
80.0
V
CC
= 13 V
V
CC
= 13 V
5.0
4.5
4.0
79.5
79.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 19. Internal Swing Period
vs. Temperature
Figure 20. Maximum Duty Cycle
vs. Temperature
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NCP1231
TYPICAL PERFORMANCE CHARACTERISTICS
70
68
66
64
62
60
58
56
54
2.00
C
= 82 nF
V
CC
= 13 V
timer
V
CC
= 13 V
1.75
PDIP
SOIC
1.50
1.25
1.00
0.75
0.50
52
50
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 21. Timer Charge/Discharge Current vs.
Temperature
Figure 22. Soft−Start Charging Current vs.
Temperature
4.5
4.0
3.5
3.0
2.5
240
235
230
V
CC
= 13 V
SS Timer Peak Voltage
SS Timer Valley Voltage
225
220
2.0
1.5
C
= 82 nF
pin7
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 23. SS Timer Peak and Valley Voltages
vs. Temperature
Figure 24. Opto−Coupler Current
vs. Temperature
24
22
20
18
16
14
190
180
170
160
V
CC
= 13 V
SOIC
PDIP
150
140
130
120
110
12
10
100
90
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 25. Internal Ramp Compensation Resistor
vs. Temperature
Figure 26. Time Delay vs. Temperature
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NCP1231
TYPICAL PERFORMANCE CHARACTERISTICS
550
4.30
4.25
4.20
525
500
475
450
4.15
4.10
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 27. Vlatchoff Threshold vs. Temperature
Figure 28. VBOhigh vs. Temperature
260
250
240
230
220
210
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
Figure 29. VBOlow vs. Temperature
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NCP1231
OPERATING DESCRIPTION
Introduction
the PFC_V
conditions.
output during standby, and overload
CC
The NCP1231 is a current mode controller which provides
a high level of integration by providing all the required
control logic, protection, and a PWM Drive Output into a
single chip which is ideal for low cost, medium to high
power off−line application, such as notebook adapters,
battery chargers, set−boxes, TV, and computer monitors.
The NCP1231 has a low startup current (30 ꢀ A) allowing
the controller to be connected directly to a high voltage
source through a resistor, providing low loss startup, and
reducing external circuitry. In addition, the NCP1231 has a
PFC_VCC
As shown on the internal NCP1231 internal block
diagram, an internal low impedance switch SW1 routes
Pin 6 (V ) to Pin 1 when the power supply is operating
CC
under nominal load conditions. The PFC_V
capable of delivering up to 35 mA of continuous current for
a PFC Controller, or other logic.
signal is
CC
Connecting the NCP1231 PFC_V
output to a PFC
CC
Controller chip is very straight forward, refer to the “Typical
Application Example” (Figure 30) all that is generally
required is a small decoupling capacitor (0.1 ꢀ F) near the
PFC controller.
PFC_V output pin which provides the bias supply power
CC
for a Power Factor Correction controller, or other logic. The
NCP1231 has an event management scheme which disables
High Voltage
Rstartup
NCP1231
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
MC33262/33260/etc.
Figure 30. Typical Application Example
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NCP1231
Feedback
0.75
s
I
+
pk
R @ 3
The feedback pin has been designed to be connected
directly to the open−collector output of an optocoupler. The
pin is pulled−up through a 20 kꢂ resistor to the internal Vdd
supply (6.5 volts nominal). The feedback input signal is
divided down, by a factor of three, and connected to the
negative (−) input of the PWM comparator. The positive (+)
input to the PWM comparator is the current sense signal
(Figure 31).
where:
I
@ R + 1V
s
pk
2 @ P
in
I
+
ǸL @ f
pk
p
where:
P = is the power level where the NCP1231 will go into
the skip mode
The NCP1231 is a peak current mode controller, where
the feedback signal is proportional to the output power. At
the beginning of the cycle, the power switch is turns−on and
the current begins to increase in the primary of the
transformer, when the peak current crosses the feedback
voltage level, the PWM comparators switches from a logic
level low, to a logic level high, resetting the PWM latching
Flip−Flop, turning off the power switch until the next
oscillator clock cycle begins.
in
L = Primary inductance
p
f = NCP1231 controller frequency
2
L @ f @ I
p
pk
P
+
in
2
P
out
+
P
in
Eff
where:
Eff = the power supply efficiency
Vdd
20k
2
E
out
+
R
out
P
out
55k
FB
−
PWM
2
S is rising edge triggered
R is falling edge triggered
+
10 V
25k
Vskip
/ Vstby−out
100 ms
1.25 V
+
2.3 Vpp
Ramp
+
S
R
−
Fault
18 k
LEB
3
Vdd
Figure 31.
PFC_V
CC
−
FB
The feedback pin input is clamped to a nominal 10 volt for
ESD protection.
Latch
Reset
+
+
Vskip
0.75 V
Skip Mode
CS Cmp
The feedback input is connected in parallel with the skip
cycle logic (Figure 32). When the feedback voltage drops
below 25% of the maximum peak current (1 V/Rsense) the
IC prevents the current from decreasing any further and
starts to blank the output pulses. This is called the skip cycle
mode. While the controller is in the burst mode the power
transfer now depends upon the duty cycle of the pulse burst
width which reduces the average input power demand.
Figure 32.
During the skip mode the PFC_Vcc signal (pin 1) is
asserted into a high impedance state when a light load
condition is detected and confirmed, Figure 33 shows
typical waveforms. The first section of the waveform shows
a normal startup condition, where the output voltage is low,
as a result the feedback signal will be high asking the
controller to provide the maximum power to the output. The
second phase is under normal loading, and the output is in
regulation. The third phase is when the output power drops
below the 25% threshold (the feedback voltage drops to 0.75
volts). When this occurs, the 100 mses timer starts, and if the
conditions is still present after the time output period, the
V + I @ R @ 3
pk
c
s
where:
V = control voltage (Feedback pin input),
c
I
= Peak primary current,
pk
R = Current sense resistor,
s
3 = Feedback divider ratio.
SkipLevel + 3V @ 25% + 0.75V
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13
NCP1231
NCP1231 confirms that the low output power condition is
The NCP1231 provides an internal 2.3 Vpp ramp which
is summed internally through a 18 kꢂ resistor to the current
sense pin. To implement ramp compensation a resistor needs
to be connected from the current sense resistor, to the current
sense pin 3.
present, and the internal SW1 opens. After the NCP1231
confirms that it is in a low power mode, versus a load
transient, the PFC_Vcc signal output is shuts down. While
the NCP1231 is in the skip mode the FB pin will move
around the 750 mV threshold level, with approximately 100
mVp−p of hysteresis on the skip comparator, at a period
which depends upon the (light) loading of the power supply
and its various time constants. Since this ripple amplitude
superimposed over the FB pin is lower than the second
threshold (1.25 volt), the PFC_Vcc comparator output stays
high (PFC_Vcc output Pin 1 is low).
Example:
If we assume we are using the 65 kHz version of the
NCP1231, at 65 kHz the dv/dt of the ramp is 130 mV/ꢀ s.
Assuming we are designing a FLYBACK converter which
has a primary inductance, Lp, of 350 ꢀ H, and the SMPS has
a +12 V output with a Np:Ns ratio of 1:0.1. The OFF time
primary current slope is given by:
In Phase four, the output power demands have increases
and the feedback voltage rises above the 1.25 volts
threshold, the NCP1231 exits the skip mode, and returns to
normal operation.
Ns
(V
) V @
f)
Np
out
= 371 mA/ꢀ s or 37 mV/ꢀ s
L
p
when imposed on a current sense resistor (Rsense) of 0.1 ꢂ.
If we select 75% of the inductor current downslope as our
required amount of ramp compensation, then we shall inject
27 mV/ꢀ s.
Max I
P
With our internal compensation being of 130 mV, the
divider ratio (divratio) between Rcomp and the 18 kꢂ is
0.207. Therefore:
Regulation
Skip + 60%
V
FB
18k @ divratio
(1 * divratio)
= 4.69 kꢂ
1.25 V
0.75 V
R
+
comp
2.3 V
0V
PFC is Off
PFC is Off
No Delay
100 ms
Delay
PFC is On
PFC is On
Figure 33. Skip Mode
18 k
CS
Rcomp
+
LEB
−
Leaving standby (Skip Mode)
Rsense
When the feedback voltage rises above the 1.25 volts
reference (leaving standby) the skip cycle activity stops and
SW1 immediately closes and restarts the PFC, there is no
delay in turning on SW1 under these conditions.
Fb/3
Figure 34.
Current Sense
The NCP1231 is a peak current mode controller, where
the current sense input is internally clamped to 1 V, so the
sense resister is determined by Rsense = 1 V/Ipk maximum.
There is a 18k resistor connected to the CS pin, the other
end of the 18k resistor is connect to the output of the internal
oscillator for ramp compensation (refer to Figure 34).
Leading Edge Blanking
In Switch Mode Power Supplies (SMPS) there can be a
large current spike at the beginning of the current ramp due
to the Power Switch gate to source capacitance, transformer
interwinding capacitance, and output rectifier recovery
time. To prevent prematurely turning off the PWM drive
output, a Leading Edges Blanking (LEB) (Figure 35) circuit
is place is series with the current sense input, and PWM
comparator. The LEB circuit masks the first 250 ns of the
current sense signal.
Ramp Compensation
In Switch Mode Power Supplies operating in Continuous
Conduction Mode (CCM) with a duty−cycle greater than
50%, oscillation will take place at half the switching
frequency. To eliminate this condition, Ramp Compensation
can be added to the current sense signal to cure sub harmonic
oscillations. To lower the current loop gain one typically
injects between 50 and 100% of the inductor down slope.
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14
NCP1231
Thermal Shutdown
Skip
high, a 100 ms timer starts. If at the end of the 100 ms timeout
period, the error flag is still asserted then the controller
determines that there is a true fault condition and stops the
PWM drive output, refer to Figure 36. When this occurs,
100 msec Timer
2.3 Vpp
Ramp
PWM Comparator
−
FB/3
+
V
CC
starts to decrease because the power supply is locked
Vccreset
R Q
18 k
LEB
out. When V drops below UVLOlow (7.7 V typical), it
CC
CS
+
−
enters a latch−off phase where the internal consumption is
reduced down to 30 ꢀ A. This reduction in current allows the
3
S
250 ns
10 V
Latch−Off
V
CC
capacitor to be charged up through the external startup
3 V
resistor, when V reaches V ON (12.6 V), the soft−start
CC
CC
circuit is activated and the controller goes through a normal
startup. If the fault has gone and the error flag is low, the
controller resumes normal operations.
Figure 35.
Under transient load conditions, if the error flag is
asserted, the error flag will normally drop prior to the 100 ms
timeout period and the controller continues to operate
normally.
If the 100 msec timer expires while the NCP1231 is in the
Skip Mode, SW1 opens and the PFC_Vcc output will shut
down and will not be activated until the fault goes away and
the power supply resumes normal operations.
Short−Circuit Condition
The NCP1231 is different from other controllers which
uses auxiliary windings to detect events on the isolated
secondary output. There maybe some conditions (for
example when the leakage inductance is high) where it can
be extremely difficult to implement short−circuit and
overload protection. This occurs because when the power
switch opens, the leakage inductance superimposes a large
spike on the switch drain voltage. This spike is seen on the
isolated secondary output and on the auxiliary winding.
Because the auxiliary winding and diode form a peak
While in the Skip Mode, to avoid any thermal runaway it
is desirable for the skip duty cycle to be kept below 20%(the
burst duty−cycle is defined as Tpulse / Tfault).
The latch−off phase can also be initiated, more classically,
rectifier, the auxiliary V capacitor voltage can be charged
CC
when V drops below UVLO (7.7 V typical). During this
CC
up to the peak value rather than the true plateau which is
proportional to the output level.
To resolve these issues the NCP1231 monitors the 1.0 V
error flag. As soon as the internal 1.0 V error flag is asserted
fault detection method, the controller will not wait for the
100 ms time−out, or the error flag before it goes into the
latch−off phase, operating in the skip mode under these
conditions.
regulation
regulation
Short−circuit
Stby
stby is left
12.6V
7.7V
Nom
Pout
Vcc
PWM
100ms
Timer
100ms
100ms
100ms
100ms
5ms
SS
1.0 V
Flag
Pin1
PFC
Vcc
Stby
confirmed
Figure 36.
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15
NCP1231
Drive Output
The NCP1231 provides a Drive Output which can be
connected through a current limiting resistor to the gate of
a MOSFET. The Driver output is capable of delivering drive
pulses with a rise time of 40 ns, and a fall time of 15 ns
through its internal source and sink resistance of 12.3 ohms
(typical), measured with a 1.0 nF capacitive load.
High Voltage
Rstartup
max
30 ꢀ A
6
UVLO
−
+
Startup Sequence
+
Auxliary
winding
When the power supply is first connected to the mains
outlet, current flows through Rstartup, charging the Vcc
capacitor (refer to Figure 37). When the voltage on the Vcc
capacitors reaches VccON level (typically 12.6 V), the
NCP1231 then turns on the drive output to the external
MOSFET in an attempt to increase the output voltage and
charge up the Vcc capacitor through the Vaux winding in the
transformer.
CVcc
+
12.6 V /
7.7 V
4
Figure 37.
During the startup sequence, the controller pushes for the
maximum peak current, which is reached after the 5 ms
soft−start period (adjustable). As soon as the maximum peak
set point is reached, the internal 1.0 V clamp actively limits
the current amplitude to 1.0 V/Rsense and asserts an error
flag indicating that a maximum current condition is being
observed. In this mode, the controller must determine if it is
a normal startup period (or transient load) or is the controller
is facing a fault condition. To determine the difference
between a normal startup sequence, and a fault condition, the
error flag is asserted, and the 100 ms timer starts to count
down. If the error flag drops prior to the 100 ms time−out
period, the controller resets the timer and determines that it
was a normal star−up sequence and enables the low
impedance switch (SW1), enabling the PFC_Vcc output.
If at the end of the 100 ms period the error flag is still
asserted, then the controller assumes that it is a fault
condition and the PWM controller enters the skip mode and
does not enable the PFC_Vcc output.
Soft−Start
The NCP1231 features an adjustable soft−start circuit. As
soon as Vcc reaches a nominal 12.6 V, the soft−start circuit
is activated. The soft−start circuit output controls a reference
on the minus (−) input to an amplifier (refer to Figure 38),
the positive (+) input to the amplifier is the feedback input
(divided by 3). The output of the amplifier drives a FET
which clamps the feedback signal. As the soft−start circuit
output ramps up, it allow the feedback pin input to the PWM
comparator to gradually increased from near zero up to the
maximum clamping level of 1 V/Rsense. This occurs over
the entire 5 ms soft−start period until the supply enters
regulation. The soft−start is also activated every time a
restart is attempted. Figure 39 shows a typical soft−start up
sequence (with soft−start), normal operation (frequency
jittering), and a confirmed over load conditon (100 msec
timeout).
Vdd
Vdd
20k
Error
Skip
Comparators
55k
FB
2
PWM
−
+
10 V 25k
CS
+
−
5 msec
OSC
Timer
Soft−Start
Ramp (1V max)
Figure 38.
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16
NCP1231
Figure 39 shows the details of the internal circuitry
charge and discharge current sources are 60 ꢀ a (typical), so
if a 82 nF capacitor is connected to Pin 7, one can achieve
a typical soft−start of 5 ms, a frequency modulation of 5 ms
and a fault timeout of 100 ms.
implemented in the NCP1231. The NCP1231 Pin 7 can
perform three different functions; 1) soft−start 2) EMI
jittering and 3) short−circuit timeout (Fault Timer). The
Fault not
confirmed
Fault
confirmed
Fault management
100ms
Jittering 10ms
100ms
Time scale
has been
purposely
reduced
4V
60ꢀ A
2V
0V
f
max
SS
5ms
f
min
SS
5ms
1V Error
Flag
Reset at UVLO
Fault
signal
Drv
Time scale
has been
purposely
reduced
Figure 39. Soft−Start is Activated during a Startup Sequence an OCP Condition
Vd
Frequency Jittering
Frequency jittering is a method used to soften the EMI
Vref1
4 V
+
+
signature by spreading out the average switching energy
around the controller operating switching frequency. The
NCP1231 offers a nominal ±4% deviation of the nominal
switching frequency. The sweep sawtooth is internally
generated and modulates the clock up and down with a 4 ms
period. Figure 41 illustrates the NCP1231 behavior:
−
Fault
−
+
Icharge1
Icharge
Soft−
jittering
7
Css
Idischarge
+
−
+
Vref2
2.2 V
Figure 40. Internal Soft−Start, 100 msec Timer and
Frequency Jittering
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17
NCP1231
Internal Ramp
62.4 kHz
65 kHz
Internal Sawtooth
67.6 kHz
4 ms
Figure 41. An Internal Ramp is used to Introduce Frequency Jittering on the Oscillator Saw Tooth
Overvoltage Protection
BO comparators because the voltage on the bulk energy
storage capacitor ripple voltage is affected by the input
voltage and output power level. For this reason when BO
comparator toggles, the internal reference changes from
500 mV to 230 mV. This effect is not latched, as soon as the
input ac voltage in back within the normal operating range
and the voltage on the bulk energy storage capacitor is back
to normal range, the controller resume normal operation.
The lower threshold (VBLow) is the level at which the
drive output is disabled. This level is dependent on the ripple
voltage on Pin 8. A capacitor can be added between Pin 8 and
ground to select the amount of ripple voltage. The larger the
capacitor, the lower the ripple voltage, the greater the
amount of hysteresis.
The NCP1231 combines an over and under−voltage
protection on Pin 8. Figure 39 shows the internal component
configuration inside the chip. When the voltage on Pin 8 is
above 4.2 V then an OVP signal permanently latches off the
controller; all output drive pulses are stopped and the Vcc Pin
6 ramps up and down between Vccon and Vccmin until the
user unplugs the converter power allows Vcc to drop below
Vccreset (4.0 V). By bringing Vcc down to the reset voltage
(around 4.0 V), the latch is released and the IC can restart.
4V
+
Latchoff
OVP
8
from
PWM
+
−
+
Thermal Protection
An internal Thermal Shutdown is provided to protect the
integrated circuit in the event that the maximum junction
temperature is exceeded. When activated (160 °C typically)
the controller turns off the PWM Drive Output. When this
occurs, Vcc will drop (the rate is dependent on the NCP1231
loading and the size of the Vcc capacitor) because the
controller is no longer delivering drive pulses to the
auxiliary winding charging up the Vcc capacitor. When Vcc
drops below 4.0 volts and the Vccreset circuit is activated,
the controller will restart. If the user is using a fixed bias
supply (the bias supply is provided from a source other than
from an auxiliary winding, refer to the typical application )
and Vcc is not allow to drop below 4.0 volts under a thermal
shutdown condition, the NCP1231 will not restart. This
feature is provided to prevent catastrophic failure from
accidentally overheating the device.
0.5 / 0.23
Brown
Out
to Dr
By arranging two comparators on the same pin, both
OVP and under voltage sensing can be implemented.
Figure 42.
Brown−Out Protection
A Brown−Out (BO) protection feature prevents the power
supply for being over stressed when the main input power
drops below the typical universal input range of 85−265 Vac.
When this occurs, the controller stops the drive output and
waits for normal power to resume. Hysteresis is used on the
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18
NCP1231
ORDERING INFORMATION
†
Device
NCP1231D65R2
Package
Shipping
SOIC−8
NCP1231D65R2G
SOIC−8
(Pb−Free)
NCP1231D100R2
NCP1231D100R2G
SOIC−8
2500/Tape & Reel
SOIC−8
(Pb−Free)
NCP1231D133R2
NCP1231D133R2G
SOIC−8
SOIC−8
(Pb−Free)
NCP1231P65
PDIP−8
NCP1231P65G
PDIP−8
(Pb−Free)
NCP1231P100
PDIP−8
50 Units/Rail
NCP1231P100G
PDIP−8
(Pb−Free)
NCP1231P133
PDIP−8
PDIP−8
(Pb−Free)
NCP1231P133G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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19
NCP1231
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)
Z
Y
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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20
NCP1231
PACKAGE DIMENSIONS
8−LEAD PDIP
P SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8
5
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−B−
1
4
MILLIMETERS
INCHES
MIN
0.370
DIM MIN
MAX
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
10.16
F
6.60 0.240
4.45 0.155
0.51 0.015
1.78 0.040
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27 0.030
0.30 0.008
0.050
0.012
0.135
K
L
3.43
0.115
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
−−−
1.01 0.030
10
_
0.040
_
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
B
0.13 (0.005)
T A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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Email: orderlit@onsemi.com
For additional information, please contact your local
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NCP1231/D
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