NCP12401EADBB1
更新时间：2024-10-29 22:53:23
品牌：ONSEMI
描述：Fixed Frequency Current Mode Controller for Flyback Converters
概述
数据手册NCP12401EADBB1 概述
Fixed Frequency Current Mode Controller for Flyback Converters
NCP12401EADBB1 数据手册
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PDF下载Fixed Frequency Current
Mode Controller for Flyback
Converters
NCP12401
The NCP12401 is a new fixed−frequency current−mode controller
featuring the Dynamic Self−Supply. This function greatly simplifies
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the design of the auxiliary supply and the V capacitor by activating
CC
the internal startup current source to supply the controller during
start−up, transients, latch, stand−by etc. This device contains a special
HV detector which detects the application unplug from the ac input
line and triggers the X2 discharge current. This HV structure allows
the brown−out detection as well.
SOIC−7
It features a timer−based fault detection that ensures the detection of
overload and an adjustable compensation to help keep the maximum
power independent of the input voltage.
Due to frequency foldback, the controller exhibits excellent
efficiency in light load condition while still achieving very low
standby power consumption. Internal frequency jittering, ramp
compensation, and a versatile latch input make this controller an
excellent candidate for the robust power supply designs.
CASE 751U
MARKING DIAGRAM
8
XXXXX
ALYWG
G
1
A dedicated Off Mode allows to reach the extremely low no load
input power consumption via “sleeping” whole device and thus
minimize the power consumption of the control circuitry.
401VWXYZf
= Specific Device Code
(see page 2)
= Assembly Location
= Wafer Lot
= Year
= Work Week
A
L
Y
W
G
Features
• Fixed−Frequency Current−Mode Operation 65 kHz or 100 kHz
Frequency Options
= Pb−Free Package
• Frequency Foldback then Skip Mode for Maximized Performance
(Note: Microdot may be in either location)
in Light Load and Standby Conditions
• Timer−Based Overload Protection with Latched (Option A) or
Autorecovery (Option B) Operation
PIN CONNECTIONS
1
4
8
5
• High−Voltage Current Source with Brown−Out Detection and
FAULT
FB
HV
Dynamic Self−Supply, Simplifying the Design of the V Circuitry
CC
• Frequency Modulation for Softened EMI Signature
CS
V
CC
• Adjustable Overpower Protection Dependant on the Mains Voltage
• Fault Input for Overvoltage and Over Temperature Protection
GND
DRV
(Top View)
• V Operation up to 28 V, with Overvoltage Detection
CC
• 300/500 mA Source/Sink Drive Peak Current Capability
• 4/10 ms Soft−Start
ORDERING INFORMATION
See detailed ordering and shipping information on page 43 of
this data sheet.
• Internal Thermal Shutdown
• No−Load Standby Power < 30 mW
• X2 Capacitor in EMI Filter Discharging Feature
• These are Pb−Free Devices
Typical Applications
• Offline Adapters for Notebooks, LCD, and Printers
• Offline Battery Chargers
• Consumer Electronic Power Supplies
• Auxiliary/Housekeeping Power Supplies
• Offline Adapters for Notebooks
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
July, 2020 − Rev. 1
NCP12401/D
NCP12401
TYPICAL APPLICATION SCHEMATIC
NCP12401
Figure 1. Flyback Converter Application using the NCP12401
Table 1. OPTIONS
Brown Out
Start−Stop
Frozen Current
Setpoint
OPN
OCP Fault
Quiet Skip
Soft Start Frequency
NCP12401CBEAB0DR2G
NCP12401EBEAB0DR2G
95 − 93 V
Autorecovery
210 mV
210 mV
No, min. 3 pulses only
No, min. 3 pulses only
4 ms
4 ms
65 kHz
65 kHz
Brown in, no BO Autorecovery
Table 2. SPECIFIC DEVICE CODE KEY
401
V
W
X
Y
Z
f
Part
BO
OCP Fault
Frozen Current
Setpoint
Quiet Skip
Soft Start
Frequency
A − 229−211 V
B − 111−103 V
C − 95−93 V
A − Latched
B − Autorecovery
A −No
A − No, min. 3
A − 10 ms
B − 4 ms
0 − 65 kHz
B − 150 mV
C − 170 mV
D − 190 mV
E − 210 mV
F − 230 mV
G − 250 mV
H − 300 mV
pulses
1 − 100 kHz
2 − 65 → 100 kHz
D − No BO
B − Yes, min. 3
pulses,
800 Hz burst
E − Brown In, no BO
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2
NCP12401
Table 3. PIN FUNCTION DESCRIPTION
Pin #
Pin Name
Function
Pin Description
1
FAULT
FAULT Input
Pull the pin up or down to stop the controller. An internal current source allows the
direct connection of an NTC for over temperature detection. Device can restart in
autorecovery mode or can be latched depending on the option.
2
3
FB
CS
Feedback + Shutdown An optocoupler connected to ground controls the output regulation. The part goes to
Pin
the low consumption Off mode if the FB input pin is pulled to GND.
Current Sense
This input senses the primary current for current−mode operation, and offers an
overpower compensation adjustment. This pin implements over voltage protection
as well.
4
5
6
GND
DRV
The controller ground.
Drive Output
Drives external MOSFET.
V
CC
V
CC
Input
This supply pin accepts up to 28 Vdc, with overvoltage detection. The pin is
connected to an external auxiliary voltage.
8
HV
High−Voltage Pin
Connects to the rectified ac line to perform the functions of start−up current source,
Self−Supply, brown−out detection and X2 capacitor discharge function and the HV
sensing for the overpower protection purposes.
It is not allowed to connect this pin to a dc voltage.
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3
NCP12401
SIMPLIFIED INTERNAL BLOCK SCHEMATIC
Vdd
Vhv DC sample
HV
Brown_In
AC_Off
OVP_CMP
OTP_CMP
55us
Filter
OVP
VccOVP_CMP
VccOVP 10us
Filter
OM & X2 & Vcc
FAULT
Dual HV
start−up
control
current source
TSD
300 us OTP
Filter
VCC
Vcc_Int
UVLO_CMP
Vcc regulator
UVLO
X 2 discharge
11 V regulator
Vdd reg
Vdd
Latch
Set
Q
PowerOnReset _CMP
RESET
ON_CMP
Brown_Out
RESET
Rese t Qb
VccON
STOP_CMP
VccMIN
VCC
Off_mode_CMP1
Off_mode_CMP2
ICstart
Set
Q
Reset Qb
GoToOffMode timer 500ms
jittering
FM input
Square output
OSC 65kHz
Vfb(reg)
ton_max output
3. 0V
freq folback
CSref
PFM input
Ramp_OTA
Saw output
FB
FBbuffer
4uMho
Skip_CMP
SkipB
VCC
Clamp
MAX_ton
DRV
Set
Q
PWM_CMP
IC stopB
PWM
Reset Qb
SoftStart_CMP
V to I
LEB 250 ns
Iopc = 0.5u*(Vhv −125)
Enable
SS_end
Soft Start timer
Vdd
Ilimit_CMP
MAX_ton
Ilimit
Fault
RESET
CS
Set
Q
Fault timer
IC stop
Latch
Vfb < 1.64 V fix current setpoint 210mV
Reset Qb
CSstop_CMP
LEB 120 ns
4 events timer
Brown_Out
TSD
GND
TSD
OVP_CMP
LEB 1 us
600ns timer
4 events timer
DRV
Figure 2. Simplified Internal Block Schematic
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4
NCP12401
Table 4. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
DRV
(pin 5)
Maximum voltage on DRV pin
(Dc−Current self−limited if operated within the allowed range) (Note 2)
–0.3 to 20
1000 (peak)
V
mA
V
V
Power Supply voltage, V pin, continuous voltage
–0.3 to 36
30 (peak)
V
mA
CC
CC
CC
(pin 6)
Power Supply voltage, V pin, continuous voltage (Note 2)
CC
HV
(pin 8)
Maximum voltage on HV pin
(Dc−Current self−limited if operated within the allowed range)
–0.3 to 500
20
V
mA
V
max
Maximum voltage on low power pins (except pin 5, pin 6 and pin 8)
(Dc−Current self−limited if operated within the allowed range) (Note 2)
–0.3 to 5.5
10 (peak)
V
mA
R
Thermal Resistance SOIC−7
°C/W
q
J−A
Junction-to-Air, low conductivity PCB (Note 3)
Junction-to-Air, medium conductivity PCB (Note 4)
Junction-to-Air, high conductivity PCB (Note 5)
162
147
115
R
Thermal Resistance Junction−to−Case
Operating Junction Temperature
73
°C/W
°C
°C
V
q
J−C
T
JMAX
−40 to +150
−60 to +150
> 4000
T
Storage Temperature Range
STRGMAX
ESD Capability, HBM model (All pins except HV) (Note 1)
ESD Capability, HBM model (pin 8, HV)
ESD Capability, Charge Discharge Model (Note 1)
> 2000
V
> 500
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 4000 V per JEDEC standard JESD22, Method A114E
Charge Discharge Model Method 500 V per JEDEC standard JESD22, Method C101E
2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
2
3. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-1 conductivity test PCB. Test conditions were under natural convection or zero air flow.
2
4. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 100 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-2 conductivity test PCB. Test conditions were under natural convection or zero air flow.
2
5. As mounted on a 80 x 100 x 1.5 mm FR4 substrate with a single layer of 650 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51-3 conductivity test PCB. Test conditions were under natural convection or zero air flow.
Table 5. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 125 V, V = 11 V unless otherwise noted)
J
J
HV
CC
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
HIGH VOLTAGE CURRENT SOURCE
Minimum voltage for current source
operation
V
−
30
40
V
HV(min)
Current flowing out of V pin
V
= 0 V
CC(on)
I
I
0.2
5
0.5
8
0.8
11
mA
mA
CC
CC
start1
start2
V
= V
− 0.5 V
CC
Off−state leakage current
V
HV
= 500 V, V = 15 V
I
start(off)
−
2
6
CC
SUPPLY
Turn−on threshold level, V going up
HV current source stop threshold
(depending on the version)
V
CC(on)
11.0
15.0
12.0
16.2
13.0
17.5
V
CC
HV current source restart threshold
V
V
9.5
8.4
10.5
8.9
11.5
9.3
V
V
V
CC(min)
Turn−off threshold
V
CC(off)
Overvoltage threshold
Overvoltage threshold (option EAHBB,
BBBBB)
25
30
26.5
32
28
34
CC(ovp)
Blanking duration on V
detection
and V
t
VCC(blank)
−
10
−
ms
CC(off)
CC(ovp)
6. Guaranteed by design.
7. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
bias
OPC
HV
bias
OPC
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5
NCP12401
Table 5. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 125 V, V = 11 V unless otherwise noted)
J
J
HV
CC
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
SUPPLY
decreasing level at which the internal
V
V
4.8
1.0
7.0
2.1
7.7
3.0
V
V
CC
CC(reset)
V
CC(inhibit)
logic resets
V
CC
level for I
to I transition
START2
START1
Internal current consumption
DRV open, V = 3 V, 65 kHz
I
1.0
1.1
1.3
1.4
2.0
2.1
mA
mA
FB
CC1
DRV open, V = 3 V, 100 kHz
FB
Cdrv = 1 nF, V = 3 V, 65 kHz
I
1.5
2.0
2.1
2.6
2.9
3.4
mA
mA
FB
CC2
Cdrv = 1 nF, V = 3 V, 100 kHz
FB
Skip or before start−up
Fault mode (fault or latch)
Off−mode
I
I
I
400
300
−
500
430
25
650
550
−
mA
mA
mA
CC3
CC4
CC5
BROWN−OUT
Brown−out thresholds (option A)
V
going up
V
210
194
229
211
248
228
V
V
V
V
HV
HV(start)
HV(stop)
V
V
V
V
going down
V
HV
Brown−out thresholds (option B)
V
HV
going up
going down
V
V
102
94
111
103
120
116
HV(start)
HV(stop)
HV
Brown−out thresholds (option BAHAB)
Brown−out thresholds (option C)
Brown−out thresholds (option E)
V
HV
going up
going down
V
V
93
90
103
100
113
110
HV(start)
HV(stop)
HV
V
HV
going up
going down
V
V
87
85
95
93
103
101
HV(start)
HV(stop)
HV
V
HV
going up
V
90
100
110
V
HV(start)
Timer duration for line cycle drop−out
(depending on the version)
t
42
48
64
73
86
98
ms
HV
X2 DISCHARGE
Comparator hysteresis observed at HV pin
HV signal sampling period
V
2.0
−
3.0
1.0
32
4.0
−
V
HV(hyst)
t
ms
ms
ms
V
sample
Timer duration for no line detection
Discharge timer duration
t
21
43
DET
t
21
32
43
DIS
Shunt regulator voltage at VCC pin during X2
discharge event
V
10.0
11.0
12.0
CC(dis)
OSCILLATOR
Oscillator frequency 65 kHz version
Oscillator frequency 100 kHz version
f
61
94
65
69
kHz
%
OSC
100
110
Maximum duty−ratio (corresponding to
maximum on time at maximum switching
frequency)
D
75
80
85
MAX
Frequency jittering amplitude, in percentage
A
F
3.0
85
4.0
5.0
kHz
Hz
jitter
of F
OSC
Frequency jittering modulation frequency
125
165
jitter
FREQUENCY FOLDBACK
Feedback voltage threshold below which
frequency foldback starts
T = 25°C
V
V
1.9
1.1
25
2.05
1.3
28
2.2
1.5
31
V
V
J
FB(foldS)
FB(foldE)
OSC(min)
Feedback voltage threshold below which
frequency foldback is complete
T = 25°C
J
Minimum switching frequency
6. Guaranteed by design.
V
FB
= V
+ 0.1
f
kHz
skip(in)
7. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
bias
OPC
HV
bias
OPC
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6
NCP12401
Table 5. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 125 V, V = 11 V unless otherwise noted)
J
J
HV
CC
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
OUTPUT DRIVER
Rise time, 10 to 90% of V
V
V
= V
DRV
+ 0.2 V,
t
rise
−
−
40
30
70
60
ns
ns
CC
CC
CC(off)
C
= 1 nF
Fall time, 90 to 10% of V
Current capability
= V
DRV
+ 0.2 V,
= 1 nF
t
fall
CC
CC
CC(off)
C
V
= V
+ 0.2 V,
= 1 nF
mA
CC
CC(off)
C
DRV
DRV high, V
DRV low, V
= 0 V
CC
I
−
−
300
500
−
−
DRV
DRV
DRV(source)
DRV(sink)
= V
I
Clamping voltage (maximum gate voltage)
V
CC
R
= V
DRV
– 0.2 V, DRV high,
V
10
12
14
V
V
CC(ovp)
DRV(clamp)
= 33 kW, C
= 220 pF
load
High−state voltage drop
V
DRV
= V
+ 0.2 V,
V
DRV(drop)
−
−
1
CC
CC(min)
R
= 33 kW, DRV high
CURRENT SENSE
Input Pull−up Current
V
= 0.7 V
> 3.5 V
I
−
0.66
−
1
−
mA
V
CS
bias
Maximum internal current setpoint
V
V
0.70
50
0.74
70
FB
CS
ILIM
Propagation delay from V
DRV off
detection to
V
= V
t
ns
Ilimit
ILIM
delay
Leading Edge Blanking Duration for V
t
180
250
320
ns
V
ILIM
LEB
Threshold for immediate fault protection
activation
V
0.95
1.05
1.15
CS(stop)
Leading Edge Blanking Duration for V
(Note 6)
t
75
120
150
ns
ms
mV
CS(stop)
BCS
st
Soft−start duration (option A)
Soft−start duration (option B)
From 1 pulse to V = V
t
SSTART
−
3.2
10
4.0
13
4.8
CS
ILIM
Frozen current setpoint (option B)
Frozen current setpoint (option D)
Frozen current setpoint (option E)
Frozen current setpoint (option H)
V
100
140
145
250
150
190
210
300
200
240
270
350
I(freeze)
Over voltage protection threshold when DRV
is low
V
CS
going up
V
t
1.00
1.05
1.10
V
OVP(CS)
Blanking duration on OVP detection
Delay time constant before OTP confirmation
INTERNAL SLOPE COMPENSATION
Slope of the compensation ramp
0.7
1.0
1.3
ms
OVP,CS
t
−
600
−
ns
OVP,del
S
S
−
−
−32.5
−50
−
−
mV /
ms
comp(65kHz)
comp(100kHz)
FEEDBACK
Internal pull−up resistor
T = 25°C
J
R
30
40
4
50
kW
FB(up)
V
FB
to internal current setpoint division ratio
K
FB
−
−
−
(Note 6)
Internal pull−up voltage on the FB pin
V
V
4.5
5
5.5
V
V
FB(ref)
Offset between FB pin and internal FB
divider
T = 25°C
J
−
0.8
−
FB(off)
SKIP CYCLE MODE
Feedback voltage thresholds for skip mode
V
FB
V
going down, T = 25°C
V
0.9
1.05
1.0
1.15
1.1
1.25
V
J
skip(in)
going up, T = 25°C
V
FB
J
skip(out)
Minimum number of pulses in burst
Skip out delay
n
3
−
−
−
P,skip
t
−
38
ms
skip
6. Guaranteed by design.
7. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
bias
OPC
HV
bias
OPC
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7
NCP12401
Table 5. ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 125 V, V = 11 V unless otherwise noted)
J
J
HV
CC
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
REMOTE CONTROL ON FB PIN
The voltage above which the part enters the
on mode
V
> V
, V = 60 V
V
ON
−
2.2
0.6
−
−
0.7
−
V
V
CC
CC(off) HV
The voltage below which the part enters the
off mode
V
CC
> V
V
OFF
0.5
500
CC(off)
Minimum hysteresis between the V and
V
CC
> V
, V = 60 V
V
HYST
mV
ON
CC(off) HV
V
OFF
Pull−up current in off mode
Go To Off mode timer
V
V
> V
> V
I
−
5
−
mA
CC
CC(off)
OFF
t
400
500
600
ms
CC
CC(off)
GTOM
OVERLOAD PROTECTION
Fault timer duration
t
108
150
0.85
128
200
1.00
178
250
1.35
ms
ms
s
fault
Fault timer reset time
V
CS
< 0.7 V, D < 90% D
t
fault,res
MAX
Autorecovery mode latch−off time duration
OVERPOWER PROTECTION
t
autorec
V
to I
conversion ratio
K
OPC
−
0.54
−
mA / V
mA
HV
OPC
Current flowing out of CS pin (Note 7)
V
HV
V
HV
V
HV
V
HV
= 125 V
= 162 V
= 325 V
= 365 V
I
I
I
I
−
−
−
0
20
110
130
−
−
−
OPC(125)
OPC(162)
OPC(325)
OPC(365)
105
150
FB voltage above which I
is applied
V
HV
V
HV
= 365 V
= 365 V
V
V
−
−
2.6
1.6
−
−
V
V
OPC
FB(OPCF)
FB voltage below which is no I
FAULT INPUT
applied
OPC
FB(OPCE)
High threshold
V
going up
V
V
2.43
0.380
7.6
2.50
0.400
8.0
2.57
0.420
8.5
V
V
Latch
OVP
Low threshold
V
going down, T = 25°C
Latch J
OTP
OTP resistance threshold (T = 25°C)
External NTC resistance is going
down
R
R
R
kW
J
OTP
OTP
OTP
OTP resistance threshold (T = 80°C)
External NTC resistance is going
down
−
−
8.5
9.5
−
−
kW
kW
mA
J
OTP resistance threshold (T = 110°C)
External NTC resistance is going
down
J
Current source for direct NTC connection
During normal operation
During soft−start
V
= 0.2 V
Latch
I
30
60
50
100
70
140
NTC
I
NTC(SSTART)
Current source for direct NTC connection
During normal operation
V
Latch
= 0.2 V, T = 25°C
I
NTC
47
50
53
mA
J
Blanking duration on high latch detection
Blanking duration on low latch detection
Clamping voltage
t
35
50
70
ms
ms
V
Latch(OVP)
t
−
350
−
Latch(OTP)
I
= 0 mA
= 1 mA
V
V
1.0
1.8
1.2
2.4
1.4
3.0
Latch
Latch
clamp0(Latch)
clamp1(Latch)
I
TEMPERATURE SHUTDOWN
Temperature shutdown
T going up
T
−
−
150
30
−
−
°C
°C
J
TSD
T
TSD(HYS)
Temperature shutdown hysteresis
T going down
J
6. Guaranteed by design.
7. CS pin source current is a sum of I
and I
, thus at V = 125 V is observed the I
only, because I
is switched off.
bias
OPC
HV
bias
OPC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP12401
TYPICAL CHARACTERISTIC
Figure 3. Minimum Voltage for HV Current Source
Figure 4. High Voltage Startup Current Flowing
Out of VCC Pin Istart1 of VCC Pin Fault/Short
Operation VHV(min)
Figure 5. HV Pin Device Startup Threshold
VHV(start)
Figure 6. Off−state Leakage Current from HV Pin
Istart(off)
Figure 7. High Voltage Startup Current Flowing
Out of VCC Pin Istart2
Figure 8. HV Pin Device Stop Threshold VHV(stop)
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NCP12401
Figure 9. Maximum Internal Current Setpoint
VILIM
Figure 10. Threshold for the Very Fast Fault
Protection Activation VCS(stop)
Figure 11. Propagation Delay tdelay
Figure 12. Frozen Current Setpoint VI(freeze) for the
Light Load Operation
Figure 13. Over Voltage Protection Threshold at
CS Pin VOVP(CS)
Figure 14. Leading Edge Blanking Duration tLEB
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NCP12401
Figure 15. FB Pin Internal Pull−up Resistor
Figure 16. Built in Offset between FB Pin and
Internal Divider VFB(off)
RFB(up)
Figure 17. FB Pin Skip−In and Skip−Out Levels
Figure 18. FB Pin Open Voltage VFB(ref)
V
skip(in) and Vskip(out)
Figure 19. FB Pin Frequency Foldback Thresholds
FB(foldS) and VFB(foldE)
V
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NCP12401
Figure 20. Oscillator Switching Frequency fOSC
Figure 21. Minimum Switching Frequency
fOSC(min)
Figure 22. X2 Discharge Comparator Hysteresis
Observed at HV Pin VHV(hyst)
Figure 23. Maximum Duty Cycle DMAX
Figure 24. The Fault Timer Duration tfault
Figure 25. HV Signal Sampling Period Tsample
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NCP12401
Figure 26. VCC Turn−on Threshold Level, VCC Going
Figure 27. VCC Turn−off Threshold (UVLO) VCC(off)
Up HV Current Source Stop Threshold VCC(on)
Figure 28. Internal Current Consumption when
DRV Pin is Unloaded ICC1
Figure 29. HV Current Source Restart Threshold
VCC(min)
Figure 30. VCC Decreasing Level at which the
Internal Logic Resets VCC(reset)
Figure 31. Internal Current Consumption when
DRV Pin is Loaded by 1 nF Capacitance ICC2
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NCP12401
Figure 32. Internal Current Consumption in Skip
Mode ICC3
Figure 33. FB Pin Voltage Level Above which is
Entered Normal Operating Mode VON
Figure 34. Go To Off Mode Timer Duration tGTOM
Figure 35. Internal Current Consumption in Off
Mode ICC5
Figure 36. FB Pin Voltage Level Below which is
Entered Off Mode VOFF
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NCP12401
Figure 37. FB Pin Voltage Thresholds for
Overpower Compensation
Figure 38. Fault Pin High Threshold for OVP VOVP
Figure 39. Current INTC Sourced Out from the
Fault Pin, allowing Direct NTC Connection
Figure 40. Current Flowing Out from CS Pin for
Over Power Compensation @ 365 V at HV Pin
IOPC(365)
NOTE: The OTP resistance maximum and minimum courses
are not the guaranteed limits, but the maximum and minimum
measured data values from the device characterization.
Figure 41. Fault Pin Low Threshold for OTP VOTP
Figure 42. The OTP Resistance Threshold ROTP
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NCP12401
APPLICATION INFORMATION
Functional Description
For loads that are between approximately 32% and 10%
of full rated power, the converter operates in frequency
foldback mode (FFM). If the feedback pin voltage is lower
than 1.4 V the peak switch current is kept constant and the
output voltage is regulated by modulating the switching
The NCP12401 includes all necessary features to build a
safe and efficient power supply based on a fixed−frequency
flyback converter. The NCP12401 is a multimode controller
as illustrated in Figure 43. The mode of operation depends
upon line and load condition. Under all modes of operation,
the NCP12401 terminates the DRV signal based on the
switch current. Thus, the NCP12401 always operates in
current mode control so that the power MOSFET current is
always limited.
Under normal operating conditions, the FB pin commands
the operating mode of the NCP12401 at the voltage
thresholds shown in Figure 43. At normal rated operating
loads (from 100% to approximately 33% full rated power)
the NCP12401 controls the converter in a fixed−frequency
PWM mode. It can operate in the continuous conduction
mode (CCM) or discontinuous conduction mode (DCM)
depending upon the input voltage and loading conditions. If
the controller is used in CCM with a wide input voltage
range, the duty−ratio may increase up to 50%. The build−in
slope compensation prevents the appearance of
sub−harmonic oscillations in this operating area.
frequency for a given and fixed input voltage V
.
HV
Effectively, operation in FFM results in the application of
constant volt−seconds to the flyback transformer each
switching cycle. Voltage regulation in FFM is achieved by
varying the switching frequency in the range from 65 kHz
to 28 kHz. For extremely light loads (below approximately
6% full rated power), the converter is controlled using bursts
of 28 kHz pulses. This mode is known as skip mode. The
FFM, keeping constant peak current and skip mode allows
design of the power supplies with increased efficiency under
the light loading conditions. Keep in mind that the
aforementioned boundaries of steady−state operation are
approximate because they are subject to converter design
parameters.
Low consumption off mode
ON
OFF
PWM at fOSC
FFM
Skip mode
0 V
VFBilim
V FB
VOFF
V
skip(in)
Vskip(out) VFB(foldE)
VON
V
FB(foldS)
Figure 43. Mode Control with FB Pin Voltage
There was implemented the low consumption off mode
allowing to reach extremely low no load input power. This
mode is controlled by the FB pin and allows the remote
control (or secondary side control) of the power supply
shut−down. Most of the device internal circuitry is unbiased
in the low consumption off mode. Only the FB pin control
circuitry and X2 cap discharging circuitry is operating in the
low consumption off mode. If the voltage at feedback pin
decreases below the 0.6 V the controller will enter the low
consumption off mode. The controller can start if the FB pin
voltage increases above the 2.2 V level.
See the detailed status diagrams for the both versions fully
latched A and the autorecovery B on the following figures.
The basic status of the device after wake–up by the V is
CC
the off mode and mode is used for the overheating protection
mode if the thermal shutdown protection is activated.
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NCP12401
Figure 44. Operating Status Diagram of the Device
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17
NCP12401
Figure 45. VCC Management Timing Diagram
Start−up of the Controller
At start−up, the current source turns on when the voltage
on the HV pin is higher than V , and turns off when
The information about the fault (permanent Latch or
Autorecovery) is kept during the low consumption off mode
due the safety reason. The reason is not to allow unlatch the
device by the remote control being in off mode.
HV(min)
V
CC
reaches V , then turns on again when V reaches
CC(on) CC
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NCP12401
V , until the input voltage is high enough to ensure a
CC(min)
the die would be too much. As a result, an auxiliary voltage
proper start−up, i.e. when V
reaches V
. The
source is needed to supply V during normal operation.
HV
HV(start)
CC
controller actually starts the next time V reaches V
.
The Dynamic Self−Supply is useful to keep the controller
alive when no switching pulses are delivered, e.g. in
brown−out condition, or to prevent the controller from
CC
CC(on)
The controller then delivers pulses, starting with a soft−start
period t during which the peak current linearly
SSTART
increases before the current−mode control takes over.
Even though the Dynamic Self−Supply is able to maintain
stopping during load transients when the V might drop.
The NCP12401 accepts a supply voltage as high as 28 V,
CC
the V voltage between V
and V
by turning
with an overvoltage threshold V
that latches the
CC
CC(on)
CC(min)
CC(ovp)
the HV start−up current source on and off, it can only be used
controller off.
in light load condition, otherwise the power dissipation on
VHV
VHV(start)
VHV(min)
Waits next
before starting
VCC(on)
time
VCC
VCC(on)
VCC(min)
HV current
source = Istart1
HV current
source = Istart2
VCC(inhibit)
time
time
DRV
Figure 46. VCC Start−up Timing Diagram
For safety reasons, the start−up current is lowered when
controller). There is only one condition for which the current
source doesn’t turn on when V reaches V : the
V
is below V
, to reduce the power dissipation in
CC
CC(inhibit)
CC
CC(inhibit)
case the V pin is shorted to GND (in case of V capacitor
voltage on HV pin is too low (below V
).
CC
CC
HV(min)
failure, or external pull−down on V
to disable the
CC
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NCP12401
VHV
VHV(start)
VHV(min)
Device starts at
VCC(on) event
time
VCC
VCC(on)
VCC(min)
VCC(off)
HV current
source = Istart2
HV current
source = Istart1
UVLO level VCC (off )
is trigged before OCP timer elapsed
VCC(inhibit)
time
DRV
Device stops thanks
to pre−short protection
time
Figure 47. Latch After the Preshort
HV Sensing of Rectified AC Voltage
thresholds are fixed, but they are designed to fit most of the
The NCP12401 features on its HV pin a true ac line
monitoring circuitry. It includes a minimum start−up
threshold and an autorecovery brown−out protection; both
of them independent of the ripple on the input voltage. It is
allowed only to work with an unfiltered, rectified ac input to
ensure the X2 capacitor discharge function as well, which is
described in following. The brown−out protection
standard ac−dc conversion applications.
When the input voltage goes below V
, a
HV(stop)
brown−out condition is detected, and the controller stops.
The HV current source maintains V between V and
CC
CC(on)
V
V
levels until the input voltage is back above
CC(min)
HV(start)
.
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NCP12401
HV timer elapsed
VHV
VHV (start )
VHV(stop)
time
HV stop
Brown−out
detected
tHV
time
Waits next
VccON before
starting
VCC
VCC(on)
VCC(min)
time
time
Brown−out
condition
resets the
DRV
Internal Latch
Figure 48. Ac Line Drop−out Timing Diagram
When V crosses the V
can start immediately. When it crosses V
threshold, the controller
drop−out. The device restart after the ac line voltage
drop−out is protected to the parasitic restart initiated e.g. the
spikes induced at HV pin immediately after the device is
stopped by the residual energy in the EMI filter. The device
HV
HV(start)
, it triggers
HV(stop)
a timer of duration t , this ensures that the controller
HV
doesn’t stop in case of line cycle drop−out.
st
When V crosses the V
threshold, the controller
restart is allowed only after the 1 watch dog signal event.
HV
HV(start)
starts when the V crosses the next V
event. When
The basic principle is shown at Figure 49 and detail of the
device restart is shown at Figure 50.
CC
CC(on)
it crosses V
, it triggers a timer of duration t , this
HV(stop)
HV
ensures that the controller doesn’t stop in case of line cycle
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21
NCP12401
HV timer elapsed
VHV
VHV(start)
VHV(stop)
time
Spike induced by
residual energy in
EMI filter
HV stop
Brown−out
detected
tHV
time
Waits next
VccON before
starting
VCC
VCC(on)
VCC(min)
time
time
Brown−out
condition
resets the
DRV
Internal Latch
Figure 49. Ac Line Drop−out Timing Diagram with the Parasitic Spike
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NCP12401
VHVSAMPLE
TSAMPLE
VHV(start )
VHV(stop )
VHV (hyst )
time
time
1st HV edge
resets the watch
dog and starts
the peak
detection of HV
pin signal
Comparator
Output
Sample clock
time
2nd sample clock
pulse after last
HV edge initiates
the watch dog
signal
2nd sample clock
Watch dog
signal
pulse after last
HV edge initiates
the watch dog
signal
time
time
HV stop
Device can restart after
1st Watch dog signal
when HV signal
Brown−out
detected
crosses V HV(start) level
tHV
VCC
VCC (on )
VCC(mini)
time
time
DRV
Device restarts
Device is stopped
Figure 50. Detailed Timing Diagram of the Device Restart after the Short ac Line Drop−out
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NCP12401
X2 Cap Discharge Feature
In case of the dc signal presence on the high voltage input,
the direct sample of the high voltage obtained via the high
voltage sensing structure and the delayed sample of the high
voltage are equivalent and the comparator produces the low
level signal during the presence of this signal. No edges are
present at the output of the comparator, that’s why the
detection timer is not reset and dc detect signal appears.
The minimum detectable slope by this ac detector is given
by the ration between the maximum hysteresis observed at
The X2 capacitor discharging feature is offered by usage
of the NCP12401. This feature save approx. 16 mW –
25 mW input power depending on the EMI filter X2
capacitors volume and it saves the external components
count as well. The discharge feature is ensured via the
start−up current source with a dedicated control circuitry for
this function. The X2 capacitors are being discharged by
current defined as I
when this need is detected.
start2
There is used a dedicated structure called ac line unplug
detector inside the X2 capacitor discharge control circuitry.
See the Figure 51 for the block diagram for this structure and
Figures 52, 53, 54 and 55 for the timing diagrams. The basic
idea of ac line unplug detector lies in comparison of the
direct sample of the high voltage obtained via the high
voltage sensing structure with the delayed sample of the high
voltage. The delayed signal is created by the sample & hold
structure.
HV pin V
and the sampling time:
HV(hyst),max
VHV(hyst),max
(eq. 1)
Smin
+
Tsample
Than it can be derived the relationship between the
minimum detectable slope and the amplitude and frequency
of the sinusoidal input voltage:
VHV(hyst),max
2 @ p @ f @ Tsample
5
2 @ p @ 35 @ 1 @ 10−3
Vmax
+
+
+
The comparator used for the comparison of these signals
is without hysteresis inside. The resolution between the
slopes of the ac signal and dc signal is defined by the
+ 22.7 V
(eq. 2)
sampling time T
and additional internal offset N
.
SAMPLE
OS
The minimum detectable AC RMS voltage is 16 V at
frequency 35 Hz, if the maximum hysteresis is 5 V and
sampling time is 1 ms.
The X2 capacitor discharge feature is available in any
controller operation mode to ensure this safety feature. The
detection timer is reused for the time limiting of the
discharge phase, to protect the device against overheating.
The discharging process is cyclic and continues until the ac
line is detected again or the voltage across the X2 capacitor
These parameters ensure the noise immunity as well. The
additional offset is added to the picture of the sampled HV
signal and its analog sum is stored in the C storage
1
capacitor. If the voltage level of the HV sensing structure
output crosses this level the comparator CMP output signal
resets the detection timer and no dc signal is detected. The
additional offset N can be measured as the V
on
OS
HV(hyst)
the HV pin. If the comparator output produces pulses it
means that the slope of input signal is higher than set
resolution level and the slope is positive. If the comparator
output produces the low level it means that the slope of input
signal is lower than set resolution level or the slope is
negative. There is used the detection timer which is reset by
any edge of the comparator output. It means if no edge
comes before the timer elapses there is present only dc signal
or signal with the small ac ripple at the HV pin. This type of
the ac detector detects only the positive slope, which fulfils
the requirements for the ac line presence detection.
is lower than V
. This feature ensures to discharge
HV(min)
quite big X2 capacitors used in the input line filter to the safe
level. It is important to note that it is not allowed to
connect HV pin to any dc voltage due this feature. e.g.
directly to bulk capacitor.
During the HV sensing or X2 cap discharging the V net
is kept above the V
mode of device operation to supply the control circuitry.
During the discharge sequence is not allowed to start−up the
device.
CC
voltage by the Self−Supply in any
CC(off)
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NCP12401
Figure 51. The ac Line Unplug Detector Structure Used for X2 Capacitor Discharge System
Figure 52. The ac Line Unplug Detector Timing Diagram
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NCP12401
Figure 53. The ac Line Unplug Detector Timing Diagram Detail with Noise Effects
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NCP12401
VHV
VHV(start)
X2 capacitor
discharge
AC line unplug
VHV(stop)
time
Starts
only at
VCC(on)
AC line Unplug
detector starts
HV
timer
starts
HV
timer
restarts
No AC detection
One Shot
tHV
tDET
time
DRV
Brown−out
X2 discharge
time
time
X2 discharge
current
tDIS
VCC
VCC(on)
VCC(dis)
VCC(min)
time
Figure 54. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence when the Application is
Unplugged Under Extremely Low Line Condition
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NCP12401
VHV
X2 capacitor
discharge
X2 capacitor
discharge
AC line unplug
VHV(start)
VHV(stop)
tHV
time
Starts
only at
VCC(on)
AC line Unplug
detector starts
HV
timer
starts
HV
timer
restarts
No AC detection
One Shot
tDET
tDET
time
DRV
Device is stopped
time
X2 discharge
X2 discharge
X2 discharge
current
tDIS
tDIS
time
time
VCC
VCC(dis)
Device shunts the
X2 discharge
current internally
Figure 55. HV Pin ac Input Timing Diagram with X2 Capacitor Discharge Sequence When the Application is
Unplugged Under High Line Condition
The Low Consumption Off Mode
Only the X2 cap discharge and Self−Supply features is
enabled in the low consumption off mode. The X2 cap
discharging feature is enable due the safety reasons and the
There was implemented the low consumption off mode
allowing to reach extremely low no load input power as
described in previous chapters. If the voltage at feedback pin
decreases below the 0.6 V the controller enters the off mode.
Self−Supply is enabled to keep the V supply, but only
CC
very low V consumption appears in this mode. Any other
CC
The internal V is turned−off, the IC consumes extremely
features are disabled in this mode.
CC
low V
current and only the voltage at external V
The information about the latch status of the device is kept
in the low consumption off mode and this mode is used for
the TSD protection as well. The protection timer
CC
CC
capacitor is maintained by the Dynamic Self−Supply circuit.
The Dynamic Self−Supply circuit keeps the V voltage
CC
between the V
and V
levels. The supply for the
GoToOffMode t
is used to protect the application
CC(on)
CC(off)
GTOM
FB pin watch dog circuitry and FB pin bias is provided via
the low consumption current sources from the external V
capacitor. The controller can only start, if the FB pin voltage
increases above the 2.2 V level. See Figure 56 for timing
diagrams.
against the false activation of the low consumption off mode
by the fast drop outs of the FB pin voltage below the 0.4 V
level. E.g. in case when is present high FB pin voltage ripple
during the skip mode.
CC
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NCP12401
VHV
DRV start
condition
AC line unplug
VHV(start)
X2 capacitor
discharge
X2 capacitor
discharge
time
VFB
Low consumption mode
Low consumption off mode
VON
Ready to RUN
tGTSG
VOFF
Starts
only at
VCC(on)
Dynamic
Self−Supply
in off mode
DSS start to
charge the Vcc
cap
VCC
VCC(on)
VCC(dis)
VCC(off)
RUN
AC line Unplug
detector starts
No AC detection
VCC(inhibit)
HV
timer
No AC detection
time
HV
restarts
timer
One Shot
starts
tDET
tDET
time
time
DRV
Skip mode
X2 cyclic discharge
process starts
tDIS
tDIS
time
Figure 56. Start−up, Shut−down and AC Line Unplug Time Diagram
fOSC
Oscillator with Frequency Jittering
The NCP12401 includes an oscillator that sets the
switching frequency 65 kHz or 100 kHz depending on the
version. The maximum duty−ratio of the DRV pin is 80%.
In order to improve the EMI signature, the switching
frequency jitters 4 kHz around its nominal value, with a
triangle−wave shape and at a frequency of 125 Hz. This
frequency jittering is active even when the frequency is
decreased to improve the efficiency in light load condition.
fOSC + 4 kHz
Nominal fOSC
fOSC − 4 kHz
Time
8 ms
(125 Hz)
Figure 57. Frequency Modulation of the Maximum
Switching Frequency
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NCP12401
Low Load Operation Modes: Frequency Foldback
Mode (FFM) and Skip Mode
In order to improve the efficiency in light load conditions,
the frequency of the internal oscillator is linearly reduced
frequency foldback mode to provide the natural transformer
core anti−saturation protection. The frequency jittering is
still active while the oscillator frequency decreases as well.
The current setpoint is fixed to 300 mV in the frequency
foldback mode if the feedback voltage decreases below the
Vfb(freeze) level. This feature increases efficiency under
the light loads conditions as well.
from its nominal value down to f . This frequency
OSC(min)
foldback starts when the voltage on FB pin goes below
Vfb(foldS), and is complete when Vfb reaches Vfb(foldE).
The maximum on−time duration control is kept during the
Fsw
Fixed Ipeak
f OSC
Skip
f OSC(min)
FB
Vskip(in)
Vskip(out)
VFB(foldE)
VFB(freeze)
VFB(foldS)
Voffset + KFB X VILIM
Figure 58. Frequency Foldback Mode Characteristic
Internal current setpoint
VILIM
Fixed I peak
VI(freeze)
VFB
Vskip(in)
Vskip(out)
KFB X VILIM
VFB(foldE)
VFB(freeze)
VFB(foldS)
Figure 59. Current Setpoint Dependency on the Feedback Pin Voltage
When the FB voltage reaches V
skip mode is activated: the driver stops, and the internal
consumption of the controller is decreased. While V is
while decreasing,
The NCP12401 device includes logic which allows going
into skip mode after the DRV cycle is finished by reaching
of the peak current value. This technique eliminates the last
short pulses in skip mode, which increases the system
efficiency at light loads and makes easier the application of
active secondary rectification circuitry.
skip(in)
FB
below V , the controller remains in this state; but as
skip(out)
soon as V crosses the skip out threshold, the DRV pin
FB
starts to pulse again.
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NCP12401
Figure 60. Skip Mode Timing Diagram
FB
Vskip(out)
Vskip(in)
time
time
OSC
(internal signa)l
Skip signal does
not immediately
stop the pulse
CS
Enters
skip
VI(freeze)
time
Figure 61. Technique Preventing Short Pulses in Skip Mode
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NCP12401
Quiet−Skip
drive pulses have been counted (if not, they do not stop until
the end of the n −th pulse). They are not allowed to start
To further avoid acoustic noise, the circuit prevents the
burst frequency during skip mode from entering the audible
range by limiting it to a maximum of 800 Hz. This is
P,skip
again until the timer expires, even if the skip−exit threshold
is reached first. It is important to note that the timer will not
force the next cycle to begin – i.e. if the natural skip
frequency is such that skip−exit is reached after the timer
expires, the drive pulses will wait for the skip−exit
threshold.
achieved via a timer t
that is activated during
quiet
Quiet−Skip. The start of the next burst cycle is prevented
until this timer has expired. As the output power decreases,
the switching frequency decreases. Once it hits minimum
switching frequency f
, the skip−in threshold is
This means that during no−load, there will be a minimum
OSC(min)
reached and burst mode is entered − switching stops as soon
as the current drive pulses ends – it does not stop
immediately.
of n
drive pulses, and the burst−cycle period will likely
P,skip
be much longer than 1250 ms. This operation helps to
improve efficiency at no−load conditions.
Once switching stops, FB will rise. As soon as FB crosses
the skip−exit threshold, drive pulses will resume, but the
controller remains in burst mode. At this point, a 1250 ms
In order to exit burst mode, the FB voltage must rise higher
than V
level. If this occurs before t
expires, the
skip(tran)
quiet
drive pulses will resume immediately – i.e. the controller
won’t wait for the timer to expire. Figure 63 provides an
example of how Quiet−Skip works, while Figure 62 shows
the immediate leaving the quiet skip mode by crossing the
(typ) timer t
is started together with a count to n
quiet
P,skip
pulses counter. This n
pulses counter ensures the
P,skip
minimum number of DRV signal pulses in burst. The next
time the FB voltage drops below the skip−in threshold, DRV
transient enhancement level V
.
skip(tran)
pulses stop at the end of the current pulse as long as n
P,skip
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NCP12401
VFB
Vskip(tran)
Crossing the transient
enhancement level
stops the quiet skip
immediately
Vskip(out)
Vskip(in)
Exits skip
after quiet
timer
Time
expires
DRV
tquiet
tquiet
Enters
skip
Enters
skip
Time
Figure 62. Leaving the Quiet−Skip Mode during Load Transient
VFB
Vskip(out)
Vskip(in)
time
time
Running just above skip
mode with fsw = fosc(min)
DRV
Sequence of events
1; 2; 3 starts the quiet
skip mode
The DRV pulses does not
start even when VFB >Vskip(out)
in the quiet skip mode
VFB
2
Vskip(out)
Vskip(in)
1
3
time
time
DRV
tquiet
tquiet
nP,skip
nP,skip
When V FB >Vskip (tran ) the quiet skip
mode immediately finishes
VFB
Vskip(tran)
Vskip(out)
Vskip(in)
time
time
DRV
tquiet
tquiet
nP,skip
nP,skip
nP,skip
Quiet skip mode
forces at least n p,skip
DRV pulses does
not start because
VFB<Vskip(in)
pulses in skip mode
burst
Figure 63. Quiet−Skip Timing Diagram − option
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NCP12401
Clamped Driver
voltage subducted by offset typically 0.8 V and divided by
4 sets the threshold: when the voltage ramp reaches this
threshold, the output driver is turned off. The maximum
value for the current sense is 0.7 V, and it is set by a dedicated
comparator.
The supply voltage for the NCP12401 can be as high as
36 V, but most of the MOSFETs that will be connected to the
DRV pin cannot accept more than 20 V on their gate. The
driver pin is therefore safely clamped below 16 V. This
driver has a typical capability of 500 mA for source current
and 800 mA for sink current.
Each time the controller is starting, i.e. the controller was
off and starts – or restarts – when V reaches V
, a
CC(on)
CC
soft−start is applied: the current sense set−point is increased
by 32 discrete steps from 0 (the minimum level can be higher
than 0 because of the LEB and propagation delay) until it
Current−Mode Control With Slope Compensation and
Soft−Start
NCP12401 is a current−mode controller, which means
that the FB voltage sets the peak current flowing in the
transformer primary inductance and the MOSFET. This is
done through a PWM comparator: the current is sensed
across a resistor and the resulting voltage is applied to the CS
pin. It is applied to one input of the PWM comparator
through a 250 ns LEB block. On the other input the FB
reaches V
(after a duration of t ), or until the FB
SSTART
ILIM
loop imposes a setpoint lower than the one imposed by the
soft−start (the 2 comparators outputs are OR’ed).
During the soft−start the oscillator frequency increase
from the minimum switching frequency to the maximum
switching frequency following the ramp applied to current
sense set−point.
VFB
KFB x VILIM
Time
VFB takes
over soft −start
Soft−start ramp
Soft−start ramp
VILIM
VILIM
tSSTART
tSSTART Time
Time
OSC frequency
fSW
CS Setpoint
VILIM
fSW,min
Time
Time
tSSTART
Figure 64. Soft−Start Feature
www.onsemi.com
34
NCP12401
Under some conditions, like a winding short−circuit for
toggles, the controller immediately enters the protection
mode.
In order to allow the NCP12401 to operate in CCM with
a duty−ratio above 50%, the fixed slope compensation is
internally applied to the current−mode control. The slope
appearing on the internal voltage setpoint for the PWM
comparator is −32.5 mV/ms typical. The slope compensation
can be observable as a value of the peak current at CS pin.
The internal slope compensation circuitry uses a saw−tooth
signal synchronized with the internal oscillator is subtracted
instance, not all the energy stored during the on−time is
transferred to the output during the off−time, even if the
on−time duration is at its minimum (imposed by the
propagation delay of the detector added to the LEB
duration). As a result, the current sense voltage keeps on
increasing above V , because the controller is blind
ILIM
during the LEB blanking time. Dangerously high current
can grow in the system if nothing is done to stop the
controller. That’s what the additional comparator, that
senses when the current sense voltage on CS pin reaches
from the FB voltage divided by K
.
FB
V
CS(stop)
( = 1.5 x V
), does: as soon as this comparator
ILIM
Figure 65. Slope Compensation Block Diagram
Internal PWM setpoint
V
FB
/ K
FB
V
FB
/ K − 0.2 V
FB
Duty Cycle
0%
40%
80%
100%
Figure 66. Slope Compensation Timing Diagram
www.onsemi.com
35
NCP12401
Internal Overpower Protection
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, leading to a significant
difference in the maximum output power delivered by the
power supply.
The power delivered by a flyback power supply is
proportional to the square of the peak current in
discontinuous conduction mode:
1
2
2
POUT
+
@ h @ LP @ FSW @ IP
(eq. 3)
Ipeak
DIpeak to be
compensated
ILIMIT
High
Line
Low
Line
time
tdelay
tdelay
Figure 67. Needs for Line Compensation For True Overpower Protection
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it
would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than V
. However, because the HV pin is
FB(OPCE)
being connected to ac voltage, there is needed an additional
circuitry to read or at least closely estimate the actual voltage
on the bulk capacitor.
IOPC
VHV
VFB
VFB(OPCE)
VFB(OPCF)
Figure 68. Overpower Protection Current Relation to Feedback Voltage
IOPC
IOPC(365)
IOPC(125)
VHV
365 V
125 V
Figure 69. Overpower Protection Current Relation to Peak of Rectified Input Line AC voltage
www.onsemi.com
36
NCP12401
Figure 70. Block Schematic of Overpower Protection Circuit
A 5−bit A/D converter with the peak detector senses the
can deliver, and the CS set−point reaches V . When this
ILIM
ac input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
sample and reset events are given by the output from the ac
line unplug detector. The sensed HV pin voltage peak value
is validated when no HV edges from comparator are present
after last falling edge during 2 sample clocks. See Figure 71
for details.
event occurs, an internal t
times out, DRV pulses are stopped and the controller is either
latched off. This latch is released in autorecovery mode. The
timer is started: once the timer
fault
controller tries to restart after t
. The other possibilities
autorec
of the latch release are the brown−out condition or the VCC
power on reset. The timer is reset when the CS set−point
goes back below VILIM before the timer elapses. The fault
timer is also started if the driver signal is reset by the
maximum on time. The controller also enters the same
protection mode if the voltage on the CS pin reaches 1.5
times the maximum internal set−point V
detect winding short−circuits) or there appears low V
supply. See Figure 71 for the timing diagram.
Overcurrent Protection with Fault Timer
The overload protection depends only on the current
sensing signal, making it able to work with any transformer,
even with very poor coupling or high leakage inductance.
When an overcurrent occurs on the output of the power
supply, the FB loop asks for more power than the controller
(allows to
CS(stop)
CC
www.onsemi.com
37
NCP12401
Figure 71. Overpower Compensation Timing Diagram
www.onsemi.com
38
NCP12401
Table 6. PROTECTION MODES AND THE LATCH MODE RELEASES
Event
Timer Protection
Next Device Status
Release to Normal Operation Mode
Overcurrent
Fault timer
Latch
Autorecovery
V
> V
Brown−out
CS
ILIM
V
V
V
< V
CC
CC(reset)
Maximum on time
Maximum duty cycle
Winding short
Fault timer
Fault timer
Latch
Latch
Latch
Brown−out
< V
CC
CC(reset)
Brown−out
< V
CC
CC(reset)
4 consecutive pulses
Autorecovery
V
> V
Brown−out
CS
CS(stop)
V
< V
CC
CC(reset)
Low supply
< V
10 ms timer
Latch
Autorecovery
V
Brown−out
CC
CC(off)
V
V
V
< V
CC
CC(reset)
External OTP, OVP
55 ms
Latch
Latch
Brown−out
< V
CC
CC(reset)
High supply
10 ms timer
HV timer
Brown−out
< V
CC(reset)
V
> V
CC(ovp)
CC
CC
Brown−out
< V
Device stops
(V > V
HV
) & (V > V
)
HV(start)
CC
CC(on)
V
HV
HV(stop)
Internal TSD
10 ms timer
500 ms timer
Device stops, HV start−up
(V > V
) & (V > V
) & TSDb
HV
HV(start)
CC
CC(on)
current source stops
Off mode
Device stops and internal
(V > V
HV
) & (V > V
) &
CC(on)
HV(start)
CC
V
FB
< V
V
CC
is turned off
(V > V
)
OFF
FB
ON
www.onsemi.com
39
NCP12401
V
CC(on)
V
CC(min)
Figure 72. Latched Timer−Based Overcurrent Protection
www.onsemi.com
40
NCP12401
Fault
disappears
Overcurrent
applied
Output Load
Max Load
time
time
Fault Flag
Fault
timer
starts
VCC
VCC (on )
VCC (min)
Restart
At VCC
ON
(new burst
cycle if Fault
still present)
time
time
DRV
Controller
stops
Fault timer
tfault
time
tfault
tautorec
Figure 73. Timer−based Protection Mode with Autorecovery Release from Latch−off
www.onsemi.com
41
NCP12401
FAULT Input
Figure 74. OVP/OTP Detection Schematic
The FAULT input pin is dedicated to the latch−off
function: it includes 2 levels of detection that define a
working window, between a high latch and a low latch:
within these 2 thresholds, the controller is allowed to run, but
as soon as either the low or the high threshold is crossed, the
controller is latched off. The controller can be released from
the latch mode by the autorecovery, but it depends on the
version of the product. The lower threshold is intended to be
used with an NTC thermistor, thanks to an internal current
Reset occurs when a brown−out condition is detected or
the V is cycled down to a reset voltage, which in a real
CC
application can only happen if the power supply is
unplugged from the ac line.
Upon startup, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
before the controller is ready to start: once V reaches
CC
source I
.
V , the latch pin High latch state is taken into account
CC(on)
NTC
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the I current. To
reach the high threshold, the pull−up current has to be higher
than the pull−down capability of the clamp (typically
and the DRV switching starts only if it is allowed; whereas
the Low latch (typically sensing an over temperature) is
taken into account only after the soft−start is finished. In
NTC
addition, the NTC current is doubled to I
during
NTC(SSTART)
1.5 mA at V
).
the soft−start period, to speed up the charging of the FAULT
pin capacitor The maximum value of FAULT pin capacitor
is given by the following formula (The standard start−up
condition is considered and the NTC current is neglected):
OVP
To avoid any false triggering, spikes shorter than 50 ms
(for the high latch and 65 kHz version) or 350 ms (for the low
latch) are blanked and only longer signals can actually latch
the controller.
t
SSTART min @ INTC(SSTART) min
3.2 @ 10−3 @ 60 @ 10−6
(eq. 4)
CFAULT max
+
+
F + 457 nF
0.420
VOTP max
www.onsemi.com
42
NCP12401
V
CC(on)
V
CC(min)
Figure 75. Latch Timing Diagram
Temperature Shutdown
low power consumption. There is kept the V supply to
CC
The NCP12401 includes a temperature shutdown
protection with a trip point typically at 150°C and the typical
hysteresis of 30°C. When the temperature rises above the
high threshold, the controller stops switching
instantaneously, and goes to the off mode with extremely
keep the TSD information. When the temperature falls
below the low threshold, the start−up of the device is enabled
again, and a regular start−up sequence takes place. See the
status diagrams at the Figure 44.
ORDERING INFORMATION
†
Ordering Part No.
NCP12401CBEAB0DR2G
Overload Protection
Switching Frequency
Package
Shipping
Autorecovery
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape &
Reel
NCP12401EBEAB0DR2G
Autorecovery
65 kHz
SOIC−7
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
43
NCP12401
PACKAGE DIMENSIONS
SOIC−7
CASE 751U
ISSUE E
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
S
M
M
B
−B−
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
C
R X 45
_
1.27 BSC
J
0.10
0.19
0.40
0
−T−
SEATING
PLANE
K
8
0
8
_
_
_
_
M
H
D 7 PL
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
M
S
S
0.25 (0.010)
T
B
A
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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PUBLICATION ORDERING INFORMATION
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Email Requests to: orderlit@onsemi.com
TECHNICAL SUPPORT
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◊
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