NCP1280 [ONSEMI]
Active Clamp Voltage Mode PWM Controller for Off-Line Applications; 有源钳位电压模式PWM控制器，用于离线应用
| 型号： | NCP1280 |
| 厂家： | 
ONSEMI |
| 描述： | Active Clamp Voltage Mode PWM Controller for Off-Line Applications |
| 文件： | 总18页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1280
Active Clamp Voltage Mode
PWM Controller for Off−Line
Applications
The NCP1280 provides a highly integrated solution for off−line
power supplies requiring high−efficiency and low parts count. This
voltage mode controller provides control outputs for driving a forward
converter primary MOSFET and an auxiliary MOSFET for active
clamp circuit. The second output with its programmable delay can also
be used for driving a synchronous rectifier on the secondary or for
asymmetric half bridge circuits. Incorporation of high voltage start−up
circuitry (with 700 V capability) reduces parts count and system
power dissipation. Additional features such as line UV/OV protection,
soft start, single resistor programmable (high) frequency oscillator,
line voltage feedforward, dual mode overcurrent protection and
maximum duty cycle control, allow converter optimization at minimal
cost. Compared to a traditional forward converter, an NCP1280 based
converter can offer significant efficiency improvements and system
cost savings.
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MARKING
DIAGRAM
16
SO−16
D SUFFIX
CASE 751B
NCP1280
AWLYWW
16
1
1
NCP1280= Device Code
A
= Assembly Location
WL
Y
= Wafer Lot
= Year
WW
= Work Week
Features
PIN CONNECTIONS
• Internal High Voltage Start−Up Regulator (25 V to 700 V)
• Dual Control Outputs with Adjustable Overlap Delay
• Programmable Maximum Duty Cycle Control
• Single Resistor Oscillator Frequency Setting
• Fast Line Feedforward
• Line Under/Overvoltage Lockout
• Dual Mode Overcurrent Protection
• Programmable Soft Start
1
16
V
in
V
AUX
NC
UV/OV
FF
OUT1
GND
OUT2
CS
t
D
C
V
V
SKIP
REF
R
T
EA
DC
SS
MAX
• Precision 5.0 V Reference
ORDERING INFORMATION
Typical Applications
Device
NCP1280DR2
Package
Shipping†
• Off−Line Power Converters in 100−500 W Range
• Desktop Power Supplies (High−End)
• Industrial Power Supplies
SO−16
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Plasma/LCD TV Front−End
L
out
TX1
Start−up
+
+
−
C
SR
Drive
clamp
(100 V − 425 V)
C
V
in
V
out
(3.3 V)
out
Feedforward
−
V
in
FF
NCP1280
UV/OV
OUT1
OUT2
Driver
t
D
Overlap
Delay
Error
Opto
Amplifier
Figure 1. Forward Converter for Off−line Applications Using PFC Inputs
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number
April, 2004 − Rev. 1
NCP1280/D
NCP1280
1
V
in
V
AUX
Disable
I
START
16
V
REF
One Shot
Pulse
(250 ns)
5.0 V Reference
DIS
V
C
AUX
11
AUX
+
−
14
GND
Disable_V
V
/V
REF
AUX(ON) AUX(OFF)
S
Q
Monotonic
Start
Disable_V
REF
R
D
+
−
V
in
Latch
+
(Reset
Dominant)
R
1.49 V
−
3
Disable_ss
STOP
UV/OV
+
−
12
+
3.6 V
−
t
D
V
REF
DIS
15
13
Disable
OUT1
OUT2
−
+
S
Q
11 m A
Clock
CSKIP
6
Output
Delay
Logic
Latch
V
AUX
−
(Reset
DIS
Dominant)
R
C
CSKIP
+
+
2 V
One Shot
Pulse
−
V
AUX
(600 ns)
+
−
+
5
0.6 V
CS
−
+
−
Soft Start
Comparator
PWM
Comparator
+
+
−
0.5 V
−
+ −
10
V
REF
V
EA
2 k
W
CURRENT MIRROR
Oscillator Ramp
6
m
A
20 kW
I
2
Disable_ss
1
9
I
1
2 V
SS
STOP
Max DC
Comparator
C
SS
+
−
+
10 pF
−
+
7
+
−
2 V
+
* Trimmed during
manufacturing to obtain
R
T
−
2 V
R
T
1.3 V*
−
1.3 V with R = 101 k
W
2 V
T
One Shot
Pulse
Clock
V
REF
V
in
40 kW
V
125 k
R
MDP
I +
R
FF
W
FF Ramp
(Adjustable)
+
5.3 k
W
32 k
W
4
+
−
8
+
V
−
FF
V
DC
MAX
DC(inv)
I
FF
6.7 k
W
27 kW
R
P
−
C
10 pF
FF
Figure 2. NCP1280 Functional Block Diagram
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2
NCP1280
PIN DESCRIPTION
Pin
Name
Application Information
1
V
in
This pin is connected to the input voltage of the system. The voltage can be a rectified, filtered line voltage
or output of a power factor correction (PFC) front end. A constant current source supplies current from this
pin to the capacitor connected on the V
voltage is 700 V.
pin. The charge current is typically 13.8 mA. Maximum input
AUX
2
3
NC
Not Connected.
UV/OV
Provides protection under line undervoltage and overvoltage conditions. The built in voltage range is
X 2:1. If needed, the OV function can be disabled by a zener from this pin to ground.
4
FF
An external resistor between V and this pin adjusts the amplitude of the Feedforward Ramp in proportion
in
to V . By varying the feedforward ramp amplitude in proportion to the input voltage, open loop line
in
regulation is improved.
5
6
CS
Overcurrent sense input. If the CS voltage exceeds 0.48 V or 0.57 V, the converter enters the Cycle by
Cycle or Cycle Skip current limit mode, respectively.
CSKIP
The capacitor connected between this pin and ground sets the Cycle Skip period. A soft start sequence
follows at the conclusion of the fault period.
7
8
R
A single external resistor between this pin and GND sets the oscillator fixed frequency.
T
DC
An external resistor between this pin and GND sets the voltage on the Max DC Comparator inverting
input. The duty cycle is limited by comparing the voltage on the Max DC Comparator inverting input to the
Feedforward Ramp.
MAX
9
SS
An internal 6.2 m A current source charges the external capacitor connected to this pin. The duty cycle is
limited during start−up by comparing the voltage on this pin to the Oscillator Ramp.
10
V
EA
The error signal from an external error amplifier, typically supplied through an optocoupler, is fed into this
input and compared to the Feedforward Ramp. A series diode and resistor offset the voltage on this pin
before it is applied to the PWM Comparator inverting input.
11
12
V
Precision 5.0 V reference output. Maximum output current is 6 mA.
REF
t
D
An external resistor between V
transitions.
and this pin sets the overlap delay between OUT1 and OUT2
REF
13
OUT2
Output of the PWM controller with leading and trailing edge overlap delay. OUT2 can be used to drive a
synchronous rectifier topology, an active clamp/reset switch, or both.
14
15
16
GND
Control circuit ground.
OUT1
Main output of the PWM controller.
V
AUX
Positive input supply voltage. This pin is connected to an external capacitor for energy storage. An
internal current supplies current from V to this pin. Once the voltage on V
reaches 11 V, the current
in
AUX
source turns OFF. It turns ON again once V
falls to 7 V. During normal operation, power is supplied to
AUX
the IC via this pin, by means of an auxiliary winding.
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3
NCP1280
MAXIMUM RATINGS (Note 1)
Rating
Symbol
Value
−0.3 to 700
−0.3 to 16
35
Unit
V
Input Line Voltage
V
in
Auxiliary Supply Voltage
V
V
AUX
AUX
Auxiliary Supply Input Current
OUT1 and OUT2 Voltage
I
mA
V
V
−0.3 to (V
+ 0.3 V)
OUT
OUT
AUX
OUT1 and OUT2 Output Current
5.0 V Reference Voltage
I
10
mA
V
V
REF
−0.3 to 6.0
6.0
5.0 V Reference Output Current
All Other Inputs/Outputs Voltage
All Other Inputs/Outputs Current
Operating Junction Temperature
Storage Temperature Range
I
mA
V
REF
V
IO
−0.3 to V
10
REF
I
IO
mA
°C
°C
W
T
J
−40 to 125
−55 to 150
0.77
T
stg
Power Dissipation at T = 25°C
P
D
A
Thermal Resistance, Junction to Ambient
R
130
°C/W
q
JA
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum−rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
A. This device series contains ESD protection and exceeds the following tests:
Pin 1 is the HV start−up of the device and is rated to the max rating of the part, or 700 V.
Machine Model Method 700 V.
Pins 2−16: Human Body Model 4000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.
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4
NCP1280
ELECTRICAL CHARACTERISTICS (V = 82 V, V
= 12 V, V = 2 V, R = 101 kW, C
= 6800 pF,
CSKIP
in
AUX
EA
T
R
= 60.4 kW, R = 1.0 MW, for typical values T = 25°C, for min/max values, T = −40°C to 125°C, unless otherwise noted)
D
FF
J
J
Characteristic
Symbol
Min
Typ
Max
Unit
START−UP CONTROL AND V
REGULATOR
AUX
V
AUX
Regulation
Start−up Threshold/V
Minimum Operating V
Hysteresis
V
Regulation Peak (V
Valley Voltage After Turn−On
increasing)
V
AUX(on)
10.5
6.6
−
11.0
7.0
4.0
11.5
7.4
−
AUX
AUX
V
AUX
AUX(off)
V
H
Minimum Start−up Voltage (Pin 1)
= 1.5 mA, V = V
V
V
START(min)
I
− 0.2 V, I = 0 A
REF
−
−
25
START
AUX
AUX(on)
Start−up Circuit Output Current
= 0 V
I
mA
START
V
AUX
T = 25°C
13
10
17.5
−
21
25
J
T = −40°C to 125°C
J
V
AUX
= V
− 0.2 V
AUX(on)
T = 25°C
10
8
13.8
−
17
19
J
T = −40°C to 125°C
J
Start−up Circuit Off−State Leakage Current (V = 700 V)
I
m
A
in
START(off)
T = 25°C
−
−
23
−
50
100
J
T = −40°C to 125°C
J
Start−up Circuit Breakdown Voltage (Note 2)
V
700
−
−
V
(BR)DS
I
= 50ꢀ mA, T = 25°C
START(off)
J
Auxiliary Supply Current After V
Outputs Disabled
Turn−On
mA
AUX
V
V
= 0 V
I
I
I
−
−
−
2.7
1.3
4.6
5.0
2.5
6.5
EA
AUX1
AUX2
AUX3
= 0.7 V
UV/OV
Outputs Enabled
LINE UNDER/OVERVOLTAGE DETECTOR
Undervoltage Threshold (V Increasing)
V
1.40
0.080
3.47
−
1.52
0.098
3.61
0.145
250
1.64
0.120
3.75
−
V
V
in
UV
Undervoltage Hysteresis
V
UV(H)
Overvoltage Threshold (V Increasing)
V
OV
V
in
Overvoltage Hysteresis
V
OV(H)
V
Undervoltage Propagation Delay to Output
Overvoltage Propagation Delay to Output
CURRENT LIMIT
t
−
−
ns
ns
UV
t
−
160
−
OV
Cycle by Cycle Threshold Voltage
I
I
0.44
−
0.48
90
0.52
150
V
LIM1
Propagation Delay to Output (V = 2.0 V)
t
ns
EA
ILIM
V
CS
= I
LIM1
to 2.0 V, measured when V
reaches 0.5 V
OUT OH
Cycle Skip Threshold Voltage
0.54
8.0
0.57
12.3
0.62
15
V
LIM2
Cycle Skip Charge Current (V
2. Guaranteed by design only.
= 0 V)
I
m
A
CSKIP
CSKIP
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5
NCP1280
ELECTRICAL CHARACTERISTICS (V = 82 V, V
= 12 V, V = 2 V, R = 101 kW, C
= 6800 pF,
in
AUX
EA
T
CSKIP
R
= 60.4 kW, R = 1.0 MW, for typical values T = 25°C, for min/max values, T = −40°C to 125°C, unless otherwise noted)
D
FF
J
J
Characteristic
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Frequency (R = 101 kW)
f
kHz
T
OSC1
OSC2
T = 25°C
285
280
300
−
315
320
J
T = −40°C to 125°C
J
Frequency (R = 220 kW, V = 1.0 V)
f
kHz
T
EA
T = 25°C
T = −40°C to 125°C
J
142
140
150
−
158
160
J
MAXIMUM DUTY CYCLE COMPARATOR
Maximum Duty Cycle (V = 3.0 V, T = 25°C)
DC
MAX
%
V
EA
J
R
R
= 0 W, R
= open, R
= open
57
75
62
80
66
85
P
P
MDP
= open
MDP
Open Circuit Voltage
V
0.40
0.47
0.60
DCMAX
SOFT START
Charge Current (V = 1.0 V)
I
5.0
20
6.2
7.4
−
m
A
SS
SS(C)
Discharge Current (V = 5.0 V, V
= 0 V)
I
52.5
mA
SS
UV/OV
SS(D)
PWM COMPARATOR
Input Resistance (V = 1.25 V, V = 1.50 V)
R
8.0
22
60
kW
1
2
IN(VEA)
R
= (V − V )/(I − I )
IN(VEA)
2
1
2
1
Lower Input Threshold
Delay to Output (from V
5.0 V REFERENCE
V
0.3
−
0.7
0.9
−
V
EA(L)
to 0.5 V
)
t
200
ns
OH
OH
PWM
Output Voltage (I
= 0 mA)
V
REF
V
REF
T = 25°C
4.9
4.8
5.0
−
5.1
5.1
J
T = −40°C to 125°C
J
Load Regulation (I
Line Regulation (V
= 0 to 6 mA)
V
−
−
10
50
50
mV
mV
REF
REF(Load)
= 7.5 to 16 V)
V
100
AUX
REF(Line)
CONTROL OUTPUTS
Output Voltage (I
Low State
= 0 mA)
V
OUT
V
−
−
0.25
11.8
−
−
OL
High State
V
OH
Overlap Delay
t
D
ns
R
= 1 MW
Leading
Trailing
D
−
−
200
170
−
−
R
= 60 k
Leading
Trailing
W
D
50
32
90
72
130
130
Drive Resistance (V = 15 V)
W
in
Sink (V = 0 V, V
= 2 V)
= 10 V)
R
SNK
R
SRC
20
50
40
90
80
170
EA
OUT
Source (V = 3 V, V
EA
OUT
Rise Time (C = 100 pF, 10% to 90% of V
)
t
−
−
30
12
−
−
ns
ns
L
OH
on
Fall Time (C = 100 pF, 90% to 10% of V
)
t
L
OH
off
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6
NCP1280
TYPICAL CHARACTERISTICS
19
18
12
11
V
= 82 V
in
START−UP
THRESHOLD
17
16
15
14
13
12
10
9
V
= 0 V
AUX
8
7
V
AUX
= V
− 0.2 V
25
AUX(on)
MINIMUM
OPERATING
THRESHOLD
11
10
9
6
5
−50 −25
0
25
50
75
100
125 150
−50 −25
0
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. Auxiliary Supply Voltage Thresholds
versus Junction Temperature
Figure 4. Start−up Circuit Output Current
versus Junction Temperature
20
16
12
8
17.0
V
in
= 82 V
16.5
16.0
15.5
15.0
14.5
T = −40°C
J
T = 25°C
J
T = 125°C
J
14.0
13.5
4
0
V
= V
− 0.2 V
AUX
AUX(on)
13.0
0
2
4
6
8
10
12
0
100
200
300
400
500
600
700
V
AUX
, AUXILIARY SUPPLY VOLTAGE (V)
V , LINE VOLTAGE (V)
in
Figure 5. Start−up Circuit Output Current
versus Auxiliary Supply Voltage
Figure 6. Start−up Circuit Output Current
versus Line Voltage
50
45
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
AUX
= 12 V
V
= 12 V
AUX
T = −40°C
J
40
35
30
25
20
15
10
V
= 0 V
EA
T = 25°C
J
T = 125°C
J
V
UV/OV
= 0 V
0.5
0
5
0
0
100 200 300 400 500 600 700 800 900
V , LINE VOLTAGE (V)
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
in
J
Figure 7. Start−up Circuit Off−State Leakage
Current versus Line Voltage
Figure 8. Auxiliary Supply Current versus
Junction Temperature
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7
NCP1280
TYPICAL CHARACTERISTICS
7
6
4.0
V
= 12 V
AUX
f
= 440 kHz
OSC
3.5
3.0
2.5
2.0
1.5
1.0
DC [ 50%
OV THRESHOLD
UV THRESHOLD
f
= 300 kHz
OSC
5
4
3
2
f
= 87 kHz
OSC
1
0
0.5
0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Operating Auxiliary Supply Current
versus Junction Temperature
Figure 10. Line Under/Overvoltage Thresholds
versus Junction Temperature
160
150
140
130
120
110
600
575
550
525
500
475
450
CYCLE SKIP
OV HYSTERESIS
CYCLE BY CYCLE
UV HYSTERESIS
100
90
425
400
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. Line Under/Overvoltage Thresholds
Hysteresis versus Junction Temperature
Figure 12. Current Limit Thresholds versus
Junction Temperature
450
400
350
300
250
200
150
100
120
115
110
105
100
95
V
= 12 V
AUX
R = 68 k
W
T
Measured from V to 0.5 V
OH
OH
R = 101 k
T
W
90
R = 220 k
T
W
85
80
R = 390 k
W
T
50
0
75
70
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. Current Limit Propagation Delay
versus Junction Temperature
Figure 14. Oscillator Frequency versus
Junction Temperature
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8
NCP1280
TYPICAL CHARACTERISTICS
600
315
310
305
300
295
T = 25°C
J
DC [ 50%
500
R = 101 k
W
T
400
300
200
100
0
290
285
−50 −25
0
25
50
75
100
125
150
50
100
150
200
250
300
350
400
T , JUNCTION TEMPERATURE (°C)
J
R , TIMING RESISTOR (kW)
T
Figure 15. Oscillator Frequency versus
Junction Temperature
Figure 16. Oscillator Frequency versus
Timing Resistor
90
80
70
60
50
40
30
20
19
18
V
V
= 3.0 V
EA
= 0 V
DCMAX
17
16
15
14
13
12
11
10
9
T = −40°C
J
T = 125°C
J
10
0
0
75
150
225
300
375
450
525
−50 −25
0
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (°C)
J
I , FEEDFORWARD CURRENT (m A)
FF
Figure 17. Feedforward Internal Resistance
versus Junction Temperature
Figure 18. Maximum Duty Cycle versus
Feedforward Current
100
90
7.0
6.5
6.0
5.5
5.0
4.5
4.0
70
65
60
55
50
45
40
R
= 1.0 MW
FF
CHARGE
R
= OPEN, R
= OPEN
MDP
P
80
DISCHARGE
70
R
= 0 W, R
= OPEN
P
MDP
60
50
3.5
3.0
35
30
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 19. Maximum Duty Cycle versus
Junction Temperature
Figure 20. Soft Start Charge/Discharge
Currents versus Junction Temperature
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NCP1280
TYPICAL CHARACTERISTICS
50
40
30
20
0.85
0.75
0.65
0.55
10
0
0.45
0.35
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 21. VEA Input Resistance versus
Junction Temperature
Figure 22. PWM Comparator Lower Input
Threshold versus Junction Temperature
350
300
250
200
150
100
5.03
5.01
4.99
4.97
R
= 1 MW, LEADING
D
I
= 0 mA
REF
I
= 6 mA
REF
R
= 60 kW, LEADING
D
4.95
4.93
50
0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 23. Reference Voltage versus Junction
Temperature
Figure 24. Outputs Overlap Delay versus
Junction Temperature
225
200
175
150
125
100
200
160
120
80
LEADING
TRAILING
T = 25°C
J
V
R
= 12 V
= 100 kW
AUX
MDP
R
(V = 0 V, V
= 10 V)
= 2 V)
SRC
EA
OUT
40
0
75
50
R
(V = 3 V, V
EA
SNK
OUT
0
200
400
600
800
1000
−50 −25
0
25
50
75
100 125 150
R , DELAY RESISTOR (kW)
D
T , JUNCTION TEMPERATURE (°C)
J
Figure 25. Outputs Overlap Delay versus
Delay Resistor
Figure 26. Outputs Drive Resistance Voltage
versus Junction Temperature
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10
NCP1280
TYPICAL CHARACTERISTICS
80
70
60
50
40
30
20
35
Measured from 10% to 90% of V
Measured from 90% to 10% of V
OH
OH
V
AUX
= 12 V
30
25
20
15
10
V
AUX
= 12 V
T = 125°C
J
T = 25°C
J
T = 125°C
J
T = 25°C
J
T = −40°C
J
T = −40°C
J
5
0
10
0
0
25
50
75
100
125
150 175
200
0
25
50
75
100 125
150
175 200
C , LOAD CAPACITANCE (pF)
L
C , LOAD CAPACITANCE (pF)
L
Figure 27. Outputs Rise Time versus Load
Capacitance
Figure 28. Outputs Fall Time versus Load
Capacitance
DETAILED OPERATING DESCRIPTION
Introduction
High Voltage Start−up Regulator
An NCP1280 based system offers significant efficiency
improvements and system cost savings over a converter
using a traditional forward topology. The NCP1280
provides two control outputs. OUT1 controls the primary
switch of a forward converter. OUT2 has an adjustable
overlap delay, which can be used to control an active
clamp/reset switch or any other complementary drive
topology, such as an asymmetric half−bridge. In addition,
OUT2 can be used to control a synchronous rectifier
topology, eliminating the need of external control circuitry.
Other distinctive features include: two mode overcurrent
protection, line under/overvoltage detectors, fast line
feedforward, soft start and a maximum duty cycle limit. The
Functional Block Diagram is shown in Figure 2.
The NCP1280 contains an internal 700 V start−up
regulator that eliminates the need for external start−up
components. In addition, this regulator increases the
efficiency of the supply as it uses no power when in the
normal mode of operation, but instead uses power supplied
by an auxiliary winding.
The start−up regulator consists of a constant current source
that supplies current from the input line voltage (V ) to the
in
capacitor on the V
pin (C ). The start−up current is
AUX
AUX
typically 13.8 mA. Once V
reaches 11 V, the start−up
AUX
regulator turns OFF and the outputs are enabled. When V
AUX
reaches 7 V, the outputs are disabled and the start−up
regulator turns ON. This “7−11” mode of operation is known
as Dynamic Self Supply (DSS). The V
pin can be biased
AUX
The features included in the NCP1280 provide some of
the advantages of Current−Mode Control, such as fast line
feedforward, and cycle by cycle current limit. It eliminates
the disadvantages of low power jitter, slope compensation
and noise susceptibility.
externally above 7 V once the outputs are enabled to prevent
the start−up regulator from turning ON. It is recommended
to bias the V
pin using an auxiliary supply generated by
AUX
an auxiliary winding from the power transformer. An
independent voltage supply can also be used. If using an
independent voltage supply and V
is biased before the
AUX
Active Clamp Topology
outputs are enabled or while a fault is present, the One Shot
Pulse Generator (Figure 2) will not be enabled and the
outputs will remain OFF.
The transformer reset voltage in a traditional forward
converter is set by the turns ratio and input voltage. Where
as the reset voltage of an active clamp topology is constant
over the converter off time and only depends on the input
voltage and duty cycle. This translates into a lower voltage
stress on the main switch, allowing the use of lower voltage
MOSFETs. In general, lower voltage MOSFETs have lower
cost and ON resistance. Therefore, lower system cost and
higher efficiency can be achieved. In addition, the lower
voltage stress allows the converter to operate at a higher duty
cycle for a given primary switch voltage stress. This allows
a reduction in primary peak current and secondary side
voltage stress as well as smaller secondary inductor size.
As the DSS sources current to the V
pin, a diode should
AUX
be placed between C
and the auxiliary supply as shown
AUX
in Figure 29. This will allow the NCP1280 to charge C
while preventing the start−up regulator from sourcing current
into the auxiliary supply.
AUX
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11
NCP1280
I
Line Under/Overvoltage Shutdown
START
I
To auxiliary supply
START
V
AUX
V
in
The NCP1280 incorporates line undervoltage and
overvoltage shutdown (UV/OV) circuits. The under voltage
(UV) threshold is 1.52 V and the overvoltage threshold
(OV) is 3.61 V, for a ratio of 1:2.4. If the input voltage range
exceeds the pre−set OV threshold, the OV function can be
disabled by connecting a zener from this pin to ground. The
zener voltage should be less than 3.6 V.
I
AUX
C
I
supply
AUX
Disable
Figure 29. Recommended VAUX Configuration
The UV/OV circuit can be biased using an external
resistor divider from the input line. The resistor divider must
Power to the controller while operating in the self−bias or
DSS mode is provided by C . Therefore, C must be
AUX
AUX
be sized to enable the controller once V is within the
in
sized such that a V
voltage greater than 7 V is
AUX
required operating range. If the UV or OV threshold is
reached, the soft start capacitor is discharged, and the
outputs are immediately disabled with no overlap delay as
shown in Figure 30. Also, if an UV condition is detected, the
5.0 V Reference Supply is disabled.
maintained while the outputs are switching and the
converter reaches regulation. Also, the V discharge time
AUX
(from 11 V to 7 V) must be greater that the soft start charge
period to assure the converter turns ON.
The start−up circuit is rated at a maximum voltage of
700 V. If the device operates in the DSS mode, power
dissipation should be controlled to avoid exceeding the
maximum power dissipation of the controller.
V
AUX(on)
V
AUX
V
AUX(off)
0 V
V
OV
UV or OV Fault
UV/OV Voltage
V
UV
0 V
Propagation delay to
outputs (t or t
)
OV
UV
OUT2
0 V
OUT1
0 V
Figure 30. UV/OV Fault Timing Diagram
Once the UV or OV condition is removed and V
The UV/OV pin can also be used to implement a remote
enable/disable function. Biasing the UV/OV pin below its
UV threshold disables the converter.
AUX
reaches 11 V, the controller initiates a soft start cycle.
Figure 31 shows the relationship between the UV/OV
voltage, the outputs and the soft start voltage.
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12
NCP1280
SOFT START
V
AUX(on)
V
AUX
V
AUX(off)
0 V
2 V
0 V
UV/OV Voltage
Soft Start Voltage
0 V
OUT2
0 V
OUT1
0 V
Figure 31. Soft Start Timing Diagram (Using Auxiliary Winding)
Feedforward Ramp Generator
Figure 18 shows the relationship between I and DC
.
FF
MAX
The NCP1280 incorporates line feedforward (FF) to
compensate for changes in line voltage. A FF Ramp
For example, if a system is designed to operate at 200 kHz,
with a 60% maximum duty cycle at 100 V, the DC pin
MAX
proportional to V is generated and compared to V . If the
can be grounded and I is calculated as follows:
in
EA
FF
1
f
1
line voltage changes, the FF Ramp slope changes
accordingly. The duty cycle will be adjusted immediately
instead of waiting for the line voltage change to propagate
T +
+
+ 5.0 m s
200 kHz
t
+ DC
T + 0.6 5.0 m s + 3.0 m s
on(max)
MAX
around the system and be reflected back on V
.
EA
C
V
125 kW
FF
DC(inv)
on(max)
A resistor between V and the FF pin (R ) sets the
in
FF
I
+
FF
6.7 kW t
feedforward current (I ). The FF Ramp is generated by
FF
charging an internal 10 pF capacitor (C ) with a constant
FF
10 pF 0.888 V 125 kW
6.7 kW 3.0 m s
+
+ 55.2 m A
current proportional to I . The FF Ramp is finished
FF
(capacitor is discharged) once the Oscillator Ramp reaches
2.0 V. Please refer to Figure 2 for a functional drawing of the
Feedforward Ramp generator.
For a minimum line voltage of 100 V, the required
feedforward resistor is calculated using the equation below:
V
I
is usually a few hundred microamps, depending on the
100 V
55.2 m A
in
FF
R
+
* 12.0 kW +
* 12.0 kW [ 1.82 MW
FF
I
FF
operating frequency and the required duty cycle. If the
operating frequency and maximum duty cycle are known,
From the above calculations it can be observed that I is
FF
I
is calculated using the equation below:
controlled predominantly by the value of R , as the
FF
FF
resistance seen into the FF pin is only 12 kW. If a tight
maximum duty cycle control overtemperature is required,
C
V
125 kW
FF
DC(inv)
on(max)
I
+
FF
6.7 kW t
R
FF
should have a low thermal coefficient.
where V
is the voltage on the inverting input of the
DC(inv)
Max DC Comparator and t
is the maximum ON time.
on(max)
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13
NCP1280
Current Limit
The CSKIP timer is set by immediately discharging the
capacitor on the CSKIP pin (C ), and then charging it
with a constant current source of 12.3 m A. The cycle skip
period ends when the voltage on the cycle skip capacitor
reaches 2.0 V. The cycle skip capacitor is calculated using
the equation below:
The NCP1280 has two overcurrent protection modes,
cycle by cycle and cycle skip. It allows the NCP1280 to
handle momentary and hard shorts differently for the best
tradeoff in performance and safety. The outputs are disabled
typically 90 ns after a current limit fault is detected.
The cycle by cycle mode terminates the conduction cycle
(reducing the duty cycle) if the voltage on the CS pin
exceeds 0.48 V. If the voltage on the CS pin exceeds 0.57 V,
the converter enters the cycle skip (CSKIP) mode. While in
the CSKIP mode, the soft start capacitor is discharged and
the converter is disabled by a time determined by the CSKIP
timer.
CSKIP
T
CSKIP 12.3 m A
C
[
CSKIP
2 V
Using the above equation, a cycle skip period of 11.0 m s
requires a cycle skip capacitor of 68 pF. The differences
between the cycle by cycle and cycle skip modes are
observed in Figure 32.
NORMAL
OPERATION
NORMAL
OPERATION
I
I
LIM1 LIM2
SOFT START
RESET
V
AUX(on)
V
AUX
V
AUX(off)
0 V
OUT2
0 V
OUT1
0 V
I
I
LIM2
LIM1
CS Voltage
0 V
T
CSKIP
Cycle Skip
Voltage
0 V
Figure 32. Overcurrent Faults Timing Diagram
Once the cycle skip period is complete and V
reaches
The voltage on the R pin is laser trim adjusted during
T
AUX
11 V, a soft start sequence commences. The possible
minimum OFF time is set by C . However, the actual
manufacturing to 1.3 V for an R of 101 kW. A current set
T
by R generates an Oscillator Ramp by charging an internal
CSKIP
T
OFF time is generally greater than C
cycle skip period added to the time it takes V
because it is the
10 pF capacitor as shown in Figure 2. The period ends
(capacitor is discharged) once the Oscillator Ramp reaches
CSKIP
to reach
AUX
11 V.
2.0 V. If R increases, the current and the Oscillator Ramp
T
slope decrease, thus reducing the frequency. If R decreases,
the opposite effect is obtained. Figure 16 shows the
T
Oscillator
The NCP1280 oscillator frequency is set by a single
external resistor connected between the R pin and GND.
relationship between R and the oscillator frequency.
T
T
The oscillator is designed to operate up to 500 kHz.
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14
NCP1280
Maximum Duty Cycle
A dedicated internal comparator limits the maximum ON
time of OUT1 by comparing the FF Ramp to V . If the
5.0 V Reference
The NCP1280 includes a precision 5.0 V reference output.
The reference output is biased directly from V
and it can
DC(inv)
AUX
FF Ramp voltage exceeds V
, the output of the Max
supply up to 6 mA. Load regulation is 50 mV and line
regulation is 100 mV over the complete operating range.
It is recommended to bypass the reference output with a
0.1 m F ceramic capacitor. The reference output is disabled
when an UV fault is present.
DC(inv)
DC Comparator goes high. This will reset the Output Latch,
thus turning OFF the outputs and limiting the duty cycle.
Duty cycle is defined as:
t
on
T
DC +
+ t f
on
PWM Comparator
In steady state operation, the PWM comparator adjusts the
duty cycle by comparing the error signal to the FF Ramp.
Therefore, the maximum ON time can be set to yield the
desired DC if the operating frequency is known. The
maximum ON time is set by adjusting the FF Ramp to reach
The error signal is fed into the V input. The V input can
EA
EA
V
DC(inv)
in a time equal to t
as shown in Figure 33.
on(max)
be driven directly with an optocoupler and a pull−up resistor
from V . The drive of the V pin is simplified by
The maximum ON time should be set for the minimum line
voltage. As line voltage increases, the slope of the FF Ramp
increases. This reduces the duty cycle below DC
is a desirable feature as the duty cycle is inversely
proportional to line voltage.
REF
EA
internally incorporating a series diode and resistor. The
, which
MAX
series diode provides a 0.7 V offset between V input and
EA
the PWM comparator inverting input. The outputs are
enabled if the V voltage is approximately 0.7 above the
EA
valley voltage of the FF Ramp.
The pull−up resistor is selected such that in the absense of
Oscillator Ramp
the error signal, the voltage on the V pin exceeds the peak
EA
2 V
amplitude of the FF Ramp. Otherwise, the converter will not
be able to reach maximum duty cycle. The V
range
EA
required to control the DC from 0% to DC
the equation below:
is given by
MAX
0 V
T
I
FF DC
t ǒ
EA(L)Ǔ
V
t V
EA
) V
FF Ramp
EA(L)
V
186.56 pf f
DC(inv)
0 V
where, V
threshold.
is the PWM comparator lower input
EA(L)
t
on(max)
Figure 33. Maximum ON Time Limit Waveforms
Soft Start
Soft start (SS) allows the converter to gradually reach
steady state operation, thus reducing start−up stress and
surges on the system. The duty cycle is limited during a soft
start sequence by comparing the Oscillator Ramp to the SS
An internal resistor divider from a 2.0 V reference is used
to set V
. If the DC
pin is grounded, V
is
DC(inv)
MAX
DC(inv)
0.88 V. If the pin is floating, V
is 1.19 V. This is
DC(inv)
equivalent to 60% or 80% of a 1.5 V FF Ramp. V
can
DC(inv)
voltage (V ) by means of the Soft Start Comparator.
A 6.2 m A current source starts to charge the capacitor on
be adjusted to other values by using an external resistor
network on the DC pin. For example, if the minimum
SS
MAX
the SS pin once faults are removed and V
reaches 11 V.
line voltage is 100 V, R is 1.82 MW, operating frequency
AUX
FF
The Soft Start Comparator controls the duty cycle while the
is 200 kHz and a maximum duty cycle of 70% is required,
SS voltage is below 2.0 V. Once V reaches 2.0 V, it exceeds
V
DC(inv)
is calculated as follows:
SS
the Oscillator Ramp voltage and the Soft Start Comparator
does not limit the duty cycle. Figure 34 shows the
relationship between the outputs duty cycle and the soft start
voltage.
I
6.7 kW t
on(max)
FF
V
+
DC(inv)
C
125 kW
FF
55.2 m A 6.7 kW 3.5 m s
10 pF 125 kW
V
+
+1.04 V
DC(inv)
This can be achieved by connecting a 19.6 kW resistor
from the DC pin to GND. The maximum duty cycle
MAX
limit can be disabled connecting a 100 kW resistor between
the DC and V pins.
MAX
REF
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15
NCP1280
Oscillator
Ramp
Generally, OUT1 controls the main switching element.
V
SS
Output 2, once inverted, can control a synchronous rectifier.
The overlap delay prevents simultaneous conduction.
Output 2 can also be used to control an active clamp reset.
Once V
reaches 11 V, the internal start−up circuit is
AUX
OUT2
OUT1
disabled and the One Shot Pulse Generator is enabled. If no
faults are present, the outputs turn ON. Otherwise, the
outputs remain OFF until the fault is removed and V
reaches 11 V again.
The control outputs are biased from V
AUX
. The outputs
AUX
can supply up to 10 mA each and their high state voltage is
usually 0.2 V below V . Therefore, the auxiliary supply
voltage should not exceed the maximum input voltage of the
driver stage.
If the control outputs need to drive a large capacitive load,
a driver should be used between the NCP1280 and the load.
ON Semiconductor’s MC33152 is a good selection for an
integrated driver. Figures 27 and 28 shows the relationship
between the output’s rise and fall times vs capacitive load.
AUX
Figure 34. Soft Start Timing Diagram
If the soft start period is too long, V
will discharge to
AUX
7 V before the converter output is completely in regulation
causing the outputs to be disabled. If the converter output is
not completely discharged when the outputs are re−enabled,
the converter will eventually reach regulation exhibiting a
non−monotonic start−up behavior. But, if the converter
output is completely discharged when the outputs are
re−enabled, the cycle may repeat and the converter will not
start.
Time Delay
The overlap delay between the outputs is set connecting
a resistor (R ) between the t and V pins. A minimum
D
D
REF
In the event of an UV, OV, or cycle skip fault, the soft start
capacitor is discharged. Once the fault is removed, a soft
start cycle commences. The soft start steady state voltage is
approximately 4.1 V.
overlap delay of 80 ns is obtained when R is 60 kW. If R
is not present, the delay is 200 ns.
D
D
The output duty cycle can be adjusted from 0% to 85%
selecting appropriate values of R and V . It should
FF
DC(inv)
be noted that the overlap delay may cause OUT2 to reach
100% duty cycle. Therefore, if OUT2 is used, the maximum
duty cycle of OUT2 needs to be kept below 100%. The
Control Outputs
The NCP1280 has two in−phase control outputs, OUT1
and OUT2, with adjustable overlap delay (t ). OUT2
precedes OUT1 during a low to high transition and OUT1
precedes OUT2 at any high to low transition. Figure 35
shows the relationship between OUT1 and OUT2.
D
maximum overlap delay, t , depends on the maximum
D(max)
duty cycle and frequency of operation. The maximum
overlap delay is calculated using the equation below.
(1 * DC)
t
v
D(max)
ƒ
2
t
D
(Leading)
t (Trailing)
D
For example, if the converter operates at a frequency of
300 kHz with a maximum duty cycle of 80%, the maximum
allowed overlap delay is 333 ns. However, this is a
theoretical limit and variations over the complete operating
range should be considered when selecting the overlap
delay.
OUT1
OUT2
Figure 35. Control Outputs Timing Diagram
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16
NCP1280
PACKAGE DIMENSIONS
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
−B−
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45
K
_
C
G
J
1.27 BSC
0.050 BSC
−T−
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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17
NCP1280
The product described herein (NCP1280) may be covered by one or more U.S. patents. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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NCP1280/D
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