NCP1336BDR2G [ONSEMI]
Quasi-Resonant Current Mode Controller for High Power Universal Off-Line Supplies; 准谐振电流模式控制器的高功率通用离线用品
| 型号： | NCP1336BDR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quasi-Resonant Current Mode Controller for High Power Universal Off-Line Supplies |
| 文件： | 总26页 (文件大小：1004K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1336A/B
Quasi-Resonant Current
Mode Controller for High
Power Universal Off-Line
Supplies
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The NCP1336 hosts a high−performance circuitry aimed to
powering quasi−resonant converters. Capitalizing on a novel
valley−lockout system, the controller shifts gears and reduces the
switching frequency as the power loading becomes lighter. This
results in a stable operation despite switching events always occurring
QUASI−RESONANT PWM
CONTROLLER FOR HIGH POWER
AC−DC WALL ADAPTERS
MARKING
DIAGRAM
th
in the drain−source valley. This system works down to the 4 valley
and toggles to a variable frequency mode beyond, ensuring an
excellent standby power performance.
14
14
1
NCP1336x
The controller takes benefit of a high−voltage start−up current
source to provide a quick and lossless power−on sequence. To improve
the safety in overload situations, the controller includes an Over Power
Protection circuit which clamps the delivered power at high−line.
Safety−wise, an adjustable timer relies on the feedback voltage to
detect a fault. On version B, this fault triggers a triple−hiccup on the
VCC pin which naturally reduces the average input power drawn by
the converter. On version A, when a fault is detected, the controller is
latched−off.
AWLYWWG
SO−14
CASE 751AN
SUFFIX O
1
A
x
WL
Y
WW
G
= Assembly Location
= A or B
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Particularly well suited for adapter applications, the controller
features two latch inputs: one dedicated to Over Temperature
protection (OTP) which offers an easy means to connect a pull−down
temperature sensor like an NTC, and a second one more classical that
can be used to perform an accurate Over Voltage Protection.
Finally, a brownout pin which stops the circuit operation in presence
of a low mains condition is included.
PIN CONNECTIONS
OPP
HV
OTP
Timer
ZCD
Ct
FB
CS
OVP
BO
VCC
DRV
GND
Features
(Top View)
• Quasi−Resonant Peak Current−Mode Control Operation
• Valley Switching Operation with Valley−Lockout for Noise−Immune
Operation
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
• Internal 5 ms Soft−Start
• Loss−Free Adjustable Over Power Protection
• Auto−Recovery or Latched Internal Output Short− Circuit Protection
• Adjustable Timer for Improved Short−Circuit Protection
• Overvoltage and Overtemperature Protection Inputs
• Brownout Input
• Extremely Low No−Load and Standby Power
• SO14 Package
• −500 mA/+800 mA Peak Current Source/Sink
Capability
• Internal Temperature Shutdown
• Direct Optocoupler Connection
• 3 ms Blanking Delay to Ignore Leakage Ringing at
Turn−Off
• These are Pb−Free Devices
• This Device uses Halogen−Free Molding Compound
Typical Applications
• High Power ac−dc Converters for TVs, Set−Top Boxes etc
• Offline Adapters for Notebooks
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
July, 2012 − Rev. 0
NCP1336/D
NCP1336A/B
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Pin Description
1
OPP
Adjust the Over Power
Protection
A negative voltage applied to this pin reduces the internal maximum peak
current setpoint. Connecting it to an auxiliary winding through a resistor
divider thus performs Over Power compensation. If grounded, OPP is null.
2
OTP
Over−Temperature
Connect an NTC between this pin and GND pin. Pin 2 features an internal
current source that biases the NTC. When the NTC pulls the pin down, the
circuit permanently latches−off.
Protection
3
4
5
Timer
ZCD
Ct
Timer
Wiring a capacitor to ground helps selecting the timer duration.
Zero Crossing Detection
Timing Capacitor
Connected to the auxiliary winding, this pin detects the core reset event.
A capacitor connected to this pin acts as the timing capacitor in foldback
mode.
6
7
FB
CS
Feedback Pin
Current Sense
−
Hooking an optocoupler collector to this pin will allow regulation.
This pin monitors the primary peak current.
8
GND
DRV
VCC
BO
This pin is the controller ground.
9
Driver Output
Supplies the Controller
Brownout
This pin is the driver’s output to an external MOSFET.
This pin is connected to an external auxiliary voltage.
This pin is the brownout input.
10
11
12
13
14
OVP
NC
Over−Voltage Protection
−
By pulling this pin high, the controller can be permanently latched−off.
This pin is omitted for improved creepage.
HV
High−Voltage Input
Connected to the bulk capacitor, this pin powers the internal current source
to deliver a startup current.
OVERCURRENT PROTECTION ON NCP1336 VERSIONS
Auto−Recovery
Latched
Overcurrent protection
Overcurrent protection
NCP1336 / A
NCP1336 / B
X
X
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2
NCP1336A/B
HV−bulk
+
Vout
OPP
14
13
12
1
2
3
4
5
6
7
OVP
OTP
GND
BO
ZCD
11
10
+
Vin
9
8
NCP1336
+
GND
Figure 1. Typical Application Example
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3
NCP1336A/B
VDD
+
1st
−
HV
2nd
+
HV
−
Rpullup
FB
3rd
4th
+
TSD
−
HV
Startup
VDD
+
Aux
−
PNOK
Latch
VCC
DRV
VCO
+
V
Management
Fault
CC
Clamp
VDD
ICt
BO Reset
Grand
Reset
DRV
1 2 3 4
Gate
Ct
Decimal Counter
CLK
Grand
Reset
+
rst
Ct
−
Setpoint
Vdd
ItimerC
R
S
Q
Q
Ct
Timer
Discharge
ZCD
+
+
ItimerD
Demag
−
A:
Latched
−
10 V
ESD
Leakage
Blanking
Vth
Laux
GND
S
3us Pulse
DRV
Q
IpFlag
Q
S
R
Q
Q
R
VDD
5us Timeout
VCC
PWMReset
/4
+
Grand
Reset
VOVP
OVP
−
−
noise delay
+
Ipeak_min = 25% Limit
100 ns
Leading
Edge
VDD
IOTP
OTP
PWM Reset
IpFlag
CS
−
T°
+
+
Blanking
−
SS End
VOTP
HV
Ilimit
+ Vopp
+
BO Reset
Noise Delay
VBO
−
OPP
+
+
BO
−
Ilimit
+
−
Soft−Start
IBO
Soft−Start End ? Then 1 Else 0
SS End
Figure 2. Internal Circuit Architecture
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4
NCP1336A/B
MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
VCCmax
ICCmax
Maximum Power Supply voltage, V pin, continuous voltage
−0.3 to 28
$30
V
mA
CC
Maximum current for VCC Pin
VHVmax
IHVmax
High voltage pin (pin 14) voltage range
Pin 14 current range
−0.3 to 500
V
mA
$20
Vmax
Imax
Maximum voltage on low power pins (except pin 9, pin 10 and pin 14)
Current range for low power pins (except pin 9, pin 10 and pin 14)
−0.3 to 10
$10
V
mA
VOPP
Recommended maximum operating voltage on pin OPP (pin 1)
Maximum negative current into OPP pin (pin 1)
−300
2
mV
mA
max
neg
IOPP
V
Maximum DRV pin voltage when DRV is in High state
Thermal Resistance Junction−to−Air
V
+ 1.0
V
°C/W
°C
°C
kV
V
DRV(MAX)
CC
R
120
150
q
JA
TJ
Maximum Junction Temperature
MAX
Storage Temperature Range
−60 to +150
ESD Capability, HBM model (All pins except HV) (Note 1)
ESD Capability, Machine Model (All pins except DRV) (Note 1)
ESD Capability, Machine Model (DRV pin) (Note 1)
2
200
160
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection rated using the following tests: Human Body Model 2000 V per JEDEC standard JESD22, Method
A114E. Machine Model Method 200 V per JEDEC standard JESD22, Method A115A.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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5
NCP1336A/B
ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V unless otherwise noted)
J
J
J
CC
Symbol
Rating
Min
Typ
Max
Unit
SUPPLY SECTION
VCC
V
V
increasing level at which the current source turns−off
14
8
15
9
16
10
−
V
V
on
CC
CC
VCC
level below which output pulses are stopped
min
VCC
Internal latch reset level
Internal IC consumption, no output load on DRV pin (Fsw = 10 kHz)
−
5.5
1.4
1.8
V
reset
I
−
2.0
mA
mA
CC1
ICC1
I
for a Feedback Voltage Equal to VH (internal bias reduction), with C =
VCO T
light
CC1
220 pF (corresponding to an Fsw of about 20 kHz)
ICC2
ICC3
Internal IC consumption, 1 nF output load on pin 9, Fsw = 65 kHz
−
−
2.5
3.0
0.6
mA
mA
Internal IC consumption, hiccup phase (VCC
< V < VCC )
on
0.45
min
CC
INTERNAL STARTUP CURRENT SOURCE (T > 05C) (HV Pin Biased to 60 Vdc)
J
IC2
High−voltage current source, V = 10 V (Note 3)
3
150
0.3
1
6
9
mA
mA
V
CC
IC1
High−voltage current source, V = 0
300
0.7
12
550
0.9
30
CC
V
Th
V transition level for IC1 to IC2 toggling point (I = 2.5 mA)
CC HV
I
Leakage current for the high voltage source, V
= 500 Vdc
HV(pin)
mA
leak
DRIVE OUTPUT
Output voltage rise−time @ C = 1 nF, 10%−90% of a 12 V output signal
T
r
−
−
40
25
75
60
−
ns
ns
L
T
f
Output voltage fall−time @ C = 1 nF, 10%−90% of a 12 V output signal
L
I
Source current capability at V
= 2 V
DRV
−
500
800
−
mA
mA
V
source
I
Sink current capability at V
= 10 V
−
−
sink
DRV
VDRV
DRV pin level at V close to VCC with a 33 kW resistor to GND and a 1 nF
min
7.6
−
low
CC
capacitor to GND
VDRV
DRV pin level at V = 28 V with a 1 nF capacitor to GND (Note 3)
−
−
17
V
high
CC
DEMAGNETIZATION INPUT
Input threshold voltage (V
V
th
decreasing)
ZCD(pin)
35
15
55
35
90
55
mV
mV
V
H
Hysteresis (V
increasing)
ZCD(pin)
Input clamp voltage
VC
High state (I
= 3.0 mA)
= −2.0 mA)
8
−0.9
10
−0.7
12
0
V
V
H
L
ZCD(pin)
ZCD(pin)
VC
Low state (I
T
Demag propagation delay (V
decreasing from 4 V to −0.3 V)
ZCD(pin)
−
−
2
4
150
10
250
−
ns
pF
ms
ms
dem
C
Internal input capacitance at V
= 1 V
ZCD(pin)
par
T
blank
Blanking Delay after t
3
4
ON
T
Timeout after last demag transition
CURRENT COMPARATOR
Input Bias Current @ 1 V input level on CS pin
Maximum internal current setpoint – T = 25°C – OPP pin grounded
5.25
6.5
out
I
−
0.76
0.744
22
0.02
0.8
0.8
25
−
mA
V
IB
I
I
0.84
0.856
28
Limit1
Limit2
J
Maximum internal current setpoint – T from −40°C to 125°C – OPP pin grounded
V
J
Ipeak_VCO Percentage of maximum peak current level at which VCO takes over (Note 4)
%
ns
ns
T
Propagation delay from current detection to gate OFF state
−
100
160
DEL
LEB
T
Leading Edge Blanking Duration T = −5°C to +125°C
240
240
295
295
350
360
J
T = −40°C to +125°C
J
3. Minimum value for T = 125°C.
J
4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak_VCO (Ipeak = cst)
5. If negative voltage in excess to −300 mV is applied to OPP pin, the current setpoint decrease is no longer guaranteed to be linear.
6. NTC on OTP pin with R = 8.8 kW at 110°C.
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NCP1336A/B
ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V unless otherwise noted)
J
J
J
CC
Symbol
CURRENT COMPARATOR
OPP Setpoint decrease for V
Rating
Min
Typ
Max
Unit
= −300 mV (Note 5)
OPP
35
37.5
0
40
%
%
max
OPP
Setpoint decrease for OPP pin shorted to ground
−
−
s
TIMING CAPACITOR
VCT
Maximum voltage on Ct capacitor, V < VFB
FB
5
5.5
−
V
max
T
I
CT
Source current (Ct pin grounded)
T = −5°C to +125°C
J
18
17.42
20
20
22
22
mA
J
T = −40°C to +125°C
VCT
Minimum voltage on Ct, discharge switch activated
Recommended timing capacitor value
−
−
−
90
mV
pF
min
Ct
220
−
FEEDBACK SECTION
R
Internal pullup resistor
T = −5°C to +125°C
J
16
15.5
18
18
24
24
kW
pullup
J
T = −40°C to +125°C
I
FB pin to current setpoint division ratio
3.75
0.26
4
4.25
0.34
ratio
VFB
FB pin threshold under which the Ct capacitor is clamped to VCT
0.3
1.4
1.2
0.9
0.8
1.4
1.6
1.8
2
V
V
V
V
V
V
V
V
V
T
2D
3D
4D
MAX
st
nd
VH
VH
VH
FB voltage where 1 valley ends and 2 valley starts (V decreasing)
1.316
1.128
0.846
0.752
1.316
1.504
1.692
1.88
1.484
1.272
0.954
0.848
1.484
1.696
1.908
2.12
FB
nd
rd
FB voltage where 2 valley ends and 3 valley starts (V decreasing)
FB
rd
th
FB voltage where 3 valley ends and 4 valley starts (V decreasing)
FB
th
VH
FB voltage where 4 valley ends and VCO starts (V decreasing)
VCOD
FB
th
VH
FB voltage where VCO ends and 4 valley starts (V increasing)
VCOI
FB
th
rd
VH
FB voltage where 4 ends and 3 valley starts (V increasing)
FB
4I
3I
2I
rd
nd
VH
VH
FB voltage where 3 ends and 2 valley starts (V increasing)
FB
nd
st
FB voltage where 2 ends and 1 valley starts (V increasing)
FB
PROTECTIONS
V
OVP level
2.79
15
3
3.21
25
V
OVP
Tlatch
Delay before latch confirmation (noise immunity)
20
ms
mA
del
Ilatch
Internal source current for OTP (Note 6)
T = −5°C to +125°C
J
85
82
93
93
97
98
J
T = −40°C to +125°C
Ilatch
Internal source current for OTP @ 110°C (Note 6)
−
91
0.8
5
−
mA
V
110
OTP
V
Fault detection level for OTP (Note 6)
0.76
4.65
0.84
5.35
VtimFault Timer Level Completion
V
ItimerC
Timer capacitor charging current
T = −5°C to +125°C
J
8.5
8.25
10
10
11.5
11.5
mA
J
T = −40°C to +125°C
ItimerD
TimerL
TSS
Timer capacitor discharging current
Timer length, Ctimer = 0.1 mF typical
Soft−start duration
8.5
−
10
50
5
11.5
−
mA
ms
ms
°C
−
−
TSD
Temperature shutdown
140
−
−
−
TSD
Temperature shutdown hysteresis
40
−
°C
hys
3. Minimum value for T = 125°C.
J
4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak_VCO (Ipeak = cst)
5. If negative voltage in excess to −300 mV is applied to OPP pin, the current setpoint decrease is no longer guaranteed to be linear.
6. NTC on OTP pin with R = 8.8 kW at 110°C.
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NCP1336A/B
ELECTRICAL CHARACTERISTICS
(For typical values T = 25°C, for min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V unless otherwise noted)
J
J
J
CC
Symbol
BROWNOUT PROTECTION
Rating
Min
Typ
Max
Unit
VBO
IBO
Brownout level
0.744
0.8
0.856
V
Hysteresis Current, V
< VBO
T = −5°C to +125°C
J
9
8.65
10
10
11
11
mA
BO(pin)
J
T = −40°C to +125°C
TBO
Delay before BO confirmation (noise immunity)
Brownout input bias current
11
17
23
ms
del
IBO
−
0.02
−
mA
bias
3. Minimum value for T = 125°C.
J
4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak_VCO (Ipeak = cst)
5. If negative voltage in excess to −300 mV is applied to OPP pin, the current setpoint decrease is no longer guaranteed to be linear.
6. NTC on OTP pin with R = 8.8 kW at 110°C.
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NCP1336A/B
APPLICATION INFORMATION
NCP1336 implements
a
standard current−mode
logic, the controller disables the high−voltage current
source after startup which no longer hampers the
consumption in no−load situations.
architecture operating in quasi−resonant mode. Thanks to a
novel circuitry, the controller prevents valley−jumping
instability and steadily locks out in selected valley as the
power demand goes down. Once the fourth valley is reached,
the controller continues to reduce the frequency further
down, offering excellent efficiency over a wide operating
range. Thanks to a fault timer combined to an OPP circuitry,
the controller is able to efficiently limit the output power at
high−line.
• Internal soft−start: a soft−start precludes the main
power switch from being stressed upon start−up. Its
duration is fixed and equal to 5 ms.
• OTP input: thanks to an internal current source, the
controller allows the direct connection of an NTC to
ground. As soon as the pin is brought below VOTP by
the NTC, the circuit permanently latches−off. During
soft−start, the OTP comparator is masked to allow the
voltage on pin OTP to rise above VOTP.
• Quasi−ResonanceCurrent−mode operation:
implementing quasi−resonance operation in peak
current−mode control, the NCP1336 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to a novel circuitry, the
controller locks−out in a selected valley and remains
locked until the output loading significantly changes.
This behavior is obtained by monitoring the feedback
voltage. When the load becomes lighter, the feedback
setpoint changes and the controller jumps into the next
• OVP input: thanks to an internal bias resistor to
ground, the controller allows the direct connection of a
zener diode (or a resistor divider for improved
accuracy) to a monitored voltage. As soon as the pin is
brought above VOVP, the controller latches−off.
• Short−circuit protection: short−circuit and especially
over−load protections are difficult to implement when a
strong leakage inductance between auxiliary and power
windings affects the transformer (where the auxiliary
winding level does not properly collapse in presence of
an output short). Here, when the internal 0.8 V
th
valley. It can go down to the 4 valley if necessary.
Beyond this point, the controller reduces its switching
frequency by freezing the peak current setpoint. During
quasi−resonance operation, in case of very damped
valleys, a 5 ms timer adds the missing valleys.
maximum peak current limit is activated, the timer
capacitor is charged. If the fault disappears, the timer
capacitor is discharged by a current equal to the
charging current. If the timer reaches completion while
the error flag is still present, the controller stops the
pulses and goes into a latch−off phase, operating in a
low−frequency burst−mode via a triple hiccup
• Frequency reduction in light−load conditions: when
th
the 4 valley is left, the controller reduces the
switching frequency which naturally improves the
standby power by a reduction of all switching losses.
• Overpower protection (OPP): a negative voltage
applied on OPP pin is directly added to the internal
peak current setpoint. If this voltage is created from an
auxiliary winding with flyback polarity, a direct image
of the input voltage is subtracted from the internal
clamp, thus reducing the peak current at high line. If the
OPP pin is connected to ground no compensation is
performed.
operation. To limit the fault output power, a
divide−by−three circuitry is installed on the V pin
CC
and requires 3 times a start−up sequence before
attempting to restart on version B. As soon as the fault
disappears, the SMPS resumes operation. The latch−off
phase can also be initiated, more classically, when V
CC
drops below VCC . On version A, the fault is latched.
min
• Internal high−voltage startup switch: reaching a low
no−load standby power represents a difficult exercise
when the controller requires an external, lossy, resistor
connected to the bulk capacitor. Thanks to an internal
• Brownout: the NCP1336 includes a brownout circuit
which safely stops the controller in case the input
voltage is too low. Restart occurs via a complete startup
sequence (latch reset and soft−start).
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9
NCP1336A/B
APPLICATION INFORMATION
The NCP1336 has two operating modes: quasi resonant
operation and VCO operation.
of its maximum value and the frequency is variable.
The frequency is set by the end of charge of Ct
capacitor. This capacitor is charged with a constant
current source and the capacitor voltage is compared to
an internal threshold fixed by FB voltage. When this
capacitor voltage reaches the threshold the capacitor is
rapidly discharged down to 0 V and a new period start.
The operating mode is fixed by the FB voltage:
• Quasi−resonant operation occurs for FB voltage higher
than 0.8 V (FB decreasing) or higher than 1.6 V (FB
increasing) which correspond to high output power and
medium output power.
During quasi−resonant operation, the operating valley
Startup
st nd rd
th
(1 , 2 , 3 or 4 ) is fixed by the FB voltage which is
compared internally to several voltage references
corresponding to the different valleys. There is a wide
hysteresis on each valley, allowing the controller to
adjust the output power by the current−mode control
without jumping between valleys. The peak current is
variable and is set by the FB voltage divided by 4.
NCP1336 includes a high voltage startup circuitry that
derives current from the bulk line to charge the V
capacitor. When the power supply is first connected to the
mains outlet, the internal current source is biased and
charges up the V capacitor. When the voltage on this V
capacitor reaches the VCC level, the current source turns
CC
CC
CC
on
off, reducing the amount of power being dissipated. At this
• VCO operation occurs for FB voltage lower than 0.8 V
(FB decreasing) or lower than 1.6 V (FB increasing).
This corresponds to low output power.
time, the controller is only supplied by the V capacitor,
CC
and the auxiliary supply should take over before V
CC
collapses below VCC . Figure 3 shows the internal
min
During VCO operation, the peak current is fixed to 25%
arrangement of this structure:
HV
HV
+
IC1 or IC2
-
VCC
+
+
VCC
VCC
on
GND
min
Figure 3. Startup Circuitry: The Current Source Brings VCC Above 15 V and Turns Off
In some fault situations, a short−circuit can purposely
V
CC
occur between V and GND. In high line conditions (V
CC
HV
= 370 Vdc) the current delivered by the startup device will
seriously increase the junction temperature. For instance,
since IC2 equals 3 mA (the min corresponds to the highest
T ), the device would dissipate 370 V x 3 mA = 1.11 W. To
J
avoid this situation, the controller includes a novel circuitry
made of two startup levels, IC1 and IC2. At power−up, as
long as V is below a certain level (0.7 V typ.), the source
CC
delivers IC1 (around 300 mA typical), then, when V
CC
reaches 0.7 V, the source smoothly transitions to IC2 and
delivers its nominal value. As a result, in case of
short−circuit between V and GND, the power dissipation
CC
will drop to 370 V x 300 mA = 111 mW. Figure 4 portrays
this particular behavior:
Figure 4. The Dual Level Startup Current Source
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10
NCP1336A/B
The first startup period is calculated by the formula, CV
ramps up the peak current to I
(0.8 V / R
) which is
sense
max
= It which implies a 22 mF x 0.9 V / 150 mA = 132 ms startup
time for the first sequence. The second sequence is obtained
by changing I to 3 mA (worst case calculation) with DV =
15 V − 0.9 V = 14.1 V, which finally leads to a second startup
time of 22 mF x 14.1 V / 3 mA = 103 ms. The total startup
time becomes 103 ms + 132 ms = 235 ms. Please note that
this calculation is approximated by the presence of the knee
in the vicinity of the transition.
reached after a typical 5 ms soft−start period. As soon as the
CS voltage reaches 0.8 V = I , the internal error flag
Limit1
IpFlag is asserted. When the error flag is asserted, the current
source on pin 3 is activated and charges up the capacitor
connected to this pin. If the error flag is still asserted when
the timer capacitor has reached the threshold level
VtimFault, then the controller assumes that the power
supply has really undergone a fault condition and
immediately stops all pulses to enter a safe burst operation.
As soon as V reaches VCC , drive pulses are delivered
CC
on
Figure 5 depicts the V evolution during a proper startup
sequence, showing the state of the error flag:
on pin 9 and the auxiliary winding increases the voltage on
the V pin. At the same time, the controller smoothly
CC
CC
Figure 5. An error flag gets asserted as soon as the current setpoint reaches its upper limit
(0.8 V/Rsense). Here the timer lasts 50 ms, a 100 nF capacitor being connected to pin 3.
NCP1336 Operation
The valley detection is done by monitoring the voltage of
toggle one after another to select the proper valley. The
activation of an “n” valley comparator disables the “n+1” or
“n−1” valley comparator (depending if FB increases or
decreases) and enables the corresponding “n” output of the
decimal counter. Figure 6 shows the internal arrangement of
the valley selection circuitry.
the auxiliary winding of the transformer. The typical
detection level is fixed at 55 mV. When a valley is detected,
the decimal counter is incremented. The operating valley
st nd rd
th
(1 , 2 , 3 or 4 ) is determined by the FB voltage. As FB
voltage decreases or increases, the valley comparators
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11
NCP1336A/B
VDD
+
−
1st
Rpullup
FB
2nd
+
−
3rd
4th
+
−
+
−
VCO
VDD
ICt
1 2 3 4
Decimal Counter
CLK
Ct
Setpoint
V
FBth
−
+
rst
Ct
Ct
Discharge
DRV
ZCD
+
−
Demag
S
R
Q
Q
Leakage
Blanking
10 V
ESD
Vth
Time
Out
Laux
DRV
Tblank
CS Comparator
Figure 6. Valley Selection and VCO Internal Schematic
When an “n” valley is asserted by the valley selection
circuitry, the controller is locked in this valley until the FB
voltage decreases of 0.6 V (“n+1” valley activates) or
increases of 0.8 V (“n−1” valley activates). The peak current
adjusts to deliver the necessary output power (See Figure 7
and Figure 8). Each comparator has a hysteresis of 600 mV
that helps to stabilize the valley selection in case of
oscillations on FB voltage.
Figure 7. Peak Current Setpoint and Selected Valley
vs. FB Voltage when FB Voltage Decreases
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12
NCP1336A/B
Figure 8. Selected Valley According to FB State
As the output load decreases (FB voltage decreases), the
to deliver the necessary output power. This allows achieving
very low standby power consumption.
Figure 9 shows a simulation case where the output current
of a 19 V / 60 W adapter decreases from 2.5 A to 0.5 A. No
instability is seen during the valley transitions (Figures 10,
11, 12 and 13.)
valleys are incremented from the first to the fourth. When
the fourth valley is reached, if FB voltage further decreases
below 0.8 V, the controller enters VCO mode as in
NCP1351.
During VCO operation, the peak current is frozen to 25%
of maximum peak current: the switching frequency expands
Figure 9. Output Load Decreases from 2.5 A to
0.5 A at VIN = 120 Vdc for a 19 V / 60 W Adapter
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13
NCP1336A/B
feedback
vdrain
vct
2
3
4
2.20
1.80
V
FB
2
1.40
1.00
600m
300
200
100
0
V
drain
3
−100
4.00
3.00
2.00
1.00
0
V
Ct
4
6.41m
6.43m
6.45m
time in seconds
6.47m
6.49m
Figure 10. Zoom 1: 1st to 2nd Valley Transition
feedback
vdrain
vct
2
3
4
2.20
1.80
V
FB
1.40
2
1.00
600m
300
200
100
0
V
drain
3
−100
4.00
3.00
2.00
1.00
0
V
Ct
4
7.135m
7.153m
7.170m
time in seconds
7.188m
7.205m
Figure 11. Zoom 2: 2nd to 3rd Valley Transition
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14
NCP1336A/B
feedback
vdrain
vct
2
3
4
2.20
1.80
V
FB
1.40
1.00
2
3
600m
300
200
100
0
V
drain
−100
4.00
3.00
2.00
1.00
0
V
Ct
4
7.902m
7.917m
7.932m
time in seconds
7.946m
7.961m
Figure 12. Zoom 3: 3rd to 4th Valley Transition
feedback
vdrain
vct
2
3
4
2.20
1.80
V
FB
1.40
1.00
2
600m
300
200
100
0
V
drain
3
−100
4.00
3.00
2.00
1.00
0
V
Ct
4
8.24m
8.26m
8.29m
time in seconds
8.31m
8.34m
Figure 13. Zoom 4: 4th Valley to VCO Mode Transistion
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15
NCP1336A/B
Time Out
integrates a Time Out function that acts as a clock for the
decimal counter. The controller thus continues its normal
operation. To avoid having a too big step in frequency, the
time out duration is set to 5.25 ms. Figures 15 and 16 detail
the time out operation.
In case of extremely damped free oscillations, the ZCD
comparator can be unable to detect the valleys.
Consequently, the decimal counter clock is in low state and
the drive pulses stops. To avoid such situation, NCP1336
1
2
3
4
Decimal Counter
clk
rst
ZCD
+
-
demag
+
10 V
Vth
ESD
Leakage
Blanking
Laux
3 ms Pulse
DRV
Vdd
5 ms
Timeout
+
-
+
100 ns
Figure 14. Time Out Circuit
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16
NCP1336A/B
Demag
Vth
3
high
low
3rd
14
12
The 3rd Valley is Validated
2nd
The 3rd Valley is Not
Detected by the ZCD Comp
high
low
ZCDcomp
TimeOut
15
16
The 2nd Valley is Detected
by the ZCD Comparator
high
low
TimeOut Adds a Pulse to Account
for the Missing 3rd Valley
high
low
Clk
17
4.79m
4.81m
4.83m
time in seconds
4.85m
4.87m
Figure 15. Time Out Operation Chronogram
Demag
Vth
3
4th
high
low
18
14
The 4th Valley is Validated
3rd
high
low
15
16
ZCDcomp
TimeOut
high
low
TimeOut Adds 2 Pulses to Account for
the Missing 3rd and 4th Valley
high
low
17 Clk
7.08m
7.12m
7.16m
7.20m
7.24m
time in seconds
Figure 16. Time Out Operation Chronogram continued
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17
NCP1336A/B
VCO Mode
VCO operation occurs for FB voltage lower than 0.8 V
(FB decreasing), or lower than 1.6 V (FB increasing). This
corresponds to low output power.
During VCO operation, the peak current is fixed to 25%
of its maximum value and the frequency is variable and
expands as the output power decreases.
the capacitor voltage is compared to an internal threshold
fixed by FB voltage (see Figure 6). When this capacitor
voltage reaches the threshold, the capacitor is rapidly
discharged down to 0 V and a new period start. The internal
threshold is inversely proportional to the FB voltage. The
relationship between V
and V is: V
= 6.5 − (10/3)
FBth
FB
FBth
The frequency is set by the end of charge of Ct capacitor.
This capacitor is charged with a constant current source and
V . When V is lower than 0.3 V, Ct voltage is clamped to
FB FB
VCT
= 5.5 V. Figure 17 shows the VCO mode at works.
max
iout
vct
v(fbint:x1)
drv
5
1
2
3
800m
600m
400m
200m
0
I
OUT
1
Ct,
7.00
5.00
FB threshold
3
2
3.00
1.00
−1.00
30.0
20.0
10.0
0
DRV
5
−10.0
7.57m
7.78m
7.99m
time in seconds
8.20m
8.40m
Figure 17. In VCO Mode, as the Power Output Decreases the Frequency Expands
HV
Vcc Management
Vcc
S
Vdd
Q
Q
DRV
Fault
I
R
timerC
PNOK
PWM
Reset
Timer
PWM
Comparator
+
-
CS
+
C
I
timer
timerD
-
+
FB/4
R
S
VtimFault
Q
Q
Max Ip
Comparator
IpFlag
+
OPP
-
+
Ilimit + Vopp
+
I
limit
Figure 18. Fault Timer Schematic
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18
NCP1336A/B
Short−circuit or Overload Mode
Figure 18 shows the implementation of the fault timer.
When the current in the MOSFET is higher than, “Max
and the PWM comparator triggers the discharge of the timer
capacitor.
If “IpFlag” and PWMreset occur at the same time, the
PWMreset signal is the strongest and the capacitor is
discharged.
(0.8 V / R ) Ip” comparator trips and the timer capacitor is
sense
charged by ItimerC current source. When the current comes
back within safe limits, “Max Ip” comparator becomes silent
v(ipflag:x1)
v(pwm:x1)
feedback
vtimer
9
3
4
8
V
FB
3.40
3.00
2.60
2.20
1.80
1.40
1.00
8
9
600m
200m
−200m
V
Timer
high
IpFlag
low
3
4
high
PWMreset
low
6.13m
6.37m
6.60m
time in seconds
6.84m
7.08m
Figure 19. Timer Operating Chronograms
There can be various events that force a fault on the
primary side controller. We can split them in different
situation, each having a particular configuration:
1. The converter regulates but the auxiliary winding
collapses: this is a typical situation linked to the
usage of a constant−current / constant−voltage
situation. If the fault goes away, the SMPS
resumes operation.
2. In the second case, the converter operates in
regulation, but the output is severely overloaded.
However, due to the bad coupling between the
power and the auxiliary windings, the controller
(CC−CV) type of controller. If the output current
increases, the voltage feedback loop gives up and
V
does not go low. The peak current is pushed
CC
to the maximum, the error flag IpFlag is
consequently asserted and the timer starts to count.
Upon completion, all pulses are stopped and
triple−startup hiccup mode is entered for
the current loop takes over. It means that V
OUT
goes low but the feedback loop is still closed
because of the output current monitoring.
Therefore, seen from the primary side, there is no
fault. However, there are numerous charger
applications where the output voltage shall not go
below a certain limit, even if the current is
controlled. To cope with this situation, the
controller features a precise under−voltage lockout
version B. If the fault goes away, the SMPS
resumes operation (Figure 21). For version A,
when the timer finishes counting, the pulses stop
and the circuit stays latched until the user cycles
down the power supply (Figure 22).
3. Another case exists where the short−circuit makes
comparator biased to a VCC level. When this
the auxiliary level go below VCC . In that case,
min
min
level is crossed, whatever the other pin conditions,
pulses are stopped and the controller enters the
safe hiccup mode, trying to re−start. Figure 20
shows how the converter will behave in this
the timer length is truncated and all pulses are
stopped. The triple hiccup fault mode is entered
and the SMPS tries to re−start. When the fault is
removed, the SMPS resumes operation.
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19
NCP1336A/B
Figure 20. First Fault Mode Case, the Auxiliary
Winding Collapses but Feedback is Still There
Figure 21. Short−Circuit Case Where Vaux Does
NOT Collapse on Version B
Figure 22. Short−Circuit Case Where Vaux Does
NOT Collapse on Version A
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20
NCP1336A/B
Figure 23. This Case is Similar to a Short−Circuit Where Vaux Does Collapse
The recurrence in hiccup mode can easily be adjusted by either reducing the timer or increasing the V capacitor. Figure 24
CC
details the various time portion a hiccup is made of:
Figure 24. The Burst Period is Ensured by the VCC Capacitor Charge / Discharge Cycle
If by design we have selected a 22 mF V capacitor, it
The total period duration is thus the sum of all these events
which leads to t = 572 ms. If t = 50 ms, then our
burst duty−cycle equals 50 ms / (572 ms + 50 ms) ≈ 8%,
which is good. Should the user like to further decrease or, to
CC
becomes easy to evaluate the burst period and its duty−cycle.
This can be done by properly identifying all time events on
Figure 8 and applying the classical formula:
hiccup
fault
the contrary, increase this duty−cycle, changing the V
capacitor is an easy job.
CC
CDV
I
t +
• t : I = 3 mA, ΔV= 15 V − 9 V = 6 V ³ t = 44 ms
1
1
• t : I = ICC3 = 600 mA, ΔV= 15 V − 9 V = 6 V ³ t =
2
2
220 ms
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21
NCP1336A/B
Over Voltage / Over Temperature Protection
The OTP and OVP pins feature circuitries to protect the circuit against high temperature and high voltage (see Figure 25).
Vcc
+
VOVP
-
OVP
+
20 ms Filter
Vdd
R
bias
End of
Soft−start
IOTP
OTP
-
+
+
T°
VOTP
Figure 25. Pin Latch Circuitry
OVP
OTP
A current flows out of the OTP pin into the NTC resistor,
When V increases (OVP), a current starts to flow in the
CC
thus imposing a voltage on the OTP pin. When the
temperature increases, the NTC’s resistance reduces (For
zener (which much be biased externally), and the voltage on
the OVP pin starts to increase. When this voltage reaches
example, at 110°C, R
= 8.8 k instead of 470 k at 25°C)
V
, the circuit immediately stops pulsing and stays
NTC
OVP
and the voltage on the OTP pin decreases until it reaches
: the comparator trips and latches−off the controller. To
latched until the user cycles down the power supply. The
reset occurs if V
V
OTP
drops below 5 V (or brownout is
CC
reset the controller, the user must unplug and re−plug the
power supply.
During start−up and soft−start, the output of the OTP
comparator is masked to allow for the voltage on the OTP
pin to grow if a capacitor is installed across the NTC for
filtering purposes.
detected).
Figures 26 and 27 details the operating diagrams in case
of an over temperature and an overvoltage event.
Ambient temperature
increases
V
OTP(pin)
V
OTP
Figure 26. Operating Diagrams in Case of an Over Temperature
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22
NCP1336A/B
V
OVP(pin)
V
OVP
Figure 27. Operating Diagrams in Case of an Over Voltage
Over Power Protection
The implementation of over power compensation in
NCP1336 is described by Figure 28. A negative voltage
applied on the OPP pin directly affects the precise maximum
peak current reference.
R
upper
OPP
0.8 V + Vopp
+
-
IpFlag
+
Aux
ESD
Protection
+
0.8 V
R
lower
CS
Leading Edge
Blanking
+
-
PWMreset
R
sense
FB/4
Figure 28. The Internal OPP Circuitry Implemented on NCP1336
By connecting the OPP pin through a resistor divider to an
auxiliary winding with flyback polarity, where a negative
voltage proportional to the input voltage appears during the
on−time, the maximum peak current setpoint is simply
decreased according to V , following Figure 29.
IN
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23
NCP1336A/B
V
HV
Figure 29. Peak Current Setpoint Variation vs. OPP Pin Voltage
Rupper
Rlower
By adding a zener diode in series with the resistor divider,
the user has the choice to adjust the level at which the OPP
is applied to the power chip.
0.25 370 * (−0.2)
−0.2
+ *
+ 461.5
With R
= 470 kW and R
= 1 kW for instance, the
upper
lower
Design Example
OPP function is performed with negligible power wasted in
the resistor divider.
Let us assume we need a current setpoint reduction of 25%
at 370 Vdc, which corresponds to a sense voltage of 600 mV.
We thus need to apply 600 mV − 800 mV = −200 mV on
OPP pin to perform the expected compensation.
Knowing that the voltage that appears on the auxiliary
Brownout
The NCP1336 features a brownout pin to protect the
power supply against low input voltage condition. This pin
permanently monitors a fraction of the bulk voltage through
a voltage divider. When this image of bulk voltage is below
the VBO threshold, the controller stops switching. When the
bulk voltage comes back within safe limits, the circuit goes
through a new startup sequence including soft−start and
restarts switching (Figure 30). The hysteresis on brownout
pin is implemented with a low side current source sinking
winding during the on−time is −N
V , with N
the
p,aux IN
p,aux
auxiliary to primary turn ratio of the transformer (N
=
p,aux
N
aux
/N ), we can simply calculate the ratio of the resistor
p
divider:
Rupper
Rlower
Np,aux
V
IN * VOPP
+ *
VOPP
Assuming the turn ratio of the transformer is N
we obtain:
= 0.25,
p,aux
10 mA when the brownout comparator is low (V
<
bulk
V
).
bulkON
Figure 30. Brownout Operating Chronograms
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24
NCP1336A/B
HV−bulk
+
VBO
20 ms Noise Delay
R
upper
BO Reset
BO
-
+
BO Comp
R
lower
IBO
IBO “on” if BO Comp “low”
IBO “off” if BO Comp “high”
Figure 31. Brownout Circuitry
The following equations show how to calculate the
resistors for BO pin.
First of all, select the bulk voltage value at which the
VBO(VbulkON * VbulkOFF
)
Rlower
+
+
I
BO(VbulkOFF * VBO)
R
lower(VbulkOFF * VBO
)
controller must start switching (V
) and the bulk
bulkON
Rupper
VBO
voltage for shutdown (V ). Then use the following
bulkOFF
equation to calculate R
and R
.
upper
lower
Design Example
V
BO
= 0.8 V
I
= 10 mA
BO
We select: VbulkON = 120 V, VbulkOFF = 60 V
VBO @ (VbulkON * VbulkOFF
)
0.8 V @ (120 V * 60 V)
10 mA @ (60 V * 0.8 V)
Rlower
+
+
+ 81.1 kW
IBO @ (VbulkOFF * VBO)
Rlower @ (VbulkOFF * VBO
)
81.1 kW @ (60 V * 0.8 V)
Rupper
+
+
+ 6 MW
VBO
0.8 V
ORDERING INFORMATION
†
Device
NCP1336ADR2G
Package Type
Shipping
SO−14 Less Pin 13
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
NCP1336BDR2G
SO−14 Less Pin 13
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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25
NCP1336A/B
PACKAGE DIMENSIONS
SOIC−14 NB, LESS PIN 13
CASE 751AN
ISSUE A
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN
MAX
1.75
0.25
0.25
0.49
8.75
4.00
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
M
S
S
0.25
C A
B
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
5.80
0.25
0.40
0
6.20
0.50
1.25
7
M
A1
e
M
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
13X
1.18
1
1.27
PITCH
13X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP1336/D
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