NCP1342AMDCDD1R2G [ONSEMI]
准谐振反激控制器,带谷锁闭开关;型号: | NCP1342AMDCDD1R2G |
厂家: | ONSEMI |
描述: | 准谐振反激控制器,带谷锁闭开关 开关 反激控制 控制器 |
文件: | 总41页 (文件大小:882K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NCP1342
High Frequency Quasi-
Resonant Flyback Controller
The NCP1342 is a highly integrated quasi−resonant flyback
controller suitable for designing high−performance off−line power
converters. With an integrated active X2 capacitor discharge feature,
the NCP1342 can enable no−load power consumption below 30 mW.
The NCP1342 features a proprietary valley−lockout circuitry,
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th
ensuring stable valley switching. This system works down to the 6
valley and transitions to frequency foldback mode to reduce switching
losses. As the load decreases further, the NCP1342 enters quiet−skip
mode to manage the power delivery while minimizing acoustic noise.
To ensure light load performance with high frequency designs, the
NCP1342 incorporates Minimum Peak Current Modulation (MPCM)
to reduce the switching frequency quickly. To help ensure converter
ruggedness, the NCP1342 implements several key protective features
such as internal brownout detection, a non−dissipative Over Power
Protection (OPP) for constant maximum output power regardless of
input voltage, a latched overvoltage and NTC−ready overtemperature
protection through a dedicated pin, and line removal detection to safely
discharge the X2 capacitors when the ac line is removed. If transient
load capability is desired, the NCP1343 offers the same performance
and features with the addition of power excursion mode (PEM).
8
9
1
1
SOIC−9 NB
D SUFFIX
CASE 751BP
SOIC−8 NB
D SUFFIX
CASE 751
MARKING DIAGRAMS
8
9
1
1342abcde
1342abcde
ALYW
ALYW
G
G
1
Features
1342abcde = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Integrated High−Voltage Startup Circuit with Brownout Detection
• Integrated X2 Capacitor Discharge Capability
• Wide V Range from 9 V to 28 V
CC
• 28 V V Overvoltage Protection
CC
• Abnormal Overcurrent Fault Protection for Winding Short Circuit or
Saturation Detection
PIN CONNECTIONS
• Internal Temperature Shutdown
1
Fault
HV
• Valley Switching Operation with Valley−Lockout for Noise−Free
FMAX
FB
ZCD/OPP
CS
Operation
VCC
DRV
GND
• Frequency Foldback with 25 kHz Minimum Frequency Clamp for
Increased Efficiency at Light Loads
• MPCM for Fast Reduction of Switching Frequency at Light Loads
1
HV
Fault
FB
• Skip Mode with Quiet−Skip Technology for Highest Performance
VCC
During Light Loads
DRV
GND
ZCD/OPP
CS
• Minimized Current Consumption for No Load Power Below 30 mW
• Frequency Jittering for Reduced EMI Signature
(Top Views)
• Latching or Auto−Recovery Timer−Based Overload Protection
• Adjustable Overpower Protection (OPP)
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
• Adjustable Maximum Frequency Clamp
• Fault Pin for Severe Fault Conditions, NTC Compatible for OTP
• 4 ms Soft−Start Timer
this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
December, 2017 − Rev. 1
NCP1342/D
NCP1342
TYPICAL APPLICATION SCHEMATIC
Vout
+
+
NCP1342
Fault
HV
+
FB
VCC
L
EMI
Filter
ZCD/OPP DRV
CS
GND
N
+
−tº
Figure 1. NCP1342 8−Pin Typical Application Circuit
Vout
+
+
NCP1342
Fault
HV
FMAX
+
FB
VCC
L
EMI
Filter
ZCD/OPP DRV
CS
GND
N
+
−tº
Figure 2. NCP1342 9−Pin Typical Application Circuit
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2
NCP1342
Table 1. PART NUMBER DECODE − NCP1342ABCDEFR2G
NCP1342
A
B
C
D
E
F*
R2G*
OTP/Overload
A − AR/AR
Jitter Frequency/Amplitude
A − 1.55 kHz/75 mV
B − 1.55 kHz/92 mV
C − 1.55 kHz/55 mV
D − 1.55 kHz/61 mV
E − 1.3 kHz/75 mV
F − 1.3 kHz/92 mV
G − 1.3 kHz/55 mV
H − 1.3 kHz/61 mV
J − 3.9 kHz/75 mV
K − 3.9 kHz/92 mV
L − 3.9 kHz/55 mV
M − 3.9 kHz/61 mV
N − Disabled
Quiet−Skip
A − 800 Hz
B − 1.2 kHz
C − 1.56 kHz
D − Disabled
CS Min
MPCM
Pins
A − 200 mV
B − 150 mV
C − 100 mV
D − 250 mV
A − 400 mV
B − 350 mV
C − 300 mV
D − 250 mV
E − Disabled
D − 8 Pins
D1 − 9 Pins
B − Latch/AR
C − AR/Latch
D − Latch/Latch
Pb
Free
Device
*In OPN only − not on device marking
Table 2. ORDERING INFORMATION
Part Number
Device Marking
Package
Shipping
NCP1342BLACADR2G
NCP1342AMDAAD1R2G
NCP1342DADBDD1R2G
1342BLACA
1342AMDAA
1342DADBD
SOIC−8 NB (Pb−Free)
2500 / Tape & Reel
SOIC−9 NB (Pb−Free)
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3
NCP1342
FUNCTIONAL BLOCK DIAGRAM
TSD
BO
X2/BO Detect
+
V
DD
HV
X2
Abnormal OCP
OVLD
V
V
Fault
CC
CC(OVP)
FMAX
Control
Management
OVP
OTP
Management
FMAX
QR_FMAX
VCC
Valley/FF
Control
FB
Fault
Off−Time
Control
Dead−Time
Control
ZCD/OPP
OPP
Control
V
CC
t
QR_FMAX
tout
Clamp
V
OPP
FB(open)
R
Quiet−Skip
Control
FB
S
R
Q
FB
DRV
GND
Jitter Ramp
K
FB
FB
CS
÷
MPCM
Control
On−Time
Control
FB
V
DD
Fault
V
DD
OVP
OTP
OVP/OTP
Detect
Fault
ILIM1
Detect
t
t
OVLD
OVLD
LEB1
R
Fault(clamp)
OPP
V
Fault(clamp)
ILIM2
Detect
t
Abnormal OCP
Count 4
LEB2
8−Pin
9−Pin
Figure 3. NCP1342 Block Diagram
Table 3. PIN FUNCTIONAL DESCRIPTION
8−Pin
9−Pin
Pin Name
Function
1
1
Fault
The controller enters fault mode if the voltage on this pin is pulled above or below the fault
thresholds. A precise pull up current source allows direct interface with an NTC thermistor.
−
2
FMAX
A resistor to ground sets the value for the maximum switching frequency clamp. If this pin is
pulled above 4 V, the maximum frequency clamp is disabled.
2
3
3
4
FB
Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
ZCD/OPP
A resistor divider from the auxiliary winding to this pin provides input to the demagnetization de-
tection comparator and sets the OPP compensation level.
4
5
6
5
6
7
CS
Input to the cycle−by−cycle current limit comparator.
Ground reference.
GND
DRV
This is the drive pin of the circuit. The DRV high−current capability (−0.5 /+0.8 A) makes it suit-
able to effectively drive high gate charge power MOSFETs.
7
8
VCC
This pin is the positive supply of the IC. The circuit starts to operate when V exceeds 17 V and
CC
turns off when V goes below 9 V (typical values). After start−up, the operating range is 9 V up
CC
to 28 V.
−
8
9
N/C
HV
Removed for creepage distance.
10
This pin is the input for the high voltage startup and brownout detection circuits. It also contains
the line removal detection circuit to safely discharge the X2 capacitors when the line is removed.
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4
NCP1342
Table 4. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
High Voltage Startup Circuit Input Voltage
High Voltage Startup Circuit Input Current
Supply Input Voltage
V
−0.3 to 700
HV(MAX)
HV(MAX)
I
20
mA
V
V
−0.3 to 30
CC(MAX)
CC(MAX)
Supply Input Current
I
30
1
mA
V/ms
V
Supply Input Voltage Slew Rate
Fault Input Voltage
dV /dt
CC
V
−0.3 to V + 0.7 V
Fault(MAX)
Fault(MAX)
CC
Fault Input Current
I
10
mA
V
Zero Current Detection and OPP Input Voltage
Zero Current Detection and OPP Input Current
Maximum Input Voltage (Other Pins)
Maximum Input Current (Other Pins)
Driver Maximum Voltage (Note 1)
Driver Maximum Current
V
−0.3 to V + 0.7 V
ZCD(MAX)
CC
I
−2/+5
−0.3 to 5.5
10
mA
V
ZCD(MAX)
V
MAX
I
mA
V
MAX
V
DRV
−0.3 to V
DRV(high)
I
500
mA
DRV(SRC)
I
800
DRV(SNK)
Operating Junction Temperature
Storage Temperature Range
T
−40 to 125
–60 to 150
°C
°C
J
T
STG
2
Power Dissipation (T = 25°C, 1 oz. Cu, 42 mm Copper Clad Printed Circuit)
P
mW
A
D(MAX)
DR2G Suffix, SOIC−8
D1R2G Suffix, SOIC−9
450
330
2
Thermal Resistance (T = 25°C, 1 oz. Cu, 42 mm Copper Clad Printed Circuit)
R
°C/W
A
qJA
DR2G Suffix, SOIC−8
D1R2G Suffix, SOIC−9
225
300
ESD Capability
Human Body Model per JEDEC Standard JESD22−A114F (All pins except HV)
Human Body Model per JEDEC Standard JESD22−A114F (HV Pin)
Charge Device Model per JEDEC Standard JESD22−C101F
Latch−Up Protection per JEDEC Standard JESD78E
2000
800
1000
V
V
V
100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, V
, when V
DRV(high)
exceeds the driver clamp voltage. Otherwise, the
CC
maximum driver voltage is V
.
CC
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5
NCP1342
Table 5. ELECTRICAL CHARACTERISTICS: (V = 12 V, V = 120 V, V
= open, V = 2.4 V, V = 0 V, V
= 0 V, V
CC
HV
Fault
FB
CS
ZCD FMAX
= 0 V, C
= 100 nF , C
= 100 pF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
VCC
DRV
J
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
START−UP AND SUPPLY CIRCUITS
Supply Voltage
dV/dt = 0.1 V/ms
V
Startup Threshold
V
increasing
decreasing
decreasing
V
16.0
17.0
8.5
17.0
18.0
9.0
–
18.0
19.0
9.5
–
CC
CC
CC
CC(on)
Discharge Voltage During Line Removal
Minimum Operating Voltage
Operating Hysteresis
V
V
V
CC(X2_reg)
V
CC(off)
V
CC(on)
− V
V
7.5
CC(off)
CC(HYS)
CC(reset)
CC(inhibit)
Internal Latch / Logic Reset Level
V
CC
decreasing
V
4.5
6.5
0.70
7.5
1.05
Transition from I
to I
V
CC
increasing, I = 650 mA
V
0.30
start1
start2
HV
V
Delay
V
decreasing
t
delay(VCC_off)
25
–
32
–
40
500
40
ms
ms
V
CC(off)
CC
Startup Delay
Delay from V
to DRV Enable
t
delay(start)
CC(on)
Minimum Voltage for Start−Up Current
Source
V
–
–
HV(MIN)
Inhibit Current Sourced from V Pin
V
= 0 V
I
I
0.2
2.4
0.5
0.65
5.0
mA
mA
mA
CC
cc
start1
Start−Up Current Sourced from V Pin
V
= V – 0.5 V
cc(on)
3.75
CC
cc
start2
Start−Up Circuit Off−State Leakage Current
V
= 162.5 V
I
I
I
–
–
–
–
–
–
15
20
50
HV
HV(off1)
HV(off2)
HV(off3)
V
= 325 V
= 700 V
HV
HV
V
Supply Current
mA
Fault or Latch
V
= V
– 0.5 V
I
I
I
−
−
−
0.115
0.230
1.0
0.150
0.315
1.5
CC
CC(on)
CC1
CC2
CC3
Skip Mode (excluding FB current)
Operating Current
V
FB
= 0 V
f
= 50 kHz, C
= open
sw
DRV
V
CC
V
CC
Overvoltage Protection Threshold
Overvoltage Protection Delay
V
27
25
28
32
29
40
V
CC(OVP)
t
ms
delay(VCC_OVP)
X2 CAPACITOR DISCHARGE
Line Voltage Removal Detection Timer
Discharge Timer Duration
t
65
21
21
13
–
100
32
32
18
–
135
43
43
23
30
ms
ms
ms
mA
V
line(removal)
t
line(discharge)
Line Detection Timer Duration
t
line(detect)
V
CC
Discharge Current
V
= 20 V
I
CC
CC(discharge)
HV Discharge Level
BROWNOUT DETECTION
System Start−Up Threshold
Brownout Threshold
Hysteresis
V
HV(discharge)
V
increasing
decreasing
increasing
decreasing
V
V
107
93
112
98
116
102
–
V
V
HV
BO(start)
BO(stop)
BO(HYS)
BO(stop)
V
HV
V
V
9.0
40
14
V
HV
HV
Brownout Detection Blanking Time
GATE DRIVE
V
t
70
100
ms
Rise Time
V
from 10% to 90%
from 90% to 10%
t
–
–
20
5
40
30
ns
ns
DRV
DRV(rise)
Fall Time
V
DRV
t
DRV(fall)
Current Capability
Source
mA
I
–
–
500
800
–
–
DRV(SRC)
Sink
I
DRV(SNK)
High State Voltage
V
CC
= V
V
+ 0.2 V, R
= 10 kW
V
V
8.0
10
–
–
V
V
CC(off)
DRV
DRV(high1)
12
14
= 30 V, R
= 10 kW
DRV(high2)
CC
DRV
Low Stage Voltage
V
= 0 V
V
–
–
0.25
Fault
DRV(low)
2. NTC with R110 = 8.8 kW
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NCP1342
Table 5. ELECTRICAL CHARACTERISTICS: (V = 12 V, V = 120 V, V
= open, V = 2.4 V, V = 0 V, V
= 0 V, V
CC
HV
Fault
FB
CS
ZCD FMAX
= 0 V, C
= 100 nF , C
= 100 pF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
VCC
DRV
J
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
FEEDBACK
Open Pin Voltage
to Internal Current Setpoint Division
V
4.8
−
5.0
4
5.1
−
V
–
FB(open)
V
FB
K
FB
Ratio
Internal Pull−Up Resistor
V
FB
= 0.4 V
R
17
20
23
kW
FB
Valley Thresholds
V
st
nd
Transition from 1 to 2 valley
V
V
V
V
V
decreasing
decreasing
decreasing
decreasing
decreasing
increasing
increasing
increasing
increasing
increasing
V
1to2
V
2to3
V
3to4
V
4to5
V
5to6
V
6to5
V
5to4
V
4to3
V
3to2
V
2to1
1.316
1.128
1.034
0.940
0.846
1.410
1.504
1.598
1.692
1.880
1.400
1.200
1.100
1.000
0.900
1.500
1.600
1.700
1.800
2.000
1.484
1.272
1.166
1.060
0.954
1.590
1.696
1.802
1.908
2.120
FB
FB
FB
FB
FB
nd
rd
Transition from 2 to 3 valley
rd
th
Transition from 3 to 4 valley
th
th
Transition from 4 to 5 valley
th
th
Transition from 5 to 6 valley
th
th
Transition from 6 to 5 valley
V
V
V
V
V
FB
FB
FB
FB
FB
th
th
Transition from 5 to 4 valley
th
rd
Transition from 4 to 3 valley
rd
nd
Transition from 3 to 2 valley
nd
st
Transition from 2 to 1 valley
Maximum Frequency Clamp
kHz
V
FMAX
V
FMAX
= 0.5 V
= 3.5 V
f
f
440
61
500
70
560
79
MAX1
MAX2
FMAX Disable Threshold
FMAX Pin Source Current
Maximum On Time
9−Pin Versions Only
V
3.85
9.0
28
4.00
10
4.15
11
V
FMAX(disable)
I
mA
ms
FMAX
t
32
40
on(MAX)
DEMAGNETIZATION INPUT
ZCD threshold voltage
V
decreasing
increasing
V
35
15
–
60
25
80
90
55
mV
mV
ns
ZCD
ZCD(trig)
ZCD hysteresis
V
V
ZCD(HYS)
ZCD
Demagnetization Propagation Delay
V
ZCD
step from 4.0 V to −0.3 V
t
250
demag
ZCD Clamp Voltage
Positive Clamp
Negative Clamp
V
I
= 5.0 mA
= −2.0 mA
V
V
12.4
−0.9
12.7
−0.7
13
0
QZCD
ZCD(MAX)
I
QZCD
ZCD(MIN)
Blanking Delay After Turn−Off
t
600
700
800
ns
ZCD(blank)
Timeout After Last Demagnetization
Detection
While in soft−start
After soft−start complete
t
t
80
5.1
100
6.0
120
6.9
ms
(tout1)
(tout2)
CURRENT SENSE
Current Limit Threshold Voltage
Leading Edge Blanking Duration
V
increasing
V
0.760
220
0.800
265
0.840
330
V
CS
ILIM1
DRV minimum width minus
t
ns
LEB1
t
delay(ILIM1)
Current Limit Threshold Propagation Delay
PWM Comparator Propagation Delay
Step V
0 V to V
+ 0.5 V,
t
delay(ILIM1)
–
–
95
175
175
ns
CS
ILIM1
V
FB
= 4 V
Step V
0 V to 0.7 V, V = 2.4
t
delay(PWM)
125
ns
CS
FB
Minimum Peak Current
Versions xxxAx
Versions xxxBx
Versions xxxCx
Versions xxxDx
V
mV
CS(MIN)
170
115
70
200
150
100
250
230
185
130
285
215
Abnormal Overcurrent Fault Threshold
V
increasing, V = 4 V
V
1.125
80
1.200
110
1.275
140
V
CS
FB
ILIM2
Abnormal Overcurrent Fault Blanking
Duration
DRV minimum width minus
t
ns
LEB2
t
delay(ILIM2)
2. NTC with R110 = 8.8 kW
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NCP1342
Table 5. ELECTRICAL CHARACTERISTICS: (V = 12 V, V = 120 V, V
= open, V = 2.4 V, V = 0 V, V
= 0 V, V
CC
HV
Fault
FB
CS
ZCD FMAX
= 0 V, C
= 100 nF , C
= 100 pF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
VCC
DRV
J
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
CURRENT SENSE
Abnormal Overcurrent Fault Propagation
Delay
Step V
0 V to V
+ 0.5 V,
t
–
–
–
80
4
175
–
ns
CS
ILIM2
delay(ILIM2)
V
FB
= 4 V
Number of Consecutive Abnormal Overcur-
rent Faults to Enter Latch Mode
n
ILIM2
Overpower Protection Delay
V
dv/dt = 1 V/ms, measured from
t
95
175
ns
CS
OPP(delay)
V
to DRV falling edge
OPP(MAX)
Overpower Signal Blanking Delay
Pull−Up Current Source
JITTERING
t
220
0.7
280
1.0
330
1.5
ns
OPP(blank)
V
CS
= V
− 10 mV
I
CS
mA
ILIM2
Jitter Frequency
f
kHz
mV
jitter
Versions xJxxx, xKxxx, xLxxx, xMxxx
Versions xAxxx, xBxxx, xCxxx, xDxxx
Versions xExxx, xFxxx, xGxxx, xHxxx
Versions xNxxx
3.5
1.43
1.2
−
3.9
1.55
1.3
−
4.2
1.68
1.4
−
Peak Jitter Voltage
V
jitter
Versions xBxxx, xFxxx, xKxxx
Versions xAxxx, xExxx, xJxxx
Versions xDxxx, xHxxx, xMxxx
Versions xCxxx, xGxxx, xLxxx
Versions xNxxx
82
65
52
45
−
92
75
61
55
−
102
85
70
65
−
FAULT PROTECTION
Soft−Start Period
Measured from
DRV pulse to V = V
t
2.8
4.0
5.0
ms
SSTART
st
1
CS
ILIM1
Flyback Overload Fault Timer
Overvoltage Protection (OVP) Threshold
OVP Detection Delay
V
= V
t
OVLD
120
2.79
22.5
380
160
3.00
30
200
3.21
37.5
420
ms
V
CS
ILIM1
V
V
increasing
increasing
decreasing
V
Fault
Fault
Fault
Fault(OVP)
delay(OVP)
t
ms
Overtemperature Protection (OTP) Thresh-
old (Note 2)
V
V
400
mV
Fault(OTP_in)
Overtemperature Protection (OTP) Exiting
Threshold (Note 2)
V
increasing
V
880
910
940
mV
Fault
Fault(OTP_out)
Versions B Only
OTP Detection Delay
V
Fault
decreasing
t
22.5
30
37.5
ms
delay(OTP)
OTP Pull−Up Current Source
V
Fault
= V
+ 0.2 V
I
OTP
43.75
45.00
46.25
mA
Fault(OTP_in)
T = 25°C to 125°C
J
Fault Input Clamp Voltage
Fault Input Clamp Series Resistor
Autorecovery Timer
V
R
1.15
1.32
1.8
1.7
1.55
2.0
2.25
1.78
2.2
V
kW
s
Fault(clamp)
Fault(clamp)
t
restart
LIGHT/NO LOAD MANAGEMENT
Minimum Frequency Clamp
f
21.5
32
25
−
27.0
−
kHz
MIN
Dead−Time Added During Frequency
Foldback
V
FB
= 400 mV
t
ms
DT(MAX)
Quiet−Skip Timer
Versions xxAxx
Versions xxBxx
Versions xxCxx
Versions xxDxx
t
ms
quiet
1.18
0.770
0.590
−
1.25
0.833
0.640
−
1.40
0.900
0.690
−
Skip Threshold
V
decreasing
increasing
V
350
20
400
50
450
70
mV
mV
FB
skip
V
skip(HYS)
Skip Hysteresis
V
FB
2. NTC with R110 = 8.8 kW
www.onsemi.com
8
NCP1342
Table 5. ELECTRICAL CHARACTERISTICS: (V = 12 V, V = 120 V, V
= open, V = 2.4 V, V = 0 V, V
= 0 V, V
CC
HV
Fault
FB
CS
ZCD FMAX
= 0 V, C
= 100 nF , C
= 100 pF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
VCC
DRV
J
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
MINIMUM PEAK CURRENT MODULATION (MPCM)
MPCM Current Shift
Versions xxxxA
Versions xxxxB
Versions xxxxC
Versions xxxxD
Versions xxxxE
V
mV
MPCM(delta)
340
300
250
200
−
400
350
300
250
−
460
400
350
300
−
MPCM Entry Threshold
Versions xxxxA, xxxxB, xxxxC, xxxxD
Versions xxxxE
V
mV
mV
ms
MPCM(entry)
780
−
800
−
820
−
MPCM Exit Threshold
Versions xxxxA, xxxxB, xxxxC, xxxxD
Versions xxxxE
V
MPCM(exit)
730
−
750
−
770
−
MPCM Transition Timer
Versions xxxxA, xxxxB, xxxxC, xxxxD
Versions xxxxE
t
MPCM
0.85
−
1.00
−
1.05
−
THERMAL PROTECTION
Thermal Shutdown
Temperature increasing
Temperature decreasing
T
–
–
140
40
–
–
°C
°C
SHDN
Thermal Shutdown Hysteresis
2. NTC with R110 = 8.8 kW
T
SHDN(HYS)
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9
NCP1342
INTRODUCTION
The NCP1342 implements a quasi−resonant flyback
two different valleys, which is often undesirable. The
NCP1342 patented VLO circuitry solves this issue by
determining the operating valley based on the system
load, and locking out other valleys unless a significant
change in load occurs.
converter utilizing current−mode architecture where the
switch−off event is dictated by the peak current. This IC is
an ideal candidate where low parts count and cost
effectiveness are the key parameters, particularly in ac−dc
adapters, open−frame power supplies, etc. The NCP1342
incorporates all the necessary components normally needed
in modern power supply designs, bringing several
enhancements such as non−dissipative overpower
protection (OPP), brownout protection, and frequency
reduction management for optimized efficiency over the
entire power range. Accounting for the needs of extremely
low standby power requirements, the controller features
minimized current consumption and includes an automatic
X2 capacitor discharge circuit that eliminates the need to
install power−consuming resistors across the X2 input
capacitors.
• High−Voltage Start−Up Circuit: Low standby power
consumption cannot be obtained with the classic
resistive start−up circuit. The NCP1342 incorporates a
high−voltage current source to provide the necessary
current during start−up and then turns off during normal
operation.
• Internal Brownout Protection: The ac input voltage is
sensed via the high−voltage pin. When this voltage is
too low, the NCP1342 stops switching. No restart
attempt is made until the ac input voltage is back within
its normal range.
• Frequency Foldback: As the load continues to
decrease, it becomes beneficial to reduce the switching
frequency. When the load is light enough, the NCP1342
enters frequency foldback mode. During this mode, the
minimum peak current is limited and dead−time is
added to the switching cycle, thus reducing the
frequency and switching operation to discontinuous
conduction mode (DCM). Dead−time continues to be
added until skip mode is reached, or the switching
frequency reaches its minimum level of 25 kHz.
• Minimum Peak Current Modulation (MPCM): In
order to reduce the switching frequency even faster (for
high frequency designs), the NCP1342 uses MPCM to
increase the minimum peak current during frequency
foldback. It also reduces the minimum peak current
gradually as the load decreases to ensure optimum skip
mode entry.
• Skip Mode: To further improve light or no−load power
consumption while avoiding audible noise, the
NCP1342 enters skip mode when the operating
frequency reaches its minimum value. To avoid
acoustic noise, the circuit prevents the switching
frequency from decaying below 25 kHz. This allows
regulation via bursts of pulses at 25 kHz or greater
instead of operating in the audible range.
• X2−Capacitor Discharge Circuitry: Per the
IEC60950 standard, the time constant of the X2 input
capacitors and their associated discharge resistors must
be less than 1 s in order to avoid electrical shock when
the user unplugs the power supply and inadvertently
touches the ac input cord terminals. By providing an
automatic means to discharge the X2 capacitors, the
NCP1342 eliminates the need to install X2 discharge
resistors, thus reducing power consumption.
• Quiet−Skip: To further reduce acoustic noise, the
NCP1342 incorporates a novel circuit to prevent the
skip mode burst period from entering the audible range
as well.
• Internal OPP: In order to limit power delivery at high
line, a scaled version of the negative voltage present on
the auxiliary winding during the on−time is routed to
the ZCD/OPP pin. This provides the designer with a
simple and non−dissipative means to reduce the
maximum power capability as the bulk voltage
increases.
• Frequency Jittering: In order to reduce the EMI
signature, a low frequency triangular voltage waveform
is added to the input of the PWM comparator. This
helps by spreading out the energy peaks during noise
analysis.
• Internal Soft−Start: The NCP1342 includes a 4 ms
soft−start to prevent the main power switch from being
overly stressed during start−up. Soft−start is activated
each time a new startup sequence occurs or during
auto−recovery mode.
• Quasi−Resonant, Current−Mode Operation:
Quasi−Resonant (QR) mode is a highly efficient mode
of operation where the MOSFET turn−on is
synchronized with the point where its drain−source
voltage is at the minimum (valley). A drawback of this
mode of operation is that the operating frequency is
inversely proportional to the system load. The
NCP1342 incorporates a valley lockout (VLO) and
frequency foldback technique to eliminate this
drawback, thus maximizing the efficiency over the
entire power range.
• Valley Lockout: In order to limit the maximum
frequency while remaining in QR mode, one would
traditionally use a frequency clamp. Unfortunately, this
can cause the controller to jump back and forth between
www.onsemi.com
10
NCP1342
is available disabled or fixed at 110 kHz. In the 9−pin
• Dedicated Fault Input: The NCP1342 includes a
dedicated fault input. It can be used to sense an
overvoltage condition and latch off the controller by
pulling the pin above the overvoltage protection (OVP)
threshold. The controller is also disabled if the Fault pin
is pulled below the overtemperature protection (OTP)
threshold. The OTP threshold is configured for use with
a NTC thermistor.
versions, the clamp can be adjusted via an external
resistor from the FMAX Pin to ground. It can also be
disabled by pulling the FMAX pin above 4 V.
HIGH VOLTAGE START−UP
The NCP1342 contains a multi−functional high voltage
(HV) pin. While the primary purpose of this pin is to reduce
standby power while maintaining a fast start−up time, it also
incorporates brownout detection and line removal detection.
The HV pin must be connected directly to the ac line in
order for the X2 discharge circuit to function correctly. Line
and neutral should be diode “ORed” before connecting to the
HV pin as shown in Figure 4. The diodes prevent the pin
voltage from going below ground. A resistor in series with
the pin should be used to protect the pin during EMC or surge
testing. A low value resistor should be used (<5 kW) to
reduce the voltage offset during start−up.
• Overload/Short−Circuit Protection: The NCP1342
implements overload protection by limiting the
maximum time duration for operation during overload
conditions. The overload timer operates whenever the
maximum peak current is reached. In addition to this,
special circuitry is included to prevent operation in
CCM during extreme overloads, such as an output
short−circuit.
• Maximum Frequency Clamp: The NCP1342 includes
a maximum frequency clamp. In all versions, the clamp
AC
CON
EMI
HV
Controller
Figure 4. High−Voltage Input Connection
Start−up and VCC Management
During start−up, the current source turns on and charges
the V capacitor with I (typically 6 mA). When V
Once V reaches V
the controller bias current increases to I (typically
, the controller is enabled and
CC
CC(on)
CC
start2
cc
CC3
reaches V
(typically 16.0 V), the current source turns
2.0 mA). However, the total bias current is greater than this
due to the gate charge of the external switching MOSFET.
CC(on)
off. If the input voltage is not high enough to ensure a proper
start−up (i.e. V has not reached V ), the controller
The increase in I due to the MOSFET is calculated using
HV
BO(start)
CC
will not start. V then begins to fall because the controller
Equation 1.
CC
bias current is at I
supply voltage is not present. When V falls to V
(typically 1 mA) and the auxiliary
DICC + fsw @ QG @ 10−3
(eq. 1)
CC2
CC
CC(off)
where DI is the increase in milliamps, f is the switching
(typically 10.5 V), the current source turns back on and
charges V . This cycle repeats indefinitely until V
CC
sw
frequency in kilohertz and Q is the gate charge of the
G
CC
HV
external MOSFET in nanocoulombs.
reaches V
. Once this occurs, the current source
BO(start)
C
VCC
must be sized such that a V voltage greater than
immediately turns on and charges V to V
, at which
CC(on)
CC
CC
V
is maintained while the auxiliary supply voltage
point the controller starts (see Figure 6).
When V is brought below V
CC(off)
increases during start−up. If C
is too small, V will fall
, the start−up
CC(inhibit)
VCC
CC
CC
below V
and the controller will turn off before the
current is reduced to I
(typically 0.5 mA). This limits
CC(off)
start1
auxiliary winding supplies the IC. The total I current after
power dissipation on the device in the event that the V pin
CC
CC
CC(inhibit)
the controller is enabled (I
considered to correctly size C
plus DI ) must be
CC
is shorted to ground. Once V rises back above V
,
CC3
CC
.
the start−up current returns to I
.
VCC
start2
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11
NCP1342
Figure 5. Start−up Circuitry Block Diagram
VHV
VBO(start)
VHV(MIN)
VCC
VCC(on)
VCC(off)
Start−up
Start−up
tdelay(start)
Current = Istart2
Current = Istart1
VCC(inhibit)
DRV
Figure 6. Start−up Timing
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12
NCP1342
DRIVER
The NCP1342 maximum supply voltage, V , is
CC(MAX)
The peak current level is clamped during the soft−start
28 V. Typical high−voltage MOSFETs have a maximum
gate voltage rating of 20 V. The DRV pin incorporates an
active voltage clamp to limit the gate voltage on the external
phase. The setpoint is actually limited by a clamp level
ramping from 0 to 0.8 V within 4 ms.
In addition to the PWM comparator, a dedicated
comparator monitors the current sense voltage, and if it
MOSFETs. The DRV voltage clamp, V
12 V with a maximum limit of 14 V.
is typically
DRV(high)
reaches the maximum value, V
(typically 800 mV), the
ILIM
gate driver is turned off and the overload timer is enabled.
This occurs even if the limit imposed by the feedback
REGULATION CONTROL
Peak Current Control
The NCP1342 is a peak current−mode controller, thus the
FB voltage sets the peak current flowing in the transformer
and the MOSFET. This is achieved by sensing the MOSFET
current across a resistor and applying the resulting voltage
ramp to the non−inverting input of the PWM comparator
through the CS pin. The current limit threshold is set by
voltage is higher than V
. Due to the parasitic
ILIM1
capacitances of the MOSFET, a large voltage spike often
appears on the CS Pin at turn−on. To prevent this spike from
falsely triggering the current sense circuit, the current sense
signal is blanked for a short period of time, t
(typically
LEB1
275 ns), by a leading edge blanking (LEB) circuit. Figure 7
shows the schematic of the current sense circuit.
The peak current is also limitied to a minimum level,
applying the FB voltage divided by K (typically 4) to the
FB
V
(0.2 V, typically). This results in higher efficiency
CS(MIN)
inverting input of the PWM comparator. When the current
sense voltage ramp exceeds this threshold, the output driver
is turned off, however, the peak current is affected by several
functions (see Figure 7):
at light loads by increasing the minimum energy delivered
per switching cycle, while reducing the overall number of
switching cycles during light load.
R
OPP
ZCD/OPP
OPP
V
FB(open)
Minimum Peak
Current
R
+
FB
FB
*
DRV Off
V
ILIM1
V
CS(MIN)
Soft−Start
Ramp
K
FB
*
+
PWM
*
+
OCP
*
+
CS
t
LEB1
LEB2
Overload Timer
R
sense
AOCP
t
+
Abnormal OCP Counter
*
V
ILIM2
Figure 7. Current Sense Logic
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13
NCP1342
Zero Current Detection
As shown by Figure 13, a valley is detected once the ZCD
pin voltage falls below the demagnetization threshold,
The NCP1342 is a quasi−resonant (QR) flyback
controller. While the power switch turn−off is determined by
the peak current set by the feedback loop, the switch turn−on
is determined by the transformer demagnetization. The
demagnetization is detected by monitoring the transformer
auxiliary winding voltage.
V
, typically 55 mV. The controller will either switch
ZCD(trig)
once the valley is detected or increment the valley counter,
depending on the FB voltage.
Overpower Protection
The average bulk capacitor voltage of the QR flyback
varies with the RMS line voltage. Thus, the maximum
power capability at high line can be much higher than
desired. An integrated overpower protection (OPP) circuit
provides a relatively constant output power limit across the
Turning on the power switch once the transformer is
demagnetized has the benefit of reduced switching losses.
Once the transformer is demagnetized, the drain voltage
starts ringing at a frequency determined by the transformer
magnetizing inductance and the drain lump capacitance,
eventually settling at the input voltage. A QR flyback
controller takes advantage of the drain voltage ringing and
turns on the power switch at the drain voltage minimum or
“valley” to reduce switching losses and electromagnetic
interference (EMI).
input voltage on the bulk capacitor, V . Since it is a
bulk
high−voltage rail, directly measuring V
will contribute
bulk
losses in the sensing network that will greatly impact the
standby power consumption. The NCP1342 OPP circuit
achieves this without the need for a high−voltage sensing
network, and is essentially lossless.
V
FB(open)
R
FB
PWM
K
FB
FB
t
LEB1
CS
OCP
DRV Off
V
OPP
ZCD/OPP
V
ILIM1
Figure 8. OPP Circuit Schematic
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14
NCP1342
⎝
⎛
⎢
⎝
NAUX
NP
⎢
.
−
VBULK
⎛
Figure 9. Auxiliary Winding Voltage
Since the auxiliary winding voltage during the power
switch on time is a reflection of the input voltage scaled by
the primary to auxiliary winding turns ratio, N (see
Figure 9), OPP is achieved by scaling down reflected
voltage during the on−time and applying it to the ZCD pin
The ratio between R
Equation 5. It is obtained by combining Equations 3 and 4.
and R
is given by
OPPL
ZCD
P:AUX
RZCD
ROPPL
VAUX * VF * VZCD
(eq. 5)
+
VZCD
A design example is shown below:
System Parameters:
as a negative voltage, V . The voltage is scaled down by
OPP
a resistor divider comprised of R
and R . The
OPPL
OPPU
VAUX + 18 V
VF + 0.6 V
maximum internal current setpoint (V
) is simply the
CS(OPP)
sum of V
and the peak current sense threshold, V
.
OPP
ILIM1
Figure 8 shows the schematic for the OPP circuit.
The adjusted peak current limit is calculated using
Equation 2. For example, a V of −150 mV results in a
NP:AUX + 0.18
The ratio between R
and R
is calculated using
OPPL
OPP
ZCD
peak current limit of 650 mV in NCP1342.
Equation 5 for a minimum V
of 8 V.
ZCD
RZCD
ROPPL
VCS(OPP) + VOPP ) VILIM1
18 V * 0.6 V * 8 V
(eq. 2)
+
+ 1.2 kW
8 V
To ensure optimal zero−crossing detection, a diode is
needed to bypass R
used to calculate R
during the off−time. Equation 3 is
R
is arbitrarily set to 1 kW. R
is also set to 1 kW
OPPU
OPPU
ZCD
OPPL
and R
.
because the ratio between the resistors is close to 1.
The NCP1342 maximum overpower compensation or
peak current setpoint reduction is 31.25% for a V
−250 mV. We will use this value for the following example:
Substituting values in Equation 3 and solving for R
we obtain:
OPPL
RZCD ) R
NP:AUX @ Vbulk * VOPP
OPPU + *
(eq. 3)
of
OPP
ROPPL
VOPP
R
OPPU
is selected once a value is chosen for R
.
OPPL
OPPU
R
OPPL
is selected large enough such that enough voltage is
available for the zero−crossing detection during the
off−time. It is recommended to have at least 8 V applied on
the ZCD pin for good detection. The maximum voltage is
RZCD ) ROPPU
0.18 @ 370 V * (−0.25 V)
+
+ 271
ROPPL
−0.25 V
internally clamped to V . The off−time voltage on the ZCD
ROPPU + 271 @ ROPPL * RZCD
CC
Pin is given by Equation 4.
ROPPU + 271 @ 1 kW * 1 kW + 270 kW
ROPPL
RZCD ) ROPPL
ǒ Ǔ
@ VAUX * VF
(eq. 4)
VZCD
+
For optimum performance over temperature, it is
recommended to keep R below 3 kW.
OPPL
Where V
is the voltage across the auxiliary winding
AUX
and V is the D
forward voltage drop.
F
OPP
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15
NCP1342
Soft−Start
in CCM for several cycles until the voltage on the ZCD pin
is high enough to prevent the timer from running. Therefore,
Soft−start is achieved by ramping up an internal reference,
V
V
, and comparing it to the current sense signal.
a longer timeout period, t
during soft−start to prevent CCM operation.
(typically 100 ms), is used
SSTART
tout1
ramps up from 0 V once the controller initially
SSTART
powers up. The peak current setpoint is then limited by the
ramp resulting in a gradual increase of the switch
Frequency Jittering
V
SSTART
In order to help meet stringent EMI requirements, the
NCP1342 features frequency jittering to average the energy
peaks over the EMI frequency range. As shown in Figure 10,
the function consists of summing a triangular wave of
current during start−up. The soft−start duration, t
typically 4 ms.
, is
SSTART
During startup, demagnetization phases are long and
difficult to detect since the auxiliary winding voltage is very
small. In this condition, the 6 ms steady−state timeout is
generally shorter than the inductor demagnetization period.
If it is used to restart a switching cycle, it can cause operation
amplitude V
and frequency f
with the CS signal
jitter
jitter
immediately before the PWM comparator. This current acts
to modulate the on−time and hence the operation frequency.
V
DD
R
FB
FB
K
FB
V
jitter
LEB
CS
V
OPP
DRV Off
V
ILIM1
V
CS(MIN)
Figure 10. Jitter Implementation
1000
Since the jittering function modulates the peak current
level, the FB signal will attempt to compensate for this effect
in order to limit the output voltage ripple. Therefore, the
bandwidth of the feedback loop must be well below the jitter
frequency, or the jitter function will be filtered by the loop.
Due to the minimum peak current, the effect of the
jittering circuit will not be seen during frequency foldback
mode.
900
800
700
600
500
400
300
200
100
0
Maximum Frequency Clamp
All 9−pin versions of the NCP1342 include an adjustable
maximum frequency clamp via an external resistor from the
FMAX Pin to ground. It can also be disabled by pulling the
FMAX pin above 4 V. The maximum frequency can be
programmed using Equation 6, and is shown in Figure 11.
0
50
100
150 200
250
300 350 250
R
(kW)
FMAX
Figure 11. FSW(MAX) vs. RFMAX
261 kHz * 1 V
(eq. 6)
+
FSW(MAX)
RFMAX * 10 mA
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16
NCP1342
LIGHT LOAD MANAGEMENT
a valley is selected, the controller stays locked in this valley
until the output power changes significantly. This technique
extends the QR mode operation over a wider output power
range while maintaining good efficiency and limiting the
maximum operating frequency.
The operating valley (1 , 2 , 3 4 , 5 or 6 ) is
determined by the FB voltage. An internal counter
increments each time a valley is detected by the ZCD/OPP
Pin. Figure 12 shows a typical frequency characteristic
obtainable at low line in a 65 W application.
Valley Lockout Operation
The operating frequency of a traditional QR flyback
controller is inversely proportional to the system load. In
other words, a load reduction increases the operating
frequency. A maximum frequency clamp can be useful to
limit the operating frequency range. However, when used by
itself, such an approach often causes instabilities since when
this clamp is active, the controller tends to jump (or hesitate)
between two valleys, thus generating audible noise.
Instead, the NCP1342 also incorporates a patented valley
lockout (VLO) circuitry to eliminate valley jumping. Once
st
nd
rd, th
th
th
6th 5th 4th
3rd
2nd
1st
5
4
4
4
4
1x10
8x10
6x10
4x10
2x10
VCO
mode
6th
5th 4th
3rd
2nd
1st
VCO
mode
0
0
20
40
60
Pout (W)
Figure 12. Valley Lockout Frequency vs. Output Power
When an “n” valley is asserted by the valley selection
circuitry, the controller is locked in this valley until the FB
voltage decreases to the lower threshold (“n+1” valley
activates) or increases to the “n valley threshold” + 600 mV
(“n−1” valley activates). The regulation loop adjusts the
peak current to deliver the necessary output power. Each
valley selection comparator features a 600 mV hysteresis
that helps stabilize operation despite the FB voltage swing
produced by the regulation loop.
Table 6. VALLEY FB THRESHOLDS (typical values)
FB Falling
FB Rising
st
nd
nd
st
1
to 2 valley
1.400 V
1.200 V
1.100 V
1.000 V
0.900 V
2
to 1 valley
2.000 V
1.800 V
1.700 V
1.600 V
1.500 V
nd
rd
rd
rd
th
nd
2
to 3 valley
3
to 2 valley
th
rd
3
4
5
to 4 valley
4
5
to 3 valley
th
th
th
th
th
to 5 valley
to 4 valley
th
th
th
to 6 valley
6
to 5 valley
Valley Timeout
signal acts as a substitute for the ZCD signal to the valley
counter. Figure 13 shows the valley timeout circuit
In case of extremely damped oscillations, the ZCD
comparator may not be able to detect the valleys. In this
condition, drive pulses will stop while the controller waits
for the next valley or ZCD event. The NCP1342 ensures
continued operation by incorporating a maximum timeout
period after the last demagnetization detection. The timeout
schematic. The steady state timeout period, t
, is set at 6
tout2
ms (typical) to limit the frequency step.
During startup, the voltage offset added by the OPP diode,
, prevents the ZCD Comparator from accurately
D
OPP
detecting the valleys. In this condition, the steady state
www.onsemi.com
17
NCP1342
timeout period will be shorter than the inductor
the FB voltage sets VLO mode to turn on at the fifth valley,
and the ZCD ringing is damped such that the ZCD circuit is
only able to detect:
demagnetization period causing CCM operation. CCM
operation lasts for a few cycles until the voltage on the ZCD
pin is high enough to detect the valleys. A longer timeout
• Valleys 1 to 4: the circuit generates a DRV pulse 6 ms
th
period, t
, (typically 100 ms) is set during soft−start to
tout1
(steady−state timeout delay) after the 4 valley
limit CCM operation.
detection.
In VLO operation, the number of timeout periods are
counted instead of valleys when the drain−source voltage
oscillations are too damped to be detected. For example, if
• Valleys 1 to 3: the timeout delay must run twice, and
rd
the circuit generates a DRV pulse 12 ms after the 3
valley detection.
Figure 13. Valley Timeout Circuitry
Frequency Foldback with Minimum Peak Current
Modulation (MPCM)
As the output load decreases (FB voltage decreases), the
valleys are incremented from 1 to 6. When the sixth valley
is reached and the FB voltage further decreases to
minimum frequency clamp prevents the switching
frequency from dropping below 25 kHz to eliminate the risk
of audible noise. Note that the dead−time is not added (it is
blanked) until MPCM is engaged to ensure valley switching
prior to entering MPCM mode.
V
(800 mV typical), the controller enters MPCM
MPCM(entry)
In addition to dead−time, the peak current setpoint is
and begins frequency foldback (FF). At this point, the
minimum peak current is increased by V
linearly reduced as V falls down to 0.4 V. This ensures that
FB
MPCM(delta)
the peak current is not too high during the lightest loads, and
has the effect of reducing the skip entry power level.
Figure 14 shows the MPCM with respect to the feedback
voltage, while Figure 15 shows the VLO to FF operation.
To reduce the output power hysteresis between entering
(400 mV typical). The increase in peak current serves to
force the switching frequency to a much lower value, thus
improving the efficiency at light loads. During this mode,
the controller regulates the power delivery by modulating
the switching frequency.
and exiting MPCM, the exit threshold (V
) is set
MPCM(exit)
Once in frequency foldback mode, the controller reduces
slightly below the entry threshold (750 mV typical). A 1 ms
timer, t , is engaged every time MPCM is entered or
th
the switching frequency by adding dead−time after the 6
MPCM
valley is detected. This dead−time increases as the FB
voltage decreases.
The dead−time circuit is designed to add 0 ms dead−time
exited to prevent oscillations during the operating point
transition. If at any time FB falls to skip mode, or rises to 5
valley, MPCM will be immediately exited regardless of
th
when V = 0.4 V and linearly increases the total dead−time
FB
DT(MAX)
t
.
MPCM
to t
(36 ms typical) as V falls down to 0.4 V. The
FB
www.onsemi.com
18
NCP1342
Minimum Peak Current
V
+ V
MPCM(delta)
CS(MIN)
V
MPCM(delta)
V
CS(MIN)
VFB
V
MPCM(entry)
Vskip
Figure 14. Minimum Peak Current Modulation
Operating Mode
V
decreases
increases
FB
FF
V
FB
Valley 6
Valley 5
Valley 4
Valley 3
Valley 2
Fault !
Valley 1
V
(V)
3.2
0.8 0.9 1.0 1.1 1.2 1.4 1.5 1.6 1.7 1.8 2.0
FB
Figure 15. Valley Lockout Thresholds
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19
NCP1342
Minimum Frequency Clamp and Skip Mode
as the current drive pulses ends – it does not stop
immediately.
Once switching stops, FB will rise. As soon as FB crosses
the skip−exit threshold, drive pulses will resume, but the
controller remains in burst mode. At this point, a 1.25 ms
As mentioned previously, the circuit prevents the
switching frequency from dropping below f (25 kHz
MIN
typical). When the switching cycle would be longer than
40 ms, the circuit forces a new switching cycle. However, the
f
clamp cannot generate a DRV pulse until the
timer, t
, is started together with a count−to−3 counter.
quiet
MIN
demagnetization is completed. In other words, it will not
cause operation in CCM.
The next time the FB voltage drops below the skip−in
threshold, drive pulses stop at the end of the current pulse as
long as 3 drive pulses have been counted (if not, they do not
Since the NCP1342 forces a minimum peak current and a
minimum frequency, the power delivery cannot be
continuously controlled down to zero. Instead, the circuit
starts skipping pulses when the FB voltage drops below the
skip level, V , and recovers operation when V exceeds
rd
stop until the end of the 3 pulse). They are not allowed to
start again until the timer expires, even if the skip−exit
threshold is reached first. It is important to note that the
timer will not force the next cycle to begin – i.e. if the natural
skip frequency is such that skip−exit is reached after the
timer expires, the drive pulses will wait for the skip−exit
threshold.
This means that during no−load, there will be a minimum
of 3 drive pulses, and the burst−cycle period will likely be
much longer than 1.25 ms. This operation helps to improve
efficiency at no−load conditions.
skip
FB
V
skip
+ V
. This skip−mode method provides an
skip(HYS)
efficient method of control during light loads.
Quiet−Skip
To further avoid acoustic noise, the circuit prevents the
burst frequency during skip mode from entering the audible
range by limiting it to a maximum of 800 Hz. This is
achieved via a timer (t ) that is activated during
quiet
In order to exit burst mode, the FB voltage must rise higher
Quiet−Skip. The start of the next burst cycle is prevented
until this timer has expired.
As the output power decreases, the switching frequency
decreases. Once it hits 25 kHz, the skip−in threshold is
reached and burst mode is entered − switching stops as soon
than 1 V. If this occurs before t
expires, the drive pulses
quiet
will resume immediately – i.e. the controller won’t wait for
the timer to expire. Figure 16 provides an example of how
Quiet−Skip works.
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20
NCP1342
MAX
Load
Fsw >= 25 kHz
Fsw >= 25 kHz
DRV
DRV
FB
1.25 ms
1.25 ms
1.25 ms
1.25 ms
Fsw >= 25 kHz
Fsw >= 25 kHz
Fsw >= 25 kHz
Fsw >= 25 kHz
DRV
FB
DRV
FB
DRV
FB
>1.25 ms
DRV
FB
MIN
Load
Figure 16. Quiet−Skip Timing Diagram
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21
NCP1342
FAULT MANAGEMENT
The NCP1342 contains three separate fault modes.
external latch input. When the NCP1342 detects a latching
fault, the driver is immediately disabled. The operation
during a latching fault is identical to that of a non−latching
fault except the controller will not attempt to restart at the
Depending on the type of fault, the device will either latch
off, restart when the fault is removed, or resume operation
after the auto−recovery timer expires.
next V
, even if the fault is removed. In order to clear
CC(on)
Latching Faults
Some faults will cause the NCP1342 to latch off. These
include the abnormal OCP (AOCP), V OVP, and the
the latch and resume normal operation, V must first be
allowed to drop below V
must be detected. This operation is shown in Figure 17.
CC
or a line removal event
CC(reset)
CC
Fault
Fault
Applied
Fault
Removed
time
VCC
VCC(on)
VCC(off)
time
time
FDRV
IHV
Istart 2
Istart(off)
time
Figure 17. Operation During Latching Fault
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22
NCP1342
Non−Latching Faults
re−enabled when V reaches V
according to the
CC
CC(on)
When the NCP1342 detects a non−latching fault
(brownout or thermal shutdown), the drivers are disabled,
initial power−on sequence, provided V
is above
HV
V
This operation is shown in Figure 18. When V
BO(start).
HV
and V falls towards V
due to the IC internal current
is reaches V
, V immediately charges to V
.
CC
CC(off)
BO(start)
CC
CC(on)
consumption. Once V reaches V
, the HV current
CC(off)
If V is already above V
when the fault is removed,
CC
CC
CC(on)
source turns on and C
begins to charge towards V
.
the controller will start immediately as long as V is above
VCC
CC(on)
HV
When V , reaches V
, the cycle repeats until the fault
V
CC
CC(on)
BO(start).
is removed. Once the fault is removed, the NCP1342 is
Fault
Fault
Fault
Applied
Removed
time
Waits for next
VCC(on) before
starting
VCC
VCC(on)
VCC(off )
time
time
FDRV
IHV
Istart 2
Istart (off)
time
Figure 18. Operation During Non−Latching Fault
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23
NCP1342
Auto−recovery Timer Faults
Some faults faults cause the NCP1342 auto−recovery
timer to run. If an auto−recovery fault is detected, the gate
running, the HV current source turns on and off to maintain
between V and V . Once the auto−recovery
V
cc
cc(off)
cc(on)
timer expires, the controller will attempt to start normally at
the next V provided V is above V . This
drive is disabled and the auto−recovery timer, t
autorec
CC(on)
HV
BO(start)
(typically 1.2 s), starts. While the auto−recovery timer is
operation is shown in Figure 19.
Fault
Fault
Applied
Removed
Fault
time
VCC
VCC(on)
VCC(off)
Restarts
At VCC(on)
(new burst
cycle if Fault
still present)
time
time
DRV
Controller
stops
Autorecovery
Timer
1.2 s
trestart
time
Figure 19. Operation During Auto−Recovery Fault
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24
NCP1342
PROTECTION FEATURES
Brownout Protection
Figure 20 shows the brownout detector waveforms during
A timer is enabled once V
drops below its disable
a brownout.
HV
threshold, V
disabled if V
brownout timer, t (typically 54 ms), expires. The timer is
(typically 99 V). The controller is
When a brownout is detected, the controller stops
switching and enters non−latching fault mode (see
Figure 18). The HV current source alternatively turns on and
BO(stop)
doesn’t exceed V
before the
HV
BO(stop)
BO
set long enough to ignore a two cycle dropout. The timer
off to maintain V between V
and V
until the
CC
CC(on)
CC(off)
starts counting once V drops below V
.
input voltage is back above V
.
HV
BO(stop)
BO(start)
VHV
VBO(start )
VBO(stop)
time
time
Fault
Cleared
Brownout
Timer
Brownout
detected
Starts
Charging
Immediately
VCC
Restarts at
next V CC(on)
VCC(on)
VCC(off)
tdelay (start )
time
time
DRV
Figure 20. Operation During Brownout
Line Removal Detection and X2 Capacitor Discharge
Safety agency standards require the input filter capacitors
to be discharged once the ac line voltage is removed. A
resistor network is the most common method to meet this
requirement. Unfortunately, the resistor network consumes
power across all operating modes and it is a major
contributor of input power losses during light−load and
no−load conditions.
discharge circuitry. A novel approach is used to reconfigure
the high voltage startup circuit to discharge the input filter
capacitors upon removal of the ac line voltage. The line
removal detection circuitry is always active to ensure safety
compliance.
The line removal is detected by digitally sampling the
voltage present at the HV pin, and monitoring the slope.
A timer, t
(typically 100 ms), is used to detect
line(removal)
The NCP1342 eliminates the need for external discharge
resistors by integrating active input filter capacitor
when the slope of the input signal is negative or below the
resolution level. The timer is reset any time a positive slope
www.onsemi.com
25
NCP1342
is detected. Once the timer expires, a line removal condition
drops to V
, it is quickly recharged to V
. The
CC(on)
CC(X2_reg)
is acknowledged initiating an X2 capacitor discharge cycle,
and the controller is disabled.
discharging process is cyclic and continues until the ac line
is detected again or the voltage across the X2 capacitor is
If V is above V
, it is first discharged to V
.
lower than V
(30 V maximum). This feature
CC
CC(on)
CC(on)
HV(discharge)
A second timer, t
the time limiting of the discharge phase to protect the device
against overheating. Once the discharge phase is complete,
(typically 32 ms), is used for
allows the device to discharge large X2 capacitors in the
input line filter to a safe level.
It is important to note that the HV pin cannot be
connected to any dc voltage due to this feature, i.e.
directly to the bulk capacitor.
line(discharge)
t
is reused while the device checks to see if the
line(discharge)
line voltage is reapplied. During the discharge phase, if V
CC
X2 Capacitor
Discharge
VHV
VBO(start)
VBO(stop)
X2 Capacitor
Discharge
AC Line Unplug
VHV(discharge )
time
AC
AC
AC
Timer
Starts
Timer
Restarts
Timer
Expires
No AC Detection
Timer
tline(removal )
tline(discharge /detect)
tline(discharge )
tline(discharge )
tline(removal )
tline(detect)
DRV
time
X2 Discharge
X2 Discharge
Device is stopped
X2 Discharge
Current
Istart2
ICC
ICC(discharge )
0
ICC3
Istart2
VCC
VCC(X2_reg)
VCC(on)
Figure 21. Line Removal Timing
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26
NCP1342
X2 Capacitor
Discharge
VHV
VBO(start)
VBO(stop)
AC Line Unplug
VHV(discharge )
time
AC
Timer
Expires
AC Detected
AC
AC
Timer
Starts
Timer
Restarts
Timer
tline(removal )
tline(discharge /detect )
time
time
tline(discharge )
tline(removal )
DRV
X2 Discharge
Device is stopped
X2 Discharge
Current
tdelay(start)
Istart2
time
time
ICC
ICC(discharge )
0
ICC3
Istart2
VCC
VCC(X2_reg)
VCC(on)
Figure 22. Line Removal Timing with AC Reapplied
An over temperature protection block monitors the
junction temperature during the discharge process to avoid
thermal runaway, in particular during open/short pins safety
tests. Please note that the X2 discharge capability is also
active at all times, including off−mode and before the
controller actually starts to pulse (e.g. if the user unplugs the
converter during the start−up sequence).
the lower fault threshold, V
(typically 0.4 V).
Fault(OTP_in)
The lower threshold is normally used for detecting an
overtemperature fault. The controller operates normally
while the Fault pin voltage is maintained within the upper
and lower fault thresholds. Figure 23 shows the architecture
of the Fault input.
The Fault input signal is filtered to prevent noise from
triggering the fault detectors. Upper and lower fault detector
Dedicated Fault Input
blanking delays, t
and t
,are both
delay(OTP)
delay(OVP)
The NCP1342 includes a dedicated fault input accessible
via the Fault pin (8−pin and 9−pin versions only). The
controller can be latched by pulling up the pin above the
typically 30 ms. A fault is detected if the fault condition is
asserted for a period longer than the blanking delay.
upper fault threshold, V
(typically 3.0 V). The
Fault(OVP)
controller is disabled if the Fault pin voltage is pulled below
www.onsemi.com
27
NCP1342
OVP
voltage drop across the thermistor. The resistance of the
An active clamp prevents the Fault pin voltage from
NTC thermistor decreases at higher temperatures resulting
in a lower voltage across the thermistor. The controller
detects a fault once the thermistor voltage drops below
reaching the upper latch threshold if the pin is open. To reach
the upper threshold, the external pull−up current has to be
higher than the pull−down capability of the clamp (set by
V
.
Fault(OTP_in)
R
at V ), i.e., approximately 1 mA.
Fault(clamp)
The controller bias current is reduced during power up by
Fault(clamp)
The upper fault threshold is intended to be used for an
disabling most of the circuit blocks including I
.
Fault(OTP)
overvoltage fault using a zener diode and a resistor in series
from the auxiliary winding voltage. The controller is latched
This current source is enabled once V reaches V
. A
CC
CC(on)
filter capacitor is typically connected between the Fault and
GND pins. This will result in a delay before V reaches
once V
exceeds V
.
Fault
Fault(OVP)
Fault
Once the controller is latched, it follows the behavior of
a latching fault according to Figure 17 and is only reset if
its steady state value once I
the lower fault comparator (i.e. overtemperature detection)
is ignored during soft−start.
is enabled. Therefore,
Fault(OTP)
V
CC
is reduced to V
, or X2 discharge is activated. In
CC(reset)
the typical application these conditions occur only if the ac
voltage is removed from the system.
Version
A latches off the controller after an
overtemperature fault is detected according to Figure 17. In
Version B, the controller is re−enabled once the fault is
removed such that V
the auto−recovery timer expires, and V reaches V
as shown in Figure 19.
OTP
increases above V
,
Fault
Fault(OTP_out)
The lower fault threshold is intended to be used to detect
an overtemperature fault using an NTC thermistor. A pull up
CC
CC(on)
current source, I
(typically 45.0 mA), generates a
Fault(OTP)
Figure 23. Fault Pin Internal Schematic
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28
NCP1342
Overload Protection
• The controller latches off (version A) or
The overload timer integrates the duration of the overload
fault. That is, the timer count increases while the fault is
present and reduces its count once it is removed. The
overload timer duration, t
the overload timer expires, the controller detects an overload
condition does one of the following:
• Enters a safe, low duty−ratio auto−recovery mode
(version B).
Figure 24 shows the overload circuit schematic, while
Figure 25 and Figure 26 show operating waveforms for
latched and auto−recovery overload conditions.
, is typically 160 ms. When
OVLD
V
FB(open)
R
FB
PWM
K
FB
FB
t
t
OVLD
LEB1
CS
OCP + OPP
Count Down
Count Up
V
OPP
ZCD/OPP
V
ILIM1
DRV Off
AOCP
t
LEB2
Abnormal OCP
Count 4
V
ILIM2
Figure 24. Overload Circuitry
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29
NCP1342
Latch
Event
Fault
Latch
time
VCC
VCC(on)
VCC(off)
time
time
DRV
IHV
Istart2
IHV(off)
time
Figure 25. Latched Overload Operation
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30
NCP1342
Fault
disappears
Overcurrent
applied
Output Load
Max Load
time
time
Fault Flag
Fault
timer
starts
VCC
VCC(on)
VCC(off)
Restarts
At VCC(on)
(new burst
cycle if Fault
still present)
time
time
DRV
Controller
stops
Fault timer
160 ms
time
tOVLD
trestart
tdelay(start)
Figure 26. Auto−Recovery Overload Operation
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31
NCP1342
Abnormal Overcurrent Protection (AOCP)
core. Due to the valley timeout feature of the controller, the
flux level will quickly walk up until the core saturates. This
can cause excessive stress on the primary MOSFET and
secondary diode. This is not a problem for the NCP1342,
however, because the valley timeout timer is disabled while
the ZCD Pin voltage is above the arming threshold. Since the
leakage energy is high enough to arm the ZCD trigger, the
timeout timer is disabled and the next drive pulse is delayed
until demagnetization occurs.
Under some severe fault conditions, like a winding
short−circuit, the switch current can increase very rapidly
during the on−time. The current sense signal significantly
exceeds V
, but because the current sense signal is
ILIM1
blanked by the LEB circuit during the switch turn−on, the
power switch current can become huge and cause severe
system damage.
The NCP1342 protects against this fault by adding an
additional comparator for Abnormal Overcurrent Fault
detection. The current sense signal is blanked with a shorter
VCC Overvoltage Protection
An additional comparator on the V pin monitors the
CC
LEB duration, t
, typically 125 ns, before applying it to
LEB2
V
CC
voltage. If VCC exceeds VCC(OVP), the gate drive is
the Abnormal Overcurrent Fault Comparator. The voltage
threshold of the comparator, V , typically 1.2 V, is set
disabled and the NCP1342 follows the operation of a
latching fault (see Figure 17).
ILIM2
50% higher than V
, to avoid interference with normal
ILIM1
operation. Four consecutive Abnormal Overcurrent faults
cause the controller to enter latch mode. The count to 4
provides noise immunity during surge testing. The counter
is reset each time a DRV pulse occurs without activating the
Fault Overcurrent Comparator.
Thermal Shutdown
An internal thermal shutdown circuit monitors the
junction temperature of the controller. The controller is
disabled if the junction temperature exceeds the thermal
shutdown threshold, T
(typically 140°C). When a
SHDN
thermal shutdown fault is detected, the controller enters a
non−latching fault mode as depicted in Figure 18. The
Current Sense Pin Failure Protection
A 1mA (typically) pull−up current source, I , pulls up the
CS pin to disable the controller if the pin is left open.
Additionally, the maximum on−time, t
typically), prevents the MOSFET from staying on
permanently if the CS Pin is shorted to GND.
CS
controller restarts at the next V
once the junction
CC(on)
temperature drops below below T
by the thermal
SHDN
(32 ms
on(MAX)
shutdown hysteresis, T
The thermal shutdown is also cleared if V drops below
, typically 40°C.
SHDN(HYS)
CC
V
, or a line removal fault is detected. A new power
CC(reset)
Output Short Circuit Protection
During an output short−circuit, there is not enough
voltage across the secondary winding to demagnetize the
up sequence commences at the next V
faults are removed.
once all the
CC(on)
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32
NCP1342
TYPICAL CHARACTERISTICS
17.14
17.12
17.1
9
8.99
8.98
8.97
8.96
8.95
8.94
8.93
17.08
17.06
17.04
17.02
17
16.98
16.96
16.94
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 27. VCC(on) vs. Temperature
Figure 28. VCC(off) vs. Temperature
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 29. Istart1 vs. Temperature
Figure 30. Istart2 vs. Temperature
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 31. IHV(off1) vs. Temperature
Figure 32. IHV(off2) vs. Temperature
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33
NCP1342
TYPICAL CHARACTERISTICS
0.126
0.124
0.122
0.120
0.118
0.116
0.114
0.112
0.110
0.108
0.106
0.255
0.250
0.245
0.240
0.235
0.230
0.225
0.220
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 33. ICC1 vs. Temperature
Figure 34. ICC2 vs. Temperature
1.075
1.070
1.065
1.060
1.055
1.050
1.045
1.040
1.035
1.030
28.35
28.3
28.25
28.2
28.15
28.1
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 35. ICC3 vs. Temperature
Figure 36. VCC(OVP) vs. Temperature
19.8
19.6
19.4
19.2
19
112.6
112.4
112.2
112
111.8
111.6
111.4
111.2
110
18.8
18.6
18.4
18.2
18
17.8
17.6
110.8
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 37. ICC(discharge) vs. Temperature
Figure 38. VBO(start) vs. Temperature
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34
NCP1342
TYPICAL CHARACTERISTICS
98.2
98
90
80
70
60
50
40
30
20
10
0
CDRV = 1 nF
97.8
97.6
97.4
97.2
97
CDRV = 100 pF
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 39. VBO(stop) vs. Temperature
Figure 40. tDRV(rise) vs. Temperature
45
40
35
30
25
20
15
10
5
111.8
111.6
111.4
111.2
111
CDRV = 1 nF
110.8
110.6
110.4
110.2
CDRV = 100 pF
0
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 41. tDRV(fall) vs. Temperature
Figure 42. fMAX1 vs. Temperature
367
366.5
366
73.45
73.4
73.35
73.3
73.25
73.2
73.15
73.1
73.05
73
365.5
365
364.5
364
363.5
363
362.5
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 43. fMAX2 vs. Temperature
Figure 44. fMAX3 vs. Temperature
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35
NCP1342
TYPICAL CHARACTERISTICS
32.5
32.4
32.3
32.2
32.1
32
63.6
63.5
63.4
63.3
63.2
63.1
63
31.9
31.8
31.7
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 45. ton(MAX) vs. Temperature
Figure 46. VZCD(trig) vs. Temperature
25.65
25.6
12.95
12.9
12.85
12.8
25.55
25.5
25.45
25.4
12.75
25.35
12.7
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 47. VZCD(HYS) vs. Temperature
Figure 48. VZCD(MAX) vs. Temperature
0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
198.8
198.6
198.4
198.2
198
197.8
197.6
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 49. VZCD(MIN) vs. Temperature
Figure 50. Vfreeze vs. Temperature
www.onsemi.com
36
NCP1342
TYPICAL CHARACTERISTICS
1.31
1.308
1.306
1.304
1.302
1.3
104.2
104
103.8
103.6
103.4
103.2
103
1.298
1.296
1.294
102.8
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 51. fjitter vs. Temperature
Figure 52. Vjitter vs. Temperature
3.1
3.09
3.08
3.07
3.06
3.05
3.04
3.03
402.5
402
401.5
401
400.5
400
399.5
399
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 53. VFault(OVP) vs. Temperature
Figure 54. VFault(OTP_in) vs. Temperature
920
918
916
914
912
910
908
906
45.1
45
44.9
44.8
44.7
44.6
44.5
44.4
44.3
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 55. VFault(OTP_out) vs. Temperature
Figure 56. IOTP vs. Temperature
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37
NCP1342
TYPICAL CHARACTERISTICS
1.731
1.73
1.55
1.545
1.54
1.535
1.53
1.729
1.728
1.727
1.726
1.525
1.52
1.515
1.51
1.505
1.5
1.495
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 57. VFault(clamp) vs. Temperature
Figure 58. RFault(clamp) vs. Temperature
24.5
24.45
24.4
1.39
1.385
1.38
24.35
24.3
24.25
24.2
1.375
1.37
24.15
24.1
24.05
1.365
24
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 59. fMIN vs. Temperature
Figure 60. tquiet vs. Temperature
840
830
820
810
800
790
780
0.8
0.799
0.798
0.797
0.796
0.795
0.794
0.793
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 61. tZCD(blank) vs. Temperature
Figure 62. VILIM1 vs. Temperature
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38
NCP1342
TYPICAL CHARACTERISTICS
1.202
1.201
1.2
40
39.9
39.8
39.7
39.6
39.5
39.4
39.3
39.2
39.1
1.199
1.198
1.197
1.196
1.195
1.194
1.193
−40
−20
0
20
40
60
80
100 120
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 64. tDT(MAX) vs. Temperature
Figure 63. VILIM2 vs. Temperature
399
398.5
398
397.5
397
396.5
396
−40
−20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
Figure 65. Vskip vs. Temperature
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39
NCP1342
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
40
NCP1342
PACKAGE DIMENSIONS
SOIC−9 NB
CASE 751BP
ISSUE A
2X
NOTES:
0.10
C
A-B
0.10
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DE-
TERMINED AT DATUM F.
D
H
A
2X
0.20
C
4 TIPS
C A-B
F
10
6
E
1
5. DIMENSIONS A AND B ARE TO BE DETERM-
INED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
5
L2
A3
SEATING
PLANE
L
C
0.20
C
9X b
DETAIL A
B
5 TIPS
M
MILLIMETERS
0.25
C A-B D
DIM MIN
MAX
1.75
0.25
0.25
0.51
5.00
4.00
TOP VIEW
A
A1
A3
b
1.25
0.10
0.17
0.31
4.80
3.80
9X
h
X 45
_
0.10
C
0.10
C
D
E
M
e
1.00 BSC
H
5.80
6.20
h
L
L2
M
0.37 REF
A
0.40
0
1.27
DETAIL A
e
SIDE VIEW
A1
SEATING
PLANE
0.25 BSC
C
8
_
_
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
1.00
PITCH
9X
0.58
6.50
1
9X
1.18
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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