NCP1345Q00D1R2G_技术文档

DATA SHEET

www.onsemi.com

High-Voltage

9

1

Quasi-Resonant Flyback

Controller With USB-PD

Optimization

SOIC−9 NB

CASE 751BP

MARKING DIAGRAM

XXXXX = Specific Device Code

9

1

A

L

= Assembly Location

= Wafer Lot

NCP1345

The NCP1345 is a highly integrated quasi−resonant flyback

controller suitable for designing high−performance off−line USB−PD

XXXXX

ALYWX

G

Y

W

G

= Year

= Work Week

= Pb−Free Package

and USB Type−C power converters. The included dual−pin V

CC

architecture allows direct connection to the aux winding for simplified

PIN CONNECTIONS

V

management with a reduced parts count and increased

CC

1

performance.

Fault

HV

The NCP1345 also features a precise, primary side based output

current limiting circuit to ensure a constant output current limit

regardless of programmed output voltage, or nameplate output power.

The quasi−resonant (QR) current−mode flyback stage features

proprietary valley−lockout circuitry to ensure stable valley switching

FB

ZCD/OPP

CS

VCCH

VCCL

DRV

GND

th

down to the 6 valley, then transitions to frequency foldback mode to

ORDERING INFORMATION

See detailed ordering and shipping information on page 4 of

this data sheet.

reduce switching losses. As the load decreases further, the NCP1345

enters skip mode to manage the power delivery.

To help ensure converter ruggedness, the NCP1345 implements

several key protective features such as internal brownout detection, a

maximum output current limit regardless of input voltage, a latched

over voltage and NTC−ready overtemperature protection through a

dedicated pin, and line removal detection to safely discharge the X2

capacitors when the line is removed.

Features

• Integrated High−Voltage Startup Circuit with Brownout Detection

• Integrated X2 Capacitor Discharge Capability

• Wide V

Range from 8 V to 38 V

CCL

• 150 V V

Pin for Connection to High−Voltage Aux Winding

CCH

• 36.5 V V Overvoltage Protection

CC

• Primary Side Based Constant Output Current Limiting

• Abnormal Overcurrent Fault Protection for Winding Short Circuit

Detection

• Internal Temperature Shutdown

• Valley Switching Operation with Valley−Lockout for Noise−Free

Operation

• Rapid Frequency Foldback for Fast Reduction of Switching

Frequency

• Skip Mode with Output Voltage Compensation

• Minimized No Load Power Consumption

• Frequency Jittering for Reduced EMI Signature

• Latching or Auto−Recovery Overload Protection

• Adjustable Overpower Protection

• Fixed/Adjustable Maximum Frequency Clamp

• Fault Pin for Severe Fault Conditions, NTC Compatible for OTP

1

Publication Order Number:

January, 2023 − Rev. 3

NCP1345/D

NCP1345

APPLICATION DETAILS

Vout

+

NCP1345

Fault

FB

HV

USB−PD

+

ZCD/OPP VCCH

Controller

L

EMI

Filter

CS

VCCL

DRV

GND

N

+

−tº

Figure 1. Typical Application Circuit

FUNCTIONAL DETAILS

TSD

BO

X2/BO Detect

+

HV

X2

Abnormal OCP

OVLD

V

Fault

Management

CC

CC(OVP)

FMAX

Control

VCCH

VCCL

OVP

OTP

FMAX

Management

VLO/FF

Control

FB

Fault

Off−Time

Control

Dead−Time

Control

ZCD/

OPP

Vsense

V

CC

t

FMAX

tout

Clamp

V

FB(open)

Quiet−Skip

Control

FB

DRV

GND

S

R

Q

Jitter Ramp

R

FB

K

FB

CS

÷

On−Time

Control

V

Fault

DD

V

DD

OVP

OTP

OVP/OTP

Detect

Fault

ILIM1

Detect

t

LEB1

LEB2

t

OVLD

R

Iout

Comp

Fault(clamp)

V

Fault(clamp)

ILIM2

Detect

Count 4

Abnormal OCP

Figure 2. NCP1345 Simplified Block Diagram

www.onsemi.com

2

NCP1345

Table 1. PIN FUNCTIONAL DESCRIPTION

Pin Name

Pin Number

Function

Fault

1

The controller enters fault mode if the voltage on this pin is pulled above or below the fault thresholds.

A precise pull up current source allows direct interface with an NTC thermistor.

FB

2

3

Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.

ZCD/OPP

A resistor divider from the auxiliary winding to this pin provides input to the demagnetization detection

comparator and sets the OPP compensation level. It is also used to detect the output voltage for Auto−

Tuning Skip Mode.

CS

4

5

6

Input to the cycle−by−cycle current limit comparator.

GND

DRV

Ground reference.

This is the drive pin of the circuit. The DRV high−current capability (−0.5 /+0.8 A) makes it suitable to

effectively drive high gate charge power MOSFETs.

VCCL

7

This pin is the positive supply of the IC. The circuit starts to operate when V exceeds 17 V and turns

CC

off when V goes below 9 V (typical values). After start−up, the operating range is 9 V up to 36.5 V.

CC

VCCH

N/C

8

9

This pin is the high voltage Aux winding input and is rated up to 150 V.

Removed for creepage distance.

HV

10

This pin is the input for the high voltage startup and brownout detection circuits. It also contains the

line removal detection circuit to safely discharge the X2 capacitors when the line is removed.

Table 2. MAXIMUM RATINGS

Rating

Symbol

Value

Unit

V

High Voltage Startup Circuit Input Voltage

High Voltage Startup Circuit Input Current

Supply Input Voltage

V

−0.3 to 800

HV(MAX)

I

20

mA

V

−0.3 to 150

CCH(MAX)

Supply Input Current

I

20

mA

V

Supply Input Voltage

V

−0.3 to 38

CCL(MAX)

Supply Input Current

I

20

1

mA

V/ms

V

CCL(MAX)

Supply Input Voltage Slew Rate

Fault Input Voltage

dV /dt

CC

V

−0.3 to V + 0.7

Fault(MAX)

CC

Fault Input Current

I

10

mA

V

Zero Current Detection and OPP Input Voltage

Zero Current Detection and OPP Input Current

Maximum Input Voltage (Other Pins)

Maximum Input Current (Other Pins)

Driver Maximum Voltage (Note 1)

Driver Maximum Current

V

−0.3 to V + 0.7

ZCD(MAX)

CC

I

−2/+5

−0.3 to 5.5

10

mA

V

MAX

I

mA

V

DRV

−0.3 to V

DRV(high)

I

500

mA

DRV(SRC)

I

800

DRV(SNK)

Operating Junction Temperature

Storage Temperature Range

T

−40 to 125

–60 to 150

_C

J

T

STG

Power Dissipation (T = 25_C, 1 Oz Cu, 0.155 Sq Inch Printed Circuit Copper Clad)

P

mW

A

D(MAX)

D1 Suffix, SOIC−9

450

225

Thermal Resistance, Junction to Ambient (1 Oz Cu Printed Circuit Copper Clad)

D1 Suffix, SOIC−9

R

_C/W

q

JA

ESD Capability

Human Body Model per JEDEC Standard JESD22−A114E

Charge Device Model per JEDEC Standard JESD22−C101E

Latch−Up Protection per JEDEC Standard JESD78

2000

1000

100

V

mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Maximum driver voltage is limited by the driver clamp voltage, V

, when V

DRV(high)

exceeds the driver clamp voltage. Otherwise, the

CC

maximum driver voltage is V

.

CC

www.onsemi.com

3

NCP1345

ORDERING DETAILS

Table 3. PART NUMBER DECODE

Options

A − 19

B − 38

C − 57

D − 75

E − 94

F − 112

G − 131

H − 149

I − N/A

A − 69

B − 75

C − 81

D − 93

E − 109

F − 140

G − 164

H − Adj

I − Off

A − 0.25

B − 0.5

C − 1

D − 1.5

E − 1.95

F − 2.6

G − 3.9

H − 7.7

I − Off

A − 1st

B − 2nd

C − 3rd

D − 4th

E − 5th

F − 6th

G − Off

A − 50

A − 400

B − 350

C − 300

D − 250

E − Off

A − 750

B − 740

C − 730

D − 720

E − N/A

B − 75

A − 40

A − 11.5

B − 12.0 A − 310

A − 9.0

B − 8.5

A − 17 C − 8.0

B − 15 D − 7.5

A − Auto

B − 200

C − 150

D − 100

A − 0.8

B − 1.2

C − 1.6

D − Off

A − 3000

B − 700

C − 500

D − 100

C − 100

D − 150

E − 200

F − N/A

A − 80/32

B − 80

A − 20

B − 400

C − N/A

B − 125/50

C − 200/80

D − 275/110

C − 160 A − AR

D − 420 B − Latch A − AR

E − N/A

A −

C − 12.5 B − 450

A − AC

B − DC

A − 100

B − Off

A − Voltage

B − Current

UVLO

A − On A − 112/98 D − 13.0 C − Adj A − On

C − Off

B − Latch B − AR

B − Off B − Off

E − Off

D − Off B − Off

Suffix

Q00

Q01

Q02

A

B

E

B

E

C

A

B

A

I

A

D

B

C

I

B

G

E

C

B

C

A

B

A

B

A

Table 4. ORDERING INFORMATION

†

Part Number

NCP1345Q00D1R2G

NCP1345Q01D1R2G

NCP1345Q02D1R2G

Device Marking

1345Q00

Package

Shipping

SOIC−9 NB (Pb−Free)

1345Q01

2500 / Tape & Reel

1345Q02

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

www.onsemi.com

4

NCP1345

Table 5. ELECTRICAL CHARACTERISTICS

(V

= 12 V, V

= V

V

= 120 V, V

= open, V = 2.4 V, V = 0 V, V

= 0 V, C

= 100 nF, C

= 100 nF,

CCL

CCH

CCL, HV

Fault

FB

CS

ZCD

VCCL

VCCH

C

= 1 nF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

DRV

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

START−UP AND SUPPLY CIRCUITS

Supply Voltage

dV/dt = 0.1 V/ms

V

Startup Threshold

Minimum Operating Voltage

Operating Hysteresis (V

V

increasing

decreasing

V

16.0

8.5

7.5

6.0

0.40

17.0

9.0

–

6.5

0.70

18.0

9.5

–

7.2

1.05

CC

CC(on)

CC(off)

− V

)

V

CC(on)

CC(off)

CC(HYS)

CC(reset)

CC(inhibit)

Internal Latch / Logic Reset Level

Transition from I to I

V

CC

decreasing

V

CC

increasing, I = 650 mA

start1

start2

HV

V

Delay

V

decreasing

t

delay(VCC_off)

25

–

32

–

40

500

30

ms

V

CC(off)

CC

Startup Delay

Delay from V

to DRV Enable

t

delay(start)

CC(on)

Minimum Voltage for Start−Up Current

Source

V

–

HV(MIN)

Inhibit Current Sourced from V Pin

V

= 0 V

I

0.2

0.5

0.65

mA

CC

cc

start1

Start−Up Current Sourced from V Pin

V

cc

= V

– 0.5 V

I

2.4

−

3.75

−

5.8

0

CC

cc(on)

start2

HV Discharge Active

start3

Start−Up Circuit Off−State Leakage Current

V

HV

= 800 V

I

–

30

mA

HV(off)

Supply Current

mA

Fault or Latch

Skip Mode (excluding FB current)

Operating Current

V

= V

– 0.5 V

I

−

0.115

0.250

1.35

0.250

0.455

2.00

CC

CC(on)

CCL1

CCL2

CCL3

V = 0 V

FB

f

= 50 kHz, C

= open

sw

DRV

DUAL VCC MANAGEMENT

Regulation Voltage

I

= 5 mA

V

REG

9.5

10.0

10.6

V

CCH

Dropout Voltage (V

− V

)

Adjust V

such that

REG

V

DO

mV

VCCH

CCL

CCH

V

= V

− 1 V

CCL

I

= 5 mA

= 500 mA

−

600

75

1300

200

CCH

I

CCH

Input Off−State Leakage Current

I

−

15

mA

VCCH(off)

INPUT FILTER CAPACITOR DISCHARGE (ALL EXCEPT Q02)

Line Voltage Removal Detection Timer

t

80

−

100

14

1

120

−

ms

mA

line(removal)

Upslope Detection Reset Timer

Downslope Detection Reset Timer

HV Discharge Current

HV increasing

HV decreasing

t

HV(up)

t

−

HV(down)

I

0.75

0.04

2

−

3.75

0.6

HV(disch)

V

HV

= V

+ 100 mV

HVdisch(end)

V

Discharge Current

V

= V

CC(on)

I

13

18

23

40

mA

V

CC

CC(disch)

Minimum Voltage for Discharge Current

Source

I

= 0.8 * I

V

−

HV

HV(disch)

HVdisch(min)

HV Discharge Active

HV Discharge Stop Level

–

30

V

HVdisch(end)

Delta Between V

Stop Level

and HV Discharge

D

0.1

−

CC(on)

discharge

BROWNOUT DETECTION

System Start−Up Threshold

Brownout Threshold

V

increasing

decreasing

increasing

decreasing

V

107

93

9

112

98

117

103

–

V

HV

BO(start)

BO(stop)

BO(HYS)

BO(stop)

V

HV

Hysteresis

V

14

V

HV

Brownout Detection Blanking Time

V

t

40

70

100

ms

2. NTC with R

= 8.8 kW

110

www.onsemi.com

5

NCP1345

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(V

= 12 V, V

= V

V

= 120 V, V

= open, V = 2.4 V, V = 0 V, V

= 0 V, C

= 100 nF, C

= 100 nF,

CCL

CCH

CCL, HV

Fault

FB

CS

ZCD

VCCL

VCCH

C

= 1 nF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

DRV

J

Characteristics

GATE DRIVE

Conditions

Symbol

Min

Typ

Max

Unit

Adaptive Gate Drive Engagement Valley

n

DRV(valley)

Q00

Q01/Q02

2

3

Rise Time

V

DRV

from 10% to 90%

t

ns

DRV(rise)

C

= 0.8 V, C

= 100 pF

–

−

20

50

200

550

−

90

−

DRV

= 1 nF

DRV

During Adaptive Gate Drive

Fall Time

V

= 100 pF

FB

DRV

= 1 nF

350

850

FB

DRV

V

DRV

from 90% to 10%

t

–

20

60

ns

DRV(fall)

Source Current Capability

During Adaptive Gate Drive

V

= 2 V

= 0.7 V

I

–

500

50

–

mA

FB

DRV(SRC)

V

FB

Sink Current Capability

Drive Clamp Voltage

High State Voltage

Low Stage Voltage

FEEDBACK

I

–

10

8

800

12

–

14

–

mA

V

DRV(SNK)

V

= 30 V, R

= 10 kW

V

DRV(clamp)

CC

DRV

V

CC

= V

+ 0.2 V, R

= 10 kW

V

DRV(high)

V

CC(off)

DRV

V

Fault

= 0 V

V

–

0.25

V

DRV(low)

Open Pin Voltage

V

4.8

3.6

5.0

4.0

5.2

4.4

V

–

FB(open)

V

FB

to Internal Current Setpoint Division

K

FB

Ratio

Internal Pull−Up Resistor

V

FB

= 0.4 V

R

17.0

20.0

25.0

kW

FB

Valley Thresholds

Transition from 1 to 2 valley

Transition from 2 to 3 valley

Transition from 3 to 4 valley

Transition from 4 to 5 valley

Transition from 5 to 6 valley

Transition from 6 to 5 valley

Transition from 5 to 4 valley

V

st

nd

V

decreasing

increasing

V

1to2

V

2to3

V

3to4

V

4to5

V

5to6

V

6to5

V

5to4

V

4to3

V

3to2

V

2to1

1.316

1.128

1.034

0.940

0.846

1.410

1.504

1.598

1.692

1.880

1.400

1.200

1.100

1.000

0.900

1.500

1.600

1.700

1.800

2.000

1.484

1.272

1.166

1.060

0.954

1.590

1.696

1.802

1.908

2.120

FB

nd

rd

th

FB

th

rd

Transition from 4 to 3 valley

Transition from 3 to 2 valley

Transition from 2 to 1 valley

rd

nd

st

Maximum On Time

t

26

32

38

ms

on(MAX)

FEEDBACK (CASCODE/HIGH BW OPTION)

Clamp Voltage

I

= 150 mA

V

2

2.5

1

−

V

FB

clamp

Dynamic Resistance

5.0 mA < I < 250 mA

R

0.5

1.6

kW

FB

dyn(FB)

DEMAGNETIZATION INPUT

ZCD threshold voltage

V

decreasing

increasing

V

35

10

–

60

25

80

95

55

mV

ns

ZCD

ZCD(trig)

ZCD hysteresis

V

ZCD(HYS)

ZCD

Demagnetization Propagation Delay

V

ZCD

step from 2.1 V to 0 V

t

150

demag

ZCD Clamp Voltage

Negative Clamp

Not including R

V

Vout

I

= −2.0 mA

V

−0.9

−0.7

0

QZCD

ZCD(MIN)

Blanking Delay After Turn−Off

t

0.60

0.70

0.80

ms

ZCD(blank)

Timeout After Last Demagnetization

Detection

While in soft−start

After soft−start complete

t

80

5.1

100

6

120

6.9

(tout1)

(tout2)

2. NTC with R

= 8.8 kW

110

www.onsemi.com

6

NCP1345

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(V

= 12 V, V

= V

V

= 120 V, V

= open, V = 2.4 V, V = 0 V, V

= 0 V, C

= 100 nF, C

= 100 nF,

CCL

CCH

CCL, HV

Fault

FB

CS

ZCD

VCCL

VCCH

C

= 1 nF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

DRV

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

DEMAGNETIZATION INPUT

Maximum Frequency Clamp

Q00, Q01, Q02

f

kHz

MAX

−

Number of Consecutive Open Pin Triggers

to Enter Latch Mode

n

ZCD

–

4

–

ZCD Pull−Down Resistor

ZCD Pull−Up Current

CURRENT SENSE

Soft−Start Period

R

0.97

0.8

1.00

1.04

1.2

kW

mA

Vout

I

1

ZCD

st

Measured from 1 DRV pulse to

t

2.8

4.0

5.0

ms

SSTART

V

= V

CS

ILIM1

Current Limit Threshold Voltage

V

CS

increasing

V

ILIM1

0.765

0.800

0.835

V

Leading Edge Blanking Duration

Q00, Q01, Q02

DRV minimum width minus

t

ns

LEB1

t

delay(ILIM1)

100

–

125

–

150

80

Current Limit Threshold Propagation Delay

Step V

25 mV below V

to

t

ns

CS

ILIM1

delay(ILIM1)

75 mV above V

, V = 4 V

ILIM1

FB

Overpower Protection Delay

Step V

25 mV below

t

–

90

CS

OPP(delay)

delay(PWM)

V

− V

to 75 mV above

ILIM1

OPP

V

ILIM1

− V

, V = 4 V

OPP FB

PWM Comparator Propagation Delay

Minimum Peak Current

Step V

25 mV below V /k to

110

ns

CS

FB FB

75 mV above V /k

FB FB

V

mV

CS(MIN)

V

= 10.5 V

= 1.25 V

170

60

200

80

230

100

ZCD(hi)

CSmin Comparator Propagation Delay

Step V

25 mV below V

t

delay(CSMIN)

–

140

ns

CS

CS(MIN)

to 75 mV above V

RFF Current Shift

Q00

Q01/Q02

V

= 800 mV

V

mV

FB

RFF(delta)

RFF(entry)

−

300

−

350

−

400

RFF Entry Threshold

(All Except Q00)

V

FB

Decreasing

Increasing

V

775

800

840

mV

ms

RFF Exit Threshold

Q01/Q02

V

FB

V

RFF(exit)

700

730

760

RFF Transition Timer

(All Except Q00)

t

0.80

1.00

1.10

RFF

Abnormal Overcurrent Fault Threshold

V

CS

increasing, V = 5.0 V

V

ILIM2

1.125

1.200

1.275

V

FB

Abnormal Overcurrent Fault Blanking

Duration

DRV minimum width minus

t

ns

LEB2

t

delay(ILIM2)

Q00, Q01, Q02

25

–

50

–

75

90

Abnormal Overcurrent Fault Propagation

Delay

Step V

25 mV below V

to

t

delay(ILIM2)

ns

CS

ILIM2

75 mV above V

, V = 5 V

ILIM2

FB

Number of Consecutive Abnormal Overcur-

rent Faults to Enter Latch Mode

n

ILIM2

–

4

–

Pull−Up Current Source

V

= 1.5 V

I

0.7

1.0

1.5

mA

CS

OVERPOWER PROTECTION (OPP)

OPP Programming Current

Start−up Only

I

19

20

21

OPP

OUTPUT CURRENT LIMIT

IOUT Pin Source Current (10−Pin Only)

I

9.0

10.0

11.0

IOUT

2. NTC with R

= 8.8 kW

110

www.onsemi.com

7

NCP1345

Table 5. ELECTRICAL CHARACTERISTICS (continued)

(V

= 12 V, V

= V

V

= 120 V, V

= open, V = 2.4 V, V = 0 V, V

= 0 V, C

= 100 nF, C

= 100 nF,

CCL

CCH

CCL, HV

Fault

FB

CS

ZCD

VCCL

VCCH

C

= 1 nF, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)

DRV

J

Characteristics

OUTPUT CURRENT LIMIT

Conditions

Symbol

Min

Typ

Max

Unit

Demagnetization End Detection Drop

Feedback Voltage Overload Threshold

V

120

150

180

mV

V

demag(det)

Apply 100 kHz Square Wave to

ZCD Pin +6.9V / 0 V, and Inverse

Square Wave to CS Pin 0.9V/0V

V

FB(OVLD)

Q01/Q02

Q00

60% Duty Cycle, V

95% Duty Cycle, V

60% Duty Cycle, V

95% Duty Cycle, V

= 310 mV

= 450 mV

1.475

0.85

2.280

1.340

1.750

0.99

2.680

1.575

2.025

1.15

3.080

1.810

REFiout

JITTERING

Jitter Frequency

Q00, Q01, Q02

f

kHz

mV

jitter

3.31

3.90

4.49

Peak−to−Peak Jitter Voltage

V

jitter

Q01/Q02

Q00

85

170

100

200

115

230

FAULT PROTECTION

Flyback Overload Fault Timer

Overvoltage Protection (OVP) Threshold

Overvoltage Protection (OVP) Delay

Output OVP Threshold

V

= V

t

120

2.99

22.5

11.4

–

160

3.20

30.0

12.0

3

200

3.41

37.5

12.4

–

ms

V

CS

ILIM1

OVLD

V

increasing

V

Fault

Fault(OVP)

delay(OVP)

increasing

t

ms

V

out(OVP)

Number of Consecutive OVP Detections to

Trigger Fault

n

out(OVP)

V

Overvoltage Protection Threshold

Overvoltage Protection Delay

V

35.0

25

36.5

32

38.0

40

V

ms

V

CC

CC(OVP)

t

delay(VCC_OVP)

CC

Overtemperature Protection (OTP)

Threshold (Note 2)

V

decreasing

increasing

decreasing

V

0.388

0.40

0.412

Fault

Fault(OTP_in)

Overtemperature Protection (OTP) Exiting

Threshold (Note 2)

V

0.880

0.920

0.960

V

Fault

Fault(OTP_out)

OTP Detection Delay

V

t

22.5

30.0

45.0

37.5

ms

delay(OTP)

OTP Pull−Up Current Source

V

Fault

= V

+ 0.2 V

I

OTP

43.75

46.25

mA

Fault(OTP_in)

T = 25°C to 125°C

J

Fault Input Clamp Voltage

Fault Input Clamp Series Resistor

Autorecovery Timer

V

R

1.15

1.52

1.8

1.7

1.75

2

2.25

1.98

2.2

V

kW

s

Fault(clamp)

t

restart

LIGHT/NO LOAD MANAGEMENT

Minimum Frequency Clamp

f

21.0

32

24.5

28.0

kHz

MIN

Dead−Time Added During Frequency

Foldback

V

FB

= 400 mV

t

−

ms

DT(MAX)

Quiet−Skip Timer

t

1.18

304

35

1.25

320

50

1.40

336

75

ms

mV

quiet

Skip Threshold

V

decreasing

increasing

V

FB

skip

V

skip(HYS)

Skip Hysteresis

V

FB

THERMAL PROTECTION

Thermal Shutdown

Thermal Shutdown Hysteresis

Temperature increasing

Temperature decreasing

T

–

140

40

–

°C

SHDN

T

SHDN(HYS)

2. NTC with R

= 8.8 kW

110

www.onsemi.com

8

NCP1345

OPERATIONAL DESCRIPTION

HIGH VOLTAGE START−UP CIRCUIT

off. If the input voltage is not high enough to ensure a proper

start−up (i.e. V has not reached V ), the controller

The NCP1345 contains a multi−functional high voltage

(HV) pin. While the primary purpose of this pin is to reduce

standby power while maintaining a fast start−up time, it also

incorporates brownout detection and line removal detection.

The HV pin must be connected directly to the ac line in

order for the HV discharge circuit to function correctly. Line

and neutral should be diode “ORed” before connecting to the

HV pin as shown in Figure 3.

HV

BO(start)

will not start. V then begins to fall because the controller

CC

bias current is at I

(typically 1 mA) and the auxiliary

CC2

supply voltage is not present. When V falls to V

CC

CC(off)

(typically 10.5 V), the current source turns back on and

charges V . This cycle repeats indefinitely until V

CC

HV

reaches V

. Once this occurs, the current source

BO(start)

immediately turns on and charges V to V

, at which

CC(on)

CC

The diodes prevent the pin voltage from going below

ground. A resistor in series with the pin should be used to

protect the pin during EMC or surge testing. A low value

resistor should be used (<5 kW) to reduce the voltage offset

during start−up. The start−up circuit block diagram is shown

in Figure 4.

point the controller starts (see Figure 5).

When V is brought below V

, the start−up

CC

CC(inhibit)

current is reduced to I

(typically 0.5 mA). This limits

start1

power dissipation on the device in the event that the V pin

CC

CC(inhibit)

is shorted to ground. Once V rises back above V

,

CC

the start−up current returns to I

.

start2

Once V reaches V

, the controller is enabled and

CC

CC(on)

the controller bias current increases to I

(typically

CC3

2.0 mA). However, the total bias current is greater than this

due to the gate charge of the external switching MOSFET.

AC

CON

EMI

The increase in I due to the MOSFET is calculated using

CC

Equation 1.

DI_CC+ f_sw@ Q_G

(eq. 1)

HV

where DI is the increase in milliamps, f is the switching

CC

sw

Controller

frequency in kilohertz and Q is the gate charge of the

G

external MOSFET in nanocoulombs.

C

CC(off)

must be sized such that a V voltage greater than

is maintained while the auxiliary supply voltage

VCC

CC

Figure 3. High−Voltage Input Connection

V

increases during start−up. If C

is too small, V will fall

VCC

CC

below V

and the controller will turn off before the

CC(off)

Start−up and V_CCManagement

During start−up, the current source turns on and charges

auxiliary winding supplies the IC. The total I current after

the controller is enabled (I

considered to correctly size C

CC

plus DI ) must be

CC3

CC

the V capacitor with I

(typically 6 mA). When V

CC

start2

cc

.

VCC

reaches V

(typically 16.0 V), the current source turns

CC(on)

Figure 4. Start−up Circuitry Block Diagram

www.onsemi.com

9

NCP1345

V_HV

V_BO(start)

V_HV(MIN)

V_CC

V_CC(on)

V_CC(off)

Start−up

Current = I_start2

t_delay(start)

Start−up

Current = I_start1

V_CC(inhibit)

DRV

Figure 5. Start−up Timing

Dual−Range V_CCManagement

For typical USB−PD 3.0 adpter designs, the output

voltage ranges from 3.3V up to 21V. This wide variation of

output voltage places a burden on the primary controller to

support a wide range of VCC voltages. , the NCP1345

HV

VCCH

Istart

incorporates a dual range V architecture. This consists of

CC

a second V pin, VCCH, rated at 200 V. The VCCH pin is

CC

designed to connect directly to a second aux winding

providing a bias voltage roughly 3x−4x the output voltage,

and thus 3x−4x the main aux winding voltage.

When the output voltage is at the minimum voltage of

3.3V, the main aux winding voltage will be too low to supply

the NCP1345. During this period, the VCCH pin will

receive ~12.6 V from the VCCH winding. This voltage is

passed to VCCL through an internal regulator with dropout

VCCL

voltage, V , of 0.5 V, resulting in a VCCL voltage of

DO

12.1 V. As the output voltage increases, the VCCH voltage

increases accordingly, and the internal regulator ensures that

VCCL is kept at 10 V.

As the output voltage continues to rise, the VCCL aux

Figure 6. Simplified V_CCManagement Circuit

winding voltage eventually exceeds V

, 10 V typical, and

REG

back−biases the internal regulator, thus disabling it. Figure 6

shows the simplified V management block.

CC

www.onsemi.com

10

NCP1345

DRIVER

Adaptive Gate Drive

The NCP1345 maximum supply voltage, V

, is

Due to the loss of valley switching during frequency

foldback, the output rectifier can be subjected to large

voltage spikes during the primary switch turn−on. The

NCP1345 includes special circuitry to reduce the driver

turn−on strength during frequency foldback, and thus reduce

the severity of the secondary voltage spike. Figure 7 shows

the operation of the adaptive gate drive.

CC(MAX)

40 V. Typical high−voltage MOSFETs have a maximum

gate voltage rating of 20 V. The DRV pin incorporates an

active voltage clamp to limit the gate voltage on the external

MOSFETs. The DRV voltage clamp, V

12 V with a maximum limit of 14 V.

is typically

DRV(high)

V

FB

800 mV

V

DRV

I_DRV

+500 mA

+100 mA

−800 mA

Figure 7. Adaptive Gate Drive Waveforms

www.onsemi.com

11

NCP1345

Option 2: Cascode Buffer High BW Architecture

The 2 option for the FB pin interface will be a Cascode

buffer, current controlled architecture and is shown in

Figure 9.

In this architecture, the collector of the optocoupler

FEEDBACK INTERFACE

Option 1: Register Pullup

The 1 (default) option will be a resistor pullup, voltage

controlled architecture as shown in Figure 8. In this

architecture the FB pin is supplied by a 5 V rail through a

nd

st

interfaces with a voltage clamp, V

, set by the cascode

clamp

pullup resistor, R . The default value of R in this

FB

buffer. The minimum value of the voltage clamp is specified

at 2 V when tested at a pull down current of 150 mA. The

clamp voltage set by the cascode transforms the

conventional voltage controlled architecture into a current

controlled architecture as the FB pin voltage remains

approximately constant regardless of the collector current

through the optocoupler. The benefit of this architecture is

that the effective impedance seen by the collector of the

optocoupler is greatly reduced when compared to the

voltage controlled architecture, allowing the SMPS to

achieve a higher closed loop bandwidth. The specified

architecture is 20 kW and there will be IPT options for R

FB

of 400 kW. In addition to the pullup resistor, a current source

in parallel with R , can be enabled via IPT options. The

I

FB

purpose of this current source is to increase the dynamic

range when using an external pull down resistor. By default,

I

is disabled, however it can be set via IPT options to

FB

100 mA. The FB pin open circuit voltage, V

specified with a typical value of 5 V.

, is

FB(open)

Internally the voltage at the FB pin divided down by a 4:1

voltage divider. The voltage directly at the FB (atop the 4:1

divider) is fed into the skip and valley comparators while the

divided down signal is fed into the PWM comparator and the

current limit comparator.

The resistor pullup is a conventional voltage controlled

architecture which translates the error signal communicated

through the optocoupler into an error voltage that controls

the duty cycle of the SMPS. In this architecture, a capacitor

to GND is placed in parallel to the collector of the

optocoupler to control the location of the optocoupler pole.

dynamic resistance for the FB pin, R , ranges from

dyn(FB)

850 W to 1.15 kW when the pulldown current is swept from

5 mA to 250 mA. With the specified dynamic resistance, it is

also still possible for the designer to place a capacitor across

the collector to GND to set a high frequency pole for

stabilization of the SMPS control loop. Typical capacitor

values will be in the range of 470 pF – 47 nF. A small 25 mA

offset current, I , is added to ensure stability of the

FB(offset)

FB pin.

Due to the resistance of R , the optocoupler pole will

FB

An additional capacitor, C , is placed after R for

filter FB

typically be in the range of 2 kHz to 4 kHz which limits the

closed loop bandwidth of the SMPS in the range of 1 – 2 kHz.

The capacitor placed in parallel to the collector of the

optocoupler will typically be in the range of 470 pF to 4.7 nF

with 1 nF being a fairly common value.

noise filtering. This capacitor is 10 pF, typical. It can also be

disconnected via IPT option.

Internal to the cascode interface is a pair of current mirrors

which sense the optocoupler collector current and transpose

an image of the collector current to the pullup resistor, R

.

FB

The pair of current mirrors also ensures that the polarity of

the error signal communicated though the optocoupler has

the intended effect of increasing or decreasing the pulse

width of the primary controlled switch in the SMPS.

In the voltage controlled architecture, the midband gain of

the AC open loop transfer function is determined by R

.

FB

However, in the current controlled architecture, the midband

gain is determined by R , the apparent pullup

FB(app)

resistance.

As previously mentioned, there will be IPT options for

. In order to reduce current consumption, R is set to

R

FB

the maximum option of 400 kW. The internal current divider

is then configured to provide a default R value of

20 kW, with IPT options of 20 kW up to 320 kW in 20 kW

FB(app)

Figure 8. Pull−up Resistor FB Interface

increments.

www.onsemi.com

12

NCP1345

Figure 9. Cascode Buffer High Bandwidth Feedback Interface

ON TIME CONTROL

In addition to the PWM comparator, a dedicated

comparator monitors the current sense voltage, and if it

reaches the maximum value, V (typically 800 mV), the

gate driver is turned off and the overload timer is enabled.

This occurs even if the limit imposed by the feedback

Peak Current Control

ILIM

The NCP1345 is a peak current−mode controller, thus the

FB voltage sets the peak current flowing in the transformer

and the MOSFET. This is achieved by sensing the MOSFET

current across a resistor and applying the resulting voltage

ramp to the non−inverting input of the PWM comparator

through the CS pin. The current limit threshold is set by

voltage is higher than V

. Due to the parasitic

ILIM1

capacitances of the MOSFET, a large voltage spike often

appears on the CS Pin at turn−on. To prevent this spike from

falsely triggering the current sense circuit, the current sense

applying the FB voltage divided by K (typically 4) to the

FB

signal is blanked for a short period of time, t

(typically

LEB1

inverting input of the PWM comparator. When the current

sense voltage ramp exceeds this threshold, the output driver

is turned off, however, the peak current is affected by several

functions (see Figure 10):

The peak current level is clamped during the soft−start

phase. The setpoint is actually limited by a clamp level

ramping from 0 to 0.8 V within 4 ms.

275 ns), by a leading edge blanking (LEB) circuit. Figure 10

shows the schematic of the current sense circuit.

The peak current is also limitied to a minimum level,

V

(0.2 V, typically). This results in higher efficiency

CS(MIN)

at light loads by increasing the minimum energy delivered

per switching cycle, while reducing the overall number of

switching cycles during light load.

www.onsemi.com

13

NCP1345

R

OPP

ZCD/OPP

OPP

V

FB(open)

Minimum Peak

Current

+

R

FB

*

DRV Off

V

ILIM1

V

CS(MIN)

Soft−Start

Ramp

K

FB

*

+

PWM

*

+

OCP

*

CS

t

LEB1

LEB2

Overload Timer

+

R

sense

AOCP

t

+

*

Abnormal OCP Counter

V

ILIM2

Figure 10. Peak Current Setpoint

Soft−Start

is high enough to prevent the timer from running. Therefore,

a longer timeout period, t (typically 100 ms), is used

during soft−start to prevent CCM operation.

Soft−start is achieved by ramping up an internal reference,

tout1

V

, and comparing it to the current sense signal.

SSTART

ramps up from 0 V once the controller initially

SSTART

Frequency Jittering

powers up. The peak current setpoint is then limited by the

ramp resulting in a gradual increase of the switch

In order to help meet stringent EMI requirements, the

NCP1345 features frequency jittering to average the energy

peaks over the EMI frequency range. As shown in Figure 12:

Jitter Implementation, the function consists of summing a

V

SSTART

current during start−up. The soft−start duration, t

typically 4 ms.

, is

SSTART

During startup, demagnetization phases are long and

difficult to detect since the auxiliary winding voltage is very

small. In this condition, the 6 ms steady−state timeout is

generally shorter than the inductor demagnetization period.

If it is used to restart a switching cycle, it can cause operation

in CCM for several cycles until the voltage on the ZCD pin

0 to 50 mV, 250 Hz triangular wave (V

) with the CS

jitter

signal immediately before the PWM comparator. This

current acts to modulate the on−time and hence the operation

frequency.

www.onsemi.com

14

NCP1345

DRV

MOD

+1

0

−1

RAMP

+V

jitter

0 mV

JITTER

+V

jitter

0 mV

−V

jitter

Figure 11. Jitter Timing

www.onsemi.com

15

NCP1345

V

DD

R

FB

CS

K

FB

V

jitter

DRV

+/− 1

LEB

V

OPP

DRV Off

V

ILIM1

V

CS(MIN)

Figure 12. Jitter Implementation

Since the jittering function modulates the peak current

level, the FB signal would normally attempt to compensate

for this effect in order to limit the output voltage ripple, thus

cancelling out the effect of the jitter. Therefore, the

NCP1345 incorporates a special circuit to alternate the

polarity of the jitter at each switching cycle. That is, during

each successive switching cycle, the jitter ramp voltage is

multiplied by 1 and −1 alternately. This causes the average

FB voltage ripple to tend to zero, and removes the cancelling

effect.

turns on the power switch at the drain voltage minimum or

“valley” to reduce switching losses and electromagnetic

interference (EMI).

As shown by Figure 14, a valley is detected once the ZCD

pin voltage falls below the demagnetization threshold,

V

, typically 55 mV. The controller will either switch

ZCD(trig)

once the valley is detected or increment the valley counter,

depending on the FB voltage.

Valley Lockout Operation

The operating frequency of a traditional QR flyback

controller is inversely proportional to the system load. In

other words, a load reduction increases the operating

frequency. A maximum frequency clamp can be useful to

limit the operating frequency range. However, when used by

itself, such an approach often causes instabilities since when

this clamp is active, the controller tends to jump (or hesitate)

between two valleys, thus generating audible noise.

Instead, the NCP1345 also incorporates a patented valley

lockout (VLO) circuitry to eliminate valley jumping. Once

a valley is selected, the controller stays locked in this valley

until the output power changes significantly. This technique

extends the QR mode operation over a wider output power

range while maintaining good efficiency and limiting the

maximum operating frequency.

Due to the minimum peak current, the effect of the

jittering circuit will not be seen during frequency foldback

mode.

OFF TIME CONTROL

Zero Current Detection

The NCP1345 is a quasi−resonant (QR) flyback

controller. While the power switch turn−off is determined by

the peak current set by the feedback loop, the switch turn−on

is determined by the transformer demagnetization. The

demagnetization is detected by monitoring the transformer

auxiliary winding voltage.

Turning on the power switch once the transformer is

demagnetized has the benefit of reduced switching losses.

Once the transformer is demagnetized, the drain voltage

starts ringing at a frequency determined by the transformer

magnetizing inductance and the drain lump capacitance,

eventually settling at the input voltage. A QR flyback

controller takes advantage of the drain voltage ringing and

st

nd

rd, th

th

The operating valley (1 , 2 , 3 4 , 5 or 6 ) is

determined by the FB voltage. An internal counter

increments each time a valley is detected by the ZCD/OPP

Pin. Figure 13 shows a typical frequency characteristic

obtainable at low line in a 65 W application.

www.onsemi.com

16

NCP1345

6^th5^th4^th

3^rd

2^nd

1^st

1x10⁵

8x10⁴

6x10⁴

4x10⁴

2x10⁴

0

VCO

mode

6^th

5^th4^th

3^rd

2^nd

1^st

VCO

mode

0

20

40

60

Pout (W)

Figure 13. Valley Lockout Frequency vs. Output Power

When an “n” valley is asserted by the valley selection

circuitry, the controller is locked in this valley until the FB

voltage decreases to the lower threshold (“n+1” valley

activates) or increases to the “n valley threshold” + 600 mV

(“n−1” valley activates). The regulation loop adjusts the

peak current to deliver the necessary output power. Each

valley selection comparator features a 600 mV hysteresis

that helps stabilize operation despite the FB voltage swing

produced by the regulation loop.

Table 6. NCP1345 VALLEY FB THRESHOLDS (TYPICAL VALUES)

FB falling

FB rising

st

nd

st

1

to 2 valley

1.400 V

1.200 V

1.100 V

1.000 V

0.900 V

2

to 1 valley

2.000 V

1.800 V

1.700 V

1.600 V

1.500 V

nd

rd

nd

2

to 3 valley

3

to 2 valley

rd

th

rd

3

4

5

to 4 valley

4

5

to 3 valley

th

to 5 valley

to 4 valley

th

to 6 valley

6

to 5 valley

Valley Timeout

operation lasts for a few cycles until the voltage on the ZCD

pin is high enough to detect the valleys. A longer timeout

In case of extremely damped oscillations, the ZCD

comparator may not be able to detect the valleys. In this

condition, drive pulses will stop while the controller waits

for the next valley or ZCD event. The NCP1345 ensures

continued operation by incorporating a maximum timeout

period after the last demagnetization detection. The timeout

signal acts as a substitute for the ZCD signal to the valley

counter. Figure 14 shows the valley timeout circuit

period, t

, (typically 100 ms) is set during soft−start to

tout1

limit CCM operation.

In VLO operation, the number of timeout periods are

counted instead of valleys when the drain−source voltage

oscillations are too damped to be detected. For example, if

the FB voltage sets VLO mode to turn on at the fifth valley,

and the ZCD ringing is damped such that the ZCD circuit is

only able to detect:

schematic. The steady state timeout period, t

, is set at

tout2

6 ms (typical) to limit the frequency step.

• Valleys 1 to 4: the circuit generates a DRV pulse 6 ms

th

During startup, the voltage offset added by the OPP diode,

, prevents the ZCD Comparator from accurately

(steady−state timeout delay) after the 4 valley

D

OPP

detection.

detecting the valleys. In this condition, the steady state

timeout period will be shorter than the inductor

demagnetization period causing CCM operation. CCM

• Valleys 1 to 3: the timeout delay must run twice, and

rd

the circuit generates a DRV pulse 12 ms after the 3

valley detection.

www.onsemi.com

17

NCP1345

Figure 14. Valley Timeout Circuitry

Maximum Frequency Clamp

The dead−time circuit is designed to add 0 ms dead−time

when V = 0.8 V and linearly increases the total dead−time

The NCP1345 includes a maximum frequency clamp. In

all versions, the clamp is available disabled or fixed at

140 kHz. In the 10−pin versions, the clamp can be adjusted

via an external resistor from the FMAX Pin to ground. It can

also be disabled by pulling the FMAX pin above 3 V.

FB

DT(MAX)

to t

(36 ms typical) as V falls down to 0.4 V. The

FB

minimum frequency clamp prevents the switching

frequency from dropping below 25 kHz to eliminate the risk

of audible noise. Note that the dead−time is not added until

RFF is engaged to ensure valley switching and prevent

reduction of the RFF entry load threshold.

LIGHT LOAD MANAGEMENT

In addition to dead−time, the peak current setpoint is

Frequency Foldback with Rapid Frequency Foldback

(RFF)

linearly reduced as V falls down to 0.4 V. This ensures that

FB

the peak current is not too high during the lightest loads, and

has the effect of reducing the skip entry power level.

Figure 15 shows the RFF with respect to the feedback

voltage.

To reduce the hysteresis between entering and exiting

RFF, the exit threshold is actually slightly below the entry

As the output load decreases (FB voltage decreases), the

valleys are incremented from 1 to 6. When the sixth valley

is reached and the FB voltage further decreases to 0.8 V, the

minimum peak current setpoint is increased by V

RFF(delta)

(0.4 V typically), and the controller enters frequency

foldback mode (FF). The increase in peak current serves to

force the switching frequency to a much lower value, thus

improving the efficiency at light loads. During this mode,

the controller regulates the power delivery by modulating

the switching frequency.

threshold (0.75 V). A 1 ms timer, t , is engaged every time

RFF

RFF is entered or exited to prevent oscillations during the

operating point transition. If at any time FB falls to skip

th

mode, or rises to 5 valley, RFF will be immediately exited

regardless of the state of the lockout timer. Figure 16

summarizes the VLO to foldback operation with respect to

the FB voltage.

Once in frequency foldback mode, the controller reduces

th

the switching frequency by adding dead−time after the 6

valley is detected. This dead−time increases as the FB

voltage decreases.

Minimum Peak Current

V_CS(MIN)+V_RFF(delta)

V

CS(MIN)

V

FB

V

skip

V_RFF(entry)

Figure 15. Rapid Frequency Foldback

www.onsemi.com

18

NCP1345

Operating Mode

V_FB

decreases

increases

FF

Valley 6

Valley 5

Valley 4

Valley 3

Valley 2

Fault !

Valley 1

V_FB(V)

0.8 0.9 1.0 1.1 1.2 1.4 1.5 1.6 1.7 1.8 2.0

3.2

Figure 16. Valley Lockout Threshold

Minimum Frequency Clamp and Skip Mode

As mentioned previously, the circuit prevents the

as the current drive pulses ends – it does not stop

immediately.

Once switching stops, FB will rise. As soon as FB crosses

the skip−exit threshold, drive pulses will resume, but the

controller remains in burst mode. At this point, a 1.25 ms

switching frequency from dropping below f

(25 kHz

MIN

typical). When the switching cycle would be longer than

40 ms, the circuit forces a new switching cycle. However, the

f

clamp cannot generate a DRV pulse until the

timer, t , is started together with a count−to−3 counter.

quiet

MIN

demagnetization is completed. In other words, it will not

cause operation in CCM.

The next time the FB voltage drops below the skip−in

threshold, drive pulses stop at the end of the current pulse as

long as 3 drive pulses have been counted (if not, they do not

Since the NCP1345 forces a minimum peak current and a

minimum frequency, the power delivery cannot be

continuously controlled down to zero. Instead, the circuit

starts skipping pulses when the FB voltage drops below the

skip level, V , and recovers operation when V exceeds

rd

stop until the end of the 3 pulse). They are not allowed to

start again until the timer expires, even if the skip−exit

threshold is reached first. It is important to note that the

timer will not force the next cycle to begin – i.e. if the natural

skip frequency is such that skip−exit is reached after the

timer expires, the drive pulses will wait for the skip−exit

threshold.

This means that during no−load, there will be a minimum

of 3 drive pulses, and the burst−cycle period will likely be

much longer than 1.25 ms. This operation helps to improve

efficiency at no−load conditions.

skip

FB

V

skip

+ V

. This skip−mode method provides an

skip(HYS)

efficient method of control during light loads.

Quiet−Skip

To further avoid acoustic noise, the circuit prevents the

burst frequency during skip mode from entering the audible

range by limiting it to a maximum of 800 Hz. This is

achieved via a timer (t ) that is activated during

quiet

In order to exit burst mode, the FB voltage must rise higher

Quiet−Skip. The start of the next burst cycle is prevented

until this timer has expired.

As the output power decreases, the switching frequency

decreases. Once it hits 25 kHz, the skip−in threshold is

reached and burst mode is entered − switching stops as soon

than 1 V. If this occurs before t

expires, the drive pulses

quiet

will resume immediately – i.e. the controller won’t wait for

the timer to expire. Figure 17 provides an example of how

Quiet−Skip works.

www.onsemi.com

19

NCP1345

MAX

Load

Fsw ≥ 25 kHz

DRV

FB

1250 ms Minimum

Fsw ≥ 25 kHz

DRV

FB

1250 ms Minimum

DRV

FB

1250 ms Minimum

DRV

FB

>1250 ms

DRV

FB

MIN

Load

Figure 17. Quiet−Skip Timing Diagram

www.onsemi.com

20

NCP1345

Figure 18. Quiet−Skip Basic Implementation

Auto−Tuning Skip Mode

The NCP1345 senses the output voltage via the ZCD pin

during the demagnetization phase. It is timed such that the

voltage is sensed right as the secondary current reaches zero,

and the ZCD voltage begins to swing down, as shown in

Figure 19. This ensures that the error from the output

rectifier voltage drop is not included. The voltage is then

scaled down by an external resistor divider. The scaling

factor should be set such that the divider output is 2 V at the

maximum nameplate output voltage.

In a typical flyback converter, skip mode is entered based

on a specific output power. With variable output converters,

this means that the output current in skip mode will be much

higher at low output voltages. For example, a 60 W adapter

that skips at 5 W will enter skip mode at 250 mA when the

output is 20 V, but at 1 A when the output is 5 V. In order to

prevent excess output ripple at low voltage, the skip

threshold is automatically tuned to provide the optimum

entry point for each output voltage.

Figure 19. Output Voltage Sensing Waveforms

www.onsemi.com

21

NCP1345

Figure 20. Auto−Tuning Skip Circuit

The minimum peak current threshold, V

, is

CS(MIN)

modulated based on the sensed output voltage such that

200 mV

V_CS(MIN)

+

(eq. 2)

V

out(MAX)

Ǹ

V

out

Where:

♦ V

is the maximum nameplate output

out(MAX)

voltage, and

♦ V is the sensed output voltage

out

Since Equation 2 is non−linear, the output voltage is

sensed at discreet intervals according to Table 7.

www.onsemi.com

22

NCP1345

Table 7. V_CSMINBINNING

Vs Threshold

V

CSMIN

(mV)

MIN

9

TYP

9.5

9

MAX

10

9.5

9

MIN

TYP

MAX

Vout

V

BIN#

To

ZCD(hi)

≥20

9.75

17

180

200

195

190

185

180

175

165

160

155

150

140

135

125

120

110

100

90

220

16to17

19

18

17

16

15

14

13

12

11

10

9

9.25

8.75

8.25

7.75

7.25

6.75

6.25

5.75

5.25

4.75

4.25

3.75

3.25

2.75

2.25

1.75

1.4

16

15

14

13

12

11

10

9

175

170

165

160

155

145

141

136

131

121

116

106

102

92

215

210

205

200

195

185

179

174

169

159

154

144

138

128

118

108

97

15to16

14to15

13to14

12to13

11to12

10to11

9to10

8to9

8.5

8

8.5

8

7.5

7

8.5

8

7.5

7

6.5

6

7.5

7

6.5

6

5.5

5

6.5

6

5.5

5

8

7to8

4.5

4

5.5

5

7

6to7

4.5

4

6

5to6

3.5

3

4.5

4

8

5

4to5

3.5

3

7

4

3to4

2.5

2

3.5

3

6

3

2to3

2.5

2

5

2

82

1to2

1.5

1.075

2.5

2.075

4

1

72

0to1

1.575

≤3.3

0

63

80

www.onsemi.com

23

NCP1345

FAULT MANAGEMENT

The NCP1345 contains three separate fault modes.

external latch input. When the NCP1345 detects a latching

fault, the driver is immediately disabled. The operation

during a latching fault is identical to that of a non−latching

fault except the controller will not attempt to restart at the

Depending on the type of fault, the device will either latch

off, restart when the fault is removed, or resume operation

after the auto−recovery timer expires.

next V

, even if the fault is removed. In order to clear

CC(on)

Latching Faults

Some faults will cause the NCP1345 to latch off. These

include the abnormal OCP (AOCP), V OVP, and the

the latch and resume normal operation, V must first be

allowed to drop below V

must be detected. This operation is shown in Figure 21.

CC

or a line removal event

CC(reset)

CC

Fault

Applied

Fault

Removed

time

V_CC

V_CC(on)

V_CC(off)

time

FDRV

I_HV

I_{start 2}

I_start(off)

time

Figure 21. Operation During Latching Fault

www.onsemi.com

24

NCP1345

Non−Latching Faults

re−enabled when V reaches V

according to the

CC

CC(on)

When the NCP1345 detects a non−latching fault

(brownout or thermal shutdown), the drivers are disabled,

initial power−on sequence, provided V

is above

HV

V

This operation is shown in Figure 22. When V

BO(start).

HV

and V falls towards V

due to the IC internal current

is reaches V

, V immediately charges to V

.

CC

CC(off)

BO(start)

CC

CC(on)

consumption. Once V reaches V

, the HV current

CC(off)

If V is already above V

when the fault is removed,

CC

CC(on)

source turns on and C

begins to charge towards V

.

the controller will start immediately as long as V is above

VCC

CC(on)

HV

When V , reaches V

, the cycle repeats until the fault

V

CC

CC(on)

BO(start).

is removed. Once the fault is removed, the NCP1345 is

Fault

Applied

Fault

Removed

time

Waits for next

V_CC(on)before

starting

V_CC

V_CC(on)

V_{CC(off )}

time

FDRV

I_HV

I_{start 2}

I_{start (off)}

time

Figure 22. Operation During Non−Latching Fault

www.onsemi.com

25

NCP1345

Auto−recovery Timer Faults

Some faults faults cause the NCP1345 auto−recovery

timer to run. If an auto−recovery fault is detected, the gate

drive is disabled and the auto−recovery timer, t

(typically 1.2 s), starts. While the auto−recovery timer is

running, the HV current source turns on and off to maintain

between V and V . Once the auto−recovery

V

cc

cc(off)

cc(on)

timer expires, the controller will attempt to start normally at

the next V provided V is above V . This

autorec

CC(on)

HV

BO(start)

operation is shown in Figure 23.

Fault

Applied

Fault

Removed

Fault

time

V_CC

V_CC(on)

V_CC(off)

Restarts

At V_CC(on)

(new burst

cycle if Fault

still present)

time

DRV

Controller

stops

Autorecovery

Timer

1.2 s

t_restart

time

Figure 23. Operation During Auto−Recovery Fault

www.onsemi.com

26

NCP1345

PROTECTION FEATURES

Brownout Protection

A timer is enabled once V

Figure 24 shows the brownout detector waveforms during

a brownout.

When a brownout is detected, the controller stops

switching and enters non−latching fault mode (see

Figure 22). The HV current source alternatively turns on and

drops below its disable

HV

threshold, V

(typically 99 V). The controller is

BO(stop)

disabled if V

doesn’t exceed V

before the

HV

BO(stop)

brownout timer, t (typically 54 ms), expires. The timer is

BO

set long enough to ignore a two cycle dropout. The timer

starts counting once V drops below V

off to maintain V between V

and V

until the

CC

CC(on)

CC(off)

.

input voltage is back above V

.

HV

BO(stop)

BO(start)

V_HV

V_{BO(start )}

V_BO(stop)

time

Fault

Cleared

Brownout

Timer

Brownout

detected

Starts

Charging

Immediately

V_CC

Restarts at

next V _CC(on)

V_CC(on)

V_CC(off)

t_{delay (start )}

time

DRV

Figure 24. Operation During Brownout

Line Removal and Input Filter Capacitor Discharge

Circuitry

The NCP1345 eliminates the need for external discharge

resistors by integrating active input filter capacitor

discharge circuitry. A novel approach is used to reconfigure

the high voltage startup circuit to discharge the input filter

capacitors upon removal of the ac line voltage. The line

removal detection circuitry is always active to ensure safety

compliance.

Safety agency standards require the input filter capacitors

to be discharged once the ac line voltage is removed. A

resistor network is the most common method to meet this

requirement. Unfortunately, the resistor network consumes

power across all operating modes and it is a major

contributor of input power losses during light−load and

no−load conditions.

www.onsemi.com

27

NCP1345

Line Removal Detection

reset timer ^t

(typically 14 ms) or the downslope

HV(up)

The line removal is detected by digitally sampling the

voltage present at the HV pin, and monitoring the magnitude

of the slope using the circuit depicted in Figure 25.

detection reset timer ^t_HV(down)(typically 1 ms).

Once the timer expires, a line removal condition is

acknowledged initiating an HV discharge cycle, and

disabling the controller. This operation is depicted in

Figure 26.

A timer, t

(typically 100 ms), starts running

line(removal)

when the slope magnitude of the input signal is below a

minimum level. The timer is reset by the upslope detection

Figure 25. Line Removal Detection Block Simplified Schematic

AC Line Unplug

V_HV

Downslope

Doesn¶t

Reset

Timer

time

Downslope

Doesn¶t

Reset

Upslope Downslope

Upslope

Resets

Timer

Upslope

Resets

Timer

Resets

Timer

Resets

Timer

Line Timer

Expires /

Discharge Begins

Timer

t_{line(removal)}

t_{line(removal )}

Figure 26. Line Removal Detection Timing

www.onsemi.com

28

NCP1345

Capacitor Discharge

It is important to note that the HV pin cannot be

connected to any dc voltage due to this feature, i.e.

directly to the bulk capacitor.

During the discharge phase, the discharge current source

_HV(disch)(typically 2 mA) is activated. The current source

I

I_HV(disch)remains active and constant until V_HVdrops to

_HVdisch(MIN)(typically 30 V). At this point, it begins to pinch

In the event that line voltage is reapplied during a

discharge phase, the circuit will simply continue to

discharge until the line zero crossing occurs, at which point

V_HVwill drop to V_HV(disch)and a new start−up cycle will

commence.

V

off until the discharge phase completes when V_HVdrops to

V_HV(disch)(typically 18 V). Once the discharge phase

completes, a new start−up cycle commences as normal. This

circuit is shown in Figure 27, while the operation is depicted

in Figure 28.

Figure 27. Discharge Block Simplified Schematic

www.onsemi.com

29

NCP1345

HV Capacitor

Discharge

V_HV

AC Line Unplug

Discharge Rate

Decreases

Discharge

Complete

V_{HVdischarge (MIN)}

V_{HV(discharge )}

time

Upslope

Resets

Timer

Downslope

Resets

Timer

Upslope

Resets

Timer

Line

Timer

Expires

Timer

t_{line(removal )}

DRV

Discharge

Current

Pinches Off

time

HV Discharge

Device is stopped

HV Discharge

Current

I_{HV(discharge )}

Figure 28. HV Discharge Timing

Dedicated Fault Input

The NCP1345 includes a dedicated fault input accessible

via the Fault pin. The controller can be latched by pulling up

from the auxiliary winding voltage. The controller is latched

once V exceeds V

Once the controller is latched, it follows the behavior of

a latching fault according to Figure 21 and is only reset if

.

Fault(OVP)

Fault

the pin above the upper fault threshold, V

Fault(OVP)

(typically 3.0 V). The controller is disabled if the Fault pin

voltage is pulled below the lower fault threshold,

V

is reduced to V

, or X2 discharge is activated. In

CC

CC(reset)

the typical application these conditions occur only if the ac

voltage is removed from the system.

V

(typically 0.4 V). The lower threshold is

Fault(OTP_in)

normally used for detecting an overtemperature fault. The

controller operates normally while the Fault pin voltage is

maintained within the upper and lower fault thresholds.

Figure 29 shows the architecture of the Fault input.

The Fault input signal is filtered to prevent noise from

triggering the fault detectors. Upper and lower fault detector

OTP

The lower fault threshold is intended to be used to detect

an overtemperature fault using an NTC thermistor. A pull up

current source, I

voltage drop across the thermistor. The resistance of the

NTC thermistor decreases at higher temperatures resulting

in a lower voltage across the thermistor. The controller

detects a fault once the thermistor voltage drops below

(typically 45.5 mA), generates a

Fault(OTP)

blanking delays, t

and t , are both

delay(OTP)

delay(OVP)

typically 30 ms. A fault is detected if the fault condition is

asserted for a period longer than the blanking delay.

V

.

Fault(OTP_in)

The controller bias current is reduced during power up by

OVP

disabling most of the circuit blocks including I

.

An active clamp prevents the Fault pin voltage from

reaching the upper latch threshold if the pin is open. To reach

the upper threshold, the external pull−up current has to be

higher than the pull−down capability of the clamp (set by

Fault(OTP)

This current source is enabled once V reaches V

. A

CC

CC(on)

filter capacitor is typically connected between the Fault and

GND pins. This will result in a delay before V reaches

Fault

its steady state value once I

is enabled. Therefore,

R

at V ), i.e., approximately 1 mA.

Fault(clamp)

Fault(OTP)

Fault(clamp)

the lower fault comparator (i.e. overtemperature detection)

is ignored during soft−start.

The upper fault threshold is intended to be used for an

overvoltage fault using a zener diode and a resistor in series

www.onsemi.com

30

NCP1345

Options Bxxxx and Dxxxx E latch−off the controller after

once the fault is removed such that V

increases above

Fault

an overtemperature fault is detected according to Figure 21.

V , the auto−recovery timer expires, and V

Fault(OTP_out) CC

In Options Axxxx and Cxxxx, the controller is re−enabled

reaches V

as shown in Figure 23.

CC(on)

Figure 29. Fault Pin Internal Schematic

Overpower Protection

voltage across the Ropp resistor determines the maximum

possible OPP amount that will be added. The typical values

The peak value of the AC line input voltage is sensed by

the HV Pin, and internally scaled down to a smaller level for

OPP. The OPP signal is then added to each of the

comparators − ILIM1, CS(MIN), and Iout(limit).

The ZCD pin has 3 functions. The primary function is to

detect the demagnetization of the transformer. The second

function is to set the OPP gain via external resistor Ropp.

During start−up, a 20 mA current is sourced from the ZCD

pin to generate a voltage across the Ropp resistor. The

of OPP vs. R

Figure 30.

for given input voltages are shown in

OPP

The third function is to sense the output voltage during the

drive off−time, and route it to the CS(MIN) comparator.

During operation, an internal 1k resistor is connected in

parallel with the Ropp resistor to create a 2:1 ratio for output

voltage sensing. A current source provides error correction

over the output voltage range. This is shown in Figure 31.

100

90

80

70

60

50

40

30

20

10

0

50

100

150

200

250

300

OPP Programming Resistor (kW)

OPP 90V

OPP 115V

OPP 230V

OPP 265V

Figure 30. OPP Voltage vs. R_OPPfor Different Input Voltages

www.onsemi.com

31

NCP1345

Figure 31. OPP Programming Block

Overload Protection

• The controller latches off or

The overload timer integrates the duration of the overload

fault. That is, the timer count increases while the fault is

present and reduces its count once it is removed. The

overload timer duration, t

the overload timer expires, the controller detects an overload

condition does one of the following:

• Enters a safe, low duty−ratio auto−recovery mode.

Figure 32 shows the overload circuit schematic, while

Figure 33 and Figure 34 show operating waveforms for

latched and auto−recovery overload conditions.

, is typically 160 ms. When

OVLD

Figure 32. Overload Circuitry

www.onsemi.com

32

NCP1345

Latch

Event

Fault

Latch

time

V_CC

V_CC(on)

V_CC(off)

time

DRV

I_HV

I_start2

I_HV(off)

time

Figure 33. Latched Overload Operation

www.onsemi.com

33

NCP1345

Fault

disappears

Overcurrent

applied

Output Load

Max Load

time

Fault Flag

Fault

timer

starts

V_CC

V_CC(on)

V_CC(off)

Restarts

At V_CC(on)

(new burst

cycle if Fault

still present)

time

DRV

Controller

stops

Fault timer

160 ms

time

t_OVLD

t_restart

t_delay(start)

Figure 34. Auto−Recovery Overload Operation

Output Current Limit

current to 8 A after 5 seconds at all times, including during

a single fault condition.

In order to maintain an output current limit of 8 A at low

output voltages, the NCP1345 incorporates a special

auto−tuning output current limit circuit.

Some regulations such as that for a Limited Power Source

(LPS) require the output current and power to be limited

during all conditions. In particular, LPS requires that the

output power must be limited to 100 W, and the output

www.onsemi.com

34

NCP1345

Figure 35. Typical Flyback Current Waveforms

Figure 36. Detailed View if Demagnetization Starting Point

www.onsemi.com

35

NCP1345

Figure 37. Detailed View if Demagnetization Ending Point

Figure 38. Output Current Limit Schematic

When measuring the demagnetization time, it is important

implementation of the output current limiting circuit. When

the OVERLOAD signal is high, the fault timer will run.

For the typical flyback converter waveforms shown in

Figure 35, the output current is given by the following

equation:

to accurately sense the beginning and end of the

demagnetization phase. The beginning of the

demagnetization phase is not when the DRV signal goes low,

but rather when the primary switch turns off. Thus, it is best

to detect the demagnetization starting point by monitoring

N

_psI_p,pkt_demag

I_out

+

(eq. 3)

the CS Pin, and waiting for it to fall below the V

CS(MIN)

2

T_sw

threshold. Figure 35 Typical Flyback Current Waveforms

shows the beginning and ending point of the

demagnetization phase, while Figure 36 shows a detailed

view of the demagnetization starting point, including both

internal and external propagation delays.

Where:

♦ t

is the demagnetization time

demag

♦ N is the primary to secondary turns ratio:

ps

N_p

N_s

N_ps

+

(eq. 4)

(eq. 5)

(eq. 6)

Figure 37 shows a detailed view of the demagnetization

ending point. The ending point is when the ZCD Pin voltage

♦ I

is the primary peak inductor current

p,pk

suddenly drops the amount V

, typically 150 mV.

demag(det)

V_CS

R_sense

I_p,pk

+

This also corresponds to the measurement point for

detecting the output voltage. As shown in Figure 37,

Due to the internal divider ratio,

t

represents an error added to the measured

demag(det)

V_FB

4

demagnetization time. The amount of this error is directly

proportional to . Figure 38 depicts the

V_CS

+

V

demag(det)

www.onsemi.com

36

NCP1345

In order to maintain a constant output current limit, the

Additionally, the maximum on−time, t

(32 ms

on(MAX)

controller creates a second feedback voltage,

typically), prevents the MOSFET from staying on

permanently if the CS Pin is shorted to GND.

T_sw

t_demag

V

_{FB_Iout}+ V_REF

(eq. 7)

Output Short Circuit Protection

and the overload timer must run when

During an output short−circuit, there is not enough

voltage across the secondary winding to demagnetize the

core. Due to the valley timeout feature of the controller, the

flux level will quickly walk up until the core saturates. This

can cause excessive stress on the primary MOSFET and

secondary diode. This is not a problem for the NCP1345,

however, because the valley timeout timer is disabled while

the ZCD Pin voltage is above the arming threshold. Since the

leakage energy is high enough to arm the ZCD trigger, the

timeout timer is disabled and the next drive pulse is delayed

until demagnetization occurs.

V

_CS+ V_{FB_Iout}

(eq. 8)

As V is not readily available, the controller compares

CS

the two feedback voltages and the overload timer runs when:

V

_FBw 4V_{FB_Iout}

(eq. 9)

Thus, by combining equations (6), (8), (10), and (11) we

obtain the output current limit equation:

V_REFN_ps

2R_sense

I_{out_lim}

+

(eq. 10)

In order to compensate for error due to propagation

V_CCOvervoltage Protection

delays, the OPP signal is subtracted from V

, such that

FB_Iout

An additional comparator on the V pin monitors the

CC

T_sw

t_demag

V

_{FB_Iout}+ V_REF

* V_OPP

V

CC

voltage. If V exceeds V

, the gate drive is

CC

CC(OVP)

(eq. 11)

disabled and the NCP1345 follows the operation of a

latching fault (see Figure 21).

Abnormal Overcurrent Protection (AOCP)

Under some severe fault conditions, like a winding

short−circuit, the switch current can increase very rapidly

during the on−time. The current sense signal significantly

Output Overvoltage Protection

In addition to auto−tuning skip mode, the output voltage

sensing includes an overvoltage protection circuit. In the

exceeds V

, but because the current sense signal is

ILIM1

event that the sensed output voltage exceeds V

out(OVP)

blanked by the LEB circuit during the switch turn−on, the

power switch current can become huge and cause severe

system damage.

The NCP1345 protects against this fault by adding an

additional comparator for Abnormal Overcurrent Fault

detection. The current sense signal is blanked with a shorter

(typically 2.4 V) for 3 consecutive cycles, the controller is

immediately latched off. This operation is depicted in

Figure 39.

Thermal Shutdown

An internal thermal shutdown circuit monitors the

junction temperature of the controller. The controller is

disabled if the junction temperature exceeds the thermal

LEB duration, t

, typically 125 ns, before applying it to

LEB2

the Abnormal Overcurrent Fault Comparator. The voltage

threshold of the comparator, V , typically 1.2 V, is set

shutdown threshold, T

thermal shutdown fault is detected, the controller enters a

(typically 140_C). When a

SHDN

ILIM2

50 % higher than V

, to avoid interference with normal

ILIM1

non−latching fault mode as depicted in Figure 22. The

operation. Four consecutive Abnormal Overcurrent faults

cause the controller to enter latch mode. The count to 4

provides noise immunity during surge testing. The counter

is reset each time a DRV pulse occurs without activating the

Fault Overcurrent Comparator.

controller restarts at the next V

temperature drops below below T

once the junction

by the thermal

CC(on)

SHDN

shutdown hysteresis, T

The thermal shutdown is also cleared if V drops below

, typically 40_C.

SHDN(HYS)

CC

V

, or a line removal fault is detected. A new power

CC(reset)

Current Sense Pin Failure Protection

A 1mA (typically) pull−up current source, I , pulls up the

CS pin to disable the controller if the pin is left open.

up sequence commences at the next V

faults are removed.

once all the

CC(on)

CS

Figure 39. Detailed View of Demagnetization Ending Point

www.onsemi.com

37

NCP1345

TYPICAL CHARACTERISTICS

18

17

16

15

14

13

12

11

10

9

4.7

4.6

4.5

4.4

4.3

4.2

4.1

4

V

CC(on)

V

CC(off)

3.9

8

3.8

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T , Junction Temperature (°C)

J

T , Junction Temperature (°C)

J

Figure 40. V_CC(on/off)vs. Temperature

Figure 41. I_start2vs. Temperature

350

300

250

200

150

100

50

1.41

1.4

I

CCL2

1.39

1.38

1.37

1.36

1.35

1.34

1.33

CCL1

0

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T , Junction Temperature (°C)

J

T , Junction Temperature (°C)

J

Figure 42. I_CCLvs. Temperature

Figure 43. I_CCL3vs. Temperature

21

20.5

20

1000

900

800

700

600

500

400

300

200

100

0

I

= 5 mA

CCH

19.5

19

18.5

18

I

= 0.5 mA

CCH

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T , Junction Temperature (°C)

J

T , Junction Temperature (°C)

J

Figure 44. V_DOvs. Temperature

Figure 45. I_CC(disch)vs. Temperature

www.onsemi.com

38

NCP1345

TYPICAL CHARACTERISTICS (CONTINUED)

2.12

2.11

2.1

100

90

80

70

60

50

40

30

20

10

0

V

ZCD(arm)

2.09

2.08

2.07

2.06

2.05

2.04

2.03

2.02

V

ZCD(trig)

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T , Junction Temperature (°C)

J

T , Junction Temperature (°C)

J

Figure 46. I_HV(disch)vs. Temperature

Figure 47. V_{ZCD(arm/trig)}vs. Temperature

810

808

806

804

802

800

798

210

190

170

150

130

110

90

V

= 10.5 V

ZCD

V

ZCD

= 1.25 V

70

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T , Junction Temperature (°C)

J

T , Junction Temperature (°C)

J

Figure 48. V_ILIM1vs. Temperature

Figure 49. V_CS(min)vs. Temperature

3

2.5

2

1.212

1.21

60% Duty − Q00

1.208

1.206

1.204

1.202

1.2

60% Duty − Q01/Q02

95% Duty − Q00

1.5

1

95% Duty − Q01/Q02

1.198

1.196

1.194

0.5

0

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T , Junction Temperature (°C)

J

T , Junction Temperature (°C)

J

Figure 50. V_ILIM2vs. Temperature

Figure 51. V_FB(OVLD)vs. Temperature

www.onsemi.com

39

NCP1345

TYPICAL CHARACTERISTICS (CONTINUED)

11.916

11.915

11.914

11.913

11.912

11.911

11.91

3.32

3.3

3.28

3.26

3.24

3.22

3.2

11.909

11.908

11.907

11.906

3.18

3.16

3.14

−40 −20

0

20

40

60

80 100 120

−40 −20

0

J

20

40

60

80 100 120

T , Junction Temperature (°C)

J

T , Junction Temperature (°C)

Figure 52. V_Fault(OVP)vs. Temperature

Figure 53. V_out(OVP)vs. Temperature

36.8

36.75

36.7

934

932

930

928

926

924

922

920

918

916

914

36.65

36.6

36.55

36.5

36.45

36.4

36.35

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T , Junction Temperature (°C)

J

T , Junction Temperature (°C)

J

Figure 54. V_CC(OVP)vs. Temperature

Figure 55. V_{FaultOTP(out)}vs. Temperature

3895

3890

3885

3880

3875

3870

3865

3860

3855

3850

8E+36

7E+36

6E+36

5E+36

4E+36

3E+36

2E+36

1E+36

0

−1E+36

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T , Junction Temperature (°C)

J

T , Junction Temperature (°C)

J

Figure 56. F_MINvs. Temperature

Figure 57. F_jittervs. Temperature

www.onsemi.com

40

NCP1345

TYPICAL CHARACTERISTICS (CONTINUED)

250

200

150

100

50

116

114

Q00

Start

112

110

108

106

104

102

100

98

Q01/Q02

Stop

20

0

96

−40 −20

0

20

40

60

80 100 120

0

J

40

60

80 100 120

T , Junction Temperature (°C)

J

Figure 58. V_jittervs. Temperature

Figure 59. V_BOvs. Temperature

404

403

402

401

400

399

398

−40 −20

0

20

40

60

80 100 120

T , Junction Temperature (°C)

J

Figure 60. V_OTPvs. Temperature

www.onsemi.com

41

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−9 NB

CASE 751BP

ISSUE A

9

1

DATE 21 NOV 2011

SCALE 1:1

2X

NOTES:

0.10

C A-B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’

AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15mm

PER SIDE. DIMENSIONS D AND E ARE DE-

TERMINED AT DATUM F.

D

H

A

2X

0.20

C

4 TIPS

0.10 C A-B

F

10

6

E

1

5. DIMENSIONS A AND B ARE TO BE DETERM-

INED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

5

L2

A3

L

SEATING

PLANE

C

0.20

C

9X b

DETAIL A

B

5 TIPS

M

MILLIMETERS

0.25

C A-B D

DIM MIN

MAX

1.75

0.25

0.51

5.00

4.00

TOP VIEW

A

A1

A3

b

D

E

1.25

0.10

0.17

0.31

4.80

3.80

9X

h

X 45

_

0.10

C

0.10

C

M

e

1.00 BSC

H

h

5.80

0.37 REF

6.20

A

L

L2

M

0.40

0

1.27

0.25 BSC

DETAIL A

e

SIDE VIEW

A1

SEATING

PLANE

C

8

_

END VIEW

GENERIC

MARKING DIAGRAM*

RECOMMENDED

SOLDERING FOOTPRINT*

9

1.00

PITCH

9X

0.58

XXXXX

ALYWX

G

1

XXXXX = Specific Device Code

6.50

A

L

= Assembly Location

= Wafer Lot

Y

W

G

= Year

= Work Week

= Pb−Free Package

1

9X

1.18

DIMENSION: MILLIMETERS

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON52301E

SOIC−9 NB

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	NCP1345Q00D1R2G
厂家：	ONSEMI
描述：	Highly integrated quasi-resonant flyback controller for off-line USB-PD and USB Type-C power converters. 光电二极管
文件：	总43页 (文件大小：1034K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP1345Q00D1R2G [ONSEMI]

相关型号：

NCP1345Q01D1R2G

NCP1345Q02D1R2G

NCP134AMX080TCG

NCP134AMX090TCG

NCP134AMX100TCG

NCP134AMX105TCG

NCP134AMX110TCG

NCP134AMX120TCG

NCP134AMX135TCG

NCP134AMX150TCG

NCP134AMX180TCG

NCP134_16