NCP1361BABAYSNT1G [ONSEMI]
低功耗离线恒定电流 PWM 电流模式控制器;
| 型号： | NCP1361BABAYSNT1G |
| 厂家： | 
ONSEMI |
| 描述： | 低功耗离线恒定电流 PWM 电流模式控制器 控制器 |
| 文件： | 总29页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MARKING
DIAGRAMS
Low Power Offline Constant
Current PWM Current-Mode
Controller with/without
High Voltage Startup
Current Source
8
SOIC−7
CASE 751U
XXXXX
ALYWX
G
1
TSOP−6
CASE 318G
xxxAYWG
G
NCP1361, NCP1366
1
1
The NCP1361/66 offers a new solution targeting output power
levels from a few watts up to 20 W in a universal−mains flyback
application. Due to a novel method this new controller offers a
primary−side constant current control, saving secondary−side
components to perform current regulation.
The NCP1361/66 operates in valley−lockout quasi−resonant peak
current mode control mode at nominal load to provide high efficiency.
When the secondary−side power starts diminishing, the switching
frequency naturally increases until a voltage−controlled oscillator
(VCO) takes the lead, synchronizing the MOSFET turn−on in a
drain−source voltage valley. The frequency is thus reduced by
stepping into successive valleys until the number 4 is reached. Beyond
this point, the frequency is linearly decreased in valley−switching
mode until a minimum is hit. Valley lockout during the first four
drain−source valleys prevents erratic discrete jumps and provides
good efficiency in lighter load situations.
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 25 of
this data sheet.
Features
•
10% Current Regulation
• 560 V Startup Current Source
• No Frequency Clamp, 80 or 110 kHz Maximum Switching
Frequency Options
• Quasi−Resonant Operation with Valley Switching Operation
• Fixed Peak Current & Deep Frequency Foldback @ Light Load
Operation
• External Constant Voltage Feedback Adjustment
• Cycle by Cycle Peak Current Limit
• Built−In Soft−Start
• Over & Under Output Voltage Protection
• Wide Operation V Range (up to 28 V)
CC
• Low Start−up Current (2.5 mA typ.) with NCP1361
• Clamped Gate−drive Output for MOSFET
• CS & Vs/ZCD pin Short and Open Protection
• Internal Temperature Shutdown
• Less than 30 mW No−Load Performance at High Line with
NCP1366 Version
• These are Pb−Free Devices
Typical Applications
• Low power ac−dc Adapters for Chargers
• Ac−dc USB chargers for Cell Phones, Tablets and Cameras
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
August, 2022 − Rev. 4
NCP1361/D
NCP1361, NCP1366
NCP1361
NCP1366
V /ZCD
1
HV
8
S
V
V /ZCD
1
2
CC
6
5
S
FB
2
3
4
FB
CS
GND
DRV
CS
6
5
V
CC
3
4
DRV
GND
(Top View)
(Top View)
Figure 1. Pin Connections
2
0
Ac
Ac
Vout
Prim
3
5
0
Sec
Aux
4
1
NCP1366
5
4
3
2
1
GND
VCC
DRV
CS
6
FB
8
HV Vs/ZCD
0
Figure 2. NCP1366 Typical Application Circuit
2
0
Ac
Ac
Vout
Prim
3
5
0
Sec
Aux
NCP1361
CS
4
5
6
3
2
1
4
1
DRV
GND
FB
Vs/ZCD VCC
0
Figure 3. NCP1361 Typical Application Circuit
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2
NCP1361, NCP1366
IHV
NCP1366 Only
HV
UVLO
Vdd
Vcc
POReset
VCC and Logic
Management of
double hiccup
VCC(Reset)
VCC(OVP)
DbleHiccup
POReset
EN_UVP
Vcc(clamp)
Rlim
Double_Hiccup_ends
Reset
Soft Start
SS
Blanking
Latch
QR multi−mode
Valley lockout &
Valley Switching &
VCO management
Vs /
ZCD
Zero Crossing &
Signal Sampling
Sampled Vout
Vcc
SS
Control Law
FBint
UVLO
CC
&
FB_CC
Control
Primary Peak
Current Control
Vref_CC
FB_CV
Clamp
S
R
VCC(OVP)
DRV
GND
OVP_Cmp
Q
4 clk
Counter
OVP
VDD
SCP
126% Vref_CV2
RFB
Latch
FB
S
R
UVP_Cmp
VCC(Reset)
Q
POReset
VUVP
Peak current
Freeze
S
UVP
Q
VDD
EN_UVP
R
DbleHiccup
ICS
1/Kcomp
FB Reset
ICS_EN
LEB1
CS
Note:
Max_Ipk reset
OCP
OVP: Over Voltage Protection
UVP: Under Voltage Protection
OCP: Over Current Protection
SCP: Short Circuit Protection
CBC: CaBle Compensation
tLEB1 > tLEB2
Count
OCP
Timer
VILIM
Reset Timer
POReset
DbleHiccup
R
S
Reset
Counter
Q
LEB2
4 clk
Counter
SCP
VCS(Stop)
CS pin Fault
CS pin Open (VCS > 2 V)
& Short (VCS < 50 mV)
detection is activated at
each startup
ICS_EN
Figure 4. Functional Block Diagram: A Version
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3
NCP1361, NCP1366
PIN FUNCTION DESCRIPTION
Pin out
Pin out
NCP1366
NCP1361
Name
Function
1
6
V /ZCD
s
Connected to the auxiliary winding; this pin senses the voltage output for the primary
regulation and detects the core reset event for the Quasi−Resonant mode of operation.
2
3
4
5
6
7
8
5
4
3
2
1
−
−
FB
CS
This pin connects to an optocoupler collector and adjusts the peak current setpoint.
This pin monitors the primary peak current.
DRV
GND
Controller switch driver.
Ground reference.
V
CC
This pin is connected to an external auxiliary voltage and supplies the controller.
Not Connected for creepage distance between high and low Voltage pins
NC
HV
Connected the high−voltage rail, this pin injects a constant current into the V capaci-
CC
tor for starting−up the power supply.
MAXIMUM RATINGS
Symbol
Rating
Value
−0.3 to 28
+0.4
Unit
V
V
Maximum Power Supply voltage, VCC pin, continuous voltage
CC(MAX)
DV /Dt
Maximum slew rate on V pin during startup phase
V/ms
CC
CC
V
I
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 1)
V
mA
DRV(MAX)
DRV(MAX)
DRV
−300, +500
V
I
Maximum voltage on low power pins (except pins DRV and VCC)
Current range for low power pins (except pins DRV and VCC)
−0.3, 5.5
−2, +5
V
mA
MAX
MAX
V
High Voltage pin voltage
−0.3 to 560
V
°C/W
°C
°C
°C
kV
V
HV
R
Thermal Resistance Junction−to−Air
200
150
q
J−A
T
Maximum Junction Temperature
J(MAX)
Operating Temperature Range
−40 to +125
−60 to +150
2
Storage Temperature Range
Human Body Model ESD Capability per JEDEC JESD22−A114F
Machine Model ESD Capability (All pins except DRV) per JEDEC JESD22−A115C
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
200
500
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
is the DRV clamp voltage V
when V is higher than V
. V
is V otherwise
DRV
DRV(high)
CC
DRV(high) DRV CC
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
www.onsemi.com
4
NCP1361, NCP1366
ELECTRICAL CHARACTERISTICS: (V = 12 V, C
= 1 nF, For typical values T = 25°C, for min/max values T = −40°C to
CC
DRV
J
J
+125°C, Max T = 150°C, unless otherwise noted)
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
HIGH VOLTAGE STARTUP SECTION (NCP1366 only)
Startup current sourced by V
pin
V
= 100 V
I
HV
70
100
150
mA
mA
CC
HV
Leakage current at HV
V
HV
= 400 V, all options except
I
HV_LKG
NCP1366AABAY and NCP1366BABAY
All other options
−
−
0.1
0.1
1.0
1.3
Minimum Start−up HV voltage
I
= 95% of I @V = 100 V, V
=
V
HV(min)
−
22
25
V
HV
HV
HV
CC
V
CC(on)
− 0.2 V
SUPPLY SECTION AND V MANAGEMENT
CC
V
level at which driving
V
increasing
decreasing
V
16
6.0
−
18
6.5
5.6
20
7.0
−
V
V
V
CC
CC
CC
CC(on)
pulses are authorized
V
CC
level at which driving
V
V
CC(off)
pulses are stopped
Internal Latch / Logic Reset
Level
V
CC(reset)
V
CC
clamp level
V
clamp level (A & C
Activated after Latch protection @ I
=
V
−
−
4.2
−
−
V
CC
CC
CC(Clamp)
version)
100 mA
Minimal current into V pin
CC
that keeps the controller
Latched (NCP1366, A & C fault
mode version)
I
20
mA
CC(Clamp)
Minimal current into V pin
CC
that keeps the controller
Latched (NCP1361, A & C fault
mode version)
I
−
−
−
7
6
−
mA
kW
CC(Clamp)
Current−limit resistor in series
with the latch SCR
R
lim
Over Voltage Protection
Over Voltage threshold
V
24
−
26
28
V
CC(OVP)
Start−up supply current,
V
CC
< V
& V increasing from
I
2.5
5.0
mA
CC(on)
CC
CC1
controller disabled or latched
(Only valid with NCP1361 )
0 V
Internal IC consumption,
steady state
F
= 65 kHz, C
= 1 nF
I
I
I
−
−
1.7
0.8
2.5
1.2
mA
mA
mA
sw
DRV
CC2
CC3
CC4
Internal IC consumption,
frequency foldback mode
VCO mode, Fsw = 1 kHz, C
= 1 nF
DRV
Internal IC consumption when
STBY mode is activated
VCO mode, Fsw = f
,
VCO(min)
= 1 nF
V
Comp
= GND, C
DRV
f
f
= 200 Hz
= 600 Hz
= 1.2 kHz
−
−
−
470
500
530
520
TBD*
TBD*
VCO(min)
VCO(min)
f
VCO(min)
CURRENT COMPARATOR
Current Sense Voltage
Threshold
V
= V
, V increasing
V
0.76
250
0.80
300
0.84
360
V
Comp
Comp(max) CS
ILIM
Cycle by Cycle Leading Edge
Blanking Duration
options NCP1366AABAY,
t
ns
LEB1
NCP1366BABAY, NCP1361AABAY,
NCP1361BABAY and NCP1361EABAY
All other options
240
300
360
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions
4. Guaranteed by Design.
* Characterization upon request
www.onsemi.com
5
NCP1361, NCP1366
ELECTRICAL CHARACTERISTICS: (V = 12 V, C
= 1 nF, For typical values T = 25°C, for min/max values T = −40°C to
CC
DRV
J
J
+125°C, Max T = 150°C, unless otherwise noted)
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
CURRENT COMPARATOR
Cycle by Cycle Current Sense
Propagation Delay
V
CS
> (V
+ 100 mV) to DRV turn−off
t
ILIM
−
50
70
100
90
ns
ILIM
Timer Delay Before Latching in
Overload Condition
When CS pin ꢀ
V
ILIM
T
OCP
50
ms
(Note 3)
Threshold for Immediate Fault
Protection Activation
V
1.08
−
1.2
1.32
−
V
CS(stop)
Leading Edge Blanking
t
120
ns
LEB2
Duration for V
CS(stop)
Maximum peak current level at
which VCO takes over or
frozen peak current
V
Comp
< 1.9 V, V increasing
V
CS(VCO)
mV
CS
option X (~15%V
)
)
−
−
−
120
160
200
−
−
−
ILIM
option Y (~20%V
option Z (~25%V
ILIM
)
ILIM
REGULATION BLOCK
Internal Voltage reference for
Constant Current regulation
T = 25°C
0.98
0.97
1.00
1.00
1.02
1.03
V
J
V
ref_CC
−40°C < T < 125°C
J
Pullup Resistor
Valley Thresholds
R
−
20
−
kW
FB
V
st
nd
Transition from 1 to 2 valley
V
V
V
V
V
V
V
V
decreasing
decreasing
decreasing
decreasing
increasing
increasing
increasing
increasing
V
H2D
V
H3D
V
H4D
−
−
−
−
−
−
−
−
2.50
2.30
2.10
1.90
2.50
2.70
2.90
3.10
−
−
−
−
−
−
−
−
Comp
Comp
Comp
Comp
nd
rd
Transition from 2 to 3 valley
rd
th
Transition from 3 to 4 valley
th
Transition from 4 valley to VCO
V
HVCOD
V
HVCOI
th
Transition from VCO to 4 valley
Comp
Comp
Comp
Comp
th
rd
Transition from 4 to 3 valley
V
H4I
V
H3I
V
H2I
rd
nd
Transition from 3 to 2 valley
nd
st
Transition from 2 to 1 valley
Minimal difference between any
two valleys
V
Comp
increasing or V
decreasing
DV
H
176
−
2
1
−
−
−
mV
ms
Comp
Internal Dead Time generation
for VCO mode
Entering in VCO when V
decreasing and crosses V
is
T
−
Comp
DT(start)
DT(ends)
HVCOD
Internal Dead Time generation
for VCO mode
Leaving VCO mode when V
increasing and crosses V
is
T
−
ms
Comp
HVCOI
Internal Dead Time generation
for VCO mode
When in VCO mode
T
DT
ms
V
Comp
V
Comp
V
Comp
= 1.8 V
= 1.3 V
= 0.8 V
−
−
−
−
−
−
6
25
220
5000
1667
833
−
−
−
−
−
−
V
V
V
< 0.4 V − 200 Hz option (Note 4)
< 0.4 V − 600 Hz option (Note 4)
< 0.4 V − 1.2 kHz option (Note 4)
Comp
Comp
Comp
Minimum Operating Frequency
in VCO Mode
V
Comp
= GND
f
VCO(MIN)
150
450
0.9
200
600
1.2
250
750
1.5
Hz
Hz
kHz
Maximum Operating Frequency
f
MAX
−
No
Clamp
80
−
N/A
Option
Option
75
103
85
117
kHz
kHz
110
DEMAGNETIZATION INPUT − ZERO VOLTAGE DETECTION CIRCUIT and VOLTAGE SENSE
V
ZCD
V
ZCD
threshold voltage
Hysteresis
V
decreasing
increasing
V
ZCD(TH)
25
15
45
30
65
45
mV
mV
ZCD
V
V
ZCD(HYS)
ZCD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions
4. Guaranteed by Design.
* Characterization upon request
www.onsemi.com
6
NCP1361, NCP1366
ELECTRICAL CHARACTERISTICS: (V = 12 V, C
= 1 nF, For typical values T = 25°C, for min/max values T = −40°C to
CC
DRV
J
J
+125°C, Max T = 150°C, unless otherwise noted)
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
DEMAGNETIZATION INPUT − ZERO VOLTAGE DETECTION CIRCUIT and VOLTAGE SENSE
Threshold voltage for output
short circuit or aux. winding
short circuit detection
After t
if V
Ù Latched
< V
BLANK_ZCD
ZCD ZCD(short)
V
30
−
50
−
70
170
−
mV
ns
ms
ZCD(short)
Propagation Delay from valley
detection to DRV high
V
ZCD
decreasing from 4 V to 0 V
t
DEM
Delay after on−time that the
(Note 4)
t
−
0.7
1.5
short_ZCD
V /ZCD is still pulled to ground
s
Blanking delay after on−time
t
1.2
1.8
ms
blank_ZCD
(V /ZCD pin is disconnected
s
from the internal circuitry)
Timeout after last
demagnetization transition
ms
Timeout while in Soft−start
Timeout after soft−start complete
t
36
4.5
44
5.5
52
6.5
outSS
t
out
Input leakage current
V
CC
> V = 4 V, DRV is low
V
I
ZCD
−
−
0.1
mA
CC(on) ZCD
DRIVE OUTPUT − GATE DRIVE
Drive resistance
DRV Sink
W
R
SNK
R
SRC
−
−
7
12
−
−
DRV Source
Rise time
C
= 1 nF, from 10% to 90%
= 1 nF, from 90% to 10%
t
−
−
45
30
−
80
60
−
ns
ns
V
DRV
r
Fall time
C
t
f
DRV
DRV Low voltage
V
= V
+ 0.2 V,
V
6.0
CC
CC(off)
DRV(low)
C
= 220 pF, R
= 33 kW
DRV
DRV
DRV High voltage
V
= V
−0.2 V C = 220 pF,
DRV
V
−
3
−
4
13.0
5
V
CC
CC(OVP)
,
DRV(high)
R
= 33 kW
DRV
SOFT START
Internal Fixed Soft Start
Duration
Current Sense peak current rising from
0.2 V to 0.8 V
t
SS
ms
FAULT PROTECTION
Thermal Shutdown
Device switching (F ~ 65 kHz)
T
−
−
150
40
−
−
°C
°C
sw
SHTDN
(Note 4)
Thermal Shutdown Hysteresis
Device switching (F ~ 65 kHz)
T
SHTDN(HYS)
sw
(Note 4)
Number of Drive cycle before
latch confirmation
V
= V
> V
,
Comp
Comp(max)
CS(stop)
V
CS
T
−
4
−
−
latch_count
Or Internal sampled V > V
out
OVP
Fault level detection for OVP Ù
Latched or Double Hiccup
autorecovery (depends on fault
version)
Internal sampled V increasing
V
OVP
2.95
3.4
3.15
3.6
3.35
3.8
V
out
V
OVP
= V
Version E
+26%
ref_CV2
Fault level detection for UVP Ù
autorecovery (depends on fault
version) (UVP detection is
Internal sampled V decreasing
Fault Mode Option A, B & C
Fault Mode Option Version E
V
UVP
V
out
Latched or Double Hiccup
1.4
0.70
1.5
0.75
1.6
0.80
disabled during T
)
EN_UVP
Blanking time for UVP
detection
Starting at the beginning of the Soft
start
T
−
37
−
ms
EN_UVP
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions
4. Guaranteed by Design.
* Characterization upon request
www.onsemi.com
7
NCP1361, NCP1366
ELECTRICAL CHARACTERISTICS: (V = 12 V, C
= 1 nF, For typical values T = 25°C, for min/max values T = −40°C to
CC
DRV
J
J
+125°C, Max T = 150°C, unless otherwise noted)
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
FAULT PROTECTION
Pull−up Current Source on CS
pin for Open or Short circuit
detection
When V > V
I
CS
−
55
−
mA
CS
CS_min
CS pin Open detection
CS pin Short detection
CS pin Short detection timer
CS pin open
(Note 4)
V
T
0.8
−
−
50
3
−
70
−
V
CS(open)
V
mV
ms
CS_min
−
CS_short
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions
4. Guaranteed by Design.
* Characterization upon request
www.onsemi.com
8
NCP1361, NCP1366
FAULT MODE STATES TABLE (WHATEVER THE VERSION)
Timer
Protection
Event
Next Device Status
Release to Normal Operation Mode
Overcurrent
OCP timer
Immediate
Double Hiccup
•
•
Resume to normal operation: if 4 pulses from FB
Reset & then Reset timer
V
CS
> V
ILIM
Resume operation after Double Hiccup
Winding short
> V
4 consecutive pulses with
V
is decreasing to V
and waiting for unplug
CC
CC(clamp)
from line V < V
CC CC(reset)
V
V
> V
before
CS
CS(stop)
CS
CS(stop)
Latching
CS pin Fault:
Short & Open
Immediate
10 ms timer
10 ms timer
Immediate
Double Hiccup
Double Hiccup
Double Hiccup
Double Hiccup
Resume operation after Double Hiccup
Resume operation after Double Hiccup
Resume operation after Double Hiccup & T < (T
Low supply
V
CC
< V
CC(off)
Internal TSD
SHTDN
− T
)
SHTDN(Hyst)
ZCD short
Resume operation after Double Hiccup (V
< V
CC
CC(on)
V
ZCD
< V
after
< V
)
ZCD(short)
CC(reset)
t
time
BLANK_ZCD
FAULT MODE STATES TABLE (ACCORDING TO THE CONTROLLER VERSIONS)
Event
A Version
B Version
C Version
E Version
V
_OVP
Latched_Timer
Auto Recovery
Latched_Timer
Auto Recovery
Auto Recovery
Auto Recovery
CC
V
CC
> V
= 26 V
CC (OVP)
V
Latched_4clk
Auto Recovery
Auto Recovery
Latched_4clk
OVP
V
OUT
> 126% · V
= 3.15 V/3.6 V [E]
REF_CV2
V
Auto Recovery
Latched_Timer
UVP
V
OUT
< 60% V
when VOUT is decreasing only
, = 1.5 V/0.75 V [E]
REF_CV2
FAULT TYPE MODE DEFINITION
Fault Mode
Timer Protection
Next Device Status
Latched
Release to Normal Operation Mode
Latched_Timer
10 ms timer
V
CC
is decreasing to V
and waiting for un-
CC(clamp)
CC(reset)
plug from line V < V
CC
Latched_4clk
Autorecovery
Immediate
4 consecutive pulses with
V
is decreasing to V
and waiting for un-
CC
CC(clamp)
CC(reset)
V
CS
> 126% V before plug from line V < V
ref_CV2
CC
Latching
Immediate
Resume operation after
Double Hiccup
Resume operation after Double Hiccup (V
<
CC(on)
V
CC
< V
)
CC(reset)
www.onsemi.com
9
NCP1361, NCP1366
CHARACTERIZATION CURVES
20
19.5
19
7.0
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6.0
18.5
18
17.5
17
16.5
16
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 5. VCC Startup Threshold versus
Temperature
Figure 6. VCC Minimum Operating versus
Temperature
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
28.0
27.5
27.0
26.5
26.0
25.5
25.0
24.5
24.0
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 7. VCC(reset) versus Temperature
Figure 8. VCC(OVP) versus Temperature
160
150
140
130
120
110
100
90
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
80
70
60
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 9. Startup Current Source versus
Temperature
Figure 10. HV Pin Leakage versus Temperature
www.onsemi.com
10
NCP1361, NCP1366
CHARACTERIZATION CURVES
2.4
2.0
2.0
1.8
1.6
1.4
1.2
1.0
24
22
20
18
16
14
12
10
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 11. Minimum Voltage for HV Startup
Current Source versus Temperature
Figure 12. ICC2 versus Temperature
520
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
500
480
460
440
420
400
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 13. ICC3 versus Temperature
Figure 14. Standby Current Consumption
(200 Hz option) versus Temperature
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.10
1.08
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 15. Max Peak Current Limit versus
Temperature
Figure 16. Second Peak Current Limit for Fault
Protection versus Temperature
www.onsemi.com
11
NCP1361, NCP1366
CHARACTERIZATION CURVES
1.02
1.01
1.00
0.99
0.98
−50
−25
0
25
50
75
100
125
150
T , TEMPERATURE (°C)
J
Figure 17. Internal Voltage Reference for
Constant Current Regulation versus
Temperature
3.40
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
2.95
2.90
1.60
1.58
1.56
1.54
1.52
1.50
1.48
1.46
1.44
1.42
1.40
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 18. Output Over Voltage Level versus
Temperature (Fault Mode Options A, B & C)
Figure 19. Output Under Voltage Level versus
Temperature (Fault Mode Options A & B)
360
340
320
300
280
260
240
180
160
140
120
100
80
60
−50
−50
−25
0
25
50
75
100
125
150
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 20. Cycle−by−Cycle Leading Edge
Blanking Duration versus Temperature
Figure 21. Leading Edge Blanking Duration for
VCS(stop) Level versus Temperature
www.onsemi.com
12
NCP1361, NCP1366
CHARACTERIZATION CURVES
100
80
60
40
20
0
52
50
48
46
44
42
40
38
36
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 22. Cycle−by−Cycle Current Sense
Propagation Delay versus Temperature
Figure 23. Timeout After Last Demagnetization
Transition in Soft−Start versus Temperature
6.5
6.3
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
95
90
85
80
75
70
65
60
55
50
45
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 24. Timeout After Last Demagnetization
Transition versus Temperature
Figure 25. Timer Delay Before Latching in
Overload Condition versus Temperature
65
60
55
50
45
40
35
30
25
45
40
35
30
25
20
15
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 26. Zero Voltage Detection Threshold
Voltage versus Temperature
Figure 27. Zero Voltage Detection Hysteresis
versus Temperature
www.onsemi.com
13
NCP1361, NCP1366
CHARACTERIZATION CURVES
1.8
1.7
1.6
1.5
1.4
1.3
1.2
8.0
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 28. Blanking Delay for ZCD Detection
versus Temperature
Figure 29. VDRV(low) versus Temperature
13.0
12.5
12.0
11.5
11.0
10.5
10.0
80
70
60
50
40
30
20
10
0
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 30. VDRV(high) versus Temperature
Figure 31. Gate Drive Rise Time versus
Temperature
60
50
40
30
20
10
0
−50
−25
0
25
50
75
100
125
150
T , TEMPERATURE (°C)
J
Figure 32. Gate Drive Fall Time versus
Temperature
www.onsemi.com
14
NCP1361, NCP1366
CHARACTERIZATION CURVES
70
65
60
55
50
45
40
35
30
200
180
160
140
120
100
−50
−25
0
25
50
75
100
125 150
−50
−25
0
25
50
75
100
125
150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 33. Minimum or Frozen Peak Current on
CS Pin versus Temperature (Frozen Peak
Current optionY)
Figure 34. Threshold Level for Detecting
Output or Aux. Winding Short versus
Temperature
40
39
38
37
36
35
34
33
32
31
30
75
70
65
60
55
50
45
40
35
30
25
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 35. Startup Blanking Time for UVP
Detection versus Temperature
Figure 36. Pull−up Current Source for
Detecting Open or Short on CS Pin versus
Temperature
75
70
65
60
55
50
45
40
35
30
25
1.20
1.10
1.00
0.90
0.80
0.70
0.60
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 37. CS Pin Short Detection Threshold
versus Temperature
Figure 38. CS Pin Open Detection Threshold
versus Temperature
www.onsemi.com
15
NCP1361, NCP1366
APPLICATION INFORMATION
The NCP1366/61 is a flyback power supply controller
providing means to implement primary side
Vout
a
constant−current regulation. This technique does not need a
secondary side feedback circuitry, associated bias current
Optocoupler−based feedback
Vnom
and an opto−coupler. NCP1366/61 implements
a
Primary−side
CC mode
current−mode architecture operating in quasi−resonant
mode. The controller prevents valley−jumping instability
and steadily locks out in a selected valley as the power
demand goes down. As long as the controller is able to detect
a valley, the new cycle or the following drive remains in a
valley. Due to a dedicated valley detection circuitry
operating at any line and load conditions, the power supply
efficiency will always be optimized. In order to prevent any
high switching frequency two frequency clamp options are
available.
Iout
0
Inom
Figure 39. Constant−Voltage & Constant−Current
Mode
• Quasi−Resonance Current−mode operation:
implementing quasi−resonance operation in peak
current−mode control optimizes the efficiency by
switching in the valley of the MOSFET drain−source
voltage. Due to a proprietary circuitry, the controller
locks−out in a selected valley and remains locked until
the input voltage significantly changes. Only the four
first valleys could be locked out. When the load current
diminishes, valley switching mode of operation is kept
but without valley lock−out. Valley−switching
operation across the entire input/output conditions
brings efficiency improvement and lets the designer
build higher−density converters.
• Soft−Start: 4 ms internal fixed soft start guarantees a
peak current starting from zero to its nominal value
with smooth transition in order to prevent any
overstress on the power components at each startup.
• Cycle−by−Cycle peak current limit: If the max peak
current reaches the V
level, the over current
ILIM
protection timer is enabled and starts counting. If the
overload lasts T delay, then the fault is latched and
OCP
the controller stops immediately driving the power
MOSFET. The controller enters in a double hiccup
mode before autorecovering with a new startup cycle.
• V Over Voltage Protection: If the V voltage
CC
CC
• Frequency Clamp: As the frequency is not fixed and
reaches the V
threshold the controller enters in
CC(OVP)
dependent on the line, load and transformer
latch mode. Thus it stops driving pulse on DRV pin:
specifications, it is important to prevent switching
frequency runaway for applications requiring maximum
switching frequencies up to 90 kHz or 130 kHz. Two
frequency clamp options at 80 kHz or 110 kHz are
available for this purpose. In case frequency clamp is
not needed, a specific version of the 1361/66 exists in
which the clamp is deactivated.
♦ A & C version − (Latched V
): V
CC
CC(OVP)
capacitor is internally discharged to the V
CC(Clamp)
level with a very low power consumption: the
controller is completely disabled. Resuming
operation is possible by unplugging the line in order
to releasing the internal V thyristor with a V
CC
CC
current lower than the I
.
CC(Clamp)
♦ B version − (Autorecovery): it enters in double
hiccup mode before resuming operation.
• Primary Side Constant Current Regulation: Battery
charging applications request constant current
regulation. NCP1361/66 controls and regulates the
output current at a constant level regardless of the input
and output voltage conditions. This function offers tight
over power protection by estimating and limiting the
maximum output current from the primary side, without
any particular sensor.
• Optocoupler−based feedback: the voltage feedback
loop is classically implemented with an optocoupler
and a NCP431 voltage reference in the secondary side.
By pulling the feedback pin low, the controller adjusts
• Winding Short−Circuit Protection: An additional
comparator senses the CS signal and stops the
controller if V reaches V
+50% (after a reduced
CS
ILIM
LEB: t
). Short circuit protection is enabled only if
LEB2
4 consecutive pulses reach SCP level. This small
counter prevents any false triggering of short circuit
protection during surge test for instance. This fault is
latched and operations will be resumed like in a case of
V
CC
Over Voltage Protection.
the peak current setpoint and regulates V
.
out
www.onsemi.com
16
NCP1361, NCP1366
power mosfet until the junction temperature decreases
by T , then the operation is resumed after a
double hiccup mode.
• V Over Voltage Protection: if the internally−built
out
SHTDN(HYS)
output voltage becomes higher than V
level
OVP
(V
ref_CV1
+ 26%) a fault is detected.
♦ A & C version: This fault is latched and operations
Startup Operation
The high−voltage startup current source is connected to
the bulk capacitor via the HV pin, it charges the V
are resumed like in the V Over Voltage Protection
CC
case.
CC
♦ B version: the part enters in double hiccup mode
before resuming operations.
capacitor. During startup phase, it delivers 100 mA to fuel the
capacitor. When V pin reaches V level, the
V
CC
CC
CC(on)
• V Under Voltage Protection: After each circuit
out
NCP1361/66 is enabled. Before sending the first drive pulse
to the power MOSFET, the CS pin has been tested for an
open or shorted situation. If CS pin is properly wired, then
the controller sends the first drive pulse to the power
MOSFET. After sending these first pulses, the controller
checks the correct Vs/ZCD pin wiring. Considering the
Vs/ZCD pin properly wired, the controller engages a
softstart sequence. The softstart sequence controls the max
peak current from the minimal frozen primary peak current
power on sequence, V UVP detection is enabled only
out
after the startup timer T . This timer ensures that
EN_UVP
the power supply is able to fuel the output capacitor
before checking the output voltage in on target. After
this startup blanking time, UVP detection is enabled
and monitors the Output voltage level. When the power
supply is running in constant−current mode and when
the output voltage falls below V
level, the controller
UVP
stops sending drive pulses and enters a double hiccup
mode before resuming operations (A & B version), or
latches off (C version).
(V
= 120 mV: 15% of V
) to the nominal pulse
CS(VCO)
ILIM
width by smoothly increasing the level.
Figure 40 illustrates a standard connection of the HV pin
to the bulk capacitor. If the controller is in a latched fault
• V /ZCD Pin Short Protection: at the beginning of
s
mode (ex V
has been detected), the power supply will
each off−time period, the V /ZCD pin is tested to check
CC_OVP
s
resume the operation after unplugging the converter from
the ac line outlet. Due the extremely low controller
consumption in latched mode, the release of the latch could
be very long. The unplug duration for releasing the latch will
be dependent on the bulk capacitor size.
whether it is shorted or left open. In case a fault is
detected, the controller enters in a double hiccup mode
before resuming operations.
• Temperature Shutdown: if the junction temperature
reaches the T
level, the controller stop driving the
SHTDN
Vbulk
RHV
L
Vs/ZCD
FB
1
2
2
4
HV
8
N
CS
Vcc
6
5
Vaux
CVcc
DRV
GND
Figure 40. HV Startup Connection to the Bulk Capacitor (NCP1366)
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative injection has the bad habit
to forward−bias the controller substrate and can induce
erratic behaviors. Sometimes, the injection can be so strong
that internal parasitic SCRs are triggered and latch the
controller. The HV pin can be the problem in certain
circumstances. During the turn−off sequence, e.g. when the
user unplugs the power supply, the controller is still fed by
The following calculation illustrates the time needed for
releasing the latch state:
ꢂ
C
bulkVin_ac
IHV
2
(eq. 1)
tunplug
ꢁ
For the following typical application with a 10 mF bulk
capacitor and a wide mains input range, in the worst case the
power supply needs to be unplug at least for 38 seconds @
265 V ac and 12 seconds @ 85 Vac. It is important to note
that the previous recommendation is no longer valid with the
B version, as all the faults are set to autorecovery mode only.
its V capacitor and keeps activating the MOSFET ON and
CC
www.onsemi.com
17
NCP1361, NCP1366
ꢂ
OFF with a peak current limited by R
the quality factor Q of the resonating network formed by L
. Unfortunately, if
sense
Vin,ac_min 2 ꢄ VHV(min)_max
(eq. 2)
RHV
ꢃ
p
IHV_max
and C
is high (e.g. the MOSFET R
+ R
are
bulk
DS(on)
sense
small), conditions are met to make the circuit resonate and
a negative ringing can potentially appear at the HV pin.
Simple and inexpensive cures exist to prevent the internal
parasitic SCR activation. One of them consist of inserting a
resistor in series with the HV pin to keep the negative current
at the lowest when the bulk swings negative (Figure 40).
Another option (Figure 41) consists of connecting the
HV pin directly to the line or neutral input via a high−voltage
diode. This configuration offers the benefits to release a
latch state immediately after unplugging the power supply
from the mains outlet. There is no delay for resetting the
controller as there no capacitor keeps the HV bias.
Where:
• V
is minimal input voltage, for example 85 V ac
in,ac_min
for universal input mains.
• V
is the worst case of the minimal input
HV(min)_max
voltage needed for the HV startup current source
(25 V−max).
• I
is the maximum current delivered by the HV
HV_max
startup current source (150 mA−max)
With this typical example
ꢂ
85 2 ꢄ 25
RHV
ꢃ
ꢅ 633 kW,
150 m
R
resistor value must be sized as follow in order to
HV
guarantee a correct behavior of the HV startup in the worst
case conditions:
then any value below this one will be ok.
Vbulk
L
Vs/ZCD
FB
1
2
2
4
HV
8
N
CS
VCC
GND
6
5
Vaux
CVcc
DRV
Figure 41. Recommended HV Startup Connection for Fast Release after a Latched Fault (NCP1366)
Primary Side Regulation: Constant Current Operation
Figure 42 portrays idealized primary and secondary
transformer currents of a flyback converter operating in
Discontinuous Conduction Mode (DCM).
Ip(t)
Ip, pk
time
Ip, pk
Nps
Is(t), IOUT
Is, pk
=
I
OUT = <Is(t)>
time
ton
tdemag
tsw
Figure 42. Primary and Secondary Transformer Current Waveforms
www.onsemi.com
18
NCP1361, NCP1366
tsw
When the primary power MOSFET is turned on, the
(eq. 6)
VFB_CC ꢅ Vref_CC
primary current is illustrated by the green curve of
Figure 42. When the power MOSFET is turned off the
primary side current drops to zero and the current into the
secondary winding immediately rises to its peak value equal
to the primary peak current divided by the primary to
secondary turns ratio. This is an ideal situation in which the
leakage inductance action is neglected.
The output current delivered to the load is equal to the
average value of the secondary winding current, thus we can
write:
tdemag
As the controller monitors the primary peak current via the
sense resistor and due to the internal current setpoint divider
) between the CS pin and the internal feedback
information, the output current could be written as follow:
(K
comp
Vref_CC
8NpsRsense
(eq. 7)
Iout
ꢅ
The output current value is set by choosing the sense
resistor value:
Ip,pk tdemag
(eq. 3)
Vref_CC
( )
Iout ꢅ ꢃ isec t ꢁ ꢅ
(eq. 8)
tsw
2Nps
Rsense
ꢅ
8NpsIout
Where:
• t is the switching period
When the power MOSFET is released at the end of the on
time, because of the transformer leakage inductance and the
drain lumped capacitance some voltage ringing appears on
the drain node. These voltage ringings are also visible on the
auxiliary winding and could cheat the controller detection
circuits. To avoid false detection operations, two protecting
sw
• t
is the demagnetizing time of the transformer
demag
• N is the secondary to primary turns ratio, where N
ps
p
and N are respectively the transformer primary and
s
secondary turns:
circuits have been implemented on the V /ZCD pin (see
Figure 43):
s
Ns
(eq. 4)
Nps
ꢅ
Np
1. An internal switch grounds the V /ZCD pin during
s
t +t
negative voltage.
in order to protect the pin from
• I is the magnetizing peak current sensed across the
on short_ZCD
p,pk
sense resistor on CS pin:
2. In order to prevent any misdetection from the zero
crossing block an internal switch disconnects
VCS
(eq. 5)
Ip,pk
ꢅ
Rsense
V /ZCD pin until t
time (1.5 ms typ.)
s
blank_ZCD
Internal constant current regulation block is building the
constant current feedback information as follow:
ends.
www.onsemi.com
19
NCP1361, NCP1366
Figure 43. Vs/ZCD Pin Waveforms
Constant−Current and Constant−Voltage Overall
Regulation:
demagnetization end is detected by monitoring the
transformer auxiliary winding voltage. Turning on the
power switch once the transformer is demagnetized (or
reset) reduces turn−on switching losses. Once the
transformer is demagnetized, the drain voltage starts ringing
at a frequency determined by the transformer magnetizing
inductance and the drain lumped capacitance, eventually
settling at the input voltage value. A QR controller takes
advantage of the drain voltage ringing and turns on the
power switch at the drain voltage minimum or “valley” to
reduce turn−on switching losses and electromagnetic
interference (EMI).
As sketched by Figure 44, a valley is detected once the
ZCD pin voltage falls below the QR flyback
demagnetization threshold, VZCD(TH), typically 45 mV. The
controller will switch once the valley is detected or
increment the valley counter depending on FB voltage.
As already presented in the two previous paragraphs, the
controller integrates two different feedback loops: the first
one deals with the constant−current regulation scheme while
the second one builds the constant−voltage regulation with
an opto−based voltage loop. One of the two feedback paths
sets the primary peak current into the transformer. During
startup phase, however, the peak current is controlled by the
soft−start.
Zero Current Detection
The NCP1361/66 integrates a quasi−resonant (QR)
flyback controller. The power switch turn−off of a QR
converter is determined by the peak current whose value
depends on the feedback loop. The switch restart event is
determined by the transformer demagnetization end. The
ZCD
QR multi−mode
Valley lockout &
Valley Switching &
VCO management
Rs1
Rs2
VZCD(TH)
S
R
DRV
(Internal)
Q
Blanking
Tblank_ZCD
Timeout
(toutSS or tout)
Figure 44. Valley Lockout Detection Circuitry internal Schematic
www.onsemi.com
20
NCP1361, NCP1366
Timeout
• Valley #1: the timeout delay must run twice so that the
The ZCD block actually detects falling edges of the
circuit generates a DRV pulse 10 ms (2*t typ.) after
out
auxiliary winding voltage applied to the ZCD pin. At
start−up or during other transient phases, the ZCD
comparator may be unable to detect such an event. Also, in
the case of extremely damped oscillations, the system may
not succeed in detecting all the valleys required by valley
lockout operation (VLO, see next section). In this condition,
the NCP1361/66 ensures continued operation by
incorporating a maximum timeout period that resets itself
when a demagnetization phase is properly detected. In case
the ringing signal is too weak or heavily damped, the timeout
signal supersedes the ZCD signal for the valley counter.
Figure 44 shows the timeout period generator circuit
valley #1 detection.
Valley LockOut (VLO) and Frequency Foldback (FF)
The operating frequency of a traditional Quasi−Resonant
(QR) flyback controller is inversely proportional to the
system load. In other words, a load reduction increases the
operating frequency. A maximum frequency clamp can be
useful to limit the operating frequency range. However,
when associated with
a
valley−switching circuit,
instabilities can arise because of the discrete frequency
jumps. The controller tends to hesitate between two valleys
and audible noise can be generated
To avoid this issue, the NCP1361/66 incorporates a
proprietary valley lockout circuitry which prevents
so−called valley jumping. Once a valley is selected, the
controller stays locked in this valley until the input level or
output power changes significantly. This technique extends
QR operation over a wider output power range while
maintaining good efficiency and naturally limiting the
maximum operating frequency.
The operating valley (from 1 to 4 valley) is determined
by the internal feedback level (FB node on Figure 4). As FB
voltage level decreases or increases, the valley comparators
toggle one after another to select the proper valley.
schematic. The timeout duration, t , is set to 5.5 ms (typ.).
out
During startup, the output voltage is still low, leading to
long demagnetization phase, difficult to detect since the
auxiliary winding voltage is small as well. In this condition,
the t
timeout is generally shorter than the inductor
out
demagnetization period and if used to restart a switching
cycle, it can cause continuous current mode (CCM)
operation for a few cycles until the voltage on the ZCD pin
is high enough for proper valleys detection. A longer
st
th
timeout period, t
, (typically 44 ms) is therefore set
outSS
during soft−start to prevent CCM operation.
In VLO operation, the timeout occurrences are counted
instead of valleys when the drain−source voltage
oscillations are too damped to be detected. For instance,
assume the circuit must turn on at the third valley and the
ZCD ringing only enables the detection of:
The decimal counter increases each time a valley is
detected. The activation of an “n” valley comparator blanks
the “n−1” or “n+1” valley comparator output depending if
V
FB
decreases or increases, respectively. Figure 45 shows a
typical frequency characteristic obtained at low line in a
10 W charger.
• Valleys #1 to #2: the circuit generates a DRV pulse t
out
(steady−state timeout delay) after valley #2 detection.
Figure 45. Typical Switching Frequency versus Output Power Relationship in a 10 W Adapter
www.onsemi.com
21
NCP1361, NCP1366
When an “n” valley is asserted by the valley selection
peak current to deliver the necessary output power at the
valley operating point. Each valley selection comparator
features a 600 mV hysteresis that helps stabilize operation
despite the FB voltage swing produced by the regulation
loop.
circuitry, the controller locks in this valley until the FB
voltage decreases to the lower threshold (“n+1” valley
activates) or increases to the “n valley threshold” + 600 mV
(“n−1” valley activates). The regulation loop adjusts the
Table 1. VALLEY FB THRESHOLD ON CONSTANT VOLTAGE REGULATION
FB Falling
FB Rising
st
nd
th
1
2
3
4
to 2 valley
2.5 V
2.3 V
2.1 V
1.9 V
FF mode to 4
2.5 V
2.7 V
2.9 V
3.1 V
nd
rd
th
rd
th
rd
to 3 valley
4
3
2
to 3 valley
th
rd
nd
nd
to 4 valley
to 2 valley
st
to FF mode
to 1 valley
Frequency Foldback (FF)
efficiency benefit inherent to the QR operation, the
controller turns on again with the next valley after the dead
time has ended. As a result, the controller will still run in
valley switching mode even when the FF is enabled. This
dead−time increases when the FB voltage decays. There is
no discontinuity when the system transitions from VLO to
FF and the frequency smoothly reduces as FB goes below
1.9 V.
As the output current decreases (FB voltage decreases),
the valleys are incremented from 1 to 4. In case the fourth
valley is reached, the FB voltage further decreases below
1.9 V and the controller enters the frequency foldback mode
(FF). The current setpoint being internally forced to remain
above 0.12 V (setpoint corresponding to V
= 1.9 V), the
Comp
controller regulates the power delivery by modulating the
switching frequency. When an output current increase
causes FB to exceed the 2.5 V FF upper threshold (600−mV
hysteresis), the circuit recovers VLO operation.
In frequency foldback mode, the system reduces the
switching frequency by adding some dead−time after the 4
The dead−time is selected to generate a 2 ms dead−time
when V
is decreasing and crossing V
(1.9 V
Comp
HVCOD
typ.). At this moment, it can linearly go down to the minimal
frequency limit (f = 200, 600 or 1200 Hz version are
VCO(min)
th
available). The generated dead−time is 1ms when V
is
Comp
valley is detected. However, in order to keep the high
increasing and crossing V
(2.5 V typ.).
HVCOI
Figure 46. Valley Lockout Threshold
Current Setpoint
starting from the frozen peak current (V
= 120 mV
CS(VCO)
As explained in this operating description, the current
setpoint is affected by several functions. Figure 47
summarizes these interactions. As shown by this figure, the
current setpoint is the output of the control law divided by
typ.) to V
(0.8 V typ.) within 4 ms (t ).
ILIM
ss
However, this internal FB value is also limited by the
following functions:
♦ A minimum setpoint is forced that equals V
CS(VCO)
K
comp
(4 typ.). This current setpoint is clamped by the
(0.12 V, typ.)
soft−start slope as long as the peak current requested by the
FB_CV or FB_CC level are higher. The softstart clamp is
♦ In addition, a second OCP comparator ensures that
in any case the current setpoint is limited to V
.
ILIM
www.onsemi.com
22
NCP1361, NCP1366
This ensures the MOSFET current setpoint remains
limited to V
in a fault condition.
ILIM
Peak current
Freeze
SoftStart
FB_CV
FB_CC
Control Law
PWM Comp
For
1/Kcomp
Primary Peak
Current Control
FB Reset
PWM
Latch
Reset
CS
OCP
Comp
LEB1
Max_Ipk reset
Count
RCS
CCS
OCP
OCP
Rsense
Timer
VILIM
Reset Timer
POReset
DbleHiccup
Reset
Counter
Short Circuit
Comp
LEB2
4 clk
SCP
Counter
VCS(Stop)
Figure 47. Current Setpoint
A 2nd Over−Current Comparator for Abnormal
Overcurrent Fault Detection
Fault mode and Protection
♦ CS pin: at each startup, a 55 mA (I ) current source
CS
A severe fault like a winding short−circuit can cause the
switch current to increase very rapidly during the on−time.
pulls up the CS pin to disable the controller if the pin
is left open or grounded. Then the controller enters
in a double hiccup mode.
The current sense signal significantly exceeds V
. But,
ILIM
because the current sense signal is blanked by the LEB
circuit during the switch turn on, the power switch current
can abnormally increase, possibly causing system damages.
The NCP1361/66 protects against this dangerous mode by
adding an additional comparator for abnormal overcurrent
fault detection or short−circuit condition. The current sense
♦ Vs/ZCD pin: after sending the first drive pulse the
controller checks the correct wiring of Vs/ZCD pin:
after the ZCD blanking time, if there is an open or
short conditions, the controller enters in double
hiccup mode.
Thermal Shutdown: An internal thermal shutdown circuit
monitors the junction temperature of the IC. The controller
is disabled if the junction temperature exceeds the thermal
signal is blanked with a shorter LEB duration, t
,
LEB2
typically 120 ns, before applying it to the short−circuit
comparator. The voltage threshold of this extra comparator,
shutdown threshold (T
), typically 150°C. A continuous
SHDN
V
, is typically 1.2 V, set 50% higher than V
. This
CS(stop)
ILIM
V
hiccup is initiated after a thermal shutdown fault is
CC
is to avoid interference with normal operation. Four
consecutive abnormal overcurrent faults cause the
controller to enter in auto−recovery mode. The count to 4
provides noise immunity during surge testing. The counter
is reset each time a DRV pulse occurs without activating the
fault overcurrent comparator or after double hiccup
sequence or if the power supply is unplugged with a new
startup sequence after the initial power on reset.
detected. The controller restarts at the next V
once the
CC(on)
IC temperature drops below T
shutdown hysteresis (T
thermal shutdown is also cleared if V
reduced by the thermal
), typically 40°C. The
SHDN
SHDN(HYS)
drops below
CC
V
. A new power up sequences commences at the
CC(reset)
next V
once all the faults are removed.
CC(on)
Driver
The NCP1361/66 maximum supply voltage, V
, is
CC(max)
Standby Power Optimization
28 V. Typical high−voltage MOSFETs have a maximum
gate voltage rating of 20 V. The DRV pin incorporates an
active voltage clamp which limits the gate voltage on the
Assuming the no−load standby power is a critical
parameter, the NCP1361/66 is optimized to reach an ultra
low standby power. When the controller enters standby
mode, a part of the internal circuitry has been disabled in
order to minimize its supply current. When the STBY mode
external mosfet. The DRV voltage clamp, V
is set to
DRV(high)
13 V maximum.
is enabled, the consumption is only 200 mA (I ) with the
CC4
200 Hz minimal frequency option.
www.onsemi.com
23
NCP1361, NCP1366
TABLE OF AVAILABLE OPTIONS
Function
Options
Fault Mode
V
Latched / Full Autorecovery /
latched
CC_OVP
V
out_UVP
Minimum operating frequency in VCO
200 Hz / 600 Hz / 1.2 kHz / 23 kHz
No Clamp / 80 kHz / 110 kHz
Frequency Clamp or Maximum operating
frequency
ORDERING TABLE OPTION
HV
Frozen Peak Current
Startup
V
Fault Mode
Min Operating F
(STBY)
D
Frequency Clamp
CS(VCO)
SW
6
1
A
B
C
E
A
B
C
E
A
B
C
X
Y
Z
Yes No
V
_OVP
_OVP Autorecovery
Full
Full Latched
Full
Autorecovery
200 Hz 600 Hz 1.2 kHz 23 kHz No No 80 kHz 110 kHz 120 mV 160 mV 200 mV
Min.
CC
V
OUT
OPN #
NCP136_ _ _ _ _
Latched
V
= 3.6 V
= 0.75 V
OVP
V
UVP
NCP1366AABAY
NCP1366BABAY
NCP1366CABAY
NCP1366EABAY
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NCP1361AABAY
NCP1361BABAY
NCP1361CABAY
NCP1361EABAY
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
www.onsemi.com
24
NCP1361, NCP1366
ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NCP1366AABAYDR2G
1366A1
SOIC−7
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
NCP1366BABAYDR2G
NCP1366EABAYDR2G
NCP1361AABAYSNT1G
NCP1361BABAYSNT1G
NCP1361EABAYSNT1G
1366B1
1366E1
ADE
SOIC−7
(Pb−Free)
SOIC−7
(Pb−Free)
TSOP−6
(Pb−Free)
ADF
TSOP−6
(Pb−Free)
ACU
TSOP−6
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
25
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
1
DATE 12 JUN 2012
SCALE 2:1
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
H
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
6
1
5
4
L2
GAUGE
PLANE
E1
E
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
2
3
L
MILLIMETERS
SEATING
M
C
NOTE 5
DIM
A
A1
b
c
D
E
E1
e
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
NOM
1.00
MAX
1.10
0.10
0.50
0.26
3.10
3.00
1.70
1.05
0.60
PLANE
b
DETAIL Z
e
0.06
0.38
0.18
3.00
c
2.75
A
0.05
1.50
0.95
L
0.40
A1
L2
M
0.25 BSC
−
DETAIL Z
0°
10°
STYLE 1:
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
STYLE 3:
PIN 1. ENABLE
2. N/C
STYLE 4:
PIN 1. N/C
2. V in
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
STYLE 6:
PIN 1. DRAIN
2. DRAIN
3. GATE
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
3. R BOOST
4. Vz
5. V in
6. V out
3. NOT USED
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
4. SOURCE
5. DRAIN
6. DRAIN
4. GROUND
5. ENABLE
6. LOAD
4. EMITTER
5. COLLECTOR
6. COLLECTOR
6. COLLECTOR 2
6. COLLECTOR 2
STYLE 7:
STYLE 8:
PIN 1. Vbus
2. D(in)
STYLE 9:
STYLE 10:
PIN 1. D(OUT)+
2. GND
STYLE 11:
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
PIN 1. LOW VOLTAGE GATE
2. DRAIN
PIN 1. SOURCE 1
2. DRAIN 2
3. D(in)+
4. D(out)+
5. D(out)
6. GND
3. SOURCE
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
3. DRAIN 2
4. N/C
5. COLLECTOR
6. EMITTER
4. DRAIN
4. SOURCE 2
5. GATE 1
4. I/O
5. DRAIN
5. VCC
6. I/O
6. HIGH VOLTAGE GATE
6. DRAIN 1/GATE 2
STYLE 13:
STYLE 14:
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
STYLE 16:
STYLE 17:
PIN 1. EMITTER
2. BASE
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
PIN 1. ANODE
2. SOURCE
PIN 1. ANODE/CATHODE
2. BASE
3. GATE
3. EMITTER
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
4. DRAIN
4. COLLECTOR
5. ANODE
5. N/C
6. CATHODE
6. CATHODE
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
XXX MG
G
G
1
1
6X
0.95
3.20
IC
STANDARD
XXX = Specific Device Code
XXX = Specific Device Code
A
Y
W
G
=Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
0.95
= Pb−Free Package
PITCH
DIMENSIONS: MILLIMETERS
*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G”
or microdot “G”, may or may not be present. Some
products may not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009
SCALE 1:1
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
S
M
M
B
−B−
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
C
R X 45
_
1.27 BSC
J
0.10
0.19
0.40
0
−T−
SEATING
PLANE
K
8
0
8
_
_
_
_
M
H
D 7 PL
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
M
S
S
0.25 (0.010)
T
B
A
GENERIC
MARKING DIAGRAM
SOLDERING FOOTPRINT*
8
XXXXX
ALYWX
1.52
0.060
G
1
XXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
7.0
0.275
4.0
0.155
Y
W
G
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12199D
7−LEAD SOIC
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009
STYLE 1:
STYLE 2:
STYLE 3:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6.
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. EMITTER, #2
7. NOT USED
8. EMITTER, #1
6. SOURCE, #2
7. NOT USED
8. SOURCE, #1
7. NOT USED
8. EMITTER
STYLE 4:
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5.
STYLE 6:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. NOT USED
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6.
6.
7. NOT USED
8. SOURCE
7. NOT USED
8. SOURCE
8. COMMON CATHODE
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR (DIE 1)
2. BASE (DIE 1)
STYLE 9:
PIN 1. INPUT
PIN 1. EMITTER (COMMON)
2. COLLECTOR (DIE 1)
3. COLLECTOR (DIE 2)
4. EMITTER (COMMON)
5. EMITTER (COMMON)
6. BASE (DIE 2)
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
3. BASE (DIE 2)
4. COLLECTOR (DIE 2)
5. COLLECTOR (DIE 2)
6. EMITTER (DIE 2)
7. NOT USED
7. NOT USED
7. NOT USED
8. FIRST STAGE Vd
8. COLLECTOR (DIE 1)
8. EMITTER (COMMON)
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE (DIE 1)
2. GATE (DIE 1)
3. SOURCE (DIE 2)
4. GATE (DIE 2)
5. DRAIN (DIE 2)
6. DRAIN (DIE 2)
7. NOT USED
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. NOT USED
8. GROUND
8. DRAIN (DIE 1)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12199D
7−LEAD SOIC
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
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