NCP1370ADR2G [ONSEMI]
LED 驱动器，用于电视背光的可调光准谐振初级侧电流模式控制器;
| 型号： | NCP1370ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | LED 驱动器，用于电视背光的可调光准谐振初级侧电流模式控制器 驱动 控制器 电视 驱动器 |
| 文件： | 总19页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1370
Product Preview
Dimmable Quasi-Resonant
Primary Side Current-Mode
Controller for LED TV
Backlight
www.onsemi.com
The NCP1370 is a PWM current mode controller targeting isolated
flyback and non−isolated constant current topologies. The controller
operates in a quasi−resonant mode to provide high efficiency. Thanks
to a novel control method, the device is able to precisely regulate a
constant LED current from the primary side. This removes the need
for secondary side feedback circuitry, biasing and an opto−coupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device supports analog/digital dimming and both
modes can be combined to enhance dimming precision. The NCP1370
has a programmable peak current limit to optimize design
compatibility over a wide range of applications. The controller
features a standby mode with reduced current consumption.
QUASI−RESONANT PWM
CONTROLLER FOR
LED DRIVERS
MARKING
DIAGRAM
8
SOIC−8
D SUFFIX
CASE 751
NCP1370x
ALYW
8
1
G
1
Features
NCP1370 = Specific Device Code
• Quasi−resonant Peak Current−mode Control Operation
• Primary Side Sensing (no opto−coupler needed)
x
A
L
= Device Option (A or B)
= Assembly Location
= Wafer Lot
• Wide V Range
CC
Y
W
G
= Year
= Work Week
= Pb−Free Package
• Source 300 mA / Sink 500 mA Totem Pole Driver with 12 V Gate
Clamp
• Precise LED Constant Current Regulation 1% Typical
• Line Feed−forward for Enhanced Regulation Accuracy
• Low LED Current Ripple
PIN CONNECTIONS
1
ILIM
DIM
VIN
• 500 mV 1.2% Guaranteed Voltage Reference for Current
ZCD
CS
Regulation
VCC
DRV
• Programmable Cycle−by−Cycle Peak Current Limit
GND
• Low V
Allowing to use a Standby Power Supply to Power the
CC(on)
(Top View)
Device
• Analog or Digital Dimming
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
• Wide Temperature Range of −40 to + 125°C
• Robust Protection Features
♦ LED Open Circuit Protection
♦ V Over Voltage Protection
CC
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Shorted Current Sense Pin Fault Detection
♦ Brown−out
Typical Applications
♦ V Under Voltage Lockout
♦ Thermal Shutdown
• Pb−free, Halide−free MSL1 Product
• TV Backlight
• Lighting with Auxiliary Power Supply
CC
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
February, 2016 − Rev. P1
NCP1370/D
NCP1370
.
Aux
.
.
VDIM
1
2
3
4
8
7
6
5
VBIAS
Figure 1. Typical Application Schematic for NCP1370
Table 1. PRODUCTS TABLE
Block or Electrical Parameter
Brown−out blanking time t
NCP1370B
100 ms
NCP1370A
2 ms
BO(blank)
Blanking circuit for leakage inductance reset detection
OVP
ON
ON
V
CC
Auto−recovery
4 cycles
Latched
4 cycles
Switching cycles count before activating the output diode short circuit
protection: V > V
CS
CS(stop)
Output Diode Short Circuit protection
Auto−recovery
1 second
ON
Latched
4 seconds
OFF
Adjustable OVP Auto−recovery timer
CS short circuit protection (impedance measurement before startup)
High mains valley switching
rd
nd
3
2
(all HL valleys incremented by 1)
Propagation delay from ZCD to DRV high state t
ON
ON
ZCD(DEM)
Table 2. PIN FUNCTION DESCRIPTION
Pin N5 Pin Name
Function
Pin Description
nd
1
ILIM
Peak current limit and 2
This pin sets the cycle−by−cycle peak current limit threshold and the threshold for
secondary diode short detection
over current protection
Zero Crossing Detection
Current sense
2
3
4
5
6
7
ZCD
CS
Connected to the auxiliary winding, this pin detects the core reset event.
This pin monitors the primary peak current.
The controller ground
GND
DRV
VCC
VIN
−
Driver output
The driver’s output to an external MOSFET
This pin is connected to an external power supply.
Supplies the controller
Brown−Out
This pin observes the HV rail and protects the circuit in case of low main conditions.
This pin also sense the line voltage for the valley selection and the line feed−forward
Input voltage sensing
Over Voltage Protection
A Zener diode can also be used to pull−up the pin and stop the controller for
adjustable OVP protection
8
DIM
Analog / PWM dimming
This pin is used for analog or PWM dimming control. An analog signal than can
be varied between V
and V
can be used to vary the current, or a
DIM(EN)
DIM100
PWM signal with an amplitude greater than V
.
DIM100
This pin is also used for the OFF mode
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2
NCP1370
Internal Circuit Architecture
Disable
CS_NOK
V
DD
V
REF
STOP
Internal
Thermal
Shutdown
OFF
OVP2
VCC
Fault
UVLO
VCC Management
Management
Standby
Aux_SCP
ILIM
Peak Current Limits
Threshold
V
V
ILIMIT
VCC_OVP
VCC Over Voltage
Protection
Ipkmax
Generation
CS(stop)
CS_STOP
BO_NOK
Qdrv
V
REF
V
VIN
VCC
Clamp
Circuit
Zero Crossing Detection
ZCD
Valley Selection
Aux. Winding
DRV
S
R
Short Circuit Prot.
Qdrv
Aux_SCP
Q
V
VIN
V
VLY
Line
Feedforward
V
STOP
REF
OFF Mode
Detection
Standby
DIM
CS
Leading
Edge
Blanking
Constant−Current
Control
CS_reset
Dimming
Type
Detection
V
DIMA
Ipkmax
STOP
V
Enable
DIMA
Disable
Max. Peak
Current
Limit
V
VIN
Ipkmax
V
ILIMIT
VIN
Brown−Out
BO_NOK
CS Short
Protection
CS_NOK
Over Voltage
Protection
Winding and
Output diode
Short Circuit
Protection
OVP2
CS_STOP
GND
V
CS(stop)
Figure 2. Internal Circuit Architecture
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3
NCP1370
Table 3. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
V
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3, +35
V
CC(MAX)
I
Internally limited
mA
CC(MAX)
V
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 1)
V
DRV(MAX)
DRV
I
−500, +800
mA
DRV(MAX)
V
Maximum voltage on low power pins (except pins DIM, DRV and VCC)
Current range for low power pins (except pins DRV and VCC)
−0.3, +5.5
−2, +5
V
MAX
I
mA
MAX
V
Maximum voltage for DIM pin
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
−0.3, +7
289
V
°C/W
°C
DIM(MAX)
R
θ
J−A
T
150
J(MAX)
−40 to +125
−60 to +150
4
°C
°C
ESD Capability, HBM model (Note 2)
ESD Capability, MM model (Note 2)
kV
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
is the DRV clamp voltage V
when V is higher than V
. V
is V unless otherwise noted.
DRV
DRV(high)
CC
DRV(high) DRV CC
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V)
J
CC
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
V
V
V
V
increasing
decreasing
decreasing
V
11
9
1.8
12
9.5
−
13
10
–
CC
CC
CC
CC(on)
V
CC(off)
Hysteresis V
– V
V
CC(on)
CC(off)
CC(HYS)
CC(reset)
Internal logic reset equal to V
V
9
9.5
10
CC(off)
Over Voltage Protection
VCC OVP threshold
V
26
28
30
V
CC(OVP)
V
V
noise filter
t
–
–
5
20
–
–
ms
CC(off)
VCC(off)
noise filter
t
CC(reset)
VCC(reset)
Startup current
I
t
–
−
−
100
250
mA
ms
CC(start)
st
Starting time from exiting OFF Mode to 1 DRV pulse
CC(start)
Supply Current
Device Disabled/Fault
Device Enabled/No output load on pin 5
Device Switching (F = 65 kHz)
mA
V
F
> V
I
I
I
0.8
–
–
1.2
2.3
2.7
1.4
4.0
5.0
CC
CC(off)
CC1
CC2
CC3
= 65 kHz
= 470 pF,
= 65 kHz
sw
C
sw
DRV
F
sw
Supply Current in OFF mode
I
50
mA
CC(off)
CURRENT SENSE AND ILIM PIN
Reference current for maximum peak current limit threshold
I
190
200
0.5
2.6
210
mA
V
LIM(REF)
Minimum value for internal V
V
< 0.5 V
V
ILIMIT
pinILIM
ILIMIT(MIN)
ILIMIT(MAX)
ILIMIT(offset)
Maximum value for internal V
Pin ILIM open
V
2.34
−30
2.86
30
V
ILIMIT
Difference between internal V
and ILIM pin voltage
V
V
= 1.5 V
= 1.5 V
V
mV
V
ILIMIT
pinILIM
pinILIM
V
at V
= 1.5 V
V
2.037
280
2.1
2.163
380
CS(stop)
pinILIM
CS(stop)1
Leading Edge Blanking Duration for V
125°C)
(T = −40°C to
j
t
330
ns
ILIM
LEB
Minimum on−time (equal to t
)
t
280
–
330
50
380
150
62.5
ns
ns
ms
LEB
on(MIN)
Propagation delay from current detection to gate off−state
Maximum on−time
t
ILIM
t
37.5
50
on(MAX)
4. Guaranteed by design
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4
NCP1370
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V)
J
CC
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
CURRENT SENSE AND ILIM PIN
Test Condition
Symbol
Min
Typ
Max
Unit
Minimum threshold value for immediate fault protection acti-
vation
V
< 0.5 V
V
0.7
V
V
pinILIM
CS(stop)MIN
Minimum threshold value for immediate fault protection acti-
vation
Pin ILIM open
V
3.64
CS(stop)MAX
Ratio between internal V
and internal V
K
STOP/ILIMIT
140
200
500
17
%
ns
mA
ms
CS(stop)
ILIMIT
Leading Edge Blanking Duration for V
t
–
–
CS(stop)
BCS
Current source for CS to GND short detection
Timer for measuring CS to GND short
GATE DRIVE
I
t
400
12
600
22
CS(short)
CS(short)
Drive Resistance
DRV Sink
DRV Source
W
R
SNK
R
SRC
–
–
13
30
–
–
Drive current capability
DRV Sink (Note 4)
DRV Source (Note 4)
mA
I
I
–
–
500
300
–
–
SNK
SRC
Rise Time (10 % to 90 %)
Fall Time (90 % to 10 %)
C
C
= 470 pF
= 470 pF
t
–
–
40
30
–
–
ns
ns
DRV
DRV
r
t
f
DRV Low Voltage
V
CC
= V +0.2 V
CC(off)
V
8
–
–
V
DRV(low)
C
= 470 pF,
DRV
R
=33 kW
DRV
DRV High Voltage
V
CC
= 30 V
V
10
12
14
V
DRV(high)
C
= 470 pF,
DRV
R
=33 kW
DRV
ZERO VOLTAGE DETECTION CIRCUIT
ZCD threshold voltage
V
increasing
decreasing
increasing
V
30
20
8
50
40
–
70
60
–
mV
mV
mV
V
ZCD
ZCD(THI)
ZCD threshold voltage (Note 4)
ZCD hysteresis (Note 4)
V
ZCD
V
V
ZCD(THD)
ZCD(HYS)
ZCD(short)
V
ZCD
Threshold voltage for output short circuit or aux. winding
short circuit detection
V
0.8
1
1.2
Short circuit detection Timer
Auto−recovery timer duration
V
ZCD
< V
t
OVLD
70
3
90
4
110
5
ms
s
ZCD(short)
t
recovery
Input clamp voltage
High state
Low state
V
I
= 3.0 mA
V
V
–
−0.9
8
−0.6
–
−0.3
pin1
ZCD(CH)
I
V
V
= −2.0 mA
decreasing
decreasing
pin1
ZCD(CL)
Propagation Delay from valley detection to DRV high
Delay from valley lockout output to DRV latch set
Blanking delay after on−time
t
−
125
1.2
0.6
5
−
480
375
2
ns
ns
ms
ms
ms
ZCD
ZCD
ZCD(DEM)
t
250
1.6
0.8
6.5
LEB4
V
> 100 mV
< 75 mV
t
t
REF
ZCD(BLANK1)
ZCD(BLANK2)
Blanking delay after on−time at light load
Timeout after last demag transition
V
1
REF
t
8
TIMO
LINE FEED−FORWARD
V
to I
conversion ratio
K
LFF
15
17
19
mA/V
mA
VIN
CS(offset)
Offset current maximum value
V
pinVIN
= 4.5 V
I
67.5
76.5
85.5
offset(MAX)
CONSTANT CURRENT CONTROL
Reference Voltage (after division by 2) (T = 25°C)
V
495
492
488
500
500
500
505
508
512
mV
mV
mV
j
REF
Reference Voltage (after division by 2) (T = 0°C to 85°C)
V
REF
j
Reference Voltage (after division by 2) (T =−40°C to 125°C)
V
REF
j
4. Guaranteed by design
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5
NCP1370
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V)
J
CC
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
CONSTANT CURRENT CONTROL
Test Condition
Symbol
Min
Typ
Max
Unit
Current sense lower threshold for detection of the leakage
inductance reset time
V
25
55
85
mV
CS(low)
Blanking time for leakage inductance reset detection
t
130
75
ns
CS(low)
V
REF
value below which the ZCD blanking time is divided by
V
decreases
V increases
REF
V
mV
REF
REF(off)
REF(on)
2 (light load)
V
REF
value above which ZCD blanking time is t
V
100
mV
ZCD(blank1)
VALLEY SELECTION
Threshold for line range detection V increasing
V
increases
decreases
V
HL
2.28
2.18
15
2.4
2.3
25
2.52
2.42
35
V
V
in
VIN
st
nd
st
rd
(1 to 2 valley or 1 to 3 transition for V
> 0.375 V)
REF
Threshold for line range detection V decreasing
V
VIN
V
LL
in
nd
st
st
rd
(2 to 1 valley or 1 to 3 transition for V
> 0.375 V)
REF
Blanking time for line range detection
t
ms
HL(blank)
Valley thresholds (V
= 500 mV)
mV
REF
st
nd
nd
rd
1
to 2 valley transition at LL and 2 to 3 valley HL
V
decreases
increases
decreases
increases
decreases
increases
decreases
increases
decreases
increases
V
V
V
V
V
V
350
366
231
249
–
373
390
248
267
150
165
75
396
414
265
285
–
REF
VLY1−2/2−3
VLY2−1/3−2
VLY2−4/3−5
VLY4−2/5−3
VLY4−7/5−8
VLY7−4/8−5
rd
th
(3 to 4 valley HL for version B) V
decreases
REF
rd
nd
th
st
rd
nd
2
to 1 valley transition at LL and 3 to 2 valley HL
V
REF
REF
(4 to 3 valley HL for version B), V
incr.
th
REF
rd
nd
th
2
to 4 valley transition at LL and 3 to 5 valley HL
V
th
th
(4 to 6 valley HL for version B), V
decr.
rd
REF
th
th
th
nd
th
4
to 2 valley transition at LL and 5 to 3 valley HL
V
REF
REF
(6 to 4 valley HL for version B), V
incr.
th
REF
th
th
th
4
to 7 valley transition at LL and 5 to 8 valley HL
V
th
th
(6 to 9 valley HL for version B), V
decr.
th
REF
th
th
th
7
to 4 valley transition at LL and 8 to 5 valley HL
V
–
–
REF
REF
th
th
(9 to 6 valley HL for version B), V
incr.
REF
th
th
th
th
th
th
7
to 11 valley transition at LL and 8 to 12 valley HL
V
V
V
–
–
VLY7−11/8−12
VLY11−7/12−8
(9 to 13 valley HL for version B), V
decr.
REF
th
th
th
th
11 to 7 valley transition at LL and 12 to 8 valley HL
V
–
100
30
–
REF
REF
th
th
(13 to 9 valley HL for version B), V
incr.
REF
th
th
th
th
th
th
11 to 13 valley transition at LL and 12 to 15 valley HL
V
V
V
–
–
VLY11−13/12−15
VLY13−11/15−12
(13 to 16 valley HL for version B), V
decr.
REF
th
th
th
th
13 to 11 valley transition at LL and 15 to 12 valley HL
V
–
40
–
REF
th
th
(16 to 13 valley HL for version B), V
incr.
REF
Valley thresholds in percentage of V
REF
nd
%
st
nd
rd
1
to 2 valley transition at LL and 2 to 3 valley HL
V
decreases
increases
decreases
increases
decreases
increases
decreases
increases
decreases
increases
V
V
V
V
V
V
70
73
46
50
–
74.5
78
79
83
53
57
–
REF
VLY1−2/2−3
VLY2−1/3−2
VLY2−4/3−5
VLY4−2/5−3
VLY4−7/5−8
VLY7−4/8−5
rd
th
(3 to 4 valley HL for version B) V
decreases
REF
rd
nd
th
st
rd
nd
2
to 1 valley transition at LL and 3 to 2 valley HL
V
REF
REF
(4 to 3 valley HL for version B), V
incr.
th
REF
rd
nd
th
2
to 4 valley transition at LL and 3 to 5 valley HL
V
49.5
53.5
30
th
th
(4 to 6 valley HL for version B), V
decr.
rd
REF
th
th
th
nd
th
4
to 2 valley transition at LL and 5 to 3 valley HL
V
REF
REF
(6 to 4 valley HL for version B), V
incr.
th
REF
th
th
th
4
to 7 valley transition at LL and 5 to 8 valley HL
V
th
th
(6 to 9 valley HL for version B), V
decr.
th
REF
th
th
th
7
to 4 valley transition at LL and 8 to 5 valley HL
V
–
33
–
REF
REF
th
th
(9 to 6 valley HL for version B), V
incr.
REF
th
th
th
th
th
th
7
to 11 valley transition at LL and 8 to 12 valley HL
V
V
–
15
–
VLY7−11/8−12
VLY11−7/12−8
(9 to 13 valley HL for version B), V
decr.
REF
th
th
th
th
11 to 7 valley transition at LL and 12 to 8 valley HL
V
V
–
20
–
REF
REF
th
th
(13 to 9 valley HL for version B), V
incr.
REF
th
th
th
th
th
th
11 to 13 valley transition at LL and 12 to 15 valley HL
V
V
V
–
6
–
VLY11−13/12−15
VLY13−11/15−12
(13 to 16 valley HL for version B), V
decr.
REF
th
th
th
th
13 to 11 valley transition at LL and 15 to 12 valley HL
V
–
8
–
REF
th
th
(16 to 13 valley HL for version B), V
4. Guaranteed by design
incr.
REF
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6
NCP1370
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V)
J
CC
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
DIMMING SECTION
DIM pin voltage for zero output current (OFF voltage)
comparator hysteresis
V
decreasing
increasing
DIM
V
0.67
−
0.7
50
3
0.73
−
V
mV
V
DIM
DIM(EN)
V
EN(HYS)
V
V
DIM(EN)
DIM pin voltage for maximum output current (T = −40 to
V
2.9
3.1
J
DIM100
125°C)
DIM pin voltage for maximum output current at T = 25°C
V
2.94
3
2.3
7
3.06
V
V
J
DIM100
Dimming range
V
–
–
–
–
–
–
DIM(range)
Clamping voltage for DIM pin
Dimming pin pull−up current source
THERMAL SHUTDOWN
Thermal Shutdown (Note 4)
V
V
DIM(CLP)
I
5
mA
DIM(pullup)
Device switching
around 65 kHz)
T
130
–
150
50
170
–
°C
°C
SHDN
(F
SW
Thermal Shutdown Hysteresis (Note 4)
BROWN−OUT AND OVP
T
SHDN(HYS)
Brown−Out ON level (IC start pulsing)
Brown−Out OFF level (IC shuts down)
BO comparators delay
V
increasing
decreasing
V
V
0.90
0.85
–
1
0.9
30
2
1.10
0.95
–
V
V
VIN
BO(on)
V
VIN
BO(off)
t
ms
ms
ms
nA
V
BO(delay)
BO(blank1)
BO(blank2)
Brown−Out blanking time for version A
Brown−Out blanking time for version B
Brown−out pin bias current
t
t
1.4
50
2.6
150
250
4.3
100
–
I
−250
3.9
BO(bias)
Clamped voltage (VIN pin left open)
VIN pin Clamp series resistor
VIN pin open
V
4.1
1
VIN(clamp)
VIN(clamp)
R
kW
V
VIN pin detection level for OVP
V
VIN
increasing
V
4.75
5
5.25
OVP
OVP(delay)
Delay before OVP confirmation
t
50
1
ms
s
Adjustable OVP auto−recovery timer (version B)
Adjustable OVP auto−recovery timer (version A)
4. Guaranteed by design
t
t
OVP(recovery1)
OVP(recovery2)
4
s
www.onsemi.com
7
NCP1370
Application Information
The NCP1370 is a LED driver for flyback and
MOSFET is turned off for the rest of the switching
cycle.
non−isolated buck−boost / SEPIC converters. It implements
a current−mode architecture quasi−resonant architecture to
prevent valley−jumping instability. A proprietary circuitry
ensures accurate regulation of the output current without the
need of a secondary side feedback. The circuit features
powerful protections to ensure a robust LED driver design
without the need of extra external components or
overdesign.
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCP1370 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to smart control
algorithm, the controller locks−out in a selected valley
and remains locked until the input voltage or the output
current set point significantly changes.
nd
• Winding Short−Circuit Protection (2 over current
protection level): an additional comparator with a short
LEB filter (t ) senses the CS signal and stops the
BCS
controller if V reaches 140% of V
). For noise
ILIMIT
CS
immunity reasons, this comparator is enabled only
during the main LEB duration t
.
LEB
• Output Short−circuit protection: If a very low
voltage is applied on ZCD pin for 90 ms (nominal), the
controllers assume that the output or the ZCD pin is
shorted to ground and enters shutdown. After waiting
for 4 seconds, the controller restarts switching.
• Linear or PWM dimming: the DIM pin allows
implementing both analog and PWM dimming.
• OFF Mode: The IC enters in OFF mode after detecting
a fault and whenever the DIM pin voltage stays low
during more than 4 seconds. In this mode, the IC is off
and has a reduced current consumption. This allows
simplifying the PCB design around the ON/OFF
opto−coupler.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller accurately controls the
output current without requiring a secondary side
feedback (no optocoupler needed). An output current
deviation below 2% is typically obtained.
• Floating or Short pin detection: The NCP1370
protections help passing safety tests. For instance, the
circuit stops operating when the CS pin is grounded or
when the GND pin is open.
• V Over Voltage Protection: if the voltage on VCC
CC
pin exceeds an internal limit, the controller shuts down
and waits 4 seconds before restarting pulsing (version
B) or stays latched (A version).
• Adjustable peak current limit: the cycle−by−cycle
maximum peak current limit and the second over
current protection level can be adjusted externally by
connecting a resistor between ILIM pin and ground.
Constant Current Control
Capitalizing on the constant current control technique
developed in the NCL3008X product, the NCP1370
accurately regulates the output current of a flyback
converter from its primary side.
By connecting the clamping capacitor of the flyback
converter to the sense resistor as shown in the typical
application schematic (Figure 1), we have an image of the
drain current waveform and of the leakage inductance
current waveform. Thus, by looking at the current sense pin
waveform, the controller is able to detect the reset of the
transformer leakage inductance. Indeed, the leakage
inductance limits the output rectifier peak current as shown
• Brown−Out: the controller includes a brown−out
circuit which safely stops the controller in case the
input voltage is too low. The device will automatically
restart if the line recovers.
• Adjustable Over voltage protection: By connecting a
zener diode to the VIN pin, an adjustable over voltage
protection can be implemented to protect against open
LEDs. Upon detection, the controller waits 4 s
(version A) or 1 s (version B) before attempting to
restart switching.
in Figure 3 where it is shown that: N * I
< I
.
sp
D,pk
L,pk
Also, by monitoring the auxiliary winding voltage
through the ZCD pin, we can detect the end of conduction
of the secondary rectifier.
• Cycle−by−cycle peak current limit: when the current
sense voltage exceeds pin ILIM voltage V
, the
ILIM
www.onsemi.com
8
NCP1370
IL,pk
NspID,pk
Isec(t)
Ipri(t)
time
T2
tdemag
t1
ton
V (t)
aux
time
Figure 3. Flyback Currents and Auxiliary Winding Voltage in DCM
VREF
2NspIout
The constant current control block picks up the leakage
inductor current, the end of conduction of the output rectifier
and controls the drain current to maintain the output current
constant.
Rsense
+
(eq. 2)
From (Equation 1), the first key point is that the output
current is independent of the inductor value. Moreover, the
leakage inductance does not influence the output current
value as the reset time is taken into account by the controller.
We have:
VREF
2NspRsense
Iout
+
(eq. 1)
Soft−Start
Where:
At startup or after recovering from a fault, there is a small
internal soft−start of 200 ms maximum.
• V
is the output current internal reference
REF
• N is the secondary to primary transformer turns ratio:
In addition, during startup, as the output voltage is zero
volts, the demagnetization time is long and the constant
current control block will slowly increase the peak current
towards its nominal value as the output voltage grows.
Figure 5 shows a soft−start simulation example for a 9 W
LED power supply.
sp
N
sp
= N / N
s p
• R
is the current sense resistor
sense
The output current value is set by choosing the sense
resistor:
www.onsemi.com
9
NCP1370
16.0
12.0
8.00
4.00
0
V
out
1
800m
600m
400m
200m
0
I
2
out
800m
600m
400m
200m
0
V
V
4
3
Control
CS
604u
1.47m
2.34m
3.21m
4.07m
time in seconds
Figure 4. Startup Simulation showing the Natural Soft−start
Adjustable Cycle−by−Cycle Current Limit
VILIMIT + VILIM + ILIM(REF)RILIM
(eq. 3)
The pin ILIM allows adjusting the threshold for maximum
The threshold for immediate short circuit protection
is given by:
nd
peak current limit V
and also the 2 over current
ILIMIT
V
CS(stop)
protection (OCP2) threshold
V
CS(stop)
which helps
VCS(stop) + 1.4 @ VILIMIT
(eq. 4)
protecting against short circuit of the secondary winding or
of the output diode.
More precisely, the maximum peak current threshold
Practically, V
can be adjusted from 0.5 V to 2.6 V,
ILIMIT
meaning V
range is from 0.7 V to 3.64 V.
CS(stop)
V
is equal to the ILIM pin voltage and V
value
ILIMIT
CS(stop)
When the current sense voltage exceeds the internal
threshold V , the MOSFET is turned off for the rest of
is derived from V . By connecting a resistor between
ILIMIT
ILIMIT
ILIM and GND pins, the value of internal cycle−by−cycle
current limit V is:
the switching cycle. Figure 5 shows the schematic of ILIM
pin.
ILIMIT
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10
NCP1370
Vdd
VILIM(MAX)
ILIM(REF)
Clamp
Clamp
ILIM
VILIM
Buffer
VCS(stop)
Gain
RILIM
VILIM(MIN)
VILIM
Figure 5. Block Diagram of ILIM Pin
Winding and Output diode Short−Circuit Protection
(OCP2)
In parallel with the cycle−by−cycle sensing of the CS pin,
The cycle−by−cycle peak current limit threshold V
also set the maximum duty cycle for a given application.
The maximum duty cycle is given by:
ILIMIT
another comparator with a reduced LEB (t ) and a higher
BCS
VREF
VILIMIT Tsw
tv
DMAX + 1 *
*
threshold (V ) is able to sense winding short−circuit
CS(stop)
(eq. 5)
and stop the controller. In version B, the controller stops the
DRV pulses after counting 4 cycles of V > V . The
Where:
CS
CS(stop)
controller attempts to re−start after waiting 4 seconds. In
• t is the valley duration
v
version A, after counting 4 cycles of V > V
, the
CS(stop)
CS
• T is the switching period
sw
controller stays latched.
For switching frequencies below 100 kHz, the term t /T
can be neglected:
v
sw
The controller is unlatched by one of the 3 following events:
• V < V
CC
CC(off)
VREF
VILIMIT
DMAX [ 1 *
(eq. 6)
• Standby by V
< V
during 4 seconds
DIM
DIM(EN)
• BO_NOK becomes high
After being unlatched, the controller goes into OFF Mode.
S
aux
DRV
Q
Q
Vdd
UVLO
VCC
Vcc
management
CS
R
LEB1
+
−
PWMreset
Ipkmax
Vcontrol
4−s timer
VCCreset
+
−
VILIMIT
STOP
LEB2
+
−
1 pulse
or
4 pulses
CS_STOP
S
OFF
Q
Q
VCS(stop)
R
4−s timer
from Fault Management Block
Figure 6. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
www.onsemi.com
11
NCP1370
PWM or Linear Dimming Detection
Practically, when V
< V
, the controller
DIM
DIM(EN)
The pin DIM allows dimming the LED light. Analog
dimming or digital (PWM) dimming can be used.
decreases the peak current from its current state to nearly
zero before stopping the DRV pulses.
If the power supply designer apply an analog signal
This allows having a very good correlation between the
dimming duty−cycle and the output current value when
dimming at low duty−cycle.
Also, it is important to note that for good correlation
between the dimming duty−cycle (which represent the
expected output current value relative to the nominal value)
and the actual measured output current, the high state
duration of the dimming signal should not be below 200 ms.
Figure 8 shows the drain source waveform during
soft−stop.
varying from V
to V
to the DIM pin, the
DIM(EN)
DIM100
output current will increase or decrease proportionally to the
voltage applied. For V = V , the power supply
DIM
DIM100
delivers the maximum output current.
If a voltage lower than V is applied to the DIM pin,
DIM(EN)
the DRV pulses are disabled. Thus, for digital dimming, a
PWM signal with a low state value lower than V and
DIM(EN)
a high state value higher than V
should be applied.
DIM100
The DIM pin is pulled up internally by a small current
source or resistor. Thus, if the pin is left open, the controller
is able to start.
OFF Mode with DIM Pin
The OFF Mode is entered when V
stays below
DIM
Soft Stop during PWM Dimming
V
for 4 seconds. In this mode, IC consumption is
DIM(EN)
The NCP1370 features an internal soft−stop of 200 ms
maximum in order to compensate the output current
decrease caused by the soft−start during PWM dimming.
reduced to I
only when V
(below 50 mA). The OFF mode is exited
CC(off)
becomes higher than V
+V
.
DIM
DIM(EN)
EN(HYS)
V
DIM
Deep PWM dimming
Analog dimming
PWM dimming
VDIM100
100% Iout
3 V
VDIM(EN)
0% Iout
0.7 V
Figure 7. Pin DIM Chronograms
VDIM
Vdrain
Figure 8. Soft−stop
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12
NCP1370
VCC Over Voltage Protection
In order to protect itself against too high supply voltage,
the controller features an over voltage protection for the V
goes through a complete sequence OFF Mode → FAULT
Mode (see Fault Management section for more information)
In the latched mode, the controller stops pulsing and waits
that one of the 3 following events occurs to reset the latch:
CC
threshold,
pin. When the V voltage reaches the V
CC
CC(OVP)
the controller stops the DRV pulses and shutdown.
Depending on the version, the controller goes in
auto−recovery mode (version B) or in latched mode
(version A).
In the auto−recovery mode, the controller waits 4 s and
tries to re−start. In order to restart pulsing, the controller
• V < V
CC
CC(off)
• Standby by V
< V
during 4 seconds
DIM
DIM(EN)
• BO_NOK becomes high
When the OVP Latch is reset, the controller goes into OFF
Mode.
VCC
VCC(OVP)
OVP
VCC(on)
VCC(off)
VDIM
VDIM(100)
VDIM(EN)
RUN
4−s Timer
RESET
STATE
OFF
RUN
FAULT
CS impedance check
FAULT
CS impedance check
OFF
VDRV
Figure 9. VCC Over Voltage Protection Chronograms
Valley Selection
The input voltage is sensed by the VIN pin. The internal
logic selects the operating valley according to VIN pin
voltage and DIM pin voltage.
Quasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
The NCP1370 changes valley as the input voltage
increases and as the output current set−point is varied during
dimming. This limits the switching frequency excursion.
Once a valley is selected, the controller stays locked in the
valley until the input voltage or the output current set−point
varies significantly.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line for version A. For version B, the
rd
controller operates in the 3 valley at high line. Table 5
summarizes the valley selected by the controller as a
function of the output current and the input voltage. The
numbers in blue are the selected valleys for version B.
www.onsemi.com
13
NCP1370
Table 5. VALLEY SELECTION
VIN pin voltage for valley change
I
value at which the
I
value at which the
out
out
V
VIN
decreases
controller changes valley
controller changes valley
(I decreasing)
out
(I increasing)
out
0
−− LL −−
2.3 V
−− HL −− 5 V
100%
75%
50%
30%
15%
100%
78%
53%
33%
20%
st
nd
rd
1
2
(3 )
nd
th
rd
th
2
3
5
8
(4 )
th
th
th
th
4
7
(6 )
th
th
(9 )
th
th
11
12 (13 )
6%
0%
8%
0%
th
th
th
13
15 (16 )
0
−− LL −−
2.4 V −− HL −− 5 V
increases
V
VIN
VIN pin voltage for valley change
Zero Crossing Detection Block
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
the valleys. To avoid such a situation, the NCP1370 features
a Time−Out circuit that generates pulses if the voltage on
ZCD pin stays below the 55−mV threshold for 6.5 ms.
The Time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations (Figure 11).
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
A valley is detected when the voltage on pin 1 crosses
down the 55−mV internal threshold.
In order to decrease the capacitor value needed on ZCD
pin to turn−on the MOSFET right in the valley or in some
case remove it, a small delay (250 ns) is added internally
before turning−on the MOSFET.
Tblank
Time−Out
ZCD
+
Clock
VZCD(TH)
.
−
Tblank
+
VZCD(short)
−
90−ms
Timer
Enable_b
S
Aux_SCP
Q
Q
R
4−s Timer
Figure 10. ZCD Block Schematic
www.onsemi.com
14
NCP1370
VZCD
VZCD(th)
3
4
The 3rd valley is
validated
high
low
14
12
2nd , 3rd
nd valley is detected
The 3rd valley is not detected by
The 2
By the ZCD comparator
the ZCD comp
high
low
high
15
16
ZCD
comp
low
TimeOut adds a pulse to account for the
TimeOut
missing 3rd
valley
high
low
17
Clock
Figure 11. Time−out Chronograms
Line Feed−Forward
Output Short Circuit Protection
Because of the time−out function, if the ZCD pin or the
auxiliary winding is shorted, the controller will continue
switching leading to improper regulation of the LED
current.
Moreover during an output short circuit, the controller
will strive to maintain the constant current operation.
In order to avoid these scenarios, a secondary timer starts
Because of the propagation delays, the MOSFET is not
turned−off immediately when the current set−point is
reached. As a result, the primary peak current is higher than
expected and the output current increases. To compensate
the peak current increase brought by the propagation delays,
a positive voltage proportional to the line voltage is added
on the current sense signal. The amount of offset voltage can
counting when the ZCD voltage is below the V
be adjusted using the R resistor as shown in Figure 12.
ZCD(short)
CS
threshold (Figure 10). If this timer reaches 90 ms, the
controller detects a fault and enters the auto−recovery fault
mode: the controller stops pulsing and waits 4−s before
going through a complete startup sequence.
VCS(offset) + KLFF VpinVIN RCS
(eq. 7)
The offset voltage is applied only during the MOSFET
on−time.
This offset voltage is always applied over the load range.
This protection is disabled when V
< V
.
DIM
DIM(EN)
www.onsemi.com
15
NCP1370
noise delay
+
−
S
R
Q
Q
OVP2
Bulk rail
VOVP
Aux
.
4−s Timer
(1-s Timer version B)
vDD
VIN
RCS
CS
ICS(offset)
Rclamp
Vclamp
Rsense
Q_drv
+
−
Blanking
time
BO_NOK
1 V if BONOK high
0.9 V if BONOK low
Figure 12. Line Feed−Forward, Adjustable OVP and Brown−out Schematic
Adjustable Over Voltage Protection
110 W typically, the circuit does not start pulsing and
shutdown. The circuit attempts to restart after waiting 4
seconds. In practice, it is recommended to place a
minimum of 250 W in series between the CS pin and
the current sense resistor to take into account parasitic
component effect and electrical parameters tolerance.
• Fault of GND pin connection
A clamping circuit on VIN pin limits the voltage
excursion to 4.1 V (Figure 12). This level is high enough to
allow good linearity of the line feedforward current for
universal mains applications with an input voltage up to
265 V rms.
When the zener diode starts conducting, it injects current
inside the clamping circuit and the voltage on VIN pin
If the GND pin is properly connected, the current
increases. When V
exceeds V
during t
, the
VIN
OVP
OVP(delay)
drawn from the positive terminal of the V capacitor
CC
circuit detects an over voltage condition and stops the DRV
pulses. The controller waits until the OVP timer
flows out of the GND pin to return to the negative
terminal of the V capacitor. If the GND pin is not
CC
(t
) has elapsed (4 s for version A, 1 s for
OVP(recovery)
connected, the circuit ESD diodes offer another return
path. The accidental non−connection of the GND pin is
monitored by detecting that one of the ESD diode is
conduction. Practically, the ESD diode of CS pin is
monitored. If such a fault is detected for 200 ms, the
circuit stops generating DRV pulses.
version B) and restarts switching.
Brown−out
In order to protect the supply against a very low input
voltage, the NCP1370 features a brown−out circuit with a
fixed ON/OFF threshold (Figure 12). The controller is
allowed to start if a voltage higher than 1 V is applied to the
VIN pin and shuts−down if the VIN pin voltage decreases
and stays below 0.9 V when the BO blanking timer has
elapsed (BO_NOK high). When a brown−out condition is
detected, the circuit stops pulsing and goes into the OFF
mode detailed in the “Fault Management Section”.
Fault Management and Startup Sequence
Figure 13 and Figure 14 shows the state diagrams of the
NCP1370.
OFF Mode
At startup, as long as V
is not high enough, the
CC
controller is reset. Its current consumption is I
. When
CC(start)
Pin Connection Faults
V
CC
> V , the controller goes in OFF mode and waits
CC(on)
• CS pin Short to ground
for the enable signal (V
> V
). In OFF mode, the
DIM
DIM(EN)
The circuit senses the CS pin impedance every time it
starts−up. If the measured impedance does not exceed
IC consumption is very low (50 mA maximum).
www.onsemi.com
16
NCP1370
The OFF mode is exited only if V > V
and V
DIM
• An Output / Auxiliary winding Short circuit is detected:
CC
CC(on)
> V
. The controller then goes in FAULT mode.
DIM(EN)
“Aux_SCP high”
More generally, the OFF mode is entered upon the
following events:
• Second OCP level triggered
When the 4−s timer has elapsed, the controller goes in
OFF Mode.
• V < V
CC
CC(off)
• Brown−out edge
Adjustable OVP Management
• V
< V
after 4 seconds
DIM
DIM(EN)
When the adjustable OVP on VIN pin is triggered, the
controller stops the DRV pulses and starts the OVP2 Timer
(4 s in version A, 1 s in version B).
• Die over temperature (TSD)
• The 4−s auto−recovery timer has elapsed
When the OVP2 timer has elapsed, the controller goes in
FAULT mode and restart switching if no other fault is
detected.
FAULT Mode
In this mode, the controller measures CS pin impedance.
If CS pin is not shorted the controller is allowed to start the
DRV pulses. If CS pin is shorted, the controller starts the 4
seconds timer. No DRV pulse is generated in this mode.
Latched Protection (VCC OVP, Output Diode Short
Circuit Protection in Version A)
nd
When V > V
or when the 2 OCP is triggered,
CC
CC(OVP)
AR Mode
the DRV pulses stop and the controller is latched
(Figure 14).
In the auto−recovery mode, the 4 seconds timer is
counting, DRV is not pulsing. The 4 seconds timer starts
counting when:
The Latch resets when one of the 3 following events occurs:
• V < V
CC
CC(off)
• V
< V
DIM(EN)
DIM
• V
< V
during 4 seconds
DIM
DIM(EN)
• A short circuit on CS pin is detected
• V > V
• BO_NOK becomes high
CC
CC(OVP)
OFF
Timer ends (AR_end)
or BO_NOK edge
or TSD_end
VddINT POR
V
low
CC too
or VCC < VCC(off)
BO_NOK edge
or TSD_end
or VCC < VCC(off)
BO_NOK edge
or TSD_end
or VCC < VCC(off)
VDIM > VDIM(EN)
and VCC > VCC(on)
Timer ends
OVP2
OVP2
Timer
AR
mode
FAULT mode
CS_short high
or VCC_OVP high
or VDIM < VDIM(EN)
CS_OK
VDIM > VDIM(EN) and
all other faults low
OVP2
RUN
VCC_OVP high or VDIM < VDIM(EN)
or CS_stop or Aux_SCP
à
With states: RESET
OFF
Controller is dead
Controller is in OFF Mode, ICC = ICC(off)
No switching, ICC = ICC1
Controller is switching
the 4−s auto−recovery timer is counting, No switching
The OVP2 Timer (4−s or 1−s) is counting, No DRV pulses
(50 μA max.)
à
à
à
à
à
FAULT Mode
RUN
AR Mode
OVP2 Timer
Figure 13. Fault State Diagram with Auto−recovery Faults
www.onsemi.com
17
NCP1370
VCC < VCC(off) or BO_NOK high
or VDIM < VDIM(EN) during 4 s
VddINT POR
VCC too
low
Timer ends (AR_end) or BO_NOK edge
or TSD_end or VCC < VCC(off)
OFF
BO_NOK edge
or TSD_end
or VCC < VCC(off)
BO_NOK edge
or TSD_end
or VCC < VCC(off)
VDIM > VDIM(EN)
and VCC > VCC(on)
CS_short high
or VDIM < VDIM(EN)
Timer ends
OVP2
OVP2
Timer
AR
mode
LATCH
FAULT mode
VCC_OVP high
CS_OK
VDIM > VDIM(EN) and
all other faults low
OVP2
VDIM < VDIM(EN) or Aux_SCP
VCC_OVP high or CS_stop
RUN
à
à
à
à
à
à
With states: RESET
OFF
Controller is dead
Controller is in OFF Mode, ICC = ICC(off)
No switching, ICC = ICC1
Controller is switching
the 4−s auto−recovery timer is counting, No switching
The OVP2 Timer (4−s or 1−s) is counting, No DRV pulses
(50 μA max.)
FAULT Mode
RUN
AR Mode
OVP2 Timer
Figure 14. Fault State Diagram with Latched Faults
ORDERING INFORMATION
Device
†
Package Type
Shipping
NCP1370BDR2G
SOIC−8
(Pb free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
18
NCP1370
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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