NCP1382DR2G [ONSEMI]
控制器，准谐振，电流模式，低待机耗量，带 PFC 关断;
| 型号： | NCP1382DR2G |
| 厂家： | 
ONSEMI |
| 描述： | 控制器，准谐振，电流模式，低待机耗量，带 PFC 关断 控制器 开关 功率因数校正 光电二极管 |
| 文件： | 总27页 (文件大小：864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1381, NCP1382
Low--Standby High
Performance PWM
Controller
Housed in a SO--14 package, the NCP1381/82 includes everything
needed to build rugged and efficient Quasi--Resonant (QR) Switching
Power Supplies. When powered by a front--end Power Factor
Correction circuitry, the NCP1381/82 automatically disconnects the
PFC controller in low output loading conditions (with an adjustable
level), thus improving the standby power. This is particularly well
suited for medium to high power offline applications, e.g. notebook
adapters. When the current setpoint falls below a given value, e.g. the
output power demand diminishes, the IC automatically enters the
so--called skip cycle mode and provides excellent efficiency at light
loads. Because this occurs at an adjustable low peak current together
with a proprietary Soft--Skipt technique, no acoustic noise takes
place. Skip cycle also offers the ability to easily select the maximum
switching frequency at which foldback and standby take place.
The NCP1381/82 also features several efficient protection options
like a) a short--circuit / overload detection independent of the auxiliary
voltage b) an auto--recovery brown--out detection and c) an input to
externally latch the circuit in case of Overvoltage Protection or Over
Temperature Protection.
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HIGH PERFORMANCE QR
CONTROLLER FEATURING PFC
SHUTDOWN
MARKING
DIAGRAM
14
SOIC--14
D SUFFIX
CASE 751A
NCP138xG
AWLYWW
14
1
1
NCP138xG = Specific Device Code
x
A
WL
Y
WW
= 1 or 2
= Assembly Location
= Wafer Lot
= Year
Features
Current--Mode Quasi--Resonant Operation
Adjustable Line Over Power Protection
Extremely Low Startup Current of 15 mA Maximum
Soft--Skip Cycle Capability at Adjustable Peak Currents
Plateau Sensing Overvoltage
= Work Week
G = Pb--Free Package
ADJ_GTS
1
2
3
4
5
6
7
14
13
12
11
10
9
nc
Brown--Out Protection
Maximum tON Limitation
BO
nc
DMG
Ref
Overpower Protection by current Sense Offset
Internal 5 ms Soft--Start Management
Short--Circuit Protection Independent from Auxiliary Level
External Latch Input Pin for an OTP Signal
Go--To--Standby Signal for the PFC Front Stage
True Frequency (tON + tOFF) Clamp Circuit
Low and Noiseless, No--Load Standby Power
Internal Leading Edge Blanking
Timer
GTS
Skip/OVP
V
CC
FB
CS
DRV
GND
8
ORDERING INFORMATION
†
+500 mA / --800 mA Peak Current Drive Capability
5 V / 10 mA Reference Voltage
These are Pb--Free Devices
Device
Package
Shipping
NCP1381DR2G
SOIC--14 2500/Tape & Reel
(Pb--Free)
NCP1382DR2G
SOIC--14 2500/Tape & Reel
(Pb--Free)
Typical Applications
High Power AC/DC Adapters for Notebooks, etc
Offline Battery Chargers
Set--Top Boxes Power Supplies, TV, Monitors, etc
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
November, 2010 -- Rev. 5
NCP1381/D
NCP1381, NCP1382
TYPICAL APPLICATION EXAMPLE
HV
+
PFC Stage
+
To PFC’s V
CC
+
OVP
NCP1381/82
V
out
V
ref
1
14
GTS_ADJ
BO
2
13
DMG
3
4
5
12
11
10
+
6
7
9
8
Skip
GTS_ADJ
OPP
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin#
Symbol
Description
An internal comparator senses the signal applied to this pin (typically a portion of
1
GTS_ADJ
GTS Level Adjustment
Brown--out
F
signal) to detect the standby condition for GTS.
B
2
3
BO
By connecting this pin to a resistive divider, the controller ensures operation at a
safe mains level.
DMG
Detects the Zero Voltage
Crossing Point
This pin detects the core reset event but also permanently senses the Flyback
plateau, offering a clean OVP detection.
4
5
Timer
Fault Timer
Connecting a capacitor to this pin adjusts the fault timer.
Skip/OVP
Adjust the Skip Level
This pin alters the default skip cycle level and offers a mean to latchoff the con-
troller when externally brought above 4 V.
6
7
FB
CS
Feedback Signal
Current Sense Pin
An optocoupler collector pulls this pin down to regulate. When the current set-
point falls below an adjustable level, the controller skips cycles.
This pin cumulates two different functions: the standard sense function plus an
adjustable offset voltage providing the adequate level of Overpower Protection.
8
9
GND
DRV
The IC Ground
--
The Driver Output
With a drive capability of ±500 mA/800 mA, the NCP1381 can drive large Q
MOSFETs.
g
10
11
V
V
Input
CC
The controller accepts voltages up to 20 V and features an UVLO of 10 V typical.
CC
GTS
Directly Powers the PFC
Frontend Stage
This pin directly powers the PFC controller by routing the PWM V to the PFC
CC
V
. In standby (defined by GTS_ADJ), fault and BO conditions, this pin is open
CC
and the PFC is no longer supplied.
This pin offers a 5 V reference voltage sourcing up to 10 mA.
Not Connected
12
13
14
Reference
NC
Reference Voltage
--
--
NC
Not Connected
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2
NCP1381, NCP1382
INTERNAL CIRCUIT ARCHITECTURE
5 mA
V
DD
ADJ_GTS
1
--
+
R
Timer
ST
ADJ_GTS Section
+
250 mV
+
--
V
DD
+
BOComp.
240 mV/
500 mV
V
Management
CC
UVLO, Latchoff
BO
S
CLK
2
Q
Q
+
--
BO
I
P
Timer
+
8 ms No DMG
Timeout
R
Flag
4 ms
Delayed
1 Shot
DRV
DRV
3 ms
1 Shot
V
latchDem
+
to
Latch
--
+
S
CLK
Q
Q
UVLO
DMG
--
3
Ref
12
11
+
+
+
R
V
V
ref
th
Prioritary
Reset
BO
DRV
GTS
V
DD
V
DD
DRV
GTS
Conf. ?
t
+ t
=8 ms
ON
OFF
Max F
Clamping
sw
1 Shot
+
--
+
--
V
DD
+
Timer
+
10
V
CC
t
> 45 ms?
ON
Fault
/ 4
SS
Timer
Skip
4
5
6
Fault /
Startup
I
PFlag
Drv
9
V
+
TimSS
LEB
Skip/
OVP
+
--
OPP
Offset
SS
Cap
Soft--Start Ended
Timer
I/V 85 mS
+
+
--
V
TimFault
--
V
V
DD
FB
CS
+
DD
Skip
Section
S
30 mA
Q
I
P
Flag
GTS
Q
25 k
R
Switches are Kept Closed until NOR
Output Goes Low
Latchoff
V
DD
7
8
GND
+
--
SS
Cap
+
4 V Reset
Soft--Skip
Soft--Start
V
latch
Plateau
Sensing
Figure 2. Internal Circuit Architecture
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3
NCP1381, NCP1382
MAXIMUM RATINGS TABLE
Symbol
Rating
Value
20
Unit
V
V
Maximum Power Supply Voltage on Pin 10 (V ), Pin 9 (DRV), and Pin 11 (GTS)
CC
supply
Maximum Current in Pin 10 (V
)
30
mA
mA
A
CC
Maximum Current in Pin 11 (GTS)
Maximum Current in Pin 9 (DRV)
20
1
Power Supply Voltage on all Other Pins Except Pin 10 (V ), Pin 9 (DRV), Pin 3 (DMG) and
--0.3 to 5
V
CC
Pin 11 (GTS)
Maximum Current Into All Other Pins Except Pin 10 (V ), Pin 9 (DRV) and Pin 11 (GTS)
10
+3 / --3
150
mA
mA
C/W
C
CC
I
Maximum Current in Pin 3 (DMG), When 10 V ESD Zener is Activated
Thermal Resistance Junction--to--Air, SO--14
dem
R
θ
J--A
TJMAX Maximum Junction Temperature
150
Storage Temperature Range
--60 to +150
2
C
ESD Capability, Human Body Model per MIL--STD--883, Method 3015 (All Pins Except Ref)
ESD Capability, Human Body Model per MIL--STD--883, Method 3015 (Ref Pin)
ESD Capability, Machine Model
kV
1.8
kV
200
V
NOTE: This device contains latchup protection and exceeds 100 mA per JEDEC standard JESD78.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS
(For typical values T = 25C, for min/max values T = 0C to +125C, V = 12 V unless otherwise noted)
J
J
CC
Symbol
Rating
Pin
Min
Typ
Max
Unit
SUPPLY SECTION
VCC
Turn--on Threshold Level, V Going Up
CC
10
10
10
10
10
10
10
10
13
9
--
15
10
7
17.9
11
--
V
V
ON
VCC
VCC
VCC
Minimum Operating Voltage After Turn--on
OFF
latch
reset
V
V
Decreasing Level at Which the Latchoff Phase Ends
Level at Which the Internal Logic Gets Reset
V
CC
CC
--
4
--
V
I
Startup Current (V < VCC )
ON
--
2
15
1.8
2.6
--
mA
mA
mA
mA
startup
CC
I
I
I
Internal IC Consumption, No Output Load on Pin 9, F
= 60 kHz
SW
--
1.4
2.1
1.4
CC1
CC2
CC3
Internal IC Consumption, 1 nF Output Load on Pin 9, F
Internal IC Consumption, Latchoff Phase
= 60 kHz
--
SW
--
DRIVE OUTPUT
Output Voltage Rise--Time @ C = 1 nF, 10--90% of Output Signal
T
r
9
9
9
9
--
--
--
--
15
15
9
--
--
--
--
ns
ns
Ω
L
T
f
Output Voltage Fall--Time @ C = 1 nF, 10--90% of Output Signal
L
R
Source Resistance
Sink Resistance
OH
R
8
Ω
OL
CURRENT COMPARATOR
Input Bias Current @ 1 V Input Level on Pin 7
Maximum Internal Current Setpoint at V = 0
I
7
7
7
7
--
0.75
70
--
0.02
0.8
85
--
0.85
100
--
mA
V
IB
I
Limit
BO
G
Transconductance Amplifier Offsetting CS at V = 2 V
mS
ns
m
BO
T
Propagation Delay from CS Detected to Gate Turned off (Pin 9 Loaded
by 1 nF)
90
DELCS
T
Leading Edge Blanking Duration
7
--
--
300
2.5
370
4.0
--
ns
ms
ms
LEB
S
Typical Internal Soft--start Period at Startup
Typical Internal Soft--start period when Leaving Skip
6.0
250
Start
S
100
175
skip
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NCP1381, NCP1382
ELECTRICAL CHARACTERISTICS
(For typical values T = 25C, for min/max values T = 0C to +125C, V = 12 V unless otherwise noted)
J
J
CC
Symbol
Rating
Pin
Min
Typ
Max
Unit
GO--TO--STANDBY
R
GTS
Pin 11 Output Impedance (or R
is Closed)
between Pin 10 and Pin 11 when SW
dson
11
--
15
--
Ω
R
V
Skip Adjustment Output Impedance
Default Skip Cycle Level
5
5
--
17
--
25
800
3.4
250
5.0
35
--
kΩ
mV
--
skip
skip
Hyst_ratio Ratio Between the Skip Level and the Skip Comparator Hysteresis
ADJ_GTS Threshold of the ADJ_GTS Comparator
--
--
1
1
220
4.0
280
6.0
mV
mA
I
Internal Current Source that Creates an Adjustable Hysteresis to the
ADJ_GTS Comparator
hyst
DEMAGNETIZATION DETECTION BLOCK
Input Threshold Voltage (V 3 Decreasing)
V
3
3
30
--
50
30
80
--
mV
mV
th
pin
V
Hysteresis (V 3 Increasing)
pin
H
Input Clamp Voltage
VC
High State (I 3 = 3.0 mA)
3
3
9
-- 0 . 9
10
-- 0 . 7
12
-- 0 . 5
V
V
H
L
pin
VC
Low State (I 3 = --3.0 mA)
pin
T
DMG Propagation Delay
3
3
3
--
--
200
10
--
--
ns
dem
C
Internal Input Capacitance at V 3 = 1 V
pin
pF
par
R
Internal Pulldown Resistor
20
30
45
down
blank
kΩ
ms
T
Internal Blanking Delay after T
3
--
--
3.5
8.0
--
ON
T
Frequency Clamp, Minimum (T + T )
OFF
7.0
9.0
ms
sw--(min)
ON
FEEDBACK SECTION
Internal Pullup Resistor
Pin 6 to Current Setpoint Division Ratio (Maximum V = 5 V)
R
6
--
7.5
--
10
4.0
5.0
--
12.5
--
kΩ
up
I
ratio
FB
Ref
Voltage Reference, I
= 1 mA
12
12
4.75
10
5.25
--
V
load
I
Reference Maximum Output Current
mA
ref
PROTECTIONS
V
V
Limitation in Latched Fault Mode
CC
10
9
--
--
6.0
45
--
--
V
ms
mA
V
zenlatch
Max
Maximum On Time Duration
Timer Charging Current
tON
I
4
7.0
3.5
--
10
13
4.5
--
timer
V
Timer Fault Validation Level
4
4.0
90
timfault
T
Timeout Before Validating Short--circuit or GTS, C = 0.22 mF
--
ms
V
delay
t
V
Latching Level On the Demagnetization Input
3
3.7
--
4.1
4.0
4.5
--
latchdem
T
Sampling Time for V
Detection after the End of the T
ON
3
ms
V
samp
latchdem
V
Latchoff Level On the Skip Adjustment Pin
NCP1381
NCP1382
5
3.15
2.25
3.5
2.5
3.85
2.75
latch
T
Propagation Delay from Latch Detected to Gate Turned Off (Pin 9
Loaded by 1 nF)
--
--
220
--
ns
DELLATCH
VBO
Brown--out Level High
2
2
2
--
0.45
0.21
--
0.5
0.24
0.04
--
0.55
V
V
high
VBO
Brown--out Level Low
0.275
low
I
Brown--out Pin Input Bias Current
Temperature Shutdown, Maximum Value
Hysteresis While in Temperature Shutdown
--
--
--
mA
C
C
BO
T
SD
140
--
TSD
--
30
hyst
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5
NCP1381, NCP1382
APPLICATION INFORMATION
The NCP1381/82 includes all necessary features to help
Skip--cycle Capability: A continuous flow of pulses in
not compatible with no--load standby power
buildingaruggedandsafeswitchingpowersupplyfeaturing
an extremely low standby power. The below bullets detail
the benefits brought by implementing the NCP1381/82
controller.
Current--mode operation with Quasi--Resonant
Operation: Implementing peak current mode control,
the NCP1381/82 waits until the drain--source voltage
crosses a minimum level. This is the quasi--resonance
approach, minimizing both EMI radiations and
capacitive losses.
Over Power Protection: Using a voltage image of the
bulk level, via the brown--out divider, the designer can
select a resistor which, placed in series with the current
sense information, provides an efficient line
compensation method.
Frequency Clamp: The controller monitors the sum of
ton and toff, providing a real frequency clamp. Also the
ton maximum duration is safely limited to 50 ms in case
the peak current information is lost. If the maximum
ton limit is reached, then the controller stops all pulses
and enters a safe auto--recovery burst mode.
requirements. Slicing the switching pattern in bunch of
pulses drastically reduces overall losses but can, in
certain cases, bring acoustic noise in the transformer.
Due to a skip operation taking place at low peak currents
only, no mechanical noise appears in the transformer.
This is further strengthened by ON Semiconductor’s
Soft--Skip technique, which forces the peak current in
skip to gradually increase. In case the default skip value
would be too large, connecting a resistor to the Pin 6 will
reduce or increase the skip cycle level. Adjusting the
skip level also adjusts the maximum switching frequency
before skip occurs.
Soft--Start: A circuitry provides a soft--start sequence
which precludes the main power switch from being
stressed upon startup. This soft--start is internal and
reaches 5 ms typical.
Overvoltage Protection: By sensing the plateau level
after the power switch has opened, the controller can
detect an overvoltage condition through the auxiliary
reflection of the output voltage. If an OVP is sensed,
the controller stops all pulses and permanently stays
latched until the VCC is cycled down below 4.0 V.
External Latch Input: By permanently monitoring
Pin 5, the controller detects when its level rises above
3.5 V, e.g. in presence of a fault condition like an OTP.
This fault is permanently latched--off and needs the
VCC to go down below 4.0 V to reset, for instance
when the user unplugs the SMPS.
Brown--out Detection: By monitoring the level on Pin 2
during normal operation, the controller protects the
SMPS against low mains condition. When the Pin 2
level falls below 240 mV, the controllers stops pulsing
until this level goes back to 500 mV to prevent any
instability. During brown--out conditions, the PFC is
not activated.
Short--circuit Protection: Short--circuit and especially
overload protection are difficult to implement when a
strong leakage inductance between auxiliary and power
windings affects the transformer (the auxiliary winding
level does not properly collapse in presence of an
output short). Here, every time the internal 0.8 V
maximum peak current limit is activated, an error flag
is asserted and a time period starts, due to an external
timing capacitor. If the voltage on the capacitor reaches
4.0 V (after 90 ms for a 220 nF capacitor) while the
error flag is still present, the controller stops the pulses
and goes into a latch--off phase, operating in a
Blanking Time: To prevent false tripping with energetic
leakage spikes, the controllers includes a 3 ms blanking
time after the toff event.
Go--to--Standby Signal for PFC Front Stage: The
NCP1381/82 includes an internal low impedance
switch connected between Pin 10 (VCC) and Pin 11
(GTS). The signal delivered by Pin 11 being of low
impedance, it becomes possible to connect PFC’s VCC
directly to this pin and thus avoid any complicated
interface circuitry between the PWM controller and the
PFC front--end section. In normal operation, Pin 11
routes the PWM auxiliary VCC to the PFC circuit which
is directly supplied by the auxiliary winding. When the
SMPS enters skip--cycle at low output power levels, the
controller detects and confirms the presence of the skip
activity by monitoring the signal applied on its pin
ADJ_GTS (typically FB signal) and opens Pin 11,
shutting down the front--end PFC stage. When this
signal level increases, e.g. when the SMPS goes back to
a normal output power, Pin 11 immediately (without
delay) goes back to a low impedance state. Finally, in
short--circuit conditions, the PFC is disabled to lower
the stress applied to the PWM main switch.
Low Startup--Current: Reaching a low no--load standby
power represents a difficult exercise when the
controller requires an external, lossy, resistor connected
to the bulk capacitor. Due to a novel silicon
architecture, the startup current is guaranteed to be less
than 15 mA maximum, helping the designer to reach a
low standby power level.
low--frequency burst--mode. As soon as the fault
disappears, the SMPS resumes its operation. The
latchoff phase can also be initiated, more classically,
when VCC drops below VCCOFF (10 V typical).
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NCP1381, NCP1382
Startup sequence
AssoonasVCC reaches15 V(VCCON),drivingpulsesare
delivered on Pin 9 and the auxiliary winding grows up the
When the power supply is first connected to the mains
outlet, theNCP1381/82startstoconsumecurrent. However,
due to a novel architecture, the internal startup current is
kept very low, below 15 mA as a maximum value. The
current delivered by the startup resistor also feeds the VCC
capacitor and its voltage rises. When the voltage on this
capacitor reaches the VCCON level (typically 15 V), the
controller delivers pulses and increases its consumption. At
thistime,theVCC capacitoralonesuppliesthecontroller:the
auxiliary supply is supposed to take over before VCC
collapses below VCCOFF. Figure 3 shows the internal
arrangement of this structure:
VCC pin. Because the output voltage is below the target (the
SMPS is starting up), the controller smoothly pushes the
peak current to Imax (0.8 V / Rsense) which is reached after
5 ms (typical internal soft--start period). After soft--start
completion, the peak current setpoint reaches its maximum
(during the startup period but also anytime a short--circuit
occurs), an internal error flag is asserted, IP Flag, testifying
that the system is pushed to the maximum power (IP = IP
maximum). This flag is used to detect a faulty condition,
where the converter asks for the maximum peak capability
longer than what has been programmed by the designer. The
duration of the faulty condition is actually set up by a
capacitor connected to Pin 4.
High Voltage
Figure 4 shows a portion of this internal arrangement. If
the fault comparator acknowledges for a problem, the
controller stops all driving pulses and turns--on the internal
ICC3 current--source. This source serves for the latch--off
phase creation, that is to say, forcing the VCC to go down,
despite the presence of the startup current still flowing via
the startup resistor. Therefore, ICC3 should be greater than
I
total
R
startup
I
startup
10
I
total to ensure proper operation. When VCC reaches a level
Auxiliary
Winding
UVLO
+
--
of 7 V, ICC3 turns to zero and the startup current can lift VCC
up again. When VCC reaches 15 V, a new attempt is made.
If the fault is still there, pulses last either the timer duration
or are prematurely stopped if a VCCOFF condition occurs
sooner, and a new latchoff phase takes place. If the fault has
gone, theconverterresumesoperation. Figure 5portraysthe
waveforms obtained during a startup sequence followed by
a fault. One can see the action of the ICC3 source which
createsthelatchoffphaseandthevariousresetseventsonthe
timercapacitorinpresenceofthesoft--startendoranaborted
fault sequence.
+
CV
+
CC
VCC
VCC
ON
OFF
8
Figure 3. The Startup Resistor Brings VCC
Above 15 V
HV
Knowing that Itimer equals 10 mA, we can calculate the
capacitor needed to reach 4 V in a typical time period.
Suppose we would like a 100 ms fault duration, therefore:
Ctimer = 10 m x 100 m / 4 = 250 nF, select a 0.22 mF.
R
startup
V
CC
10
V
CC
Management Latchoff
+ CV
I
CC3
CC
V
DD
I
timer
+
--
4
Fault
Confirmed
+
C
timer
4.0 V
Soft--Start
Soft--Burst
SW
Reset
I
Flag
P
Figure 4. The Timer Section Uses a Current Source
to Charge Up the Capacitor
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7
NCP1381, NCP1382
Figure 5. A Typical Startup Sequence Followed by a Faulty Condition
Startup Resistor Calculation
above: Icharge > 15 x 22 u / 2 > 165 mA. If we add
the 15 mA of ICC1, the total startup current shall be
above 180 mA.
For the sake of the example, we will go through the
calculation of the startup element. Suppose that we have the
following information:
3. The minimum input voltage is 85 x 1.414 = 120 V.
Then, Rstartup should be below (120 -- 15) / 180 m
< 580 kΩ.
VCCON = 15 V.
VCCOFF = 10 V.
4. From this value, we can calculate the dissipated
power at high line: Pstartup = (265 x 1.414)2 / 580 k
= 242 mW.
I
CC2 = 4 mA, given by the selected MOSFET Qg.
Startup duration below 2 s at minimum input voltage.
Input voltage from 85 VAC to 265 VAC.
Standby power below 500 mW.
In latched mode, an internal zener diode is activated and
clamps VCC to around 6 V. When VCC goes below 4 V, this
zener is relaxed and the circuit can startup again.
1. From a startup ΔV of 15 -- 10 = 5 V and a 4 mA
total consumption, we can obtain the necessary
VCC capacitor to keep enough voltage, assuming
Please note that in fault mode the VCC comparator has the
priority and stops the pulses anytime VCC falls below its
the feedback loop is closed within 10ms: CVCC
=
4 m x 10 m / 5 = 8 mF or 22 mF for the normalized
value if we account for the natural dispersion.
2. If we want a startup below 2 s, then the charging
current flowing inside the VCC capacitor must be
minimum operating level VCCOFF
.
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8
NCP1381, NCP1382
V
CC
TW
VCC
ON
VCC
OFF
t
OFF
Leakage
Ringing
DRV
1st Valley
t
ON
Figure 7. Typical Quasi--Resonance Waveform
100 ms
Bunch Length Given by Timer
< 100 ms
I
Bunch Length Given
peak
(Vout + Vf)
by VCC
Vin
LP
OFF
sOFF = N ⋅
sON
=
LP
If V drops below VCC
during a portion where the timer
OFF
CC
counts, pulses are immediately stopped and the latchoff phase
is entered. Here, in this example, the timer was set to 100 ms.
Figure 6.
I
= 0
P
ON
OFF
Quasi--Resonance Operation
0
Quasi--Resonance (QR) implies that the controller
permanently monitors the transformer core flux activity and
ensures Borderline Conduction Mode (BCM) operation.
That is to say, when the switch closes, the current ramps up
in the magnetizing inductance LP until it reaches a setpoint
imposed by the feedback loop. At this point, the power
switch opens and the energy transfers from the primary side
to the secondary (isolated) portion. The secondary diode is
now biased and the output voltage “flies back” to the
primary side, now demagnetizing the primary inductance
LP. When this current reaches zero, the transformer core is
said to be “reset” (φ = 0). At this time, we can turn the
MOSFET on again to create a new cycle. Figure 7 and 8
portray the typical waveforms with their associated
captions. If a delayTWisintroducedfurther tothe core reset
detection and before biasing the power MOSFET, the drain
signal Vds(t) has the time to go through a minimum, also
called valley. Therefore, when we will finally reactivate the
power MOSFET, its drain--to--source voltage will be
minimum, reducing capacitive losses but also its
gate--charge value, since the Miller effect gets diminished at
low Vds.
TW
Figure 8. Magnetizing Inductance Current
Waveforms
The flux activity monitoring is actually made via an
auxiliary winding, obeying the law, Vaux = N . dφ / dt.
Figure 9 describes how the detection is made, since the
signal obtained on the auxiliary winding is centered to zero.
Let’s split the events with their associated circuitry:
tON
The D flip--flop output is high, the MOSFET is enhanced
and current grows--up in the primary winding. This is the on
portion of Figure 8, left side of the triangle. When the driver
output went high, its rising edge triggered a 8 ms timer. This
8 ms timer provides a true frequency clamp by driving the
D--input of the flip--flop. Now, when the peak current
reaches the level imposed by the feedback loop, a reset
occurs and the flip--flop output comes low.
If for any reason the controller keeps the gate high
(DRVout) implying a tON longer than 50 ms, then all pulses
are stopped and the controller enters a safe, autorecovery,
restart mode. This condition can occur if the current sense
pin does not receive any signal from the sense resistor or if
a short--circuit brings the CS pin to ground for instance.
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NCP1381, NCP1382
tOFF
frequency to 8 ms or 125 kHz. Please note that the 8 ms timer
clamps tON + tOFF
As one can see from Figure 7, a parasitic ringing takes
.
place at the switch opening: this is the leakage inductance
contribution. Unfortunately, this leakage can be detected as
a core reset event if no precaution is taken. This explains the
presence of the 3 ms blanking timer that prevents any restart
before the completion of this circuit. After leakage, the
voltage applied over the primary winding is an image of the
output voltage: this is the flyback level, or plateau level,
equal to N(Vout + Vf), with N the turn ratio between the
primary and the secondary, Vout the output voltage and Vf,
the secondary diode forward drop. We are on the right
portion of Figure 8, OFF portion, the secondary current
ramping down. If we now observe the voltage on the
auxiliary winding, we will see something like what
Figure 10 shows where the plateau lasts until the core is
reset. At this reset event, a natural ringing takes place whose
amplitude depends on the ratio N and Vout. A comparator
observes this activity and detects when the voltage drops
below ground, actually below 45 mV typically. In Figure 9,
one can see the ESD protection arrangement which
introducesasmallcapacitivecomponenttoPin 3input. This
capacitive component associated with the demagnetization
resistor can thus realize the necessary above TW delay.
The comparator output now propagates to the clock input
of a D flip--flop. Hence, the demagnetization is edge
triggered. At the beginning of the cycle (the rising edge of
the ON time), the 8 ms timer was started. The output of this
timer goes to the D--input of the D flip--flop. Thus, if the
demagnetization comparator attempts to trip the D flip--flop
when the 8 ms timer has not been completed, the restart is
ignored until a new demagnetization signal comes in. This
offers the benefit to clamp the maximum switching
If everything is met, then the flip--flop output goes high
and a new switching cycle occurs. Several events can alter
this behavior, as described below:
1. The converter is in light load conditions and the
theoretical frequency is above 125 kHz. There, the
D--input is not validated and the reset event is
ignored. The flip--flop waits for another wave to
appear. If outside of the 8 ms window, i.e. Fswitching
below 125 kHz, the event is acknowledged and a
new cycle occurs. Note that wave skipping will
always occur in the drain--source valley.
2. We are skipping cycle at moderate power and the
skip comparators dictates its law. In that case, if
the flip--flop is permanently reset, it naturally
ignores all demagnetization restart attempts,
provided that the drain oscillations are still there.
When the flip--flop reset is released, the controller
acknowledges the incoming demagnetization order
and drives the output high. Again, skip cycles
events always take place in the valley.
3. The controller skips cycles at low power and the
order appears in a fully damped drain--source
portion. In that case, the 8 ms timeout generator
will give the signal in place of the demagnetization
comparator. This timeout generator is reset
everytime waves appear but starts to count down
when there is no sufficient amplitude on the drain.
At the end of the 8 ms, if no wave has appeared, it
goes high, indicating that the controller is ready to
restart anytime a skip order takes place. See skip
section for more details.
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10
NCP1381, NCP1382
V
DD
S
V
D
Q
Q
DD
+
--
CLK
R
+
3 ms
Blanking
S
DRV
Demag
2
D
Q
Q
DRV
--
CLK
+
Prioritary
Reset
+
R
45 mV
One
Shot
DRV
V
V
DD
DD
Skip
I
Limit
Reset Reset
+
--
+
--
+
+
Fault
Figure 9. Internal QR Architecture
Skipping Cycle Mode
7.00
5.00
The NCP1381/82 automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, pin 6 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so--called skip cycle mode, also
named controlled burst operation. The power transfer now
dependsuponthewidthofthepulsebunches(Figure 11)and
follows the following formula:
Possible
Restart
3.00
1.00
45 mV
0 V
--1.00
1
2
Figure 10. Core Reset Detection is Done Through the
Monitoring of a Dedicated Auxiliary Winding
⋅ L ⋅ I 2 ⋅ F ⋅ D
burst
(eq. 1)
P
P
sw
with
LP = Primary Inductance
sw = Switching Frequency Within the Burst
IP = Peak Current at which Skip Cycle Occurs
burst = Burst Width/Burst Recurrence
F
D
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11
NCP1381, NCP1382
V
Figure 12 depicts the internal comparator arrangement.
The FB pin level is permanently compared to a fixed level,
skip, also available on Pin 5 for adjustment. As a result, the
DD
V
6
user can wire a resistor to ground and alter the skip level in
case of noise problems. When the FB pin is above Vskip, the
comparator is transparent to the operation. When the load
becomes lighter, the FB level goes down too. When it
reaches Vskip, the comparator goes high and resets the
internalflip--flop:thedrivingpulsesarestopped. Asaresult,
Vout starts to also decrease since no energy transfer is
ensured. Detectingadecayintheoutputvoltage,theFBloop
will react by increasing its level. When the level crosses
V
DD
Soft--Start
Activation
30 mA
--
V
Reset
skip
+
5
Hysteresis = 50 mV
R
25 k
8
Vskip plus a slight hysteresis, pulses restart again: a ripple
occurs on the FB pin. Please note that the soft--start will be
activated every time the skip comparator asks to restart.
Therefore, insteadofhavingsharpskiptransitions, asmooth
current rampup can be observed on the current envelope.
This option significantly decreases the acoustical noise.
Figure 13 shows a typical shot and Figure 15 portrays
several skip cycles.
Figure 12. A Resistor to GND can Adjust the Skip
Level
As soon as the feedback voltage goes up again, there can
be two situations as we have seen before: in normal
operating conditions, e.g. when the drain oscillations are
generous, the demagnetization comparator can detect the
45 mV crossing and gives the “green light”, alone, to
reactive the power switch. However, when skip cycle takes
place (e.g. at low output power demands), the restart event
slidesalongthedrainringingwaveforms(actuallythevalley
locations) which decays more or less quickly, depending on
theLprimary-- C parasitic networkdampingfactor. Thesituation
can thus quickly occur where the ringing becomes too weak
to be detected by the demagnetization comparator: it then
permanently stays locked in a given position and can no
longer deliver the “green light” to the controller. To help in
this situation, the NCP1381/82 implements a 8 ms timeout
generator: each time the 45 mV crossing occurs, the timeout
is reset. So, as long as the ringing becomes too low, the
timeout generator starts to count and after 8 ms, it deliversits
“green light”. If the skip signal is already present then the
controller restarts; otherwise the logic waits for it to release
the reset input and set the drive output high. Figure 14
depicts these two different situations:
Maximum
Peak Current
200
Skip Cycle
Current Limit
100
0
Width
Recurrence
Figure 11. The Skip Cycle Takes Place at Low Peak
Currents Which Guaranties Noise Free Operation
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12
NCP1381, NCP1382
Figure 13. The Soft--start Starts During Skip Mode
Figure 15. The Internal Soft--start is Activated During
Each Skipped Cycles
and Smooths the Current Signature
Overpower Compensation
A
FLYBACK converter operating in Borderline
Conduction Mode (BCM) transfers energy from primary to
secondary according to the following law:
P
out
1
2
⋅ L ⋅ I 2 ⋅ FSW
P P
(eq. 2)
P
in
=
=
η
Therefore, we can see that for various switching frequency
values (dependent on the input condition if the output
demand is fixed), the converter will permanently adjust the
peak current IP to keep the output power constant. By
manipulating the slope definitions SON and SOFF (see
Figure 8), we can show that the peak current is defined by:
Demag Restart
N ⋅ (V
out
+ V ) + V
in
F
(eq. 3)
I
= 2 ⋅ P ⋅
out
P
Current Sense and Timeout Restart
η ⋅ V ⋅ N ⋅ (V
in out
+ V )
F
where η is the converter’s efficiency, Vin the input voltage,
Vout the output voltage. Feeding a math processor lets us
graph the peak variation with the input voltage, as depicted
by Figure 16 for a 90 W converter operating on universal
mains and featuring the following parameters:
Vout = 19 V @ 4.7 A,
NP:NS = 1:0.166,
Rsense = 0.25 Ω, 200 VDC -- 400 VDC Input Voltage,
tP (Propagation Delay) = 100 ns,
LP = 700 mH, η = 0.85 and VF = 0.8 V
Notethattheseelementswereselectedtodesignfor a100 W
value, giving us design margin.
8 ms
8 ms
Figure 14. The 8 ms Timeout Helps to Restart the
Controller
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13
NCP1381, NCP1382
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
4
3
2
1
0
Required I
Pmax
200
250
300
V , VOLTAGE (V)
350
400
0
20
40
60
80
100
P
O
in
Figure 16. Peak Current Evolution with Input
Voltage in a QR Converter at Constant Output
Power (100 W)
Figure 17. IP Evolution with Output Power
As a result, we will probably calculate our sense resistor
to let the converter bring the peak currentup to3.15 A atlow
mains (200 VDC in follower--boost configuration).
Unfortunately, in high mains conditions, where the PFC
delivers up to 400 VDC, the controller will also allow the
same 3.15 A maximum peak current (even a little more with
the propagation delay) and the power will dramatically
increase. In these conditions, the maximum power shall
absolutely be clamped in order to avoid lethal runaways in
presenceof afault. If overpower compensationvia aresistor
tothebulkcapacitoroffersapossibleway, itsuffersfromthe
lackofprecisionandgoodrepeatabilityinproduction.Italso
degrades the standby consumption.
variable offset that will compensate the maximum output
power. This would result in a variable IPmax as exemplified
by the dashed line on Figure 16.
From the peak current definition, we can extract the
output power variation, with a fixed peak current (the
maximum peak the controller will authorize is 0.8 / Rsense
)
and thus quantify the difference between low and high line:
0.8
V
L
in ⋅ t
P
+
R
S
P
P (V ) :=
nc in
(eq. 4)
V
2
in
⋅ V
+ V
+
N
out
F
(η⋅(V ⋅(V +V )))
in out
F
where
tP is the propagation delay (100 ns typically).
Since our controller integrates a brown--out (BO)
protection that permanently senses the bulk capacitor, we
naturally have a voltage image of the bulk voltage. By
converting the BO level into a current, then routing this
current in the current sense (CS) pin, we can easily create a
If we enter our previous parameters into the
noncompensated output power definition and plot the result
versustheinputvoltage, thenweobtainthefollowinggraph,
Figure 18:
130
125
120
115
110
105
100
I
LL
P
0.8 V
0.64 V
t
200
250
300
V , VOLTAGE (V)
350
400
in
Figure 19. A Possible Way to Compensate the
Current Excursion Lies in Offsetting the
Current Floor
Figure 18. Output Power Evolution with the Input
Voltage (No Compensation)
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NCP1381, NCP1382
Asonecanobserve, theoutputpowerrunsoutoftheinitial
0.25 = 653 mV at high line. Figure 19 shows the situation at
both line levels. A possible solution lies in offsetting the
current floor by the necessary value, which is, in our case,
0.8 -- 0.653= 147 mV. The traditionalway of doing thisgoes
through the wiring of a high value resistor to the bulk
capacitor. This unfortunately dissipates heat. The
NCP1381/82 offers a more elegant option since it
transforms the voltage available from the Brown--out pin
into a fixed current, routed to the CS pin. That way, we can
calculate a resistor value which, once inserted in series with
currentsensevoltageimage,willcreateournecessaryoffset.
Figure 20 shows this internal connection:
100 W specification when we enter the high line region. To
cope with this problem, we need to compensate the
controller in such a way that its peak capability gets reduced
at higher input voltages. How much do we need to
compensate the peak excursion? We can find the answer by
calculating ΔIP = IPLL -- I PHL, with VinLL = 200 V and VinHL
= 400 V. With our previous numbers, ΔIP = 588 mA. We
therefore need to instruct the controller to reduce its peak
excursionby588 mAathighline. Otherwisespeaking, ifwe
thinkinvoltages, theCSpinexcursionshalldropfrom0.8 V
(at low line, the maximum peak is 0.8 / RS) to (3.2 -- 0.588).
V
bulk
G1
80 mS
105
--
BO
+
100
95
To BO
Comp.
CS
R
offset
90
R
sense
200
250
300
350
400
V , VOLTAGE (V)
in
To CS Comp.
Figure 21. The Compensated Converter Output
Power Response to Input Variations
Figure 20. A Transconductance Amplifiers
Transforms the BO Voltage into a Current
We can now calculate our Roffset resistor to generate the
necessary static voltage. Suppose that the BO network
divides the bulk voltage by 400 (VBO = α . Vin = 0.0025 x
Vin). Therefore, in presence of a 400 V input voltage, we
will have 1 V on the BO pin. due to the transconductance
amplifier of a 80 mS gm, it will turn into a 80 mA offset
current. To get our 147 mV, we just divide it by 80 mA:
Roffset = Voffset / VinHL x α . gm = 1.8 kΩ.
were originally shooting for and the total power excursion
is now kept within 15 W.
Overvoltage Protection
The NCP1381/82 features an overvoltage protection
made by sensing the plateau voltage at the switch turn--off.
However, a sampling delay is introduced to avoid
considering the leakage inductance. When the
demagnetization pin goes above Vdemlatch, the comparator
goes high. If this condition is maintained when the sampling
pulse arrives, then a fault is latched. Figure 22 shows the
arrangement and Figure 23 portrays a typical waveform.
Oncelatched, thecontroller stopsalldrivingpulsesandVCC
is clamped to 6 V. Reset occurs when the user unplugs the
converter from the mains and VCC reduces below 4 V.
We can now update Equation 4 with Equation 5, where
the peak current is affected by the variable offset:
0.8
V
in ⋅ t
−
V
in
⋅ α ⋅ g ⋅ R
m
offset
+
P
R
L
S
P
P (V ) :=
O in
2
V
in
(eq. 5)
⋅ V
+ V
+
N
out
F
(η⋅(V ⋅(V +V )))
in out
F
If we now plot the compensated curve, we obtain
Figure 21graph.Theoutputpowerisslightlyabovewhatwe
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15
NCP1381, NCP1382
Demag
To Demag
Comp.
700
500
300
+
- -
+
V
latchdem
100
1 Shot
Timer
Latch
Input
--100
T
samp
58.5
62.5
66.5
TIME (mS)
70.4
74.4
Figure 23. Typical Sensed Waveforms
DRV
Figure 22. Plateau Sensing Overvoltage Protection
External Latchoff
occurswhenVCC fallsbelow4 V,e.g. whentheuserunplugs
the converter from the mains. Figure 24 shows several
options on how to connect a PNP to implement an OVP or
Overtemperature Protection (OTP).
By lifting up Pin 5 above Vlatch (3.5 V Typ -- NCP1381,
2.5 V Typ -- NCP1382), the circuit is permanently latched.
Thatistosay, Pin 9goeslow, theGTSpinnolongersupplies
the PFC and the VCC is clamped to 6 V. The latch reset
V
ref
OVP
V
ref
OVP
Skip
Skip
+
- -
+
- -
Skip
Latch
Latch
NTC
+
+
V
latch
V
latch
V
< 5 V!
max
Figure 24. Wiring a PNP Transistor on the Skip Cycle Input Pin will Latch the Circuit.
Go--To--Standby detection
Keep in mind that the 5 V maximum limit on all low
voltage pins implies some precaution when triggering the
latch voltage. The cheapest option is obtained when wiring
a simple zener diode in series with the monitored line. Care
must be taken to limit the excursion of the skip pin before
fully latching the controller.
The PFC front--end stage delivers an elevated voltage to
the Flyback converter and keeps the mains power factor
close to unity. However, in standby, this PFC stage is no
longer needed and must be turned off to save watts and thus
reduce the no--load standby power. To detect when the
converter enters standby, the controller observes the voltage
available on Pin 1: typically, a portion of the feedback
voltage will be used. In higher power conditions, this level
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16
NCP1381, NCP1382
N ⋅ (V
+ V ) + V
F in
is high, in low power conditions, this voltage is low.
out
V
L
in
P
) := 2 ⋅ P
⋅ tP
F (V
⋅
−
B
in
O
Unfortunately,thesituationcomplicateswithQRconverters
since the input voltage plays a significant role in the
feedback voltage evolution. A case can happen where the
converter is supplied by a 400 V rail and suddenly enters
standby: the PFC turns off and the bulk voltage goes low,
let’s say 120 VDC (Vin = 85 VAC). At this time, the power
transfer changes, the propagation delay plays a smaller role
and the feedback voltage naturally goes up again. If a
sufficient hysteresis is not built, there are possibilities to see
hiccup on the PFC VCC, which is not a desirable feature.
Therefore, hysteresis is mandatory on top of the
Go--To--Standby (GTS) detection level. For this reason it is
possible to increase the hysteresis of the ADJ_GTS
comparator due to an internal 5 mA current source that can
create an offset to the input signal if a series resistor is
inserted. The ADJ_GTS detectionlevel isalso adjustable by
tuning the portion of the external signal applied to Pin 1 (the
reference of the internal comparator is 250 mV).
η ⋅ V ⋅ N ⋅ (V
+ V )
F
in out
(eq. 6)
⋅ R ⋅ F
S
BCS
WhereFBCS istheratiobetweentheFBlevelandthecurrent
setpoint. In our controller, this ratio is 4. If we now
incorporate our offset voltage generated by the Roffset
resistor and the input voltage, the compensated FB variation
expression becomes:
N ⋅ (V
+ V ) + V
F in
out
η ⋅ V ⋅ N ⋅ (V
(eq. 7)
2 ⋅ P
F
(V ) :=
BComp in
⋅
O
⋅ V )
in
out
F
V
in
P
−
⋅ t ] ⋅ R + V ⋅ α ⋅ g ⋅ R ]
P
S
in offset
m
L
⋅ F
BCS
with α the BO divider ratio (0.00414 in our example), gm
the transconductance slope of 80 mS and Roffset, the selected
offset resistor.
If now plot Equation 6 and Equation 7 for a 8 W output
power, we will obtain Figures 25 and 26:
Again, to check how we manage the feedback variations,
we can plot these variations without compensation for a
givenpower, andwiththe offsetresistor connectedtotheCS
pin. In the first case, the FB voltage dependency on Vin can
be expressed by:
0.35
0.3
0.75
0.7
0.65
0.6
0.25
0.2
0.55
0.5
0.15
0.1
0.45
100
150
200
250
300
350
400
100
150
200
250
300
350
400
V , VOLTAGE (V)
in
V , VOLTAGE (V)
in
Figure 25. Uncompensated FB Variations for
out = 8 W
Figure 26. Compensated FB variations
out = 8 W
P
P
As one can see on Figure 26, the FB level now falls down
when the PFC is shut off. It now goes in the right direction
(FB growing up with Vin) and this plays in our favor to not
cross again the upper comparison level, as it could be the
case in Figure 25. However, we must check that the offset
programmed by Roffset (147 mV in our example) multiplied
by 4, is still below our skip cycle level, otherwise the
converter will never enter skip at high line (the permanent
offset at high line will force a higher feedback):
PFC will be shutdown at Pout = 8 W, or a bit less than 10%
of the nominal power. If the designer needs to increase or
decrease this value, it can adjust the ADJ_GTS level, still
keeping in mind Equation 8 relationship.
To avoid a false tripping, the timer (90 ms with Pin 4
capacitor of 220 nF) will be started every time the GTS
signal goes high. If at the end of the 90 ms the GTS signal
is still high, the standby is confirmed and the SW switch
between Pins 11 and 10 opens. To the opposite, when the
output power is needed, there is no delay and the SW switch
turns on immediately. Figure 27 zooms on the internal
circuitrywhereasFigure 28showstypicalsignalevolutions:
(eq. 8)
0.147 ⋅ 4 = 588 mV < 0.75 V
This is okay.
The drawback of Figure 26 is the higher forced level for
lower power outputs. In our example, a 90 W adapter, the
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NCP1381, NCP1382
V
To PFC
DD
GTS
V
CC
5 mA
Ext, SIgnal
(FB, AUX)
V
CC
CV
CC
ADJ_GTS
V
+
DD
R
hyst
--
Timer
+
+
- -
250 mV
+
Figure 27. The SW Switch is Turned Off After the Timer Confirms the Presence of a Standby
During the startup sequence, the PFC is disabled (in short--circuits too) and runs as soon as the I Flag goes down. When the standby is
P
detected, the timer runs and confirms the standby mode. When the mode is left, there is no delay and the PFC is turned--on immediately.
Figure 28.
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18
NCP1381, NCP1382
HV
During the startup sequence, the converter starts by itself,
the PFC is in off mode (SW switch is open). However, when
the IP Flag is down, without delay, the PFC is turned on. In
short--circuit mode, the IP Flag is constantly high during
startup attempts and the PFC never turns on. This option
reduces the stress on all the elements. The PFC is also in off
mode when in presence of a brown--out detection.
Inbrown--outconditions, thePFCisturned--off. Whenthe
level on Pin 2 is back to normal conditions, then a clean
startup sequence takes place as Figure 28 depicts and the
PFC turns on after the IP Flag release. The bullets below
summarize what we have described:
BOK
OPP
R
upper
+
- -
2
+
250 mV/
500 mV
R
lower
1. On startup, the PFC is turned on immediately after
the IP Flag has disappeared (converter is
stabilized). There is no delay.
2. If a short--circuit occurs, a delay takes place before
shutting off the driving pulses. When the delay is
elapsed, pulses are turned off and the PFC goes in
the off mode. The controller starts to hiccup.
3. In short--circuit hiccup mode, as IP Flag always
stays high (in short--circuit, there is no FB signal),
the PFC is never activated.
4. if a VCCOFF condition occurs, all pulses are
immediately shutdown and the PFC VCC goes low
as well.
8
Figure 29. A Way to Implement a BOK Detector
on Pin 2
The calculation procedure for Rupper and Rlower requires
a few lines of algebra. In this configuration, the first level
transition is always clean: the SMPS is not working during
the startup sequence and no ripple exists superimposed on
bulk. Supposed we want to start the operation at
bulk = Vtrip = 120 VDC (VinAC = 85 V).
C
V
5. if a brown--out condition is sensed, all pulses are
immediately shut down and the PFC VCC goes low
as well.
1. Fix a Bridge Current Ib Compatible with Your
standby Requirements, for Instance an Ib of 50 mA
2. Then Evaluate Rlower by: Rlower = 0.5 / Ib = 10 kΩ
3. Calculate Rupper by:
The freedom is given to the designer to use an other signal
than the FB to detect the standby mode and shutdown the
PFC (the voltage from the auxiliary winding, or the average
of the DRV signal for instance).
(Vtrip -- 0 . 5 V ) / I b = (120 -- 0.5) / 50 m = 2.39 MΩ
The second threshold, the level at which the power supply
stops (Vstop), depends on the capacitor Cfil but also on the
selected bulk capacitor. Furthermore, when the load varies,
the ripple also does and increases as Vin drops. If Cfil allows
too much ripple, then chances exist to prematurely stop the
converter. By increasing Cfil, you have the ability to select
the amount of hysteresis you want to apply. The less ripple
appears on Pin 2, the larger the gap between Vtrip and Vstop
(themaximumbeingVstop =Vtrip /2). Thebestwaytoassess
the right value of Cfil, is to use a simple simulation sketch as
theonedepictedbyFigure 30. Abehavioralsourceloadsthe
rectified DC line and adjusts itself to draw a given amount
of power, actually the power of your converter (35 W in our
example). The equation associated to Bload instructs the
simulator to not draw current until the brown--out converter
gives the order, just like what the real converter will do. As
a result, Vbulk is free of ripple until the node CMP goes high,
giving the green light to switch pulses. The input line is
modulated by the “timing” node which ramps up and down
to simulate a slow startup / turn--off sequence. Then, by
adjusting the Cfil value, it becomes possible to select the
right turn off AC voltage. Figure 31 portrays the typical
signal you can expect from the simulator. We measured a
turn on voltage of 85 VAC whereas the turn--off voltage is
72 VAC. Further increasingCfil lowersthislevel(e.g. a1 mF
gives 65 VAC in the example).
Brown--Out Protection
Alsocalled“BulkOK”signal (BOK), thebrown--out(BO)
protection prevents the power supply from being adversely
destroyed in case the mains drops to a very low value. When
this occurs, the controller no longer pulses and waits until
the bulk voltage goes back to its normal level. A certain
amount of hysteresis needs to be provided since the bulk
capacitor is affected by some ripple, especially at low input
levels. For thatreason, whenthe BOcomparator toggles, the
internalreference voltage changesfrom500 mVto250 mV.
This effect is not latched: that is to say, when the bulk
capacitor is below the target, the controller does not deliver
pulses. As soon as the input voltage grows--up and reaches
the level imposed by the resistive divider, pulses are passed
to the internal driver and activate the MOSFET. Figure 29
offers a way to connect the elements around Pin 2 to create
a brown--out detection. Please note that this technique does
not use a current source for the hysteresis but rather a
capacitor. It offers a way to freely select the resistive bridge
impedance.
http://onsemi.com
19
NCP1381, NCP1382
Bulk
+
V
load
2
3
+
V(line) × V(timing)
C
bulk
B
B1
load
IN
47 mF
= 40
Voltage
Current
Δ
I
35
C
V
> 3 ?
: 0
--
(CMP)
V
(bulk)
PSpice
EBload
:
35
Value = IF (V
, 0)
> 3,
(CMP)
Bulk
R
V(bulk)
Line
Timing
+
upper
+
TiCMP
+
V1
V2
Brown Out
--
5
+
C
220 n
fil
B
brown
R
lower
Voltage
V(CMP) > 3 ? 250 m : 500 m
PSpice
V1 Timing 0 PWL 0 0.2 3s 1 7s 1 10s 0.2
V2 Line 0 SIN 150 50
:
> 3, 250 m, 0)
EBbrown Value = IF (V
(CMP)
Figure 30. A Simple Simulation Configuration Helps to Tailor the Right Value for Cfil
Turn--off Voltage Occurs at:
= 72.3 V
200 16
100 12
V
inRMS
0
--100
--200
8
4
0
V
brown--out
8.156
8.175
8.195
8.215
8.235
Figure 31. Typical Signals Obtained from the Simulator
Brown--out internal circuit
Giventhelowstartupcurrentandtheweakoverallconsumptionof thecontroller, acircuitneedstobefoundinorder tocreate
a hiccup mode when there is not enough mains detected on Pin 2. Figure 32 portrays the solution based on a 1mA current
source, solely activated when the VCC is going low and the BOK has not authorized the controller to pulse. This 1 mA actually
discharges the VCC capacitor to make VCC reach 10 V. At this point, the source goes to zero and the startup resistor replenishes
the VCC capacitor. When we reach 15 V, the logic checks whether the BOK gives the green light. If not, VCC goes low via the
1 mA. The logic arrangementismade in sucha waythat if the mainscomes backasynchronously toVCC (e.g. in the downslope
or in the upslope), we always restart at VCC = 15 V. Figure 33 shows a simulated behavior with a mains going up and down.
Figure 34 and 35 confirm the good restart synchronization with the 15 V level.
http://onsemi.com
20
NCP1381, NCP1382
I
Flag
P
GTS
SS
V
bulk
One
Shot
Reset
Activated During Fault Only
V
+
DD
--
+
+
VCC
VCC
ON
R
2
+
--
startup
4
latch
C
timer
+
+
--
11
I
CC3
+
8
CV
CC
VCC
VCC
ON
OFF
+
--
8
S
R
Q
Q
One
Shot
Fault
Simplified Timer for
and Fault Only
B
OK
Fault
S
OK to
Pulse
Q
Q
S&R are Positive
Edge Triggered
R
Figure 32. The Internal Brown--out Circuit
Figure 32 also includes the short--circuit latch--off phase generation. The difference between behaviors in BO or
short--circuit, is the lack of latch--off phase in brown--out conditions: VCC ramps up and down between VCCON and VCCOFF
in BO, whereas it goes down to 7 V and up to 15 V in short--circuit conditions. Figure 36 shows how VCC moves when a
short--circuit is detected. In BO conditions, the PFC is disabled as in UVLO conditions.
http://onsemi.com
21
NCP1381, NCP1382
200
160
120
80
Plot1
Bulk Voltage
40
35
25
Plot2
2
15
5.0
-- 5 . 0
V
CC
6.5
4.5
Plot3
3
2.5
500m
-- 1 . 5
Internal OK Signal
10.0m
30.0m
50.0m
70.0m
90.0m
TIME (s)
The mains goes up and down, the bottom signal stops pulses at low mains but reactivates them when V = 15 V.
CC
Figure 33.
35.0
Plot2
V
CC
25.0
15.0
5.00
--5.00
6.5
4.5
Plot3
Plot1
P
Reset
ON
2.5
500m
-- 1 . 5
14
10
B
OK
6.0
2.0
-- 2 . 0
41.3m
41.8m
42.4m
42.9m
43.5m
TIME (s)
The B comes back in the descent but the logic waits until the UVOL circuitry detects 15 V to restart the controller.
OK
Figure 34.
http://onsemi.com
22
NCP1381, NCP1382
35
25
15
Plot2
V
CC
5.0
-- 5 . 0
41.3m
Plot3
41.8m
42.4m
42.4m
42.9m
43.5m
43.5m
6.5
4.5
2.5
500m
-- 1 . 5
P
Reset
ON
41.3m
Plot1
41.8m
42.9m
14
10
6.0
B
OK
2.0
-- 2 . 0
41.3m
41.8m
42.4m
42.9m
43.5m
TIME (s)
The B comes back in the upslope but the logic 2 waits until UVOL circuitry detects 15 V to restart the Controller.
OK
Figure 35.
8.50
6.50
18.0
14.0
10.0
6.00
2.00
15 V
V
CC
4.50
2.50
V
OK
500m
20.0m
60.0m
100m
140m
180m
TIME (s)
In short--circuit, the V drops to VCC
and goes up to 15 V. The blue trace corresponds to the “ok to pulse” signal whose duration is
latch
CC
given by the fault timer (purposely reduced on this simulation). Should a VCC
condition be detected, or a B fault, the duration would
OFF
OK
be accordingly truncated.
Figure 36.
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23
NCP1381, NCP1382
VCC
ON
V
CC
VCC
OFF
VCC
latch
Timer
V
in
Short--Circuit
Interruption
UVLO Interruption
BO Interruption
Pulse
OK
B
OK
Comp.
50.0m
150m
250m
350m
450m
A mix of conditions, BO, short--circuit and UVLO fault are represented on this diagram. In BO, the pulses (pulse ok signal) are started at
V
= 15 V and there is no latch--off phase. In short--circuit, pulses are stopped by the timer and finally, in a UVLO conditions (not a
CC
short--circuit), there is a latch--off phase but the timer is flat since there is no short--circuit.
Figure 37.
PFC Behavior During BO Conditions
15 V
During brown--out, the PFC is disabled; otherwise the
PFC controller consumption would prevent the charging of
the VCC capacitor. The PFC will be shutdown until BO
comesbackandacleanstartupsequencehasproperlyended.
V
CC
Soft--start
TheNCP1381/82featuresasoft--startactivatedduringthe
power on sequence (PON) and in short--circuit conditions to
lower the acoustical noise in the transformer. As soon as
VCC reaches 15 V, the peak current is gradually increased
from nearly zero up to the maximum clamping level (e.g.
0.8 V / Rsense). Every restart attempt is followed by a
soft--start activation.
0 V (Fresh P
)
ON
or V
CClatch
Current
Sense
Max I
P
A shorter soft--start is also activated during the skip cycle
condition to implement our soft--burst. This Soft--Skip is
cancelled whenever a fault conditionappears, inorder notto
degrade the transient behavior in case of load transients
when the controller is initially in skip mode.
5 ms
Figure 38. Soft--Start is Activated During a Startup
Sequence or an OCP Condition
Soft--Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC).
http://onsemi.com
24
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
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