NCP1445 [ONSEMI]
4.0 A 280 kHz/560 kHz Boost Regulators; 4.0 280千赫/ 560 kHz的升压稳压器
| 型号： | NCP1445 |
| 厂家： | 
ONSEMI |
| 描述： | 4.0 A 280 kHz/560 kHz Boost Regulators |
| 文件： | 总20页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1442, NCP1443,
NCP1444, NCP1445
4.0 A 280 kHz/560 kHz
Boost Regulators
The NCP1442/3/4/5 products are 280 kHz/560 kHz switching
regulators with a high efficiency, 4.0 A integrated switch. These parts
operate over a wide input voltage range, from 2.7 V to 30 V. The
flexibility of the design allows the chips to operate in most power
supply configurations, including boost, flyback, forward, inverting,
and SEPIC. The ICs utilize current mode architecture, which allows
excellent load and line regulation, as well as a practical means for
limiting current. Combining high−frequency operation with a highly
integrated regulator circuit results in an extremely compact power
supply solution. The circuit design includes provisions for features
such as frequency synchronization, shutdown, and feedback controls
for either positive or negative voltage regulation.
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PowerFLEX]
7−PIN
F SUFFIX
CASE 936J
1
7
7 LEAD, TO−220
T SUFFIX
CASE 821P
1
Part Number
NCP1442
NCP1443
NCP1444
NCP1445
Frequency
280 kHz
280 kHz
560 kHz
560 kHz
Feedback Voltage Polarity
Positive
7
PIN CONNECTIONS AND
MARKING DIAGRAMS
Negative
Positive
Negative
NC
Features
NC
P144xT
AWLYWW
P144xF
AWLYWW
• Pb−Free Packages are Available*
• Integrated Power Switch: 4.0 A Guaranteed
• Wide Input Range: 2.7 V to 30 V
• High Frequency Allows for Small Components
• Minimum External Components
1
7
PowerFLEX
7−PIN
1
7
7 LEAD, TO−220
• Easy External Synchronization
• Built−in Overcurrent Protection
• Frequency Foldback Reduces Component Stress During an
Overcurrent Condition
NCP1443/5
NCP1442/4
1. V
Pin 1. V
C
C
2. TEST
3. NFB
4. GND
2. FB
3. TEST
4. GND
• Thermal Shutdown with Hysteresis
• Regulates Either Positive or Negative Output Voltages
• Shut Down Current: 50 mA Maximum
5. V
5. V
SW
SW
6. SS
6. SS
7. V
7. V
CC
CC
Applications
x
A
= Device Number 2, 3, 4, or 5
= Assembly Location
• Boost Converter
WL = Wafer Lot
= Year
WW = Work Week
• Inverting Converter
• Distributed Power
• Portable Computers
• Battery Powered Systems
Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
October, 2004 − Rev. 7
NCP1442/D
NCP1442, NCP1443, NCP1444, NCP1445
V
SW
10 mH
3.3 V
+
+
+
MBRS320T3
22 k
33 mF
33 mF
33 mF
7
5 V
/1.5 A
OUT
V
CC
1
5
V
C
V
SW
2
3
NC
SS
FB
4
220 pF
SS
+
+
+
6
GND
0.01 mF
33 mF
33 mF
33 mF
GND
7.5 k
5.1 k
GND
Figure 1. Application Diagram − NCP1442/4,
3.3 V to 5.0 V/1.5 A Boost Converter
MAXIMUM RATINGS
Rating
Value
Unit
Thermal Resistance Junction−to−Air, TO220−7 Version In Air (Socketed)
66.7
1.45
°C/W
Thermal Resistance Junction−to−Air, TO220−7 Version On Cold Plate (25°C)
Thermal Resistance Junction−to−Air, PowerFLEX on 2.1 sq. in. 1 oz.
53.8
0 to +150
−65 to +150
230 Peak
2.0
°C/W
°C
Junction Temperature Range, T
J
Storage Temperature Range, T
°C
STORAGE
Lead Temperature Soldering: Reflow (Note 1)
ESD, Human Body Model
°C
kV
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Name
IC Power Input
Pin Symbol
V
V
I
I
SINK
MAX
MIN
SOURCE
V
CC
30 V
30 V
6.0 V
10 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
N/A
200 mA
1.0 mA
10 mA
1.0 mA
Shutdown/Sync
SS
1.0 mA
10 mA
1.0 mA
Loop Compensation
Voltage Feedback Input
V
C
FB
(NCP1442/4 only)
Negative Feedback Input
(Transient, 10 ms)
NFB
10 V
−10 V
1.0 mA
1.0 mA
(NCP1443/5 only)
Test Pin
Test
6.0 V
0.3 V
40 V
−0.3 V
−0.3 V
−0.3 V
1.0 mA
9.0 A
1.0 mA
10 mA
9.0 A
Ground
GND
Switch Input
V
SW
10 mA
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2
NCP1442, NCP1443, NCP1444, NCP1445
ELECTRICAL CHARACTERISTICS (2.7 V < V < 30 V; 0°C < T < 85°C; 0°C < T < 125°C; For all NCP1442/3/4/5 specifications
CC
A
J
unless otherwise stated.) (See Note 2)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Positive and Negative Error Amplifiers
FB Reference Voltage (NCP1442/4 only)
NFB Reference Voltage (NCP1443/5 only)
FB Input Current (NCP1442/4 only)
NFB Input Current (NCP1443/5 only)
V
V
tied to FB; measure at FB
= 1.25 V
1.246
−2.60
−1.0
1.276
−2.475
0.1
1.300
−2.40
1.0
V
V
C
C
FB = V
mA
mA
%/V
REF
NFB = NV
−16
−10
−5.0
0.03
REF
FB Reference Voltage Line Regulation
(NCP1442/4 only)
V
C
= FB
−0.03
0.01
NFB Reference Voltage Line Regulation
(NCP1443/5 only)
V
C
= 1.25 V
−0.05
0.01
0.05
%/V
Positive Error Amp Transconductance
Negative Error Amp Transconductance
Positive Error Amp Gain
I
I
= ± 25 mA
= ± 5.0 mA
300
115
200
100
−90
200
1.5
550
160
500
180
−50
460
1.64
0.47
1.05
800
225
−
mMho
mMho
V/V
V/V
mA
VC
VC
(Note 3)
(Note 3)
Negative Error Amp Gain
320
−25
1500
1.9
V
C
V
C
V
C
V
C
V
C
Source Current
Sink Current
FB = 1.0 V or NFB = −1.9 V, V = 1.25 V
C
FB = 1.5 V or NFB = −3.1 V, V = 1.25 V
mA
C
High Clamp Voltage
Low Clamp Voltage
Threshold
FB = 1.0 V or NFB = −1.9 V; V sources 25 mA
V
C
FB = 1.5 V or NFB = −3.1 V, V sinks 25 mA
0.30
0.70
0.70
1.30
V
C
Reduce V from 1.5 V until switching stops
V
C
Oscillator
Base Operating Frequency
Reduced Operating Frequency
Maximum Duty Cycle
Base Operating Frequency
Reduced Operating Frequency
Maximum Duty Cycle
FB Frequency Shift Threshold
NFB Frequency Shift Threshold
Sync/Shutdown
NCP1442/3, FB = 1.0 V or NFB = −1.9 V
NCP1442/3, FB = 0 V or NFB = 0 V
NCP1442/3
240
30
280
68
320
120
−
kHz
kHz
%
90
96
NCP1444/5, FB = 1.0 V or NFB = −1.9 V
NCP1444/5, FB = 0 V or NFB = 0 V
NCP1444/5
480
60
560
120
92
640
160
−
kHz
kHz
%
82
Frequency drops to reduced operating frequency
Frequency drops to reduced operating frequency
0.36
−0.80
0.40
−0.68
0.44
−0.50
V
V
Sync Range
NCP1442/3
−
−
−
500
1000
2.5
−
−
−
kHz
kHz
V
Sync Range
NCP1444/5
Sync Pulse Transition Threshold
SS Bias Current
Rise time = 20 ns
SS = 0 V
−10
−
−1.0
0.2
−
mA
mA
SS = 3.0 V
4.0
Shutdown Threshold
Shutdown Delay
−
0.50
0.85
1.20
V
2.7 V ≤ V ≤ 12 V
12
12
100
40
500
400
ms
ms
CC
12 V < V ≤ 30 V
CC
2. For the FR4 suffix parts, production testing is performed at 25°C and 85°C; limits at 0°C are guaranteed by design.
3. Guaranteed by design, not 100% tested in production.
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3
NCP1442, NCP1443, NCP1444, NCP1445
ELECTRICAL CHARACTERISTICS (continued) (2.7 V < V < 30 V; 0°C < T < 85°C; 0°C < T < 125°C; For all
CC
A
J
NCP1442/3/4/5 specifications unless otherwise stated.) (See Note 2)
Characteristic
Power Switch
Test Conditions
Min
Typ
Max
Unit
Switch Saturation Voltage
I
I
I
= 4.0 A
−
−
−
0.6
0.14
0.9
1.0
0.5
0.4
V
V
V
SWITCH
SWITCH
SWITCH
= 10 mA, 2.7 V < V < 12 V
= 10 mA, 12 V < V < 30 V
CC
CC
Switch Current Limit
Minimum Pulse Width
50% duty cycle (Note 4)
80% duty cycle (Note 4)
5.0
4.0
6.0
−
8.0
−
A
A
FB = 0 V or NFB = 0 V, I
= 4.0 A (Note 4)
200
250
300
ns
SW
Switch Transconductance, DI / DIV
2.7 V ≤ V ≤ 12 V, 10 mA ≤ I
≤ 4.0 A
≤ 4.0 A
SW
−
−
8.0
10
30
50
mA/A
CC
SW
CC
SW
12 V < V ≤ 30 V, 10 mA ≤ I
CC
Switch Leakage
General
V
SW
= 40 V, V = 0V
−
2.0
20
mA
CC
Operating Current
Shutdown Mode Current
I
= 0
−
15
27
mA
SW
V
V
< 0.8 V, SS = 0 V, 2.7 V ≤ V ≤ 12 V
< 0.8 V, SS = 0 V, 12 V ≤ V ≤ 30 V
−
−
16
25
60
60
mA
C
C
CC
CC
Minimum Operation Input Voltage
Thermal Shutdown
V
switching, maximum I
10 mA
SW =
−
150
−
2.2
180
25
2.6
210
−
V
SW
(Note 4)
(Note 4)
°C
°C
Thermal Hysteresis
4. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
Package Pin Number
Pin Symbol
Function
1
V
C
Loop compensation pin. The V pin is the output of the error amplifier and is used for loop
compensation, current limit and soft start. Loop compensation can be implemented by a sim-
ple RC network as shown in the application diagram on page 2.
C
2 (NCP1442/4 only)
FB
Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to
1.276 V. When the voltage at this pin falls below 0.4 V, chip switching frequency reduces to
20% of the nominal frequency.
2 (NCP1443/5 only)
3 (NCP1442/4 only)
Test
NFB
GND
These pins are connected to internal test logic and should either be left floating or tied to
ground. Connection to a voltage between 2.0 V and 6.0 V shuts down the internal oscillator
and leaves the power switch running.
3 (NCP1443/5 only)
Negative feedback pin. This pin senses a negative output voltage and is referenced to −2.475
V. When the voltage at this pin goes above −0.65 V, chip switching frequency reduces to 20%
of the nominal frequency.
4
5
6
Ground pin. This pin provides a ground for the controller circuitry and the internal power
switch. This pin is internally connected to the metal pad of the package to provide an addition-
al ground connection as well as an effective means of dissipating heat.
V
SW
High current switch pin. This pin connects internally to the collector of the power switch. The
open voltage across the power switch can be as high as 40 V. To minimize radiation, use a
trace as short as practical.
SS
Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly
twice the base frequency. A TTL low will shut the part down and put it into low current mode.
If synchronization is not used, this pin should be either tied high or left floating for normal
operation.
7
V
CC
Input power supply pin. This pin supplies power to the part and should have a bypass capaci-
tor connected to GND.
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NCP1442, NCP1443, NCP1444, NCP1445
V
CC
Thermal
Shutdown
Shutdown
2.0 V
Regulator
V
SW
PWM
Latch
R
Oscillator
S
Delay
Timer
Switch
Q
Driver
Sync
SS
Frequency
Shift 5:1
×5
200 k
2.0 V
Slope
Compensation
Negative
Error Amp
15 mW
250 k
NFB
+
−
GND
Ramp
Summer
NCP1443/5
only
PWM
Comparator
−0.65 V Detector
0.4 V Detector
+
−
FB
−
+
NCP1442/4
only
Positive
Error Amp
1.276 V
V
C
Figure 2. Block Diagram
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NCP1442, NCP1443, NCP1444, NCP1445
20
12
V
V
= 30 V
= 12 V
CC
10
8
V
= 30 V
CC
CC
15
10
V
= 12 V
CC
V
CC
= 2.7 V
6
V
CC
= 2.7 V
4
5
0
2
0
DI
SW
= 2.99 A
0
20
40
60
80
0
20
40
60
80
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 3. Supply Current versus Temperature
Figure 4. DICC / DISW versus Temperature
800
700
600
500
400
300
200
300
295
290
285
280
275
270
265
T = 25°C
A
T = 85°C
A
V
= 2.7 V
3.5
CC
260
100
0
255
250
0
10
20
30
40
50
60
70
80
0
0.5
1.0
1.5
2.0
2.5
3.0
4.0
I , SWITCH CURRENT (A)
SW
T , AMBIENT TEMPERATURE (°C)
A
Figure 5. Switch Saturation Voltage versus
Switch Current
Figure 6. Switching Frequency versus
Temperature (NCP1442/3 Only)
600
595
590
585
580
575
570
125
100
75
T = 25°C
A
T = 85°C
A
50
565
25
0
560
555
V
CC
= 12 V
550
0.45
0
10
20
30
40
50
60
70
80
0.38 0.39
0.40
0.41
0.42
0.43
0.44
T , AMBIENT TEMPERATURE (°C)
A
V
FB
, POSITIVE FEEDBACK VOLTAGE (V)
Figure 7. Switching Frequency versus
Temperature (NCP1444/5 Only)
Figure 8. Switching Frequency versus Positive
Feedback Voltage
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NCP1442, NCP1443, NCP1444, NCP1445
125
1.276
1.275
V
V
= 30 V
= 12 V
CC
100
75
1.274
1.273
T = 85°C
A
CC
T = 25°C
A
1.272
1.271
V
CC
= 2.7 V
50
1.270
25
0
V
CC
= 12 V
1.269
1.268
−0.665 −0.67 −0.675 −0.68 −0.685 −0.69 −0.695
0
10
20
30
40
50
60
70
80
V
NFB
, NEGATIVE FEEDBACK VOLTAGE (V)
T , AMBIENT TEMPERATURE (°C)
A
Figure 9. Switching Frequency versus
Negative Feedback Voltage
Figure 10. Feedback Reference Voltage versus
Temperature (NCP1442/4 Only)
0.30
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.22
−2.46
−2.47
−2.48
V
= 12 V
CC
V
CC
= 2.7 V
V
= 12 V
CC
V
CC
= 2.7 V
V
CC
= 30 V
−2.49
−2.50
V
= 30 V
CC
0.21
0.20
0
20
40
60
80
0
20
40
60
80
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 11. Feedback Reference Voltage versus
Temperature (NCP1443/5 Only)
Figure 12. Error Amplifier Bias Current versus
Temperature (NCP1442/3 Only)
−8
−9
97.0
96.5
96.0
95.5
95.0
94.5
94.0
V
CC
= 30 V
12 V
2.7 V
−10
−11
−12
−13
V
CC
= 2.7 V
V
CC
= 12 V
93.5
93.0
V
CC
= 30 V
60
−14
0
20
40
60
80
80
0
20
40
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 13. Error Amplifier Bias Current versus
Temperature (NCP1443/5 Only)
Figure 14. Maximum Duty Cycle versus
Temperature
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NCP1442, NCP1443, NCP1444, NCP1445
1.0
0.9
0.8
1.14
1.12
1.10
1.08
1.06
0.7
0.6
0.5
0.4
0.3
0.2
1.04
1.02
0.1
0
1.00
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 15. VC Threshold Voltage versus
Temperature
Figure 16. Shutdown Threshold versus
Temperature
180
250
200
150
100
160
140
120
100
80
V
CC
= 2.7 V
V
= 2.7 V
CC
V
V
= 12 V
= 30 V
V
V
= 12 V
= 30 V
CC
CC
60
40
50
0
CC
CC
20
0
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 17. Shutdown Delay versus Temperature
(NCP1442)
Figure 18. Shutdown Delay versus Temperature
(NCP1444)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
45
40
35
30
25
20
15
T = 85°C
A
T = 25°C
A
10
0.5
0
5
0
30
0
5
10
15
(V)
20
25
30
0
5
10
15
20
25
V
V
CC
, SUPPLY VOLTAGE (V)
SS
Figure 19. ISS versus VSS
Figure 20. Supply Current versus Supply
Voltage During Shutdown
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NCP1442, NCP1443, NCP1444, NCP1445
570
560
550
540
530
520
510
500
490
−600
−650
−700
−750
−800
−850
−900
−950
480
470
0
20
40
60
80
0
20
40
60
80
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 21. Error Amplifier Transconductance
versus Temperature
Figure 22. Negative Error Amplifier
Transconductance versus Temperature
100
0
100
50
−100
−200
−300
0
−50
−100
−400
−500
−150
−200
−0.25 −0.2 −0.15 −0.1 −0.05
0
0.05 0.1 0.15 0.2 0.25
−0.3
−0.2
V −V
ref
−0.1
, FEEDBACK VOLTAGE (mV)
NFB
0
0.1
0.2
V
ref
−V , FEEDBACK VOLTAGE (mV)
FB
Figure 23. Error Amplifier Output Current
versus Positive Feedback Voltage
Figure 24. Error Amplifier Output Current versus
Negative Feedback Voltage
6.0
5.5
5.0
4.5
4.0
3.5
3.0
0
20
40
60
80
T , AMBIENT TEMPERATURE (°C)
A
Figure 25. Switch Leakage Current versus
Temperature
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NCP1442, NCP1443, NCP1444, NCP1445
APPLICATIONS INFORMATION
THEORY OF OPERATION
The oscillator is trimmed to guarantee frequency
accuracy. The output of the oscillator turns on the power
switch at a frequency of 280 kHz (NCP1442/3) or 560 kHz
(NCP1444/5), as shown in Figure 26. The power switch is
turned off by the output of the PWM Comparator.
Current Mode Control
V
CC
Oscillator
A TTL−compatible sync input at the SS pin is capable of
syncing up to 1.8 times the base oscillator frequency. As
shown in Figure 27, in order to sync to a higher frequency,
a positive transition turns on the power switch before the
output of the oscillator goes high, thereby resetting the
oscillator. The sync operation allows multiple power
supplies to operate at the same frequency.
S
R
L
Q
−
+
V
C
Power Switch
D1
PWM
Comparator
V
SW
In Out
Driver
C
O
R
LOAD
X5
SUMMER
W
15 m
A sustained logic low at the SS pin will shut down the IC
and reduce the supply current.
Slope Compensation
An additional feature includes frequency shift to 20% of
the nominal frequency when either the NFB or FB pins
trigger the threshold. During power up, overload, or short
circuit conditions, the minimum switch on−time is limited
by the PWM comparator minimum pulse width. Extra
switch off−time reduces the minimum duty cycle to protect
external components and the IC itself.
Figure 26. Current Mode Control Scheme
The NCP144X family incorporates a current mode
control scheme, in which the PWM ramp signal is derived
from the power switch current. This ramp signal is compared
to the output of the error amplifier to control the on−time of
the power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and error amplifier, which is commonly found
in voltage mode controllers. The second benefit comes from
inherent pulse−by−pulse current limiting by merely
clamping the peak switching current. Finally, since current
mode commands an output current rather than voltage, the
filter offers only a single pole to the feedback loop. This
allows both a simpler compensation and a higher
gain−bandwidth over a comparable voltage mode circuit.
Without discrediting its apparent merits, current mode
control comes with its own peculiar problems, mainly,
subharmonic oscillation at duty cycles over 50%. The
NCP144X family solves this problem by adopting a slope
compensation scheme in which a fixed ramp generated by
the oscillator is added to the current ramp. A proper slope
rate is provided to improve circuit stability without
sacrificing the advantages of current mode control.
As previously mentioned, this block also produces a ramp
for the slope compensation to improve regulator stability.
Error Amplifier
200 k
2.0 V
250 k
NFB
+
−
NCP1443/5
negative error−amp
V
C
C1
120 pF
1MW
0.01 mF
Voltage
Clamp
+
1.276 V
R1
5 kW
−
FB
NCP1442/4
positive error−amp
Figure 28. Error Amplifier Equivalent Circuit
For NCP1443/5, the NFB pin is internally referenced to
−2.475 V with approximately a 250 kW input impedance.
For NCP1442/4, the FB pin is directly connected to the
inverting input of the positive error amplifier, whose
non−inverting input is fed by the 1.276 V reference. Both
amplifiers are transconductance amplifiers with a high
output impedance of approximately 1.0 MW, as shown in
Oscillator and Shutdown
Figure 28. The V pin is connected to the output of the error
amplifiers and is internally clamped between 0.5 V and
C
Sync
Current
Ramp
1.7 V. A typical connection at the V pin includes a capacitor
C
in series with a resistor to ground, forming a pole/zero for
loop compensation.
V
SW
An external shunt can be connected between the V pin
C
Figure 27. Timing Diagram of Sync and Shutdown
and ground to reduce its clamp voltage. Consequently, the
current limit of the internal power transistor current is
reduced from its nominal value.
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10
NCP1442, NCP1443, NCP1444, NCP1445
Switch Driver and Power Switch
output through the inductor and diode. Once V reaches
CC
The switch driver receives a control signal from the logic
section to drive the output power switch. The switch is
grounded through emitter resistors (15 mW total) to the
GND pin. The peak switching current is clamped by an
internal circuit. The clamp current is guaranteed to be
greater than 4.0 A and varies with duty cycle due to slope
compensation. The power switch can withstand a maximum
approximately 1.5 V, the internal power switch briefly turns
on. This is a part of the NCP144X’s normal operation. The
turn−on of the power switch accounts for the initial current
swing.
When the V pin voltage rises above the threshold, the
C
internal power switch starts to switch and a voltage pulse can
be seen at the V pin. Detecting a low output voltage at the
SW
voltage of 40 V on the collector (V pin). The saturation
voltage of the switch is typically less than 1.0 V to minimize
power dissipation.
FB pin, the built−in frequency shift feature reduces the
switching frequency to a fraction of its nominal value,
reducing the minimum duty cycle, which is otherwise
limited by the minimum on−time of the switch. The peak
current during this phase is clamped by the internal current
limit.
When the FB pin voltage rises above 0.4 V, the frequency
increases to its nominal value, and the peak current begins
to decrease as the output approaches the regulation voltage.
The overshoot of the output voltage is prevented by the
active pull−on, by which the sink current of the error
amplifier is increased once an overvoltage condition is
detected. The overvoltage condition is defined as when the
FB pin voltage is 50 mV greater than the reference voltage.
SW
Short Circuit Condition
When a short circuit condition happens in a boost circuit,
the inductor current will increase during the whole
switching cycle, causing excessive current to be drawn from
the input power supply. Since control ICs don’t have the
means to limit load current, an external current limit circuit
(such as a fuse or relay) has to be implemented to protect the
load, power supply and ICs.
In other topologies, the frequency shift built into the IC
prevents damage to the chip and external components. This
feature reduces the minimum duty cycle and allows the
transformer secondary to absorb excess energy before the
switch turns back on.
COMPONENT SELECTION
Frequency Compensation
The goal of frequency compensation is to achieve
desirable transient response and DC regulation while
ensuring the stability of the system. A typical compensation
network, as shown in Figure 30, provides a frequency
response of two poles and one zero. This frequency response
is further illustrated in the Bode plot shown in Figure 31.
I
L
V
OUT
V
CC
V
C
V
C
R1
NCP1442/3/4/5
C2
C1
GND
Figure 29. Startup Waveforms of Circuit Shown in
the Application Diagram. Load = 400 mA.
Figure 30. A Typical Compensation Network
The NCP144X can be activated by either connecting the
The high DC gain in Figure 31 is desirable for achieving
DC accuracy over line and load variations. The DC gain of
a transconductance error amplifier can be calculated as
follows:
V
pin to a voltage source or by enabling the SS pin.
CC
Startup waveforms shown in Figure 29 are measured in the
boost converter demonstrated in the Block Diagram
(Figure 2). Recorded after the input voltage is turned on, this
waveform shows the various phases during the power up
transition.
Gain
+ G R
M O
DC
where:
= error amplifier transconductance;
When the V voltage is below the minimum supply
CC
G
M
voltage, the V
pin is in high impedance. Therefore,
SW
R = error amplifier output resistance ≈ 1.0 MW.
O
current conducts directly from the input power source to the
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11
NCP1442, NCP1443, NCP1444, NCP1445
The low frequency pole, f is determined by the error
amplifier output resistance and C1 as:
P1,
−V
OUT
2 V
R
1
P
f
+
P1
200 kW
R1
2pC1R
O
R
IN
NFB
+
The first zero generated by C1 and R1 is:
250 kW
1
f
+
R2
Z1
−
2pC1R1
The phase lead provided by this zero ensures that the loop
has at least a 45° phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:
Negative Error−Amp
Figure 32. Negative Error Amplifier and NFB Pin
It is shown that if R1 is less than 10 k, the deviation from
the design target will be less than 0.1 V. If the tolerances of
the negative voltage reference and NFB pin input current are
1
f
P
+
2pC R
O LOAD
where:
considered, the possible offset of the output V
in the range of:
varies
OFFSET
C = equivalent output capacitance of the error amplifier
O
≈120pF;
*0.0.5 (R1 ) R2)
R
= load resistance.
LOAD
ǒ
Ǔ* (15 mA R1) v V
OFFSET
R2
0.0.5 (R1 ) R2)
The high frequency pole, f , can be placed at the output
P2
filter’s ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:
v ǒ
Ǔ* (5 mA R1)
R2
VSW Voltage Limit
In the boost topology, V pin maximum voltage is set by
SW
1
f
+
P2
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes:
2pC2R1
One simple method to ensure adequate phase margin is to
design the frequency response with a −20 dB per decade
slope, until unity−gain crossover. The crossover frequency
V
+ V
)V
OUT(MAX)
SW(MAX)
F
should be selected at the midpoint between f and f where
Z1
P2
where:
V = output diode forward voltage.
the phase margin is maximized.
F
In the flyback topology, peak V voltage is governed by:
SW
V
+ V
)(V
CC(MAX)
)V ) N
OUT
SW(MAX)
F
f
P1
where:
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage
spike superimposed on top of the steady−state voltage.
Usually this voltage spike is caused by transformer leakage
f
Z1
f
P2
inductance charging stray capacitance between the V and
SW
GND pins. To prevent the voltage at the V
pin from
SW
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
Frequency (LOG)
Figure 31. Bode Plot of the Compensation Network
Shown in Figure 30
the V pin and ground.
SW
Negative Voltage Feedback
Since the negative error amplifier has finite input
impedance as shown in Figure 32, its induced error has to be
considered. If a voltage divider is used to scale down the
negative output voltage for the NFB pin, the equation for
calculating output voltage is:
*2.475 (R1 ) R2)
+ ǒ
Ǔ*10 mA R1
*V
OUT
R2
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12
NCP1442, NCP1443, NCP1444, NCP1445
I
L
Magnetic Component Selection
I
IN
When choosing a magnetic component, one must consider
factors such as peak current, core and ferrite material, output
voltage ripple, EMI, temperature range, physical size and
cost. In boost circuits, the average inductor current is the
+
−
V
CC
C
IN
product of output current and voltage gain (V
/V ),
OUT CC
assuming 100% energy transfer efficiency. In continuous
conduction mode, inductor ripple current is:
R
ESR
V
(V
CC OUT
* V
)
CC
I
+
RIPPLE
(f)(L)(V
OUT)
where:
f = 280 kHz for NCP1442/3 and 560 kHz for NCP1444/5.
The peak inductor current is equal to average current plus
half of the ripple current, which should not cause inductor
saturation. The above equation can also be referenced when
selecting the value of the inductor based on the tolerance of
the ripple current in the circuits. Small ripple current
provides the benefits of small input capacitors and greater
output current capability. A core geometry like a rod or
barrel is prone to generating high magnetic field radiation,
but is relatively cheap and small. Other core geometries,
such as toroids, provide a closed magnetic loop to prevent
EMI.
Figure 34. Boost Circuit Effective Input Filter
The situation is different in a flyback circuit. The input
current is discontinuous and a significant pulsed current is
seen by the input capacitors. Therefore, there are two
requirements for capacitors in a flyback regulator: energy
storage and filtering. To maintain a stable voltage supply to
the chip, a storage capacitor larger than 20 mF with low ESR
is required. To reduce the noise generated by the inductor,
insert a 1.0 mF ceramic capacitor between V and ground
CC
as close as possible to the chip.
Input Capacitor Selection
Output Capacitor Selection
In boost circuits, the inductor becomes part of the input
filter, as shown in Figure 34. In continuous mode, the input
current waveform is triangular and does not contain a large
pulsed current, as shown in Figure 33. This reduces the
requirements imposed on the input capacitor selection.
During continuous conduction mode, the peak to peak
inductor ripple current is given in the previous section. As
we can see from Figure 33, the product of the inductor
current ripple and the input capacitor’s effective series
V
OUT
ripple
resistance (ESR) determine the V
ripple. In most
CC
applications, input capacitors in the range of 10 mF to
100 mF with an ESR less than 0.3 W work well up to a full
4.0 A switch current.
I
L
Figure 35. Typical Output Voltage Ripple
V
CC
ripple
By examining the waveforms shown in Figure 35, we can
see that the output voltage ripple comes from two major
sources,
charging/discharging of the output capacitor. In boost
circuits, when the power switch turns off, I flows into the
namely
capacitor
ESR
and
the
I
IN
L
output capacitor causing an instant DV = I × ESR. At the
IN
I
L
same time, current I − I
charges the capacitor and
L
OUT
increases the output voltage gradually. When the power
switch is turned on, I is shunted to ground and I
L
OUT
discharges the output capacitor. When the I ripple is small
L
enough, I can be treated as a constant and is equal to input
L
Figure 33. Boost Input Voltage and Current
Ripple Waveforms
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13
NCP1442, NCP1443, NCP1444, NCP1445
V
IN
current I . Summing up, the output voltage peak−peak
IN
ripple can be calculated by:
V
CC
(I * I
(1 * D)
(f)
IN
OUT)
OUT)
V
+
OUT(RIPPLE)
(C
R2
R3
I
D
OUT
(C
)
) I ESR
IN
V
C
)(f)
OUT
D1
The equation can be expressed more conveniently in
terms of V , V
and I
for design purposes as
CC
OUT
OUT
follows:
I
(V
(C
* V
)(f)
)
CC
OUT OUT
1
OUT
V
+
OUT(RIPPLE)
(C
)(f)
R1
OUT
C1
(I )(ESR)
)(V
OUT OUT
)
V
CC
C2
The capacitor RMS ripple current is:
Ǹ
2
2
) (D)
OUT
I
+
(I * I
) (1 * D))(I
RIPPLE
IN
OUT
Figure 36. Current Limiting using a Diode Clamp
V
* V
OUT
V
CC
OUT Ǹ
+ I
CC
Another solution to the current limiting problem is to
externally measure the current through the switch using a
sense resistor. Such a circuit is illustrated in Figure 37.
Although the above equations apply only for boost
circuits, similar equations can be derived for flyback
circuits.
V
CC
Reducing the Current Limit
In some applications, the designer may prefer a lower
limit on the switch current than 4.0 A. An external shunt can
V
C
PGND
AGND
be connected between the V pin and ground to reduce its
C
+
−
V
IN
clamp voltage. Consequently, the current limit of the
internal power transistor current is reduced from its nominal
value.
R1
C2
The voltage on the V pin can be evaluated with the
equation:
C
C1
R2
C3
Q1
V
+ I R A
SW E V
C
Output
Ground
where:
R = .015 W, the value of the internal emitter resistor;
R
SENSE
E
Figure 37. Current Limiting using a Current Sense
Resistor
A = 5.0 V/V, the gain of the current sense amplifier.
V
Since R and A cannot be changed by the end user, the
E
V
only available method for limiting switch current below
The switch current is limited to:
4.0 A is to clamp the V pin at a lower voltage. If the
C
V
R
BE(Q1)
SENSE
maximum switch or inductor current is substituted into the
equation above, the desired clamp voltage will result.
A simple diode clamp, as shown in Figure 36, clamps the
I
+
SWITCH(PEAK)
where:
V voltage to a diode drop above the voltage on resistor R3.
C
V
BE(Q1)
= the base−emitter voltage drop of Q1, typically
Unfortunately, such a simple circuit is not generally
0.65 V.
acceptable if V is loosely regulated.
IN
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NCP1442, NCP1443, NCP1444, NCP1445
The improved circuit does not require a regulated voltage
The dashed box contains the normal compensation
circuitry to limit the bandwidth of the error amplifier.
to operate properly. Unfortunately, a price must be paid for
this convenience in the overall efficiency of the circuit. The
designer should note that the input and output grounds are
no longer common. Also, the addition of the current sense
Resistors R2 and R3 form a voltage divider off of the V
SW
pin. In normal operation, V
looks similar to a square
SW
wave, and is dependent on the converter topology. Formulas
for calculating V in the boost and flyback topologies are
resistor, R , results in a considerable power loss which
SENSE
SW
increases with the duty cycle. Resistor R2 and capacitor C3
form a low−pass filter to remove noise.
given in the section “V Voltage Limit.” The voltage on
SW
V
SW
charges capacitor C3 when the switch is off, causing
the voltage at the V pin to shift upwards. When the switch
turns on, C3 discharges through R3, producing a negative
C
Subharmonic Oscillation
Subharmonic oscillation (SHM) is a problem found in
current−mode control systems, where instability results
when duty cycle exceeds 50%. SHM only occurs in
switching regulators with a continuous inductor current.
This instability is not harmful to the converter and usually
does not affect the output voltage regulation. SHM will
increase the radiated EM noise from the converter and can
cause, under certain circumstances, the inductor to emit
high−frequency audible noise.
SHM is an easily remedied problem. The rising slope of
the inductor current is supplemented with internal “slope
compensation” to prevent any duty cycle instability from
carrying through to the next switching cycle. In the
NCP144X family, slope compensation is added during the
entire switch on−time, typically in the amount of
180 mA/ms.
slope at the V pin. This negative slope provides the slope
compensation.
The amount of slope compensation added by this circuit
C
is
*(1*D)
R
f
3
SW
(1 * D)R A
E V
DI
DT
R C f
3 SW
3
SW ǒ
Ǔ
ǒ1 * e Ǔǒ
Ǔ
+ V
R )R
2 3
where:
DI/DT = the amount of slope compensation added (A/s);
= the voltage at the switch node when the transistor
V
SW
is turned off (V);
= the switching frequency, typically 280 kHz
f
SW
(NCP1442/3) or 560 kHz (NCP1444/5) (Hz);
D = the duty cycle;
R = 0.015 W, the value of the internal emitter resistor;
E
A = 5.0 V/V, the gain of the current sense amplifier.
V
In some cases, SHM can rear its ugly head despite the
presence of the onboard slope compensation. The simple
cure to this problem is more slope compensation to avoid the
unwanted oscillation. In that case, an external circuit, shown
in Figure 38, can be added to increase the amount of slope
compensation used. This circuit requires only a few
components and is “tacked on” to the compensation
network.
In selecting appropriate values for the slope compensation
network, the designer is advised to choose a convenient
capacitor, then select values for R2 and R3 such that the
amount of slope compensation added is 100 mA/ms. Then
R2 may be increased or decreased as necessary. Of course,
the series combination of R2 and R3 should be large enough
to avoid drawing excessive current from V . Additionally,
SW
to ensure that the control loop stability is improved, the time
constant formed by the additional components should be
chosen such that:
V
SW
V
SW
1 * D
R C
3 3
t
f
SW
V
C
Finally, it is worth mentioning that the added slope
compensation is a trade−off between duty cycle stability and
transient response. The more slope compensation a designer
adds, the slower the transient response will be, due to the
external circuitry interfering with the proper operation of the
error amplifier.
R1
R2
C1
C2
Soft−Start
Through the addition of an external circuit, a soft−start
function can be added to the NCP1442/3/4/5 family of
components. Soft−start circuitry prevents the V pin from
C
slamming high during startup, thereby inhibiting the
inductor current from rising at a high slope.
C3
R3
This circuit, shown in Figure 39, requires a minimum
number of components and allows the soft−start circuitry to
activate any time the SS pin is used to restart the converter.
Figure 38. Technique for Increasing Slope
Compensation
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15
NCP1442, NCP1443, NCP1444, NCP1445
The internal control circuitry, including the oscillator and
V
IN
linear regulator, requires a small amount of power even
when the switch is turned off. The specifications section of
V
V
CC
this datasheet reveals that the typical operating current, I ,
Q
SS
SS
due to this circuitry is 5.5 mA. Additional guidance can be
found in the graph of operating current vs. temperature. This
graph shows that IQ is strongly dependent on input voltage,
C
V , and the ambient temperature, T . Then:
IN
A
P
+ V
I
IN Q
BIAS
D2
D1
Since the onboard switch is an NPN transistor, the base
drive current must be factored in as well. This current is
R1
C1
drawn from the V pin, in addition to the control circuitry
IN
current. The base drive current is listed in the specifications
C2
C3
as DI /DI , or switch transconductance. As before, the
CC
SW
designer will find additional guidance in the graphs. With
that information, the designer can calculate:
I
CC
P
+ V
I
IN SW
D
DRIVER
DI
SW
Figure 39. Soft−Start
where:
= the current through the switch;
D = the duty cycle or percentage of switch on−time.
I
SW
Resistor R1 and capacitors C1 and C2 form the
compensation network. At turn on, the voltage at the V pin
C
starts to come up, charging capacitor C3 through Schottky
I
and D are dependent on the type of converter. In a
SW
diode D2, clamping the voltage at the V pin such that
boost converter,
C
switching begins when V reaches the V threshold,
typically 1.05 V (refer to graphs for detail over
temperature).
C
C
I
I
^ I D
LOAD
SW(AVG)
efficiency
V
* V
IN
OUT
D ^
V
+ V
)V
F(D2) C3
C
V
OUT
Therefore, C3 slows the startup of the circuit by limiting
In a flyback converter,
the voltage on the V pin. The soft−start time increases with
C
V
I
OUT LOAD
I
I
^
the size of C3.
SW(AVG)
V
efficiency
IN
Diode D1 discharges C3 when SS is low. If the shutdown
function is not used with this part, the cathode of D1 should
V
OUT
)
D ^
n
n
V
s V
IN
p
be connected to V .
OUT
IN
where:
n = number of turns in the transformer secondary winding.
Calculating Junction Temperature
To ensure safe operation of the NCP1442/3/4/5, the
designer must calculate the on−chip power dissipation and
determine its expected junction temperature. Internal
thermal protection circuitry will turn the part off once the
junction temperature exceeds 180°C ± 30°. However,
repeated operation at such high temperatures will ensure a
reduced operating life.
Calculation of the junction temperature is an imprecise
but simple task. First, the power losses must be quantified.
There are three major sources of power loss on the
NCP144X:
s
n = number of turns in the transformer primary winding.
p
The switch saturation voltage, V
, is the last major
(CE)SAT
source of on−chip power loss.
V
is the
(CE)SAT
collector−emitter voltage of the internal NPN transistor
when it is driven into saturation by its base drive current. The
value for V
can be obtained from the specifications
(CE)SAT
or from the graphs, as “Switch Saturation Voltage.” Thus,
P
^ V
I
D
SAT
(CE)SAT SW
Finally, the total on−chip power losses are:
• biasing of internal control circuitry, P
BIAS
P
+ P
)P
BIAS
)P
DRIVER SAT
D
• switch driver, P
DRIVER
• switch saturation, P
SAT
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NCP1442, NCP1443, NCP1444, NCP1445
Power dissipation in a semiconductor device results in the
generation of heat in the junctions at the surface of the chip.
This heat is transferred to the surface of the IC package, but
a thermal gradient exists due to the resistive properties of the
package molding compound. The magnitude of the thermal
surface of the chip might be considered to reduce T . A
copper “landing pad” can be connected to ground −
designers are referred to ON Semiconductor applications
note SR006 for more information on properly sizing a
copper area.
A
gradient is expressed in manufacturers’ data sheets as q
or junction−to−ambient thermal resistance. The on−chip
,
JA
Circuit Layout Guidelines
In any switching power supply, circuit layout is very
important for proper operation. Rapidly switching currents
combined with trace inductance generates voltage
transitions that can cause problems. Therefore the following
guidelines should be followed in the layout.
junction temperature can be calculated if q , the air
temperature near the surface of the IC, and the on−chip
power dissipation are known.
JA
T + T )(P q
D JA
)
J
A
where:
T = IC or FET junction temperature (°C);
1. In boost circuits, high AC current circulates within the
loop composed of the diode, output capacitor, and
on−chip power transistor. The length of associated
traces and leads should be kept as short as possible. In
the flyback circuit, high AC current loops exist on both
sides of the transformer. On the primary side, the loop
consists of the input capacitor, transformer, and
on−chip power transistor, while the transformer,
rectifier diodes, and output capacitors form another
loop on the secondary side. Just as in the boost circuit,
all traces and leads containing large AC currents
should be kept short.
J
T = ambient temperature (°C);
A
P = power dissipated by part in question (W);
D
q
= junction−to−ambient thermal resistance (°C/W).
JA
For ON Semiconductor components, the value for q can
JA
be found on page 19 of the datasheet, under “Package
Thermal Data.” Note that this value is different for every
package style and every manufacturer. For the NCP144X,
q
varies between 10−50°C/W, depending upon the size of
JA
the copper pad to which the IC is mounted.
Once the designer has calculated T , the question of
J
2. Separate the low current signal grounds from the
power grounds. Use single point grounding or ground
plane construction for the best results.
3. Locate the voltage feedback resistors as near the IC as
possible to keep the sensitive feedback wiring short.
Connect feedback resistors to the low current analog
ground.
whether the NCP144X can be used in an application is
settled. If T exceeds 150°C, the absolute maximum
J
allowable junction temperature, the NCP144X is not
suitable for that application.
If T approaches 150°C, the designer should consider
J
possible means of reducing the junction temperature.
Perhaps another converter topology could be selected to
reduce the switch current. Increasing the airflow across the
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NCP1442, NCP1443, NCP1444, NCP1445
ORDERING INFORMATION
Operating
Temperature Range
†
Device
Package
Shipping
NCP1442FR4
7 Lead PowerFLEX Short−Leaded
2000 Tape & Reel
2000 Tape & Reel
NCP1442FR4G
7 Lead PowerFLEX Short−Leaded
(Pb−Free)
NCP1442T
7 Lead TO−220 (Straight Lead)
50 Units/Rail
NCP1443FR4
NCP1443FR4G
7 Lead PowerFLEX Short−Leaded
2000 Tape & Reel
2000 Tape & Reel
7 Lead PowerFLEX Short−Leaded
(Pb−Free)
0°C < T < 85°C
A
NCP1443T
7 Lead TO−220 (Straight Lead)
7 Lead PowerFLEX Short−Leaded
7 Lead TO−220 (Straight Lead)
7 Lead PowerFLEX Short−Leaded
7 Lead TO−220 (Straight Lead)
50 Units/Rail
2000 Tape & Reel
50 Units/Rail
NCP1444FR4
NCP1444T
NCP1445FR4
NCP1445T
2000 Tape & Reel
50 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP1442, NCP1443, NCP1444, NCP1445
PACKAGE DIMENSIONS
PowerFLEX
7−PIN
F SUFFIX
CASE 936J−01
ISSUE O
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAX.
C
A
L
AE
B
M
P N
J
INCHES
DIM MIN MAX
MILLIMETERS
MIN
8.89
8.89
1.78
0.66
0.13
0.79
MAX
9.14
9.14
2.03
0.76
0.38
1.04
A
B
0.350
0.350
0.070
0.026
0.005
0.031
0.360
0.360
0.080
0.030
0.015
0.041
C
D 7 PL
D
DETAIL AG
G 7 PL
E
F
G
0.050 BSC
1.270 BSC
H
0.008
0.410
0.012
0.420
0.199
10.41
9.27
0.301
10.67
9.53
J
0.076 (0.003)
R
K
0.365 00.375
0.040 REF
(TOP OFFSET)
S
L
1.02 REF
M
N
0.361
0.310
0.394
0.002
0.070
0.001
0.367
0.320
0.400
−−−
9.16
7.87
10.00
0.05
1.78
0.03
9.31
8.13
10.16
−−−
−T−
V
K
SEATING
R 0.25 (0.010)
P
PLANE
R
S
0.080
0.005
2.03
0.13
U
E
H
12 °
12 °
V
U
W
Y
0.296 REF
0.075 REF
0.071 REF
0.140 REF
0.220 REF
0.281 REF
12 °
7.52 REF
1.91 REF
1.81 REF
3.56 REF
5.58 REF
7.14 REF
12 °
THERMAL
DIE PAD
AA
AB
AC
AD
AE
AF
AF
F
R 0.20 (0.008)
W
3 °
6 °
3°
6°
AA
Y
DETAIL AG
AB
AC
AD
PACKAGE THERMAL DATA
Parameter
PowerFLEX 7−PIN
1.0−4.0
Unit
R
R
Typical
Typical
°C/W
°C/W
q
q
JC
JA
10−50*
*Depending on thermal properties of substrate. R
R
+ R
q
JC CA.
q
q
JA =
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19
NCP1442, NCP1443, NCP1444, NCP1445
PACKAGE DIMENSIONS
7 LEAD TO−220
T SUFFIX
CASE 821P−03
ISSUE B
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. 821P−01 AND −02 OBSOLETE. NEW
STANDARD IS 821P−03.
C
A
E
M
N
Q
U
MILLIMETERS
INCHES
MIN
B
DIM MIN
MAX
10.54
9.40
4.83
0.81
1.40
MAX
0.415
0.370
0.190
0.032
0.055
L
A
B
C
D
E
F
9.91
8.23
4.19
0.66
0.89
0.390
0.324
0.165
0.026
0.035
K
7.62 TYP
0.3 TYP
G
H
J
1.22
2.16
0.30
24.00
26.67
6.10
7 °
1.32
2.92
0.64
26.54
29.03
6.48
−−−
0.048
0.085
0.012
0.945
1.050
0.240
7 °
0.052
0.115
0.025
1.045
1.143
0.255
−−−
J
D 7 PL
G 6 PL
H
K
L
F
M
N
Q
U
3.53
4 °
3.96
6 °
0.139
4 °
0.156
6 °
PowerFLEX is a trademark of Texas Instruments Incorporated.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NCP1442/D
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