NCP1568DD00DBR2G_技术文档

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DC-DC Active Clamp

Flyback PWM IC

Product Preview

NCP1568D

The NCP1568D is a highly integrated PWM controller designed to

implement an active clamp flyback topology. NCP1568D employs a

proprietary variable frequency algorithm to enable zero voltage

switching (ZVS) of Super−Junction or GaN FETs across line, load,

and output conditions. The ZVS feature increases power density of a

power converter by increasing the operating frequency while

achieving high efficiency. The Active Clamp Flyback (ACF)

operation simplifies EMI filter design to avoid interference with other

sensitive circuits in the system. The NCP1568D features a HV startup

circuit, a strong low side driver, and a 5 V logic level driver for the

active clamp FET. The NCP1568D is suitable for a variety of

applications including power brick, industrial, telecom, lighting, and

other applications where power density and efficiency are important

requirements.

The NCP1568D also features multimode operation and transitions

from ACF mode to Discontinuous Conduction Mode (DCM) to have

outstanding light load operation. The NCP1568D further implements

skip in standby mode, resulting in excellent standby power. The

combination of flexible control scheme and user programmable

features allow the use of NCP1568D with Super−Junction MOSFETs

(Si) and Gallium Nitride (GaN) FETs.

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MARKING DIAGRAM

1

1568

DXXX

ALYWG

G

TSSOP−16

DT SUFFIX

CASE 948BW

16

1568D = Specific Device Code

XXX

= Specific Variant

= (D00)

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

A

L

Y

W

G

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Features

• Active Clamp Flyback Topology Aids in ZVS

• Proprietary Multi−Mode Operation to Enhance Efficiency at all

Loads

Features (Continued)

• Proprietary Adaptive ZVS Algorithm Allows High Frequency

Operation while Reducing EMI

• Adaptive Dead−Time Control Both Main and Active Clamp FETs

• Peak Current−Mode Control with built in Slope Compensation

Options

• Flexible Control Scheme and Programmability Allow for

Configuration with Either External Silicon or GaN FETs

• Programmable Optional Transition to DCM

• DCM Mode Frequency Foldback with Minimum Frequency Clamp

• Quiet Skip Eliminates Audible Noise

• 700 V Startup Circuit

• 0.85 A/1.5 A Source/Sink for Low Side

• 65 mA/150 mA Active Clamp Driver Output

• Programmable Frequency from 100 kHz to 1 MHz

• Soft−Start Timer with 4 Options

• Dedicated FLT Pin Compatible with a

Thermistor

• Adjustable Over Power Protection (OPP)

• Option for Auto−Recovery or Latched

Faults

• Internal Thermal Shutdown

Applications

• USB Power Delivery

• Power Over Ethernet

nd

• 1/32 Brick

• Industrial Power Supplies

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

1

Publication Order Number:

January, 2021 − Rev. P2

NCP1568D/D

NCP1568D

ORDERING INFORMATION

Fixed Dead−Time

from LDRV OFF to

HDRV or ADRV

ON (ns)

LEB/DTMAX/

T_ZVSA

ACF FET

Soft Start Time

(ms)

ACF FET

Soft Stop Time

(ms)

T_ZVSB

(ns)

ATH Pin

Mapping

†

(ns)

Device

Package

Shipping

NCP1568DD00DBR2G

99/240/120

40

4

0.5

0

I = 1.92 E = 1

TSSOP−16

(Pb−Free)

2,500 /

Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Figure 1. Typical Application for the NCP1568D Active Clamp Flyback

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2

NCP1568D

PIN DESCRIPTION

HV

1

16

SW

NCP1568D

FLT

RT

4

5

6

7

8

13

12

11

10

9

ATH

ADRV

VCC

DTH

FB

LDRV

GND

CS

Figure 2. Pinout

Table 1. PIN FUNCTIONAL DESCRIPTION

Pin Out

Controller

Option

Name

Function

1

HV

Input to the HV startup circuit. A resistor can be placed in series with the HV pin to limit current in case of

a short on the board. The recommended value for the resistor is 10 W.

2,3,14,15

−

Removed for creepage and clearance compliance.

4

5

FLT

RT

The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds.

A resistor from the RT pin to ground sets the minimum frequency of the internal oscillator. A typical resis-

tor of 100 kW sets 100 kHz and 20 kW sets 50 kHz.

6

7

8

DTH

FB

A resistor to ground sets the ACF to DCM transition threshold with a precise 16 mA current source.

Placing a 10 nF capacitor in parallel with the DTH setting resistor from this pin to ground reduces noise in

the system. A typical value of resistor is 34.8 kW.

Feedback input allows direct connection to an opto−coupler and is pulled up with an internal resistor and

current source. Typical compensation will place a 120 pF capacitor as close to the pin as possible and a

34.8 kW in parallel.

CS

Current sense input. Placing a 47 pF capacitor to ground along with a resistor from the CS pin the low

side FET source sense resistor connection typically 249 W will increases noise immunity? The value of

the resistor can be adjusted for OPP Line compensation.

9

GND

Ground reference.

10

11

LDRV

Low−side drive output. Clamped to 12 V output.

V

CC

Supply input. At startup, an internal HV current charges the V capacitor. Once the power stage is

CC

enabled, an auxiliary winding supplies current to the V capacitor and the internal HV current source is

CC

turned−off. Placing a 10 nF capacitor in parallel with the ATH setting resistor from this pin to ground re-

duces noise in the system. A typical value of resistor is 47.5 kW.

12

13

16

ADRV

ATH

SW

ADRV is the 5 V alternate ground based high side driver signal.

A resistor to ground sets the DCM to ACF transition threshold with a precise 10 mA current source.

Connect to SW node used for adaptive dead−time control and ZVS based frequency modulation. Place a

2 kW resistor from the pin to the switch node to protect the device.

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3

NCP1568D

BLOCK DIAGRAM

VCC

Management

HV Startup

HV

VCC

V_{(OCP)_ACFC1_100,166}

V_{(OCP)_ACFC1_175}

V_{(OCP)_ACFC1_213}

V_{(OCP)_ACFC1_238}

V_{(OCP)_ACFC1_250}

V_{(OCP)_ACFC1_265}

V_{(OCP)_ACFC1_300, 400}

V_CC_OK

VDD

V_ILIM(OCP)

VDD

ACF

ADRV

SW

CLK

Adaptive Delay

Circuitry

RT

Oscillator

DMAX

SKIP

V_FB

SW

HS sense

DCM ZVS Frequency

Modulation

VCO

VCC

VDD

Slope

Clamp

Compensation

R_FB

I_FB

1/4

FB

PWM

Comparator

LDRV

CLK

Q

S

_

DMAX

Q

R

VDD

OPP

LEB1

VDD

CS

10 mA

Overload

Abnormal

Quantizer

and look-up

CS_PD

V_ILIM(OCP)

ATH

DTH

NOCP

V_{ILIM(OCP)_trans}

Mux

Trans

Overload

LEB2

VDD

NAbnormal

Mode

V_ILIM(SCP)

16 mA

V_{ILIM(SCP)_trans}

Transition &

Frequency

+

-

Trans

V_FB

VDD

Foldback Logic

DCM

V_fault(OVP)

OVP

OTP

I_FLT(OTP)

R_{FLT (clamp)}

FLT

S

TSD

nOVLD

nAbnormal

OVP

V_{FLT(OTP_out_1st)}

V_{FLT(OTP_out)}

Latch

Fault

Logic

V_{FLT (clamp)}

OTP

V_CCOVP

1st Power up

GND

Temp

TSD

Sensor

Auto-Recovery

R

VCC_(reset)

Line_Removal

S

_

Figure 3. Block Diagram

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4

NCP1568D

Table 2. MAXIMUM RATINGS

Rating

Symbol

Value

−0.3 to 700

20

Unit

V

High Voltage Startup Circuit Input Voltage

High Voltage Startup Circuit Input Current

Supply Input Voltage

V

HV(MAX)

I

mA

V

−0.3 to 30

30

CC(MAX)

Supply Input Current

I

mA

mV/ms

V

Supply Input Voltage Slew Rate

SW Pin to GND

dV /dt

CC

25

V

−1 to 700

1

SW(MAX)

SW Pin Circuit Input Current

ADRV Pin to GND

I

mA

V

ADRV

−0.3 V to 5.5

ADRV Driver Maximum Current

I

130

190

mA

ADRV(SRC)

ADRV(SNK)

Low Side Driver Voltage (Note 1)

V

−0.3 V to V

V

DRV

DRV(high)

Maximum Input Voltage ATH, DTH, CS

Maximum Input Current ATH, DTH, CS

Maximum Input Voltage (Other Pins: FB, RT, FLT)

Maximum Input Current (Other Pins: FB, RT, FLT)

Operating Junction Temperature

V

0.3 V to 5.5

10

ATH(MAX)

I

mA

V

MAX

−0.3 to 30

27

I

mA

°C

mW

MAX

T

J

−40 to 125

–60 to 150

833

Storage Temperature Range

T

STG

Power Dissipation (T = 25°C, 1 Oz Cu, 0.231 Sq Inch Printed Circuit Copper Clad)

P

D(MAX)

A

Plastic Package TSSOP16

Thermal Resistance, Junction to Ambient 1 Oz Cu Printed Circuit Copper Clad)

Plastic Package TSSOP16

R

150

°C/W

q

JA

ESD Capability

Human Body Model per JEDEC Standard JESD22−A114F Except SW Pin

Human Body Model per JEDEC Standard JESD22−A114F SW Pin

Charge Device Model per JEDEC Standard JESD22−C101F.

2000

1500

1000

V

Latch−Up Protection per JEDEC Standard JESD78E

100

mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Maximum driver voltage is limited by the driver clamp voltage, V

, when V

DRV(high)

exceeds the driver clamp voltage. Otherwise, the

CC

maximum driver voltage is V

.

CC

Table 3. RECOMMENDED OPERATING CONDITIONS

Description

Symbol

Min

10

Typ

Max

27

Units

V

CC

operating voltage

V

CC

16

Operating Junction temperature

Jc

−40

125

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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5

NCP1568D

Table 4. ELECTRICAL CHARACTERISTICS

(V = 12 V, V = 120 V, V

= open, V = 2 V, RT1= 33 kW, V = 0 V, C

= 100 nF, A

= 100 pF, L

= 1.5 nF for typical

CC

HV

FLT

FB

CS

VCC

DRV

values T = 25°C, for min/max values, T is –40°C to 125°C, unless otherwise noted)

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

START−UP AND SUPPLY CIRCUITS

Supply Voltage

V

Startup Threshold

Minimum Operating Voltage After Turn−On

Operating Hysteresis

V

increasing

decreasing

V

14.5

8.5

5.5

5.6

0.27

15.2

9.0

–

6.1

0.57

15.9

9.9

–

6.6

1.03

CC

CC(on)

CC

CC(off)

− V

V

CC(on)

CC(off)

CC(HYS)

CC(reset)

CC(inhibit)

Internal Latch/Logic Reset Level

decreasing

increasing, I = I

V

CC

V

CC

Level at Which I

Transitions to I

start1

start2

HV

start1

V

to Drive Turn−Off Timeout Delay

V

decreasing

t

delay(Vcc_off)

−

42

34

100

60

ms

CC(off)

CC

Startup Delay

Delay from V

pulse

to first LDRV

t

8

CC(on)

delay(start)

Start−Up Time

C

= 0.47 mF, V = 0 V to V

t

start−up

–

2.53

–

6.5

25

ms

V

VCC

CC

CC(on)

Minimum HV Pin Voltage for Rated

Start−Up Current Source

V

= V

– 0.5 V

V

HV(MIN)

CC

CC(on)

0.342

2.5

0.540

3.67

0.794

4.4

Inhibit Current Sourced from V Pin

V

= 0 V

I

mA

CC

start1

Start−Up Current Sourced from V Pin

V

CC

= V

CC(on)

– 0.5 V

CC

start2

Start−Up Circuit Off−State

Leakage Current

V

hv

V

hv

V

hv

= 162.5 V

= 325 V

= 700 V

I

–

23

24

25

HV(off1)

HV(off2)

HV(off3)

Switch Pin Off−State Leakage Current

FLT = 0 V

mA

V

hv

V

hv

V

hv

= 162 V

= 325 V

= 700 V

I

–

1.5

2

4

SW(off1)

SW(off2)

SW(off3)

Switch Pin Active Current Draw

V

ATH

= V

= 0 V

DTH

V

HV

V

HV

V

HV

= 162 V

= 325 V

= 700 V

I

92

117

118

119

152

153

154

SW(on1)

SW(on2)

SW(on3)

Supply Current

mA

FLT PIN OTP

FLT PIN OVP

Latch Fault

Skip Mode (Excluding FB & FLT Current)

Operating Current 500 kHz

Operating Current 100 kHz

Operating Current 500 kHz

V

= V

= 0 V

= 500 kHz, A

– 0.5 V

I

0.14

0.18

2.25

2.0

0.24

0.25

0.22

0.26

4.00

4.0

0.32

0.35

6.17

6.0

CC

FB

sw

CC(on)

CC1A

CC1B

CC1C

CC2

CC3

CC4

CC5

F

= L

=100 pF

DRV

= 100 kHz, V = 20 V

= 500 kHz, V = 10 V

sw

CC

9

13

16

CC

V

CC

V

CC

Overvoltage Protection Threshold

Latched event

V

26.6

40

27.8

63

29.2

90

V

CC(OVP)

Overvoltage Protection Timeout Delay

t

ms

delay(Vcc_OVP)

SOFT−START

Soft−Start Time

Ramp time for CS from 0 to I

t

6

7.5

9

ms

limit

soft−start

Forced DCM Time at the Beginning of

Soft Start

RT = 33 kW (303 kHz)

t

512

706

850

ms

DCM_SS

Time at which FB is Compared to DTH

Threshold

Time from the End of Soft Start to

the ACF/DCM Assessment

t

13.5

16

18.5

ms

MODE_Sam

OSCILLATOR

Minimum Oscillator Frequency in ACF Mode VSW = 15 V, RT = 100 kW

Minimum Oscillator Frequency in ACF Mode VSW = 15 V, RT = 20 kW

F

78

100

532

121

650

kHz

osc_ACF_100

430

osc_ACF_500

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6

NCP1568D

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 120 V, V = open, V = 2 V, RT1= 33 kW, V = 0 V, C

= 100 nF, A

= 100 pF, L

= 1.5 nF for typical

CC

HV

FLT

FB

CS

VCC

DRV

values T = 25°C, for min/max values, T is –40°C to 125°C, unless otherwise noted)

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

OSCILLATOR

Frequency Modulation Bounds

VSW = Modulated

RT = 100 kW, 4.20 * F

RT = 42.2 kW, 4.20 * F

(Note 3)

kHz

F

310

700

420

861

530

1000

osc_ACF

osc1_LL_ACF_UB1

osc1_LL_ACF_UB2

osc_ACF

DCM Oscillator Frequency

Maximum Duty Cycle

RT = 20 kW, FB = DCM to ACF

Trip Threshold −5 mV

F

200

260

320

kHz

%

osc_DCM_2

F

= 100 kHz, RT = 100 kW

= 205 kHz ,RT = 49.9 kW

D

53

60

53

75

79

69

96

92

88

osc

Max_100

Max_400

Max_500

osc

= 500 kHz, RT = 20 kW, T

osc

min_OFF

Minimum Off Time for ADRV

Measured at 50% of Drive Voltage

From Falling Edge to Rising Edge

of LDRV

T

365

582

808

ns

min_OFF

TRANSITION MODE

ACF to DCM Transition

ADRV LEM Soft Stop Time

D00

ms

#

t

1

0.506

1

ACF_DCM_Trans

DCM to ACF Transition

ADRV LEM Soft Start Time

D00

t

3.5

0.9

4

1

4.7

1.1

DCM_ACF_Trans1

DCM to ACF Blanking Time after

Transition

Time the DCM to ACF Comparator

is Blanked

t

DCM_ACF_HOLD

ACF to DCM Level Trip Time

Time the ACF to DCM Comparator

must be High before Transition

t

11

18

12

17

ACF_DCM_HOLD

Required DCM Cycles Before ACF

ATH FUNCTION

Current Sourced From ATH

ATH BIN 0

DCM Operation

NDCM

ATH = 2 V

50 mV

I

9.4

10

10.5

1.07

mA

−

ATH

1.00

1.16

1.04

1.20

1.36

1.52

1.68

1.84

2

ATH_BIN0

ATH_BIN1

ATH_BIN2

ATH_BIN3

ATH_BIN4

ATH_BIN5

ATH_BIN6

ATH_BIN7

ATH_BIN8

ATH_BIN9

ATH_BIN10

ATH_BIN11

ATH_BIN12

ATH_BIN13

ATH_BIN14

ATH BIN 1

180 mV

220 mV

270 mV

330 mV

390 mV

460 mV

540 mV

630 mV

740 mV

870 mV

1.02 V

1.23

V

ATH BIN 2

1.326

1.482

1.638

1.794

1.95

1.394

1.558

1.722

1.886

2.05

ATH BIN 3

ATH BIN 4

ATH BIN 5

ATH BIN 6

ATH BIN 7

2.106

2.262

2.418

2.574

2.73

2.16

2.32

2.48

2.64

2.8

2.214

2.378

2.542

2.706

2.87

ATH BIN 8

ATH BIN 9

ATH BIN 10

ATH BIN 11

ATH BIN 12

1.19 V

2.886

3.042

3.198

2.96

3.12

3.28

3.034

3.198

3.362

ATH BIN 13

1.39 V

ATH BIN 14

1.63 V

DTH FUNCTION

DTH Pin Pullup Current

DTH Trip Voltage

RT = 100 kW

I

15.25

16.0

16.75

mA

DTH

VDTH = 500 mV FB Decreasing

VDTH = 1.5 V FB Decreasing

VDTH = 3.0 V FB Decreasing

V

0.45

1.45

2.95

0.50

1.5

3.0

0.55

1.55

3.05

V

FB_DTH1

FB_DTH2

FB_DTH3

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7

NCP1568D

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 120 V, V = open, V = 2 V, RT1= 33 kW, V = 0 V, C

= 100 nF, A

= 100 pF, L

= 1.5 nF for typical

CC

HV

FLT

FB

CS

VCC

DRV

values T = 25°C, for min/max values, T is –40°C to 125°C, unless otherwise noted)

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

SLOPE COMPENSATION

Duty Cycle at which Ramp

Compensation Begins

Both ACF and DCM Mode

D

32

41.2

143

50

%

Slope_Start

Slope of Compensating Ramp

S

RAMP

110

190

mV/ms

DCM MODE FREQUENCY FOLDBACK

Feedback Voltage Below which CS

Detected Peak Current is Frozen

(at the FB Pin)

V

740

792

850

mV

FB(Ipk_freeze)_0

CS Pin Peak Current Floor Threshold

Set when FB is Lower than

RT = 100 kW

RT = 33.3 kW

RT = 20 kW

V

160

280

390

220

349

475

270

410

560

CS(Ipk_freeze)_0

CS(Ipk_freeze)_1

CS(Ipk_freeze)_2

V

FB(Ipk_freeze)

Minimum Oscillator Frequency

Operating Mode = DCM,

FB

F

20.5

30

40

kHz

osc(min)

V

= 400 mV

Oscillator Frequency in DCM Mode

RT = 20 kW

F

220

260

305

osc_DCM_2

FB = DCM to ACF Trip

Threshold −5 mV

Feedback Voltage at which Minimum

Switching Frequency is Reached

(at the FB Pin)

Fsw = F

V

370

400

440

mV

osc(min)

Fosc(min)

Feedback Voltage at which Skip Cycle

Comparator Trips (at the FB Pin)

Feedback Falling

V

FB(skip)

Skip Cycle Comparator Hysteresis

Skip Wakeup Time

Feedback Rising (Positive)

V

38

14

66

24

94

34

mV

FB(skip)_hys

FB > (V

+ V

+

T

Skip_wake

ms

FB(skip)

FB(skip)_hys

100 mV)

FEEDBACK

Open Pin Voltage

V

4.89

3.75

5.0

5.1

V

FB(open)

VFB to Internal Current Set Point

Division Ratio

VFB = 4 V

K

FB

4.00

4.20

Internal Pull−Up Resistor

Internal Pull−Up Current

FLT PROTECTION

V

= 0.4 V

R

16

83

20

99

24

kW

mA

FB

RFB_0

I

114

FB

FB_0

Overvoltage Protection (OVP) Threshold

OVP Detection Delay

V

Increasing

V

2.9

21

3.0

35

3.1

49

V

ms

V

FLT

FLT (OVP)

delay(OVP)

FLT(OTP_in)

t

Over Temperature Protection (OTP)

Threshold

Decreasing (Note 2)

Increasing (Note 2)

Increasing with first V

V

0.35

0.40

0.45

Over Temperature Protection Exiting

Threshold

V

0.870

0.370

0.937

0.418

0.990

0.470

V

FLT

FLT(OTP_out)

Over Temperature Protection Exiting

Threshold on Startup

V

FLT(OTP_out_1st)

FLT

CC

Power on

OTP Detection Delay

V

Decreasing

t

21

33

49

ms

mA

V

FLT

delay(OTP)

OTP Pull−Up Current Source

FLT Input Clamp Voltage

FLT Input Clamp Series Resistor

OVER POWER PROTECTION

OPP Current GM

= V

+ 0.2 V

I

42.5

1.69

1.26

45.5

1.75

1.58

48.5

1.90

FLT (OTP_in)

FLT(OTP)

FLT (clamp)

V

R

kW

V

= 40 V

= 120 V

HV_GM

112

188

265

nS

ms

HV

HV Update Time

Guaranteed by Design

T

30.7

UPDATE

www.onsemi.com

8

NCP1568D

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 120 V, V = open, V = 2 V, RT1= 33 kW, V = 0 V, C

= 100 nF, A

= 100 pF, L

= 1.5 nF for typical

CC

HV

FLT

FB

CS

VCC

DRV

values T = 25°C, for min/max values, T is –40°C to 125°C, unless otherwise noted)

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

CURRENT LIMIT PROTECTION

Count of OCP Events Before Fault is

Declared

V

> V

N

OCP

5

k #

#

CS

ILIM(OCP)

Count of SCP Events Before Fault is

Declared

N

5

CS

ILIM(SCP)

SCP

Restart Timer for Auto − Recovery

CS Pin Internal Pull−up Current

CURRENT SENSE

T

1460

0.7

1600

1

1755

1.3

ms

auto_retry

V

CS

= 0.8 V

I

mA

bias

Cycle by Cycle Current Limit Threshold

Over Current Protection (OCP)

DCM threshold

V

740

785

825

mV

ILIM(OCP)_DCM

Cycle by Cycle Current Limit Threshold

ACF

RT = 100 kW

FSW = 100 kHz

FSW = 166 kHz

FSW = 175 kHz

FSW = 213 kHz

FSW = 238 kHz

FSW = 250 kHz

FSW = 263 kHz

FSW = 300 kHz

FSW = 400 kHz

V

740

710

670

635

610

580

550

785

750

710

680

650

620

590

825

795

750

725

688

660

630

(OCP)_ACFC1_100

(OCP)_ACFC1_166

(OCP)_ACFC1_175

(OCP)_ACFC1_213

(OCP)_ACFC1_238

(OCP)_ACFC1_250

(OCP)_ACFC1_263

(OCP)_ACFC1_300

(OCP)_ACFC1_400

V

Cycle by Cycle Current Limit Threshold

Over Current Protection (OCP) During

LEM

In Transition Mode

V

1.12

1.19

1.26

V

ILIM(OCP)_Trans

(ACF to DCM or DCM to ACF)

Both ACF and DCM

Short Circuit Protection (SCP) Threshold

V

1.12

1.31

1.19

1.26

1.48

V

ILIM(SCP)

Short Circuit Protection (SCP) Threshold

During LEM

In Transition Mode

(ACF to DCM or DCM to ACF)

VI

1.391

LIM(SCP)_Trans

OCP Leading Edge Blanking Delay

D00

T

195

121

230

141

ns

LEB(OCP)0

SCP Leading Edge Blanking Delay

OCP Propagation Delay

T

38

83

78

ns

LEB(SCP)0

CS ramped from 0 to 1 V at dv/dt =

20 V/ms to LDRV 8.5 V falling edge

T

PROP(OCP)

SCP Propagation Delay

CS ramped from 0 to 1.6 V at dv/dt =

T

43

78

80

ns

PROP(SCP)

20 V/ms to LDRV 8.5 V falling edge

CS Switch Discharge Resistance

Measured with 5 mA Pull Up Current

R

W

DS(ON)_CS

DEAD TIME MANAGEMENT IN ACF MODE

Resonant Mode to Energy Storage

Voltage Threshold

Falling Edge of SW Pin Voltage

Rising Edge of SW Pin Voltage

D

8

9

9.6

46

10.7

11

V

T_R_E_VTH

T_E_R_VTH

Energy Storage to Resonant Mode

Voltage Threshold

Dead Time from Energy Storage to

Resonant Mode

V

SW

> D

to ADRV 2.5 V

D

T_E_R1

20

229

76

ns

T_E_R_VTH

Maximum Dead Time (Timer Starts at

ADRV Falling Edge and is Reset when

D00

D

276

320

T_Max_1

D

Expires)

T_R_E

ZVS Reference Time for Frequency

T

160

ns

_ZVS_1

Modulation (Timer Starts at ADRV Falling

Edge and is Reset when D

)

T_Max

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9

NCP1568D

Table 4. ELECTRICAL CHARACTERISTICS (continued)

(V = 12 V, V = 120 V, V = open, V = 2 V, RT1= 33 kW, V = 0 V, C

= 100 nF, A

= 100 pF, L

= 1.5 nF for typical

CC

HV

FLT

FB

CS

VCC

DRV

values T = 25°C, for min/max values, T is –40°C to 125°C, unless otherwise noted)

J

Characteristics

Conditions

Symbol

Min

Typ

Max

Unit

LOW SIDE DRIVER

LDRV Rise Time

V

= 2.4 V to 8.5 V

ns

LDRV

= V

+ 0.5 V

T

2

10.7

10.6

20

CC

CC(off)

LS_rise

= 18 V

T

LS_rise(Clamp)

LDRV Fall Time

V

= 8.5 V to 2.4 V

ns

LDRV

= V

+ 0.5 V

T

1

6.5

5.9

15

CC

CC(off)

LS_fall

= 18 V

LS_fall(Clamp)

LDRV Source Current

LDRV Sink Current

V

= V

+ 0.5 V

I

LS_src

0.855

0.847

A

V

CC

CC(off)

= 18 V

V

CC

V

CC

= V

I

LS_snk

1.41

1.55

CC(off)

= 18 V

LDRV Clamp Voltage

ADRV

V

CC

= 18 V, R

= 10 kW

V

LDRV(Clamp)

10.5

11.75

12.6

DRV

ADRV Rise Time

V

= 1V to 3V with 920 pF Load

= 3V to 1V with 920 pF Load

= 2.5 V

T

15

7

28.5

12.2

65

49

21

ns

ADRV

ADRV_rise

ADRV Fall Time

V

ADRV

T

ADRV_fall

ADRV Source Current

ADRV Sink Current

Minimum Pulse Width Allowed

ADRV Clamp Voltage

THERMAL SHUTDOWN

Thermal Shutdown

Thermal Shutdown Hysteresis

V

ADRV

I

mA

ns

ADRV_SRC

V

ADRV

= 2.5 V

I

150

234

4.75

ADRV_SNK

MIN

196

280

_PW_GD

ADRV(Clamp)

R

= 10 kW

V

4.25

5.25

V

DRV

Temperature Increasing

Temperature Decreasing

T

SHDN

150

40

°C

T

SHDN(HYS)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. On first startup the V

is set to V

If the FLT voltage decreases below V

after the first soft start the

FLT(OTP_out)

FLT(OTP_out_1st).

FLT(OTP_out)

V

changed to 900 mV.

FLT(OTP_out)

3. Operating at switching frequencies beyond those specified in the data sheet may result in damage to the IC or system and functionality cannot

be guaranteed.

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10

NCP1568D

Introduction

The NCP1568D will continue to source I

from the HV

start2

The NCP1568D implements an active clamp flyback

converter utilizing current mode architecture where the main

switch turn off event is dictated by the peak current. The

NCP1568D is an ideal candidate for high frequency high

density modules, open frame power supplies, Power Over

Ethernet (POE) and many more applications. The

NCP1568D incorporates advanced control and power

management techniques as well as multimode operation to

meet stringent regulatory requirements. The NCP1568D is

also enhanced with non−dissipative overpower protection

(OPP), and frequency modulation in both ACF and DCM

mode of operation for optimized efficiency over the entire

power range. The controller can meet low standby power

requirements at light loads with a combination of burst mode

operation and low current consumption.

pin to the V pin when thevoltage is below V

and the

is disabled

CC

CC(on)

voltage on the HV pin is above V

. I

HV(MIN) start2

if the V pin falls below V

. In this condition, the

CC(inhibit)

CC

startup current is reduced to I

. The internal high voltage

start1

startup circuits eliminate the need for external startup

components. In addition, these current sources reduce no

load power and increase the system efficiency as the HV

startup circuit has negligible power consumption in the

normal, light load, and standby operations.

Once the V capacitor C is charged to the startup

CC

threshold, V

, the HV pin startup current sources are

CC(on)

disabled the IC then checks for faults before entering soft

start. If a fault is flagged the IC will take the appropriate

action. If a fault remains for any length of time the V

CC

energy will need to be replenished periodically. The startup

current sources remain disabled until V falls below the

CC

High Voltage Startup

minimum operating voltage threshold, V

after the

CC(off)

The NCP1568D integrates a high voltage startup circuit

accessible through the HV pin. A low value resistor in series

with the HV pin can be used to limit current in the event of

a pin short or surge. The series resistance of the HV pin

should not exceed 3 kW, as the function of line detection and

HV startup will be hampered. A value of 10 W is

recommended.

tdelay

expires. Once the threshold is reached, the

(Vcc_off)

current sources are again enabled to charge V

up to

CC

V . Figure 5 shows a typical startup sequence. If a fault

CC(on)

is detected on the FLT pin, the part will continue to operate

by providing current to the V capacitor as needed in

CC

HVBC until all faults are cleared. Once the V

CC(on)

threshold is exceeded and no faults are flagged, the part will

charge up to V and the soft start sequence will begin.

CC(on)

VIN

A dedicated comparator monitors V and latches the

CC

R1_HV≤ 3 kΩ

R1_HV

controller into a low power state if V exceeds V

CC

CC(OVP)

for t

To reset the OVP fault, the V voltage

Recommend = 10 Ω

delay(Vcc_OVP).

CC

must decrease to less than V

.

CC(reset)

The C provides power to the controller during power

CC

^HVNCP1568D

GND

up. The capacitor must be sized such that a V voltage

CC

greater than V

is maintained while the auxiliary

CC(off)

GND

supply voltage is ramping up. Otherwise, V will collapse

CC

and the controller will turn off. The operating IC bias

current, I , the high side driver current, and gate charge

CC4

load at the low side and high side driver outputs must be

considered to correctly size C . The increase in current

CC

Figure 4. Typical HV Pin Connection

consumption due to external gate charge is calculated using

Equation 2. Since the switching frequency is ramped from

31 kHz to the desired switching frequency, a trapezoidal

shape is assumed for the frequency both in the DCM mode,

the LEM operation, and ACF mode. The high side driver has

no gate drive losses during DCM operation, thus the

frequency is set to zero and the switch only has the average

of the applied switching time from LEM and ACF

operations as shown in Equation 1.

The HV startup regulator consists of constant current

sources that supply current from the input voltage (V ) to

in

the supply a capacitor on the V pin (C ). When the input

CC

voltage is greater than V

, current is sourced from the

, typically 0.5 mA until the

start1

HV(MIN)

HV pin to the V pin at I

CC

voltage on the V pin exceeds V

, typically 700

CC

CC(inhibit)

mV. Once the V

threshold has been exceeded, the

CC(inhibit)

startup circuit current increases to I

, typically 3.25 mA.

start2

(eq. 1)

FSW

*FSW

FSW

*FSW

DCM_MAX

2

DCM_MAX

MIN

ACF_MAX

_@ǒ_T

Ǔ

ǒ

FSW_MIN

)

Ǔ

@ T_DCM

)

ǒ

FSW_{DCM_MAX}

T_SS

)

Ǔ

_SS* T_DCM

2

f_SW+

³

50 kHz*31.25 kHz

420 kHz*50 kHz

ǒ

Ǔ

ǒ_{31.25 kHz )}

Ǔ_{@ 695 ms )}ǒ_{50 kHz )}

Ǔ_{@ 8 ms * 695 ms}

2

220.3 kHz+

8 ms

www.onsemi.com

11

NCP1568D

Assuming a typical gate charge of 17 nC for the high side and low side MOSFETs.

(eq. 2)

I

_{ICC(gate_Charge_Total)}+ fsw_ls @ Q_{g_ls}) fsw_hs @ Q_{g_hs}

³

7.7 mA + 218.1 kHz @ 17 @ nC ) 235 kHz @ 17 @ nC ³

Equation 2 has ƒ

frequency of the low side or high side MOSFET and Qg is

the gate charge of the external MOSFETs.

as the average soft start switching

Once the C is charged to the startup threshold, a delay

CC

SW

of t

is used to stabilize all internal power supplies

delay(start)

and ensure biasing is up before operation and level setting

can continue. After t expires, the IC will not start

delay(start)

switching until timers expire as shown in Figure 6.

Fault

V_CC(on)

V_CC(Off)

Startup Current

= Istart1

Startup Current

= Istart2

V_CC(Inhibit)

T_delay(start)

LDRV

Figure 5. Startup Timing Diagram

The V capacitor value must account for the startup

delay time, soft start time, and all of the currents provided

during that time. Equation 3 shows the calculated

provided by the equation should be increased by 20% to

allow for capacitor tolerances. Further increases may be

made by the designer to account for operating temperature

range.

CC

capacitance to soft start without the V voltage dipping

CC

below the V

threshold. The capacitance value

CC(OFF)

_@ǒ_I

Ǔ _{) T}

ǒ

Ǔ

Ǔ_{@ I}

ǒ

Ǔ

(eq. 3)

T_Delay(Start)

_CC1A) I_DRVQ

_{Soft_start1}) T_{MODE_SAM1}

_CC3) I_DRV) I_{CC(gate charge)}

C_{VCC_MIN}

+

V

_CCON* V_CCOFF

ǒ

Ǔ

ǒ

Ǔ

ǒ

Ǔ

ǒ

Ǔ

34 ms @ 0.24 mA ) 0.250 mA ) 8 ms ) 16 ms @ 4.0 mA ) 2.5 mA ) 7.85 mA

15.2 V * 9.9 V

64.3 mF +

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12

NCP1568D

HV PIN

V _CC(on)

V _CC(off)

V _CC(reset)

VCC V _CC(inhibit)

RT

LDRV

T_delay(start)

Figure 6. Normal Startup Timing Diagram and Delays

HV Currents and No load Operation

PWM Architecture

When considering no load operation, it is important to

understand that the NCP1568D has a static loss on the HV

pin due to off state leakage currents. The DC leakage

The NCP1568D implements peak current mode control

architecture for pulse width modulation. Peak current mode

control simplifies the loop compensation and typically will

result in a simple Type II compensator. With relatively

simple compensation schemes, aggressive bandwidths can

be achieved compared to a standard voltage mode control.

Further, current mode control inherently provides current

limiting while also providing a line feed forward, resulting

in excellent line transient response. However, peak current

mode control is susceptible to subharmonic oscillation for

duty cycles greater than 50%. Subharmonic oscillation is

characterized by alternating narrow and wide pulse widths.

To prevent subharmonic oscillation, NCP1568D also

features internal slope compensation.

currents on the pin are shown in the datasheet as I

,

HV(Off1)

I

and I

.

HV(Off2),

HV(Off3)

Line Detection

The input voltage measured at the HV pin. The Over

Power Protection (OPP) is changed based on the input

voltage detection. Please refer to appropriate sections for

more information. The controller compares a divided

version of VHV to internal line select thresholds. The

default power−up mode of the controller is low voltage. No

line changes are applied until after the soft start has

completed and soft start wait or the forced ACF period has

ended to ensure a repeatable reliable soft start free from

glitches. Once soft start wait has completed, the system is

free to apply changes to parameters based on line voltage.

The HV detector uses internal comparators and a divided

down version of the HV voltage to digitally track the line as

it increases and decreases.

The NCP1568D features multi−mode operation to

optimize efficiency across line and load conditions. Below

are the modes of operation:

1. Active Clamp Operation with Variable Frequency

2. Transition into and out of ACF Operation from

DCM Operation

3. Discontinuous Conduction Mode with Frequency

Foldback

4. Skip Mode

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13

NCP1568D

Multi Mode Algorithm

Multi mode algorithm is implemented in the NCP1568D

to optimize the efficiency across load conditions. The

magnetizing current is in Continuous Conduction Mode

(CCM) in active clamp operation. Therefore, when the

power supply is in standby condition, the active clamp

flyback topology will work at high peak currents and the

primary side clamp FET along with the main FET will form

a synchronous buck boost structure with magnetizing

current traversing both the first and the third quadrants.

If an IC were to remain in the ACF operation at a fixed

frequency in all line and load conditions, the result would be

high peak currents leading to high conduction losses, core

losses, and copper losses while achieving ZVS as the load

decreases. At light load, ZVS will not offset the three large

loss contributors and the efficiency will be lower compared

to DCM operation.

Fmax=4.2*F

Frequency

Active Clamp Mode

Transition Mode

F(RT)

F(RT)/2

31 kHz

DCM Mode Frequency

Foldback

Clamp

Skip

FB a I_load

DTH ATH

Figure 7. Frequency Transition from No Load to Full Load and DCM to ACF Operation

Oscillator

where F

is the frequency set by the RT resistor value

OSC

The RT resistor sets the minimum frequency of operation

for the internal oscillator.

An internal amplifier forces 2 V on the RT pin and the

current sourced from the resistor on the RT pin is used by the

internal oscillator to set the minimum switching frequency.

The frequency programmed at the RT pin sets the minimum

ACF switching frequency. Typically, for an active clamp

flyback topology, minimum frequency is selected to be at its

lowest input voltage, lowest output voltage, and maximum

load current. Figure 8 shows the RT resistor versus the

oscillator frequency from 10 kW to 100 kW. The minimum

RT resistor value is 10 kW.

The frequency set by the RT resistor follows Equation 4

noted below:

(eq. 4)

1

F_OSC

+

³ 100 kHz +

RT @ 100 pF

100 kW @ 100 pF

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14

NCP1568D

Figure 8. Minimum ACF Operating Oscillator Frequency vs. RT

Switching Cycle On and Off Time Restrictions

maintained to continue ACF operation past a certain

operating frequency. With a constant off time of 590 ns, the

maximum duty cycle is governed by the minimum off time

past 350 kHz. The resulting frequency versus duty cycle plot

is shown in Figure 9. Equation 5 shows the maximum duty

ratio.

The NCP1568D has an internally set minimum off time of

590 ns that is always imposed in ACF mode. The minimum

off time is to ensure that enough time remains in each

switching cycle to fully execute a successful high side pulse.

The minimum off time is constant, but the IC also has a

maximum duty cycle of approximately 78% to allow for

recharging of the high side driver boot capacitance and to

avoid transformer saturation. The maximum duty cycle is

therefore not constant, as the minimum off time must be

(eq. 5)

FSW t 350 kHz

Duty_Ratio + 133ns * (FSW) ) 73.7%

ƫƪ_{FSW u 350 kHz}ƫ

Duty_Ratio + 1 * FSW @ 0.59 @ ms

ƪ

80%

75%

70%

65%

60%

55%

50%

45%

40%

35%

30%

Switching Frequency (kHz)

Figure 9. Maximum Duty Ratio vs. Switching Frequency

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15

NCP1568D

ACF Oscillator Operation

In order to minimize the power loss in ACF operation, as

load and input voltage change, the frequency of operation

needs to change such that additional circulating current is

kept to a minimum. The negative current needed for ZVS is

typically in the order of −0.5 A for super junction FETs. The

current could be lower for wide bandgap semiconductors

such as gallium nitride (GaN) as their COSS is typically

lower. Keeping the negative magnetization current

sufficient to achieve ZVS is accomplished digitally by

adjusting the frequency of the oscillator until the SW node

fall time is modulated to a predetermined dead time across

line and load conditions.

A time reference T_ZVS is internally programmed in the

NCP1568D and an error signal is accumulated based on the

time the switch node takes to fall from the falling edge of

ADRV to the sensing of ZVS at the switch node by the ZVS

comparator. If the switch node decreases quickly and ZVS

occurs before the reference time T_ZVS, then there is more

than enough energy to reset the node and therefore the

frequency of operation should be increased which

effectively reduces the off time. The increased frequency

will result in less energy available for resetting the switch

node, and as such will result in less required on time for the

low side switch and a smaller D IM. The smaller D IM results

in fewer losses in the system. If the switch node ZVS occurs

coincident with the time reference T_ZVS, no frequency

adjustment is necessary. If the ZVS occurs after the T_ZVS,

the frequency is too high and needs to be reduced to ensure

good ZVS. Finally, if the ZVS never occurs and instead

reaches a maximum allowable time limit (DT_Max), the

current switching cycle ends and the LDRV is driven on, but

the frequency reduction will be applied to the following

switching cycle.

The net result is that the duty ratio would be maintained,

the load current would be supported, and the frequency

would adjust with load to provide enough energy to achieve

ZVS. The TZVS is composed of 2 internally programmable

times T_ZVS_A and TZVS_B. T_ZVS_A is half of the

D

T_Max

time. The T_ZVS_A is a course adjustment to the

total T_ZVS time. The T_ZVS_B is a fine adjustment to the

total T_ZVS time. See part number decode for available

options. T_ZVS it the addition of T_ZVS_A and T_ZVS_B

as shown below.

Switch Node

ZVS Detection

0 V

0A

Magnetizing

Current

ADRV

LDRV

ZVS

T_ZVS

T_ZVS = T_ZVS_A+ T_ZVS_B

DTMAX

Figure 10. Time Referenced Digital Modulation of Operating Frequency Regulating the ZVS Point

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16

NCP1568D

DCM Oscillator Operation

with the FB voltage and the peak current. The FB voltage

also sets the frequency of operation from the V

In DCM mode of operation, the frequency is dependent on

the DCM to ACF threshold setting and the FB voltage. The

maximum oscillator frequency is 1/2 of the minimum ACF

frequency set by the RT resistor. A frequency foldback

proportional to the FB pin voltage is also implemented in the

DCM mode. Please refer to the frequency foldback section

for a description.

TH_DCM_ACF

threshold to the V

threshold. Once the FB

on the FB pin, the peak

FB(Ipk_freeze)

voltage reaches V

FB(Ipk_freeze)

current floor is frozen to the V

value. The IC

CS( Ipk_freeze)

can produce a peak current that is greater than the V

CS(

if the PWM comparator requires a longer on time

Ipk_freeze)

to satisfy the control loop. Freezing the peak current to a

minimum value accelerates the slope of the frequency

foldback. The peak current is frozen and the oscillator

frequency is changed to maintain output voltage regulation.

As the load decreases, the frequency will keep decreasing

Frequency Foldback

In DCM operation, the frequency is the highest once the

FB reaches a settable V

threshold. The frequency of

ATH

operation is reduced as FB voltage falls to its lowest point at

the V skip threshold. Since the DCM to ACF

until it stops at the minimum frequency clamp of F

OSC(min)

FB(skip)

31 kHz. The minimum frequency occurs at the V

threshold, typically at 400 mV on the FB pin. At V

threshold, skip cycle operation is enabled.

FB(skip)

threshold is programmable, the VCO must change slopes

based on the selected V threshold as shown in Figure 11.

ATH

In frequency foldback mode, the NCP1568D on time is set

FSW/2

VATH

VCO = FSW/(2x0.8V)

VCO = FSW/(2x3.2V)

SKIP

V_FB

0.8 V

3.2V

Figure 11. VCO Frequency Change with V_ATHVoltage Selection

DCM Minimum Frequency Clamp and Skip Mode

DCM TO ACF Transition (ADRV Soft Start)

The minimum switching frequency clamp prevents the

Once all of the criteria to transition from DCM to ACF

operation have been met, the NCP1568D soft starts the

ADRV employing Leading Edge Modulation (LEM). The

ADRV soft start slowly discharges the energy stored in the

clamp capacitor in DCM operation to the output. During the

switching frequency from dropping below F

OSC(min)

(31 kHz typical). When the switching cycle is longer than

40 ms, a new switching cycle is initiated. Since the

NCP1568D forces a minimum peak current and a minimum

frequency, the power delivery cannot be continuously

controlled to zero load. Instead, the circuit starts skipping

pulses when the FB voltage drops below the skip level,

ADRV soft start time, T

, ADRV pulses will

DCM_ACF_Trans

increase from a minimum of approximately 250 ns to 1−D

in a controlled progression.

V

, and recovers operation when V

exceeds

Figure 12 shows leading edge modulation of ADRV

during the DCM to ACF transition. The secondary current

shape starts to resemble that of resonant current during the

LEM period and eventually resonant current can be seen

throughout the 1−D cycle as the ADRV soft start finishes.

FB(skip)

FB

+ V . The skip mode method provides an

FB(skip)_hys

FB(skip)

efficient method of control during light loads.

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17

NCP1568D

HSOUT

>>>>>

LSDRV

>>>>>

Upper Slow Ramp

Threshold

Leading Edge

Modulation

ACF Slow Ramp

Lower Slow Ramp

Threshold

SW

Secondary Current

Figure 12. Leading Edge Modulation of ADRV During DCM to ACF Transition

MAX

Load

0A

ADRV

LDRV

DCM

Skip

DCM

Skip

DCM

Skip

DCM

LEM

ACF

Stays at Elevated

Level 1 ms After

Completion of

LEM

3.2V

ATH Threshold

(DCM to ACF Threshold)

Qskip Exit

1.2V

FB

Frequency Based

Current Limit

790 mV

Current Limit

F

F/2

32 kHz

Frequency

Required 18

Switches in DCM

Mode

Figure 13. Typical Transition

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18

NCP1568D

Transition Hard Switch Avoidance

switch node edges and predict the ideal times to turn on the

high side switch.

Before the high side switch begins the LEM process, the

switch node demagnetizes and rings as a classic flyback

would. During the start of LEM, the switch node

demagnetization is interrupted by the switch node pulling up

to the clamp capacitor voltage. The time the switch node is

pulled up to the clamp capacitor voltage steadily increases

and the demagnetization switch node signature continues to

increase the amplitude of resonation. Either the LEM

finishes with no ringing to ground and is in full ACF mode

of operation, or the switch node is clamped on a falling edge

ring to ground by the body diode of the low side FET. When

the body diode of the low side FET is conducting, turning on

the high side switch creates a disturbance to the system,

drains the energy in the clamp capacitor, and causes large

spikes on the primary and secondary side of the transformer.

The NCP1568D has a proprietary algorithm to sense the

ACF to DCM Transition (ADRV Soft Stop)

In ACF operation, if the FB voltage is below the externally

set DTH for T

, then the system will start the

ACF_DCM_HOLD

transition from ACF switching to DCM switching using

LEM. During the T time, the active clamp

ACF_DCM_trans

FET (ADRV) duty cycle is decreased in a controlled fashion

over multiple cycles. At the same time, a non−linear

frequency foldback to half the frequency (1/2*F ) set by

osc

the RT resistor is also implemented.

A leading edge modulation technique is employed to soft

stop the active clamp FET. The soft stop time

T

is typically around 500 ms, a diagram of the

ACF_DCM_trans

soft stop is shown in Figure 14.

Last Pulses

Are ≈ 250 ns

ADRV

>>>>>

LDRV

Upper Slow Ramp

Threshold

ACF Slow Ramp

>>>>>

Leading Edge

Modulation

Lower Slow Ramp

Threshold

SW

>>>>>

Secondary Current

Figure 14. ACF to DCM Transition Waveforms

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19

NCP1568D

ATH Pin Functionality

The function of the ATH pin is to set the DCM to ACF

threshold. The threshold is set with a fixed current and a

resistor to create an analog voltage. The analog voltage is

quantized into bins; each bin is mapped to a precise internal

reference voltage which is compared against feedback to

transition into ACF operation.

Internal 5 V Rail

10 mA

4 Bit

A to D

ATH PIN

40 mV -1.15 V

ATH [0:3]

OTP

BITS

ATHS [0:1]

BG

DCM to ACF

Comparator

Taps

+

-

FB

Figure 15. ATH Setting Threshold System Diagram

ATH Pin Turn On and Sourcing Current

The ATH pin current is sourced once V exceeds the

Table 5. ATH RESISTOR SET VALUES

CC

R96 Resistor (kW) Internal Reference for FB Trip Point (V)

V (on) threshold. The sourced current is 10 mA 5%.

CC

161.2

139.6

118

3.28

3.12

2.96

2.8

Current is sourced from the ATH pin during all normal

operating conditions, DCM operation, ACF operation, and

skip. Turn on timing for the ATH pin current source is shown

in Figure 16 where the ATH pin current source turns on once

102.2

86.4

74.8

63.2

53.4

46.4

39.2

33

V

CC(on)

is reached and remains on during DCM and ACF

2.64

2.48

2.32

2.16

2

operation.

V_CCON

V_CCOFF

V

CC

Voltage

1.84

1.68

1.52

1.36

1.2

27.4

22

ATH Voltage

ATH Current

18.2

8

1.04

Figure 16. ATH Setting Threshold

Resistor Setting Range

Once a bin is selected, the selected bin maps to a set

internal voltage. The voltage measured on the ATH pin only

serves to select a digital bin and its tolerance does not affect

the internally selected voltage. The mapped reference taps

have a tolerance of approximately 2.5%. Table 5 includes the

DCM to ACF binning thresholds and resistor map.

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20

NCP1568D

DTH Pin Functionality

the standard recommended value for noise cancellation and

timing. The resistance range that will be applied to the DTH

pin can range from 0 W to 187.5 kW to set a voltage threshold

between 0 V and 3 V. The most common anticipated ACF to

DCM thresholds are shown in Figure 17. The DTH current

source is turned off in DCM operation.

The DTH pin is a real time pin that is observed

continuously once soft start has completed and forced ACF

time (please refer to soft start section) has expired. Once

V

CC

has exceeded the V (on) threshold, the DTH pin will

CC

begin sourcing 16 mA. The size of the capacitor placed on the

ATH pin governs the delay the designer will see before the

pin reaches its steady state voltage. A 100 nF capacitance is

V

_DTH+ IDTH * RDTH

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

RDTH(kΩ)

Figure 17. Setting Threshold for DTH PIN

Soft Start

reference to its final value. After TDCM_SS, the IC slowly

increases the ADRV on time via the LEM process. Once the

internal current limit reaches its maximum value, the IC then

operates in ACF mode. The IC must wait for an additional

The soft start of the NCP1568D is initiated once all of the

criteria has been satisfied for the V to reach V

other faults are present, and t

, no

CC

CC(on)

has expired. Before

delay(start)

the first pulses of the LDRV are initiated, the FB voltage is

held high by the internal pull up current source and resistor

tied to an internal 5 V source. During normal operation, the

optocoupler and current sources regulate the FB node, but in

soft start it is not regulated until the output voltage is greater

than the secondary side reference voltage and the forward

diode drop of the optocoupler. The IC will want to transition

to ACF mode immediately on the first switching pulse, as

the FB voltage will be higher than any threshold that can be

set by the ATH pin. The IC’s natural tendency is to transition

to ACF operation when heavy loads are applied to the

output. Thus, all of the criteria are met to enter the ACF

during soft start, but the boot pin for the high voltage level

shifter and driver is not charged. The NCP1568D works in

time referred to as T

time), to allow the output voltage to reach regulation and the

FB node to stabilize. After T expires, the ACF

detection circuits and logic are no longer manipulated, but

are allowed to transition as the output load requires to

achieve optimal frequency.

(typically, twice the soft start

MODE_Sam

Forced DCM

The forced DCM operation allows a sufficient number of

low side pulses to charge the high side drivers, boot

capacitor, and to allow the driver sufficient time to perform

internal startup sequences. The maximum current provided

to the output for the first few switching cycles is regulated

by the minimum on time. Minimum on time is a sum of LEB,

propagation delay of CS comparator, gate drive, and the FET

turn off. To reduce primary and secondary start up current

stress, the frequency is ramped to half the oscillator

DCM operation for the first part of the soft start T

DCM_SS

(typically 706 ms) to make sure that the boot capacitor is

charged. During the soft start, the PWM pulse width is

gradually increased by ramping the internal current limit

frequency set by RT during T

typically 706 ms.

DCM_SS

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21

NCP1568D

CS

LDRV

0V

ADRV

0V

F_OSC

F_OSC/ 2

Frequency

31 kHz

0Hz

T_{soft_start}

T_{MODE_sample}

T_{DCM_ACF_trans}

DCM/ACF

Logic Release

VOUT

T_{DCM_SS}

Figure 18. Duty Cycle and Frequency Modulation

Feedback Pin

Slope Compensation

Fixed frequency peak current mode control architecture is

prone to subharmonic oscillation for duty cycles greater than

50%. Subharmonic oscillations are typically characterized

by observing the SW node alternating wide and narrow

pulse widths. An additional compensating ramp, if either

added to the sensed inductor current or subtracted from the

loop error voltage (FB), will prevent the subharmonic

oscillations. In a flyback topology employing current mode

control, the slope of this stabilizing ramp also known as

slope compensation, is proportional to the down slope of the

power converter (duty cycle greater than 50%). The

minimum amount of slope compensation to negate the

oscillation is equal to 1/2 the down slope. However, for

dead band compensation, the ramp is equal to the down

slope. Note that with higher slope compensation, the power

converter’s ac characteristics will start resembling that of

voltage mode control. Slope compensation is set to

143 mV/ms.

The FB pin is equipped with a 100 mA pullup current

source and a 20 kW resistor. The pullup current source and

resistor work in conjunction with the optocoupler to regulate

the system output voltage.

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22

NCP1568D

VOUT

pull down circuitry is needed as the sinking current I

LS_snk

VDD

(typically 2.5 A) results in a fall time of T

(typically

LS_fall

6.5 ns) with a 1.5 nF load. The low side driver is also

equipped with an internal clamp V (typically

11.75 V) to prevent the voltage on the gate from exceeding

LDRV(low)

R_FB

I_FB

FB

the maximum rating if the V voltage of the controller

CC

increases beyond 20 V and to minimize losses in the system.

The IC draws I

(typically 3.9 mA) when the IC is

CC3

switching both LDRV and ADRV drivers at 500 kHz with

100 pF load, but increases to I and I when fully

CC4

CC5

loaded at 100 kHz and 500 kHz to 4.0 mA and 13 mA,

respectively with a 1.5 nF load.

Active Clamp Driver

The Active Clamp Driver ADRV ground based driver is

suitable for sending 5 V logic square wave signals to a high

side driver with a built in level shifter to modulate the on

time of the active clamp FET. The drive with 95 mA of

sourcing current and 231 mA of sinking current is also

sufficient to drive a pulse transformer.

Figure 19. FB Resistor and Current Pullup Diagram

Low Side Driver

The low side driver is a ground based driver and is suitable

for direct driving high capacitance switches, as its sourcing

current is I

(typically 1.3 A) resulting in a rise time of

LS_src

T

(typically 10.7 ns) with a 1.5 nF load. No additional

LS_rise

5V

5 V

Regulator

V_CC

5 V

APU

EN_V

S

Q

CC

GND

5V

ADRV

VSW

-

R

APD

V

_OFF

CC

+

9.0 V

HYS = 600 mV

HYS=

1V

Clamp

-

V

CC

12V

+

DeadTime

Logic

V

CC

_OFF

LSPU

LSPD

12 V

S

Q

GND

5V

LDRV

GND

R

R_PDLS

DEADTime_SETFR [2:0]

DEADTime_SETRF [2:0]

Figure 20. Driver Block Diagram

Adaptive Dead Time

FET or body diode is conducting. When the low side FET is

conducting, the SW is near ground potential when the

primary inductor current has a positive slope, and is referred

to as energy storage mode. The magnetizing inductance

current is ramped up during the energy storage mode until

the low side drive transitions from high to low. The switch

node is then pulled high by the circulating currents. The rate

at which the SW changes voltage is dependent on the voltage

controlled parasitic capacitance of the selected FETs at the

bridge node, the primary current, the magnetizing

inductance, the leakage inductance, and other factors. Since

The NCP1568D implements a built in adaptive dead time

that maximizes the efficiency of an active clamp flyback

converter. The dead time for the active clamp topology can

be described by first identifying the two modes of operation

of the switch node (SW) or bridge node. When the topology

is actively clamping and the SW is high, current can flow

into and out of the clamp capacitor. The time that the energy

is stored and recycled in the clamp capacitor is referred to as

the resonant mode and is identified with a high voltage on

the switch node. During the resonant mode, the high side

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23

NCP1568D

many of the governing factors determining the rise and fall

DT_E_R timer has expired, the ADRV will generate a 5 V

logic level high to turn on the high side FET so that the high

time of the switch node are design specific, an active dead

time control circuitry must be employed to optimize

efficiency for a wide range of applications. During the

energy storage to resonant mode SW node transition, the

majority of the transition time is spent charging the

side FET will start conducting. If the D

timer expires

T_Max

before the 10 V threshold is met, and the additional DT_E_R

timer has not expired, this failure will be counted, but the

ADRV will not be forced on. Once the SW is high and the

high side FET is conducting, the high side drive will remain

high until the end of the cycle. At the end of the cycle, the

ADRV will output a 5 V logic level low. When the internal

prelevel shifted ADRV TTL logic transitions from high to

relatively large C

capacitance of the low side FET when

OSS

the SW node is near ground potential and the C

OSS

capacitance of the high side FET as the SW node nears the

clamp voltage. The resulting slope of the voltage change at

low voltages is in the order of 100 MV/s. Once the switch

low, a D

timer is started. The switch node then

T_Max

node has started to charge the C , the capacitance

discharges until it reaches DT_R_E_TH, at which time the

DT_R_E timer is started. Once either the DT_R_E or the

OSS

decreases rapidly and the slope can increase on the switch

node to as much as 10 GV/s. The active dead time control

starts a timer once the LDRV internal logic has transitioned

D

T_Max

timer has expired, the LDRV will transition from

low to high and the process will continue. The dead time

D only applies to the full ACF mode of operation and

T_Max

from TTL logic level high to low referred to as D

. The

T_Max

D

is a fail safe dead timer that ensures normal

as such is blanked from ACF to DCM and DCM to ACF

transitions when the ADRV pulses are phased in and out with

T_Max

operation. After the low side driver logic transition is

tripped, the part will monitor the voltage at SW to determine

when it has exceeded 10 V. Once the 10 V threshold is

exceeded, a second timer is started called DT_E_R. After the

LEM. Further, D

is not observed during the LEM

T_Max

portion of soft start of ACF.

V_LO

V_HO

D_{T_Max}

Begin

D_{T_Max}

Begin

D_{T_Max}

Begin

D_{T_R_E}

D_{T_E_R}

D_{T_R_E}

Resonant Mode

Energy Storage

V_BRIDGE

V_IN

10 V

Figure 21. Dead Time and Mode Identification

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24

NCP1568D

OTHER PROTECTION FEATURES

FLT Input

latched off or restarted if the FLT pin voltage, V , is pulled

FLT

The NCP1568D includes a dedicated fault input

accessible via the FLT pin. The controller can be latched off

or restarted by pulling the pin up above the upper fault

threshold (typically 3.0 V). Likewise, the controller can be

below the lower fault threshold (typically 0.4 V). The

controller operates normally while the FLT pin voltage is

maintained within the upper and lower fault thresholds.

Figure 22 shows the architecture of the FLT input.

VAUX

+

-

Blanking

Tdelay (Fault _OVP)

S

Q

Latch

VDD

V_FLT(OVP)

R

I_FLT(OTP)

FLT

+

-

Blanking

Tdelay (Fault _OTP)

R

_FLT(clamp)

NTC

Thermistor

Soft Start

End

V_FLT(OTP)

V_FLT(clamp)

Hysteresis

Control

Option

Auto _Restart

Control

Figure 22. FLT Pin Diagram

OTP FLT Threshold Startup

OTP FLT Threshold and Fault Handling

The primary purpose of the lower FLT threshold is to

detect an over temperature fault using an NTC thermistor. A

pull up current source, (typically 45.5 mA) generates a

voltage drop across an external thermistor. The resistance of

the NTC thermistor decreases as the temperature rises,

resulting in a lower voltage across the thermistor. The

controller detects a fault once the thermistor voltage drops

A bypass capacitor is usually connected between the FLT

and GND pins and it will take some time for VFLT to reach

its steady state value once IFLT(OTP) is enabled. The IC is

prevented from switching as long as the FLT voltage is

below the V

threshold. When adapters are

FLT(OTP_in)

produced they must go through a burn in process. The

process calls for the adapter to be heated up to higher

ambient temperatures (typically 65°C), then powered on and

allowed to operate for an extended period of time to catch

any assembly or part defects early before they are shipped

to end customers. With the above burn in process, the FLT

pin can cause the NTC to trip and keep the part off during the

burn in process. To prevent the adapter from failing the burn

in test, the adapter must start up when the FLT voltage

below the V

threshold. The FLT voltage must

FLT(OTP_in)

drop below the threshold for longer than t

delay(OTP)

(typically 33 ms), then the IC will take the appropriate

action. If the IC is programmed to latch, the V voltage

CC

must go below Vcc(reset) before normal operation can

continue. If the IC is programmed to restart, the part will

initiate a soft start once the temperature decreases and the

corresponding NTC voltage has increased enough to exceed

exceeds V

(typically 418 mV), rather than

FLT(OTP_out_1st)

V

(typically 937 mV). Further, the IC must

the V

threshold (typically 937 mV).

FLT(OTP_out)

successfully complete a soft start by reaching the end of

forced ACF without triggering a V

Figure 23.

off as shown in

CC

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25

NCP1568D

N

First

Soft Starts

Soft Start

0.920 V

0.40 V

V_{FLT(OTP_out)}

V_{FLT(OTP_in)}

OFF

ON

OFF

ON

Figure 23. FLT Pin Diagram

Over Power Protection

in soft start

The IC is enabled above V

FLT(OTP_out_1st)

The maximum power delivered by an isolated power

converter is controlled by limiting the peak inductor current

on a pulse by pulse basis on the primary side. Power

converters typically do not deliver the same maximum

output power across all line conditions. Energy delivery is

influenced by duty ratio, line voltage, and switching

frequency. The duty ratio changes with line voltage and

hence with a fixed peak current, the average inductor current

varies over line voltage. The slope of the current increases

as the line voltage increases, delivering more energy with a

fixed propagation delay in high line operation. An internal

line OPP compensation is provided where line sensed

discrete steps provide an approximate transconductance

only, rather than V

of the FLT pin after a successful soft start is unchanged.

Therefore, a lower fault (i.e. over temperature) is

acknowledged under the V

start, holding the part in reset until the threshold is clear.

When the FLT pin is below the V threshold, the

The rest of the functionality

FLT(OTP_out).

threshold in soft

FLT(OTP_out_1st)

FLT(OTP_in)

(typically 240 mA).

current draw of the IC is I

CC1A

OVP FLT Threshold

The upper fault threshold is intended to be used to prevent

an overvoltage using a zener diode and a resistor in series

from the auxiliary winding voltage (V

the FLT pin connected at the anode as shown in Figure 22.

To reach the upper threshold, the external pull up current has

) to ground with

AUX

(g ) of 188 nA/V sourced out of the CS pin such that a

m

to be greater than the pull down capability of the clamp V

FLT

designer can compensate for the selected inductance. The

propagation delays of all comparators connected to the CS

pin such as SCP, OCP, peak current freeze, and the PWM

comparator all benefit from the line compensation.

(typically 1.75 V) and R

(typically

(clamp)

FLT (clamp)

1.57 kW) the resistor in series. The FLT voltage must

increase above the threshold for longer than t

(typically 33 ms), then the IC will take the appropriate action

delay(OTP)

Current Limit

of latching or restarting. If the IC is programmed to latch, the

The current passing through the primary main FET is

sensed via a resistor at the CS pin. The ramping current

sensed by the CS pin is used to modulate the loop error

voltage (FB) to generate PWM signals; it is also used for

cycle by cycle peak current limit control and detection of a

short circuit condition. Figure 24 below shows the block

diagram of the current limit circuitry.

V

voltage must go below V

before normal

CC

CC(reset)

operation can continue. If the IC is programmed to restart,

the part will initiate the restart timer once V voltage

decreases below the hysteresis of the OVP comparator. The

internal clamp prevents the FLT pin voltage from reaching

the upper latch threshold if the pin is open. When the FLT pin

AUX

is above the V

threshold, the current draw of the IC

FLT(OVP)

Internal Leading Edge Blanking (LEB) circuitry masks

the current sense information before applying it to the

current monitoring comparators. LEB prevents unwanted

noise from terminating the drive pulses prematurely. Placing

a small RC filter (typically 47 pF and 732 W) close to the CS

pin to suppress additional noise is suggested. The LEB

period begins once LDRV reaches approximately 2 V. An

is I

(typically 240 mA).

CC1B

When the auto recovery option is selected for the fault pin,

remains enabled while the lower fault is present

I

FLT(OTP)

independent of V

hysteresis. The controller can detect an upper OVP fault

once V exceeds V Once the controller is latched,

it is reset if V is cycled down to its reset level, V

In the typical application these conditions occur only if the

ac voltage is removed from the system.

in order to provide temperature

CC

CC(reset).

.

CC

CC(reset)

internal switch R

discharges and holds the CS pin

CS(switch)

low at the conclusion of every cycle for 100 ns. In DCM

operation, LEB is implemented by pulling the CS pin low for

the LEB period at the beginning of LDRV pulse.

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26

NCP1568D

OCP

Comparator

OCP LEB

_

+

CS

nOVLD

Restart

OR

V_{(OCP)_DCM}

V_{(OCP)_ACF}

Multiplexer

D

S1

S8

Latch

C1 C2 C3 E NB

LEM & Line

Logic

V_{(OCP)_trans}

PWM STOP

V

C

1

ENB

D

S

ILIM(SCP)

S

+

_

2

M1

V

(SCP)_trans

nAbnormal

Restart

OR

SCP LEB

Latch

SCP Comparator

(Abnormal OCP)

Figure 24. Current Limit Comparators

Cycle by Cycle Current Limiting

Cycle by Cycle (CBC) current limiting is implemented

using the OCP comparator and terminates the LSDRV drive

load conditions, the time it takes to reach full count varies.

If the counter has reached full count, a latch or auto recover

is initiated dependent on options selected referred to as OCP

reaction.

pulse if the CS voltage exceeds the V

threshold in

ILIM (OCP)

ACF and DCM modes of operation. In transition mode of

operation this threshold is raised to V to

facilitate the increased DIm while transitioning into orout of

The OCP threshold depends on mode of operation, i.e.,

DCM versus ACF and frequency pf operation. In the DCM

operation, the OCP threshold is 784 mV. However, in ACF

operation, the OCP comparator trip voltage varies with the

ILIM (OCP) Trans

ACF operation. When the CS voltage crosses the V

ILIM

, an error flag is asserted and the counter counts up 2

frequency of operation from

V

to

(OCP)

(OCP)_ACF_C1_100

counts. If a single cycle occurs in which the V

is

V

,

this feature is implemented to

ILIM (OCP)

(OCP)_ACF_C1_400

not triggered, the counter counts down 1 count. The counter

update is done at switching frequency. Hence depending

upon the mode of operation (ACF vs. DCM) and line and

compensate for higher frequency of operation in a variable

environment. Please refer to the electrical table for

frequency vs OCP level.

Table 6. CURRENT LIMIT COUNTS AND TIMING

Switching Frequency (kHz)

Counts (k)

Limiting Time (ms)

100

250

5

25

10

5

500

1000

2.5

CL Limit

CS

>>>>

0

2

4

6

5

7

9

11

49995001 Restart

Count

Figure 25. Current Limit Counting Scheme

Short Circuit Protection

A sharp rise in the CS pin sensed current can occur in the

primary side if a winding is shorted or a component is faulty.

Short circuit protection is implemented using the SCP

comparator; it terminates the drive pulse if the CS voltage

approximately 50 ns to ensure a short circuit is properly

identified. When the SCP comparator trips, a count is

incremented and a counter tracks the number of SCP events.

Once the number of consecutive SCP events crosses N

SCP

exceeds the V

mode of operation after the T

threshold in ACF, DCM, and skip

as defined in the electrical table, then the part latches or

restarts according to the OTP bits programmed referred to as

SCP reaction.

ILIM (SCP)

blanking time. The

LEB(SCP)

time

T

is shorter than the

T

by

LEB(SCP)

LEB(OCP)

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27

NCP1568D

OCP and SCP Level During Transition

ACF operation to DCM operation or DCM operation to ACF

operation via the LEM process described in the

corresponding sections, the current limits are changed.

When the system is undergoing the transition, the OCP and

The OCP and SCP have two discrete voltage trip levels at

an operating point. In ACF mode, the current limit is

modulated with frequency change. The NCP1568D ZVS

frequency modulation scheme increases the frequency as the

line voltage increases. The current limit must be decreased

to compensate for the increased available output power

when the voltage and frequency increases. The SCP and

OCP levels described in the above section are steady state

normal protections. When the system is transitioning from

SCP levels are increased from the V

(784 mV

(OCP)_ACF_100

at low line) to the V

1.2 V and the V

ILIM(OCP)_Trans

ILIM(SCP)

1.2 V to V

1.4 V. The current limit levels are

ILIM(SCP)_Trans

increased on the rising edge of the first low side drive pulse

of the transition and remain at that level for 1 ms after the

transition process has completed, as shown in Figure 26.

SCP

1 ms

OCP

1 ms

LDRV

0V

ADRV

0V

F_OSC

F_OSC/ 2

Frequency

DCM

ACF

DCM

DCM TO ACF

LEM

ACF TO DCM

LEM

Figure 26. OCP and SCP Timing

Auto Recovery and Latch

HV Bias Cycle (HVBC)

When the IC is not switching due to a fault condition and

is either waiting for restart or in latched state the IC’s VCC

The auto recovery fault behavior is used to protect the end

user from any abnormal conditions, to reduce power

consumption during a fault condition, and to allow the

adapter to recover quickly as soon as the issue has been

resolved without the need to unplug and replug the power

supply. If a fault occurs when the IC is configured to auto

recovery, ADRV and LDRV are driven low and the part

power is maintained by sourcing I

from the HV pin to

start2

the VCC pin. The V

pin is charged to the V

CC

CC(on)

threshold, at which time it will turn off. The part dissipates

a small amount of power monitoring critical nodes and

tracking restart timers while waiting to take the next action.

The standby current slowly discharges the V pin voltage

remains off for T time maintaining V voltage

auto_retry CC

CC

until the V

threshold is tripped. Once the V

through the HVBC process. At the end of T , the IC

auto_retry

CC(off)

threshold is tripped, the part will source I

, charging the

is allowed to restart via the soft start process once V

is reached.

start2

CC(on)

V

CC

capacitor to maintain critical functions. The charging

and discharging of the V voltage, also referred to as HV

CC

Bias Cycle (HVBC), will continue until the HV pin’s voltage

is removed, the V

voltage drops below V

,

CC

CC(reset)

T

has expired.

auto_retry

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28

NCP1568D

Fault Applied

Fault Removed

Fault

V_CC

V_{CC (on)}

V_{CC (off )}

Restarts

At V_CC(on)

(new bias

cycle if fault is

still present)

DRV

Controller

Stops

Autorecovery

Timer

Tauto _retry

T_{auto _retry}

Figure 27. Fault Recovery Behavior

Latching Fault Behavior

The purpose of a latch fault is to require user intervention

to restore proper operation of the adapter or power supply.

The user is expected to unplug and replug the adapter to

enable the power supply to attempt regulation. If a fault

occurs and the NCP1568D is configured to have a latch fault

in ACF operation or DCM operation once the current clock

cycle expires, both LDRV and ADRV are terminated. In skip

operation since there are no pulses, no pulses will be

produced as a result of a latch fault. The part then monitors

the line to determine when power has been removed and

maintains V

voltage by HVBC. When the FLT pin

CC

initiates a latch fault, the current draw of the IC is I

CC1C

(typically 220 mA).

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29

NCP1568D

Latch Event

Latch

Time

V

CC

V

CC(on)

CC(off)

Time

DRV

I

HV

I

start2

I

HV(off)

Time

Figure 28. Fault Latched Behavior

Thermal Shutdown

nonlatching fault mode and remains there until the junction

temperature drops below T by the thermal shutdown

An internal thermal shutdown circuit monitors the

junction temperature of the controller. The controller is

disabled if the junction temperature exceeds the thermal

shutdown threshold, T

thermal shutdown fault is detected, the controller enters a

SHDN

hysteresis, T

shutdown is also cleared if V drops below V

, (typically 40°C). The thermal

SHDN(HYS)

, or

CC

CC(reset)

(typically 150°C). When a

a line removal fault is detected. A new power up sequence

commences at the next V

SHDN

.

CC(on)

www.onsemi.com

30

NCP1568D

TYPICAL CHARACTERISTICS

15.29

15.28

15.27

15.26

9.090

9.085

9.080

9.075

9.070

9.065

15.25

15.24

15.23

9.060

9.055

15.22

15.21

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 29. V_CC(on)vs. Temperature

Figure 30. V_CC(off)vs. Temperature

0.60

0.58

3.65

3.64

3.63

3.62

3.61

0.56

0.54

0.52

0.50

0.48

3.60

3.59

0.46

0.44

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 31. I_start1vs. Temperature

Figure 32. I_start2vs. Temperature

17

16

I

3

2

HV(Off)

15

HV(Off)

14

13

12

I

1

HV(Off)

11

10

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

Figure 33. I_HV(off)vs. Temperature

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31

NCP1568D

TYPICAL CHARACTERISTICS (Continued)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

132

128

I

3

SW(Off)

I

3

1

124

120

116

112

108

SW(Off)

I

2

SW(Off)

I

2

1

SW(Off)

0.2

0

104

100

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 34. I_SW(off)vs. Temperature

Figure 35. I_SW(on)vs. Temperature

300

290

280

270

260

250

240

230

4.0

3.9

I

3.8

3.7

3.6

3.5

3.4

CC3

I

CC2

I

CC1b

I

CC1a

CC4

I

CC1c

3.3

3.2

220

210

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 36. I_CC1and I_CC2vs. Temperature

Figure 37. I_CC3and I_CC4vs. Temperature

9.0

8.9

8.8

8.7

8.6

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

Figure 38. I_CC5vs. Temperature

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32

NCP1568D

TYPICAL CHARACTERISTICS (Continued)

1.6

1.5

1.4

1.3

2.3

2.2

2.1

2.0

1.9

1.8

1.7

ATH3

ATH2

ATH1

ATH0

ATH7

ATH6

ATH5

ATH4

1.2

1.1

1.0

0.9

1.6

1.5

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 39. ATH 0−3 vs. Temperature

Figure 40. ATH 4−7 vs. Temperature

2.9

2.8

3.4

ATH11

ATH10

ATH9

ATH14

3.3

3.2

2.7

ATH13

ATH12

2.6

2.5

2.4

3.1

3.0

ATH8

2.9

2.8

2.3

2.2

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 41. ATH 8−11 vs. Temperature

Figure 42. ATH 12−14 vs. Temperature

17

16

15

14

13

12

11

45.6

45.5

I

DTH

I

45.4

45.3

FLT

45.2

45.1

45.0

44.9

I

ATH

10

9

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 43. I_DTHand I_ATHvs. Temperature

Figure 44. I_FLTvs. Temperature

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33

NCP1568D

TYPICAL CHARACTERISTICS (Continued)

34

33

32

31

30

29

28

108

106

104

102

100

98

96

27

26

94

92

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 45. F_MINvs. Temperature

Figure 46. Fosc_LL_ACF_100 vs. Temperature

435

430

425

420

162.0

161.5

161.0

160.5

160.0

415

159.5

159.0

410

405

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 47. Fosc_LL_ACF_UB1 vs.

Temperature

Figure 48. TZVS_2 NCP1568D00DBR2G vs.

Temperature

810

790

V(OCP)_ACF_C1_100

V(OCP)_ACF_C1_175

770

750

730

710

690

670

650

630

V(OCP)_ACF_C1_213

V(OCP)_ACF_C1_238

V(OCP)_ACF_C1_250

V(OCP)_ACF_C1_263

V(OCP)_ACF_C1_300

610

590

570

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

Figure 49. V_(OCP)vs. Temperature

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34

NCP1568D

TYPICAL CHARACTERISTICS (Continued)

416.5

416.0

415.5

415.0

399.1

399.0

398.9

398.8

414.5

398.7

398.6

414.0

413.5

−40 −25 −10

5

20 35 50 65 80 95 110 125

−40 −25 −10

5

20 35 50 65 80 95 110 125

T , JUNCTION TEMPERATURE (°C)

J

T , JUNCTION TEMPERATURE (°C)

J

Figure 50. V_FB(skip)vs. Temperature

Figure 51. V_{FLT(OTP_in)}vs. Temperature

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35

NCP1568D

PART NUMBER DECODING INFORMATION

Disable OPP Sampling

Enable NDTMAX

ATH Pin Mapping

ATH Internal = I / External = E

Select DCM Lockout Time (ms)

LEM Collision Avoidance Enable

OPP Disable

LDRV OFF to HDRV or ADRV ON)

(Fixed Dead-Time from

Restart Timer (ms)

Consecutive SCP Events (#)

Consecutive OCP Events (k#)

FB Pullup Current (mA)

FB Pullup Resistor (kΩ)

Slope Comp Ramp (mV/ms)

Skip Type /Skip Disable

Disable Fast Freq Step

Frozen Peak Onset (V)

ACF Soft Stop (ms)

ACF FET Softᖝ start Time (ms)

Disable Slope Comp

DCM Oscillator Frequency Max

ATH Threshold/ ACF Only

VHV Hyst

VHV

FLT Pin OVP (Latch = L Reset = R)

FLT Pin OTP (Latch = L Reset = R)

OCP Reaction (Latch = L Reset = R)

SCP Reaction (Latch = L Reset = R)

T_ZVSB (ns)

LEB/ DTMAX/ T_ZVSA (ns)

Softᖝ Start Time (ms)

Part Number Extension 2

Part Number Extension 1

Switch Technology

Part Number

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36

NCP1568D

PACKAGE DIMENSIONS

TSSOP16 MINUS PINS 2,3,14 & 15

CASE 948BW

ISSUE O

www.onsemi.com

37

NCP1568D

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38


型号：	NCP1568DD00DBR2G
厂家：	ONSEMI
描述：	DC-DC Active Clamp Flyback PWM Controller
文件：	总39页 (文件大小：769K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP1568DD00DBR2G [ONSEMI]

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