NCP1623ASNT1G [ONSEMI]
Critical Conduction Mode (CrM) Power Factor Correction Controller, Follower Boost;
| 型号： | NCP1623ASNT1G |
| 厂家： | 
ONSEMI |
| 描述： | Critical Conduction Mode (CrM) Power Factor Correction Controller, Follower Boost |
| 文件： | 总20页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Enhanced, High-Efficiency
Power Factor Controller
PACKAGE PICTURES
8
1
NCP1623
1
TSOP−6
(SOT23−6)
SOIC−8
D SUFFIX
Features
SN SUFFIX
CASE 318G−02
CASE 751−07
• Valley Synchronized Frequency Fold−back (VSFF):
♦ CrM at Heavy Load
♦ DCM at Light Load by Dead Time Control
♦ Valley Switching in Both CrM and DCM
• On−time Modulation for High PFC in Both CrM and DCM
MARKING DIAGRAMS
8
• Follower Boost Capability (NCP1623A Only)
♦ Lowered Output Voltage Regulation at Low Line
♦ High−Efficient Boost Stage and Downsized Inductor Design
• Skip Mode for Light Load Regulation
1623x
ALYW
G
XXXAYWG
G
1
1
x = A
XXX = Specific Device Code
• Sleep Mode with Low Current Consumption (SOIC8 Only)
A = Assembly Location
L = Wafer Lot
A
Y
W
G
= Assembly Location
= Year
• Fast Line / Load Transient Control
♦ Dynamic Response Enhancer at Output Undershoot
♦ Soft OVP and Fast OVP at Output Overshoot
• Excessive Current Protection
Y = Year
= Work Week
W = Work Week
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
♦ Over Current Protection (OCP)
♦ Over Stress Protection (OVS)
PIN CONNECTIONS
• Brown Out Protection
• Second Over Voltage Protection (OVP2)
• These are Pb−Free Devices
1
2
3
4
8
7
6
5
6
5
4
FB
VCTRL
NC
1
2
3
VCTRL
FB
V
CC
GND
V
CC
DRV
CS/ZCD
DIS
CS/ZCD
Typical Applications
DRV
GND
• USB−PD
(Top View)
TSOP−6
(Top View)
SOIC−8
• Flat TV
• Industrial Power Supplies
• All Off−line Appliances Requiring Power Factor Correction
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
December, 2021 − Rev. 0
NCP1623/D
NCP1623
L
BST
D
BST
L
EMI
Filter
V
AUX
C
IN
C
Load
BULK
N
R
FB1
C
P
FB
6
VCTRL
1
C
Z
R
Z
GND
2
VCC
5
R
NCP1623
TSOP6
FB2
V
EXT
V
DS
CS/ZCD
3
DRV
4
R
CS2
R
SENSE
NCP1623
SOIC8
V
DS
PFC
ENABLE
SIGNAL
R
CS1
Option 1: Drain ZCD sensing
5
DIS
V
AUX
R
R
AUX
CS1
C
AUX
C
DIS
D
AUX
opto
Option 2: Auxiliary
Disable circuit example
−winding ZCD sensing
Figure 1. Application Schematic
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2
NCP1623
I
I
VCTRL(START)
VCTRL(DRE)
I
FB(LL)
OTA current
detection
PFCOK
PFCOK
DRE
VCTRL
LLINE
FB
VREF
OFF
Transconductance
Error Amplifier
BONOK
DIS
VCTRL
Clamping
Under Voltage
Protection
V
V
STATICOVP
Detection
CTRL(MAX)
UVP
V
V
FB(UVP)
CTRL(MIN)
CS/ZCD
STATICOVP
Dynamic
Response
Enhancer
Over Current
Protection
DRE
OCP
V
FB(DRE)
CS(OCP)
Over Stress
Protection
O VS
ZCD
Soft OVP
Fast OVP
SOVP
FOVP
V
CS(OVS)
V
FB(SOVP)
Zero Cross
Detection
V
ZCD(TH−H/L)
V
FB(FOVP)
Line
Detection
VCC
DRV
LLINE
BONOK
OVP2
V
CS/ZCD(HL/LL)
UVLO
V
/V
CC(ON) CC(OFF)
Brown Out
Protection
V
CS/ZCD(BO)
Second
OVP
ZCD
VCTRL
VSFF
Q
S
R
V
ZCD(OVP2)
Driver
SOIC8 Only
Saw −tooth
Generator
R
DIS
LLINE
DIS
DIS
Detection
DIS
V
DIS
On −time
VCTRL
VCTRL
Modulation
SKIP
V
STATICOVP
BONOK
DIS
CTRL(SKIP)
GND
OFF Mode
Management
(IC reset)
OFF
UVP
OCP
OVS
OVP2
SOVP
FOVP
UVLO
STOP
Thermal
Shutdown
TSD
Figure 2. Simplified Block Diagram
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3
NCP1623
PIN CONNECTIONS
VCTRL
GND
6
FB
1
2
FB
8
7
6
VCTRL
NC
1
2
3
V
CC
5
V
CC
DRV
CS/ZCD
DIS
5
GND
4
4
DRV
CS/ZCD
3
(Top View)
(Top View)
SOIC−8
TSOP−6
Table 1. PIN DESCRIPTION
Pin Number
TSOP−6
Pin Number
SOIC−8
Pin Name
Description
1
8
VCTRL
The error amplifier output is connected to this pin. The regulation loop bandwidth is
adjusted by the feedback compensation network connected between this pin and
ground. When IC is reset at off mode, the NCP1623 grounds the VCTRL pin to provide
a soft−start function at a subsequent startup.
2
3
4
6
GND
Power Supply Ground
CS/ZCD
Based on a novel technique, this multi−functional pin is designed to monitor inductor
current, ZCD signal and input/output voltage.
4
3
DRV
The high−current capability of the totem pole gate drive makes it suitable to drive high gate
charge power FETs.
5
6
2
1
V
IC operating current is supplied to this pin.
CC
FB
The feedback pin is connected to the input of the error amplifier to monitor the PFC output
voltage for regulation. Also, this pin detects the PFC output transient condition to enable
DRE, SOVP and FOVP for overshoot−less and undershoot−less output regulation.
A 250 nA sink current is built−in to trigger the UVP protection and disable the part if the
feedback pin is accidently open.
NCP1623A FB pin further sources a current (I
of 25 mA typically) to adjust a lower
FB(LL)
output regulation level in low−line conditions for higher efficiency and downsized boost
inductor design.
5
7
DIS
NC
A high level or open circuit on this pin disables the controller and reduces I bias current
CC
for low standby power.
No Connect (Note 1)
1. True no connect. Printed circuit board traces are allowable.
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4
NCP1623
Table 2. MAXIMUM RATINGS
Parameter
Symbol
Value
−0.3 to 30
−0.3 to 11.5
−0.3 to 9
−0.3 to 9
−0.3 to 9
Units
Power Supply Input
V
CC
V
V
V
V
V
V
CS/ZCD Pin with 5 mA of Clamp Current
Feedback Pin
CS/ZCD
FB
V
CTRL
Pin
V
CTRL
Disable Pin, SOIC−8 Version
DIS
Driver Voltage
DRV
−0.3 to V
DRV(HIGH)
(Note 2)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature Soldering
T
150
°C
°C
°C
J(MAX)
T
−60 to 150
260
STG
T
SLD
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
ESD Capability, Human Body Model (Note 4)
ESD Capability, Charge Device Model (Note 4)
Moisture Sensitivity Level
ESD
ESD
2
1
1
kV
kV
−
HBM
CDM
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. V
is the DRV high clamp voltage if V is higher than V VDRV is V otherwise.
DRV(HIGH)
CC
DRV(HIGH) CC
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
THERMAL CHARACTERISTICS (Note 5)
Parameter
Symbol
Value
230
Unit
°C/W
°C/W
Thermal Characteristics, TSOP−6
Thermal Resistance, Junction−to−Air
R
q
JA
Thermal Characteristics, SOIC−8
Thermal Resistance, Junction−to−Air
R
153
q
JA
2
5. Mounted on a JEDEC standard 51−3 (1s0p) test board, 100 mm copper area, 1 oz copper thickness.
RECOMMENDED OPERATING RANGES
Parameter
Operating Junction Temperature Range
Symbol
Min
Max
Unit
T
J
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCP1623
Table 3. ELECTRICAL CHARACTERISTICS
(V = 18.5 V and T = −40°C to 125°C, unless otherwise noted)
CC
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SUPPLY CIRCUIT
V
V
V
V
Turn−On Voltage
V
V
rising
falling
9.75
8.5
1.0
6
10.50
9.0
1.5
7
11.25
9.5
2.0
8
V
V
CC
CC
CC
CC
CC(ON)
CC
Turn−Off Voltage
V
V
V
V
CC
CC(OFF)
CC(HYS)
CC(RST)
Turn−On/Off Hysteresis
V
V
V
CC(ON) − CC(OFF)
Reset Voltage, I Drops to I
V
CC
falling
= 7 V
V
CC
CC(START)
IC Start−Up Current
I
V
−
20
0.5
2
50
mA
mA
mA
mA
CC(START)
CC
IC Operating Current without Switching
IC Operating Current when Switching
IC Sleep Mode Current, SOIC−8
GATE DRIVE
I
I
No switching
−
1.0
3
CC1
f
= 50 kHz, No C load
−
CC2
SW
L
I
DIS pin high
−
−
100
CC(DIS)
DRV Rising Time
t
C = 1 nF
15
10
−
30
20
10
7
90
50
20
15
14
ns
ns
W
W
V
R
L
DRV Falling Time
t
C = 1 nF
L
F
DRV Source Resistance
DRV Sink Resistance
R
OH
R
−
OL
DRV(HIGH)
DRV High Clamp Voltage
ON–TIME CONTROL
V
V
CC
= 30 V, R = 33 kW
10
12
L
Maximum On−Time at Low Line
t
ms
ms
ON(MAX−LL)
t
ON(MAX−HL)
Ver. A
Ver. C
10.8
13.5
12.5
16.5
14.2
19.5
Maximum On−Time at High Line
Ver. A
Ver. C
4.2
5.6
5.0
6.6
5.8
7.6
On−Time Ratio of Low and High Line
Minimum On Time at Low−Line
Minimum On Time at High−Line
FREQUENCY FOLDBACK AND SKIP
Dead−Time 1
K
t
/t
2.0
100
50
2.5
180
100
3.0
250
150
−
TON(LL−HL)
ON(LL) ON(HL)
t
ns
ns
ON(MIN−LL)
t
ON(MIN−HL)
t
t
V
V
= 0.63 V
= 0.75 V
13
5.5
18
8.5
23
ms
ms
V
DT1
CTRL
Dead−Time 2
11.5
2.29
2.40
120
32
DT2
CTRL
VCTRL Frequency Foldback Enter Voltage
VCTRL Frequency Foldback Exit Voltage
VCTRL Frequency Foldback Hysteresis
Minimum Frequency
V
V
V
falling
rising
1.87
1.96
75
2.08
2.18
100
28
CTRL(FF−EN)
CTRL(FF−EX)
CTRL
V
V
CTRL
V
mV
kHz
V
CTRL(FF−HYS)
f
24
MIN
VCTRL Skip Enter Voltage
V
V
V
falling
rising
0.50
0.55
40
0.56
0.62
70
0.62
0.68
100
CTRL(SKIP−EN)
CTRL(SKIP−EX)
CTRL
VCTRL Skip Exit Voltage
V
V
CTRL
VCTRL Skip Hysteresis
V
mV
CTRL(SKIP−HYS)
FEEDBACK REGULATION
FB Regulation Reference Voltage
FB Source Current at Low Line, Ver. A
Error Amplifier Source Current
Error Amplifier Sink Current
Error Amplifier Gain
V
2.44
23.75
15
2.50
25.00
20
2.56
26.25
25
V
REF
I
mA
mA
mA
mS
V
FB(LL)
I
V
V
= 2.4 V
= 2.6 V
EA(SOURCE)
FB
I
−25
110
4.0
−20
200
4.5
−15
290
5.0
EA(SINK)
FB
G
EA
CTRL(MAX)
VCTRL Maximum Clamping Voltage
VCTRL Minimum Clamping Voltage
VCTRL Startup Source Current
V
V
= 2 V
= 3 V
FB
V
V
0.3
0.5
0.8
V
CTRL(MIN)
VCTRL(START)
FB
I
90
120
150
mA
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NCP1623
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V = 18.5 V and T = −40°C to 125°C, unless otherwise noted)
CC
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FEEDBACK DYNAMIC RESPONSE ENHANCER (DRE)
FB DRE Enter Voltage Ratio
FB DRE Exit Voltage Ratio
FB DRE Hysteresis Ratio
VCTRL DRE Source Current
K
K
V
V
/ V
/ V
94.5
96.5
1
95.5
97.5
2
96.5
98.5
3
%
%
FB(DRE−EN)
FB(DRE−EN)
REF
FB(DRE−EX)
FB(DRE−EX)
REF
K
%
FB(DRE−HYS)
I
180
215
250
mA
VCTRL(DRE)
FEEDBACK SOFT AND FAST OVER VOLTAGE PROTECTION (SOVP AND FOVP)
FB SOVP Enter Voltage Ratio
K
V
/ V
/ V
103.5
101.5
1
105.0
103.0
2
106.5
104.5
3
%
%
%
%
%
%
%
%
%
%
%
%
FB(SOVP−EN)
FB(SOVP−EX)
FB(SOVP−EN)
FB(SOVP−EX)
REF
FB SOVP Exit Voltage Ratio
K
V
REF
FB SOVP Hysteresis Ratio
K
FB(SOVP−HYS)
FB SOVP Enter Voltage Ratio at Low Line, Ver. A
FB SOVP Exit Voltage Ratio at Low Line, Ver. A
FB SOVP Hysteresis Ratio at Low Line, Ver. A
FB FOVP Enter Voltage Ratio
K
K
V
V
/ V
108.5
106.5
1
110.0
108.0
2
111.5
109.5
3
FB(SOVP−EN−LL)
FB(SOVP−EX−LL)
FB(SOVP−EN−LL)
REF
/ V
FB(SOVP−EX−LL)
REF
K
FB(SOVP−HYS−LL)
K
K
V
V
/ V
REF
105.5
103.5
1
107.0
105.0
2
108.5
106.5
3
FB(FOVP−EN)
FB(FOVP−EX)
FB(FOVP−EN)
FB FOVP Exit Voltage Ratio
/ V
REF
FB(FOVP−EX)
FB FOVP Hysteresis Ratio
K
FB(FOVP−HYS)
FB FOVP Enter Voltage Ratio at Low Line, Ver. A
FB FOVP Exit Voltage Ratio at Low Line, Ver. A
FB FOVP Hysteresis Ratio at Low Line, Ver. A
K
V
V
/ V
112.5
110.5
1
114.0
112.0
2
115.5
113.5
3
FB(FOVP−EN−LL)
FB(FOVP−EX−LL)
FB(FOVP−EN−LL)
REF
K
/ V
FB(SOVP−EX−LL)
REF
K
FB(FOVP−HYS−LL)
FEEDBACK UNDER VOLTAGE PROTECTION (UVP)
FB UVP Enter Voltage
V
V
V
falling
rising
falling
rising
240
470
1.1
1.2
50
300
530
1.2
360
590
1.3
mV
mV
V
FB(UVP−EN)
FB
FB UVP Exit Voltage
V
FB(UVP−EX)
FB
FB
FB UVP Enter Voltage at Low Line, Ver. A
FB UVP Exit Voltage at Low Line, Ver. A
FB UVP Sink Current
V
V
FB(UVP−EN−LL)
FB(UVP−EX−LL)
V
V
1.3
1.4
V
FB
I
250
450
nA
FB(UVP)
CURRENT SENSE AND ZERO CURRENT DETECTION
CS Over−Current Protection (OCP) Voltage
CS OCP Leading Edge Blanking Time
CS OCP to DRV Off Delay Time
V
450
320
−
500
400
40
550
460
200
825
350
900
75
mV
ns
CS(OCP)
OCP(LEB)
OCP(DLY)
t
t
dV
/ dt = 10 V/ms
ns
CS/ZCD
CS Over−Stress Protection (OVS) Voltage
CS OVS Leading Edge Blanking Time
CS OVS Watch Dog Timer
V
675
50
750
200
800
40
mV
ns
CS(OVS)
t
OVS(LEB)
t
700
5
ms
OVS(WDG)
ZCD High Threshold Voltage
ZCD Low Threshold Voltage
ZCD Low Threshold Hysteresis
ZCD Blanking Time
V
V
rising
falling
mV
mV
mV
ns
ZCD(TH−H)
CS/ZCD
V
V
−75
50
−40
80
−5
ZCD(TH−L)
CS/ZCD
V
110
700
ZCD(TH−HYS)
t
500
600
ZCD(BLANK)
ZCD to DRV On Delay Time
t
ns
ZCD(DLY)
Ver. A
Ver. C
170
250
220
310
270
370
ZCD Watch Dog Timer
t
80
40
200
50
320
60
ms
ZCD(WDG)
CS/ZCD Source Current
for Short−to−Ground Pin Detection
I
mA
ZCD(GND)
CS/ZCD Threshold Voltage
V
200
8.0
240
9.5
280
mV
V
ZCD(GND)
for Short−to−Ground Pin Detection
CS/ZCD Clamp Voltage
V
I
= 5 mA
11.5
CS/ZCD(CL)
CS/ZCD
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NCP1623
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V = 18.5 V and T = −40°C to 125°C, unless otherwise noted)
CC
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
LINE RANGE DETECTION
CS/ZCD High Line Detection Voltage
ZCD Low Line Detection Voltage
ZCD Line Detection Hysteresis
V
V
rising
falling
1.65
1.45
200
20
1.80
1.55
300
25
1.95
1.65
400
30
V
V
CS/ZCD(HL)
CS/ZCD
V
V
CS/ZCD(LL)
CS/ZCD(LD−HYS)
CS/ZCD
V
mV
ms
ms
CS/ZCD Line Detection Blanking Time
CS/ZCD Line Detection Watch Dog Timer, Ver. A
t
V
falling
LD(BLANK)
CS/ZCD
t
430
500
560
LD(WDG)
BROWN–OUT (BO) − DISABLED IN A AND C VERSION
CS/ZCD BO Enter Voltage
CS/ZCD BO Exit Voltage
CS/ZCD BO Hysteresis
CS/ZCD BO Blanking Time
VCTRL BO Sink Current
V
V
V
falling
rising
730
860
130
35
790
940
145
50
850
1020
160
65
mV
mV
mV
ms
mA
CS/ZCD(BO−EN)
CS/ZCD(BO−EX)
CS/ZCD
V
CS/ZCD
V
CS/ZCD(BO−HYS)
t
I
BO(BLANK)
VCTRL(BO)
20
30
40
SECOND OVER VOLTAGE PROTECTION (OVP2) − C VERSION ONLY
ZCD OVP2 Enter Voltage
V
V rising
CS/ZCD
3.61
0.8
55
3.77
1.0
75
3.93
1.2
95
V
ZCD(OVP2−EN)
ZCD OVP2 Blanking Time
t
ms
ms
OVP2(BLANK)
ZCD OVP2 Reset Time to Disable DRV
THERMAL SHUTDOWN
t
OVP2(RST)
Thermal Shutdown Threshold (Note 6)
Thermal Shutdown Hysteresis (Note 6)
DISABLE MODE − SOIC8 ONLY
DIS Sleep Mode Enter Voltage
DIS Sleep Mode Exit Voltage
DIS Sleep Mode Hysteresis
T
150
−
−
−
°C
°C
LIMT
H
−
50
TEMP
V
V
V
rising
1.5
0.8
0.5
1.8
1.1
0.7
2.1
1.4
0.9
V
V
V
DIS(EN)
DIS
V
DIS
falling
DIS(EX)
V
DIS(HYS)
DIS Sleep Mode Detection Blanking Time
Ver. A
Ver. C
t
DIS(BLANK)
16
16
25
25
34
34
ms
ms
DIS Pull*Up Resistance
R
370
530
690
kW
DIS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Values based on design and/or characterization.
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NCP1623
DEFINITIONS
General
Feedback Transient Control (SOVP, FOVP and DRE)
Extremely compact, the NCP1623 is designed to optimize
Since PFC stages exhibit low loop bandwidth, abrupt
changes in the load or input voltage (e.g. at start−up) may
cause excessive over or under voltages. Firstly, the soft
and fast over voltage protections (SOVP and FOVP)
interrupt the power delivery when the output voltage is
excessive. At output voltage undershoot, the circuit
dramatically speeds up the regulation loop when the output
voltage goes below the low detect threshold (dynamic
response enhancer − DRE).
the efficiency of your PFC stage throughout the load range.
It also incorporates protection features for a rugged
operation. More generally, NCP1623 is ideal in systems
where cost−effectiveness, reliability, high power factor and
efficiency ratios are key requirements:
Low Start−Up Current and Large VCC Range
The A and C versions (V
of 10.5 V typically) are
CC(ON)
preferred in applications where the controller is fed by an
external power source (from an auxiliary power supply or
from a downstream converter). Its maximum start−up level
Over Current and Over Stress Protection (OCP, OVS)
The circuit senses the FET current and turns it off if the
sensed current exceeds the OCP limit. In addition, the circuit
pauses FET switching for 800 ms when the current reaches
OVS threshold as result of an inductor saturation or a short
of the bypass diode.
(11.25 V, V ) eases circuit powering from traditional
CC(ON)
12−V rails. After start−up, the high V maximum rating
CC
allows a large V operation range from 9.5 V up to 30 V,
CC
thus easing the circuit feeding.
Output Stage Totem Pole
Brown−Out Protection
(BO, Disabled in A and C Version)
The circuit detects too low ac line conditions and stops
operation thus protecting the PFC stage from excessive
stress.
NCP1623 incorporates a −0.5 A / +0.8 A gate driver to
efficiently drive most power FETs typically used in 70 to
300 W power supplies. As V can be as high as 30 V, an
CC
internal clamp limits the DRV pin to 14 V max to be
compatible with typical gate−source max ratings of industry
MOSFETs.
Second Over−Voltage Protection
(OVP2, C Version Only)
CS/ZCD multi−functional pin is used to detect excessive
output voltage levels and prevent a destructive output
voltage runaway if the feedback network happens to be
wrong. (incorrect resistors value, aging effects...)
Valley Synchronized Frequency Fold−Back
NCP1623 classically operates in critical conduction mode
(CrM) until the power drops below a threshold level where
the PFC stage enters the discontinuous conduction mode
(DCM) with a dead time prolonged as the load further
decays (frequency foldback). This novel technique also
provides stable valley turn−on in both CrM and DCM for a
maximized efficiency. In addition, the minimum frequency
clamp (33 kHz typically) prevents audible frequencies and
the on−time is modulated to ensure near−unity power factor
in both CrM and DCM operations.
Under−Voltage Protection (UVP)
This circuit turns off FET switching when the FB pin
voltage drops close to 0 V at low ac line or a failure in the
feedback network (e.g., accidental short to ground / open
failure of the FB pin).
Thermal Shutdown (TSD)
An internal thermal circuitry disables the gate drive when
the junction temperature exceeds 150°C. The circuit
resumes operation once the temperature drops below
approximately 100°C (50°C hysteresis).
Compactness
The NCP1623 features the CS/ZCD multifunctional pin
based on a novel technique for an enhanced control and a
large bunch of protections in a small TSOP6 (or SOIC8)
package with few external components. In addition, the
NCP1623A forces a lower output regulation level in
low−line condition to raise the PFC stage efficiency and
reduce its size. This 2−level Follower Boost technique best
fits for applications where the downstream converter (like a
flyback power supply) can withstand input voltage
variations in a cost−effective and efficient manner.
Disable Function (SOIC8 Package Only)
In case of SOIC8 package option, DIS pin is provided to
disable most of the internal blocks in NCP1623 to minimize
V
CC
supply current.
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9
NCP1623
APPLICATIONS INFORMATION
FREQUENCY CONTROL
voltage is not minimum. In other words, the dead−time is
extended until the next valley is detected.
Valley Synchronized Frequency Foldback (VSFF)
The NCP1623 implements the Valley Synchronized
Frequency Fold−back (VSFF) which consists of operating
the PFC stage in critical conduction mode (CrM) until the
power drops below a threshold level. As the power is further
reduced under the threshold, the PFC stage enters the
discontinuous conduction mode (DCM) with a dead time
which gets longer.
Whether the frequency is reduced by VSFF, an on−time
modulation in NCP1623 adjusts the DRV turn−on time to
compensate the dead−times in DCM for unity power factor.
Also, the minimum frequency clamp prevents the system
from operating at audible frequencies.
Minimum Switching Frequency
The DCM dead−time is an increasing function of
Practically, the output of the regulation error amplifier
V
− V . This frequency foldback function
CTRL
CTRL(FF−EN)
(V ) is used to select the operation mode and to adjust
CTRL
reduces the light−load switching frequency to optimize the
efficiency. However, an internal minimum frequency logic
limits the switching frequency above the audible frequency.
the dead−time duration. More specifically, the circuit enters
the DCM mode when V
foldback enter voltage, V
drops below a frequency
CTRL
and remains in this
CTRL(FF−EN)
mode until V
exceeds a frequency foldback exit
CTRL
Minimum frequency synchronized by ZCD
voltage,
V
with 100 mV hysteresis,
CTRL(FF−EX)
V
. Figure 3 summarizes this functioning.
CTRL(FF−HYS)
V
ZCD
V
CTRL
> V
CTRL(FF−EX)
⇒ No dead−time
⇒ CrM
Dead−time by VSFF
32 ms (31 kHz)
V
CTRL
< V
CTRL(FF−EN)
36 ms (28 kHz)
⇒ Short dead−time
⇒ DCM
V
V
DRV
Dead−time
V
CTRL
<< V
CTRL(FF−EN)
Minimum frequency without ZCD
⇒ Longer dead−time
⇒ deep DCM
Dead−time
ZCD
Figure 3. Drain Voltage in VSFF
Dead−time by VSFF
32 ms (31 kHz)
V
CTRL
determines the turn−on time (t ) in the voltage
ON
mode where V
– V (0.5 V) sets t
CTRL(MIN) ON
CTRL
36 ms (28 kHz)
proportionally and V
control range is up to
CTRL
V
DRV
V
(4.5 V). Therefore, the input power is
CTRL(MAX)
determined by:
Figure 4. Minimum Switching Frequency
V2
ǒ
Ǔ
tON(MAX) @ VCTRL * VCTRL(MIN)
IN.RMS
PIN
+
@
2L
VCTRL(MAX) * VCTRL(MIN)
As shown by Figure 4, 32 ms switching period is counted
and the DRV output will then turn on when the circuit detects
the next valley. However, if no valley can be detected, DRV
is forced high in 36 ms switching period whatever the
drain−source voltage is. As a result, the minimum frequency
is typically between 31 kHz (32 ms switching period) if a
valley is immediately detected and 28 kHz (36 ms switching
period) if no valley can be detected.
Note that if the circuit cannot detect ZCD signal at all
during DRV turn−off time, the circuit does not generate any
DRV pulses until the 200 ms ZCD watchdog time has
elapsed.
(eq. 1)
V
is typically 2.08 V for the A and C version
CTRL(FF−EN)
so that the input power level entering frequency foldback is:
V2
PIN
+
IN.RMS @ tON(MAX) @ 0.395
2L
(eq. 2)
To further improve efficiency, the MOSFET turn on is
delayed until its drain−source voltage is at its valley.
Practically, the circuit forces the dead−time dictated by the
V
CTRL
level. However, the NCP1623 does not immediately
generate a DRV pulse if it detects that the FET drain−source
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10
NCP1623
ON−TIME MODULATION
FEEDBACK REGULATION
When the FET is on, the inductor current of a CrM/DCM
PFC boost stage starts from zero and ramps up with the slope
OTA and VCTRL Function
A trans−conductance error amplifier (OTA) with access to
the inverting input and output is provided as shown in
Figure 6. It features a FB reference voltage for output
voltage regulation of 2.5 V, a typical trans−conductance gain
of 200 mS and a maximum capability of about 20 mA OTA
output current. The VCTRL pin is the output of the error
amplifier for external loop compensation. Typically,
a type−2 network is applied between the VCTRL pin and
ground to set the regulation bandwidth below about 20 Hz.
VCTRL basically controls turn−on time, dead time in VSFF,
skip mode and STATICOVP:
of V /L where L is the inductor value as shown in Figure 5.
IN
At the end of the on time (t or t ), the inductor starts to
1
ON
demagnetize. The inductor current ramps down until it
reaches zero. The duration of this phase is t . At that
2
moment, a new switching cycle starts if the circuit operates
in CrM. When in DCM, there is a dead time t that lasts until
3
the next clock is generated.
t
2
t
t
3
1
I
L
(= t
)
ON
• Turn−on time is proportional to V
– V
as
CTRL
CTRL(MIN)
in eq. 5.
V
IN
/L
• Dead time (ZCD to DRV turn−on delay time) is
lengthened as V is lowered from V
time
.
CTRL(FF−EN)
CTRL
T
• V
is pulled down by 30 mA I
when
CTRL
VCTRL(BO)
Figure 5. Inductor Current in DCM
brown−out or DIS sleep mode entering process starts. If
is lower than 0.5 V V in the 30 mA
V
CTRL
CTRL(MIN)
One can show that in both CrM and DCM, the input
current is given by:
current enable condition, STATICOVP is triggered and
NCP1623 enters OFF mode.
ǒ
Ǔ
ǒ
Ǔ
t1 @ t1 ) t2
tON @ t1 ) t2
IIN + VIN
+ VIN
Follower Boost − A version only
2 @ L @ T
2 @ L @ T
(eq. 3)
At low−line, a Follower Boost reduces the output voltage
to optimize the PFC stage efficiency and significantly shrink
its size and cost. In particular, the boost inductance and the
MOSFET losses can be dramatically reduced. Since, the
output voltage must remain higher than the line voltage, the
output voltage is lowered in low line only while it remains
regulated to the default nominal level generally set to 400 V
in high−line conditions. Practically, the NCP1623A controls
this 2−level follower boost operation through the feedback
where T = t + t + t , switching period (t being 0 in CrM).
1
2
3
3
In the light of the eq. 3, we note that I is proportional to
IN
V
if t ·(t + t )/T is a constant. In the voltage mode without
IN
1 1 2
On−time Modulation, DRV turn−on time (t or t in eq. 3)
ON
1
is set by:
VCTRL * VCTRL(MIN)
tON + tON(MAX)
@
VCTRL(MAX) * VCTRL(MIN)
(eq. 4)
pin which sources the current I
low line detection condition. I
voltage as follows:
(25 mA typically) in
offsets the feedback
FB(LL)
FB(LL)
where t
is maximum turn−on time and t
at
ON(MAX)
ON(MAX)
low−line is 2.5 times longer than high−line condition by
2−level line feedforward.
RFB2
In order to keep t ·(t + t )/T constant, NCP1623 further
VFB
+
@ VOUT ) RFB1 ø RFB2 @ IFB(LL)
1
1
2
RFB1 ) RFB2
modulate t by the factor of T/(t + t ) information detected
ON
1
2
(eq. 7)
from previous switching:
where R
and R
are the upper and the lower resistors
VCTRL * VCTRL(MIN)
FB1
FB2
T
tON + tON(MAX)
@
@
of the feedback bridge as shown in Figure 1.
Finally, the output regulation voltage level is:
t1 ) t2
VCTRL(MAX) * VCTRL(MIN)
(eq. 5)
RFB1 ) RFB2
(t + t )/T in eq. 3 is removed by T/(t + t ) in the modulated
VOUT
+
@ VREF * RFB1 @ IFB(LL)
1
2
1
2
RFB2
t
eq. 5 so that the input current is finally given by:
ON
(eq. 8)
tON(MAX)
VCTRL * VCTRL(MIN)
Thus, the low−line regulation level depends on the
feedback upper resistance, R . As an example, if is
IIN + VIN
@
2 @ L
VCTRL(MAX) * VCTRL(MIN)
FB1
RFB1
(eq. 6)
6 MW and R
is 37.7 kW:
FB2
Therefore, NCP1623 controls both CrM and DCM with
no degradation in power factor and no discontinuity in the
power delivery.
6 M ) 37.7 k
VOUT(HL)
+
@ 2.5 + 400 V
37.7 k
VOUT(LL) + 400 V * 6 M @ 25 m + 250 V
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11
NCP1623
Low Line
A version
LL&A
I
PFCOK
R
S
Q
I
I
VCTRL(START)
OFF
FB(LL)
VCTRL(DRE)
DRE
PFCOK
VCTRL
LL&A
−
FB
G
m
V
REF
+
I
FB(UVP)
V
Clamp BONOK DIS
CTRL(MAX)
+
4.5 V
FASTOVP
−
V
FB(FOVP)
0
STATIC
OVP Detection
V
Clamp
CTRL(MIN)
V
V
FB(FOVP−LL)
1
STATICOVP
0.5 V
LL&A
+
Switching control for regulation
SOFTOVP
V
−
FB(SOVP)
0
1
On−time
Modulation
FB(SOVP−LL)
LL&A
Valley Sync.
Freq. Foldback
−
DRE
+
V
PFCOK
OVP2
FB(DRE)
−
SKIP
+
V
VCTRL(SKIP)
−
UVP
V
+
FB(UVP)
0
1
V
FB(UVP−LL)
LL&A
Figure 6. Feedback Regulation and Transient Control
FEEDBACK TRANSIENT CONTROL
higher than a fast OVP threshold, V
, switching is
FB(FOVP)
immediately disabled. At low−line condition with A version
enabling follower boost, soft and fast OVP thresholds,
Soft Start
At startup,
compensation capacitor properly for soft start. When FB
voltage reaches close to V , the sourcing current of the
OTA is reduced to 0 A where PFCOK signal is set to high
level and I
I
sources an external
VCTRL(START)
V
and V , are increased.
FB(FOVP−LL)
FB(SOVP−LL)
Based on these control methods at output voltage transient
condition, NCP1623 triggers DRE, soft OVP and fast OVP
at below levels:
REF
is turned off.
VCTRL(START)
• DRE:
Dynamic Response Enhancer (DRE)
− V
= 95.5%/97.5% x V
FB(DRE)
REF
The NCP1623 embeds a “Dynamic Response Enhancer”
(DRE) that deals with the under−shoots of the output voltage
at abrupt increases of the load current. An internal
comparator monitors the FB pin and when this voltage is
• Soft OVP:
− V
− V
= 105%/103% x V
FB(SOVP)
REF
= 110%/108% x V
FB(SOVP−LL)
REF
• Fast OVP:
lower than 95.5% V , a 200 mA I
is sourced
REF
VCTRL(DRE)
− V
− V
= 107%/105% x V
REF
FB(FOVP)
to speed up the charge of the compensation network as
shown in Figure 6. Effectively this appears as a 10x increase
in the loop gain. DRE is disabled during the start−up
sequence until the PFC stage has stabilized and PFCOK is
high. DRE is also disabled when the OVP2 (Second Over
Voltage Protection) is triggered.
= 114%/112% x V
FB(FOVP−LL)
REF
where V
and V
are set at low−line
FB(SOVP−LL)
FB(FOVP−LL)
with Follower Boost enabled in A version.
Under Voltage Protection (UVP)
If the FB pin is open, V is pulled down lower than an
FB
Soft / Fast Over Voltage Protection (SOVP, FOVP)
In case of output over−shoots, soft OVP is firstly triggered
by comparing FB voltage and a soft OVP threshold,
UVP threshold voltage (V
stops. The output voltage of the PFC stage is scaled down by
a resistor divider and monitored by the OTA inverting input
) and DRV switching
FB(UVP)
V
as in Figure 6. Once the soft OVP is triggered, the
(FB pin voltage). FB sink current, I
for UVP, is
FB(SOVP)
FB(UVP)
turn−on time is gradually decreased in 4 to 5 switching
periods to smoothly reduce powering. If FB voltage is even
minimized less than 450 nA to allow the use of a high
impedance feedback resistor network.
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12
NCP1623
CURRENT SENSE AND ZERO CROSS DETECTION
auxiliary winding as shown in Figure 1. The direct V
DS
The NCP1623 uses CS/ZCD pin to detect a switching FET
conduction current and drain voltage. The FET current is
sensing is a simple solution with no auxiliary winding and
the auxiliary winding based ZCD sensing is generally
preferred to improve CS/ZCD noise immunity with lower
standby power.
As illustrated in Figure 7, the CS/ZCD pin provides the
input signal for the following functions:
detected by a current sense resistor (R ) inserted
SENSE
between the FET source and ground. The drain voltage is
monitored by directly sensing V using a resistive bridge
DS
or by monitoring a reflected V , typically obtained from an
DS
SOURCE
DRAIN
R
SENSE
R
R
CS1
CS2
CSZCD
OCP blanking
400 ns t
OCP
OCP(LEB)
V
V
CS(OCP)
Buffer
H
OVS blanking
200 ns t
OVS(LEB)
OVS
ZCD
CS(OVS)
L
DRV
ZCD blanking
600 ns t
OVS(LEB)
Hysteresis
+ V
+ V
if ZCD is high
if ZCD is low
Filter
ZCD(TH−H)
ZCD(TH−L)
enable
50 ms timer
BONOK
reset
t
BD(BLANK)
Hysteretic reference
if BONOK is high
V
SNS
V
V
CS/ZCD(BO−EX)
Filter
if BONOK is low
CS/ZCD(BO−EN)
enable
reset
25 ms timer
LL
t
Hysteretic reference
LD(BLANK)
V
V
if LL is high
if LL is low
CS/ZCD(HL)
CS/ZCD(LL)
500 ms timer
count
done
t
LD(WDG)
OVP 2 blanking
reset
DRV
1 ms t
OVP2
OVP2(BLANK)
V
ZCD(OVP2−EN)
Figure 7. CS/ZCD Internal Circuit Block
Excessive Current Protection (OCP and OVS)
The NCP1623 turns off the FET when V
compared with the sum of the filtered V
and
CS/ZCD
reaches
V
hysteresis to generate ZCD signal.
CS/ZCD
ZCD(TH−H/L)
the over−current threshold (500 mV V
) after OCP
When no signal is received that triggers the ZCD
comparator during the off−time, an internal 200 ms
(t ) watchdog timer initiates the next drive pulse.
CS(OCP)
blanking time (400 ns t ) from DRV on. In addition,
OCP(LEB)
if V
V
further exceeds the overstress level (750 mV
) after OVS blanking time (200 ns t
CS/ZCD
ZCD(WDG)
) from
At the end of this delay, CS/ZCD pin sources 50 mA
I and compare V with 240 mV V
ZCD(GND)
CS(OVS)
OVS(LEB)
DRV on, FET is turned off for OVS watch dog time (800 ms
).
CS/ZCD
ZCD(GND)
t
to detect a possible grounding of this pin and prevent a
subsequent fault operation.
OVS(WDG)
Zero Current Detection (ZCD)
The NCP1623 turns on DRV at the valley of the
drain−source voltage to minimize switching loss and noise.
Line Sensing
A low pass filtered CS/ZCD voltage, V , is an image of
SNS
After ZCD blanking time (600 ns t
), V
is
the input voltage. The blanking time (25 ms, t ) for
LD(BLANK)
ZCD(BLANK)
CS/ZCD
www.onsemi.com
13
NCP1623
OFF MODE
low−line (LL) detection is set longer than a half−line cycle
but not that long to quickly detects an abrupt line transient
from high to low. When the line changes from low to high
The NCP1623 turns off DRV switching and enters the
OFF mode when one of the following faults is detected:
• UVLO when V < V
• TSD when T > 150°C.
• UVP when V < V
• STATICOVP triggered by BO or DIS sleep mode.
and V
is over V
, high line mode is
SNS
CS/ZCD(HL)
CC
CC(OFF).
immediately entered. When high−line is detected (that is,
when signal “LL” of Figure 7 is low), the loop gain, t
J
/
ON
.
FB
FB(UVP)
(V
– V
) ms/V, is divided by about 2.5 to
CTRL
CTRL(MIN)
ensure a 2−level feedforward.
The FB pin of the A version sources the current I
FB(LL)
In OFF mode, V
reset to low. Also, the major part of the circuit sleeps except
for UVLO, TSD, UVP, BO and DIS blocks.
In case of OFF mode triggered by DIS function, the circuit
consumption is further minimized to I
is grounded and PFCOK signal is
CTRL
when low−line is detected. This is used to reduce the
regulation level at low−line and hence provide the follower
boost capability. Also, when follower boost is enabled, the
line sensing result is forced to high−line if DRV switching
is disabled for a line detection watch dog time (500 ms
(100 mA max).
CC(DIS)
DISABLE FUNCTION
t
).
LD(WDG)
The NCP1623 operation is disabled when the DIS pin
voltage exceeds the DIS sleep mode enter voltage (V
Brown Out
The NCP1623 uses V
voltage detection same as the line sensing. By default, when
powered, the circuit is in a fault state (“BONOK” high) and
BONOK is set to low when V
As shown in Figure 7, when V
brown−out enter voltage (V
blanking time (50 ms t
and the drive is not immediately disabled. Instead, a 30 mA
current source (I ) gradually reduces V . As a
result, the circuit keeps generating DRV pulses until the
STATICOVP trips (that is when V
minimum clamp level, 0.5 V V
Figure 6). This method relieves the risk of input voltage
bouncing the fault line detection caused by EMI filter
oscillation from an abrupt DRV stop.
,
DIS(EN)
(filtered V
) for the input
SNS
CS/ZCD
2.1 V maximum) for DIS blanking time (t
).
DIS(BLANK)
Practically, this occurs if the DIS pin is let floating since an
internal 530 kW resistor pulls up the pin. In this case, the V
CC
exceeds V
.
SNS
CS/ZCD(BO−EX)
current consumption is reduced to I
(100 mA
CC(DIS)
is lower than the
SNS
maximum) and the PFC stage stops operating.
Similar to power reducing sequence in brown−out, the
drive is not immediately disabled and 30 mA current source
) for BO
CS/ZCD(BO−EN)
), BONOK signal is high
BO(BLANK)
gradually reduces V
until the STATICOVP function
CTRL
VCTRL(BO)
CTRL
trips in Figure 6. The DIS sleep mode is maintained until the
DIS pin is externally pulled down below the DIS sleep mode
reaches the
as shown in
CTRL
exit voltage (V
, 0.8 V minimum).
DIS(EX)
CTRL(MIN)
If the NCP1623 enters the OFF mode by other fault
detections (not by STATICOVP in DIS process), the DIS pin
is grounded through a 530 kW resistor.
OUTPUT DRIVE
Second Over Voltage Protection (OVP2)
The output stage in DRV pin contains a totem pole
optimized to minimize cross−conduction currents, making
the NCP1623 compatible with high−frequency operation.
Its high current capability (−500 mA / +800 mA) allows it
to effectively drive high gate charge power FET. In the large
During the FET turn−off time, the CS/ZCD pin signal is
proportional to the output voltage and can hence unveil
overshoots. This provides an additional protection to protect
the PFC stage in case of a failure of the resistive network at
FB pin. When an OVP2 fault is detected after OVP2
V range (up to 30 V), the DRV pin turn−on voltage is
blanking time (t ) from DRV off, the circuit
OVP2(BLANK)
CC
clamped up to 14 V.
stops generating DRV pulses for 75 ms t
typically.
OVP2(RST)
OVP2 is disabled for 60 ms at startup and for 10 ms at the
end of 75 ms t time to prevent an abnormal OVP2
detection at the transient condition, but the output voltage
could be over the OVP2 level if the bulk voltage is abruptly
charged during these OVP2 disabling times.
FAILURE DETECTION
OVP2(RST)
When manufacturing a power supply, components can be
accidently shorted or improperly soldered. Such failures can
also happen to occur later on because of the components
fatigue or excessive stress. The false open/short circuits are
generally required not to cause fire, smoke nor big noise.
The NCP1623 integrates functions which help meet this
requirement.
THERMAL SHUT−DOWN
An internal thermal sensing circuitry disables the circuit
gate drive and keeps the power switch off when the junction
temperature exceeds 150°C. The NCP1623 remains off until
the junction temperature drops below about 100°C (50°C
hysteresis). The temperature shutdown remains active as
FB Pin Open Protection
A 250 nA sink current (I
voltage if it is floating so that the UVP protection trips. This
current source is small (450 nA maximum) so that its impact
) pulls down the FB pin
FB(UVP)
long as V is higher than V
. The reset action forces
CC(RST)
CC
the TSD threshold to 150°C so that any cold start−up will be
done with the proper TSD level.
www.onsemi.com
14
NCP1623
on the bulk voltage regulation level remains negligible with
typical feedback resistor dividers.
NCP1623 checks the CS/ZCD pin short condition where the
operation stops if V is lower than 275 mV
CS/ZCD
(V
maximum) when shortly sourcing 40 mA
minimum). Therefore, CS/ZCD pin external
ZCD(GND)
GND Pin Open Protection
(I
ZCD(GND)
If the GND pin is not connected, GND pin voltage is
floating and could be higher than PFC stage power ground
level. If NCP1623 detects a reversed voltage between GND
and CS/ZCD pin for 800 ms, IC is reset with no switching
operation.
impedance should be higher than 7 kW.
Bypass Diode Short Protection
A bypass diode is generally placed between the input and
output high−voltage rails to divert this inrush current. When
the bypass diode is short−circuited, the inductor current
enters deep CCM as the discharging inductor current slope
is very gentle. In such case, the overstress protection (OVS)
CZ/ZCD Pin Short Protection
If ZCD signal is not detected at all at CS/ZCD pin short
condition, ZCD watchdog timer doesn’t allow DRV turn−on
can trip and stop the drive switching for 800 ms t
.
OVS(WDG)
for 200 ms t . After the watchdog time, the
ZCD(WDG)
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15
NCP1623
Table 4. ORDERING INFORMATION
Device
†
Marking
UPD
Package
Shipping
NCP1623ASNT1G
NCP1623ADR2G
TSOP−6 (Pb−Free)
SOIC−8 (Pb−Free)
3000 / Tape & Reel
2500 / Tape & Reel
1623A
1623C
NCP1623CDR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Table 5. CIRCUITS SPECIFIC OPTIONS
NCP1623 Versions
A
C
SOIC8
No
Options
Package
TSOP6 / SOIC8
Follower Boost
Yes
12.5 ms / 5.0 ms
25 ms
Maximum On−time at LL/HL
DIS Mode Detection Blanking Time (SOIC8 Only)
OVP2 Protection
16.6 ms / 6.6 ms
25 ms
No
Yes
Brown−Out Protection
No
No
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16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
1
DATE 12 JUN 2012
SCALE 2:1
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
H
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
6
1
5
4
L2
GAUGE
PLANE
E1
E
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
2
3
L
MILLIMETERS
SEATING
M
C
NOTE 5
DIM
A
A1
b
c
D
E
E1
e
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
NOM
1.00
MAX
1.10
0.10
0.50
0.26
3.10
3.00
1.70
1.05
0.60
PLANE
b
DETAIL Z
e
0.06
0.38
0.18
3.00
c
2.75
A
0.05
1.50
0.95
L
0.40
A1
L2
M
0.25 BSC
−
DETAIL Z
0°
10°
STYLE 1:
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
STYLE 3:
PIN 1. ENABLE
2. N/C
STYLE 4:
PIN 1. N/C
2. V in
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
STYLE 6:
PIN 1. DRAIN
2. DRAIN
3. GATE
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
3. R BOOST
4. Vz
5. V in
6. V out
3. NOT USED
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
4. SOURCE
5. DRAIN
6. DRAIN
4. GROUND
5. ENABLE
6. LOAD
4. EMITTER
5. COLLECTOR
6. COLLECTOR
6. COLLECTOR 2
6. COLLECTOR 2
STYLE 7:
STYLE 8:
PIN 1. Vbus
2. D(in)
STYLE 9:
STYLE 10:
PIN 1. D(OUT)+
2. GND
STYLE 11:
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
PIN 1. LOW VOLTAGE GATE
2. DRAIN
PIN 1. SOURCE 1
2. DRAIN 2
3. D(in)+
4. D(out)+
5. D(out)
6. GND
3. SOURCE
3. D(OUT)−
4. D(IN)−
5. VBUS
6. D(IN)+
3. DRAIN 2
4. N/C
5. COLLECTOR
6. EMITTER
4. DRAIN
4. SOURCE 2
5. GATE 1
4. I/O
5. DRAIN
5. VCC
6. I/O
6. HIGH VOLTAGE GATE
6. DRAIN 1/GATE 2
STYLE 13:
STYLE 14:
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
STYLE 16:
STYLE 17:
PIN 1. EMITTER
2. BASE
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
PIN 1. ANODE
2. SOURCE
PIN 1. ANODE/CATHODE
2. BASE
3. GATE
3. EMITTER
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
4. DRAIN
4. COLLECTOR
5. ANODE
5. N/C
6. CATHODE
6. CATHODE
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
XXXAYWG
XXX MG
G
G
1
1
6X
0.95
3.20
IC
STANDARD
XXX = Specific Device Code
XXX = Specific Device Code
A
Y
W
G
=Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
0.95
= Pb−Free Package
PITCH
DIMENSIONS: MILLIMETERS
*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G”
or microdot “G”, may or may not be present. Some
products may not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14888C
TSOP−6
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
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provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
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