NCP1681ABD2R2G [ONSEMI]
Totem Pole Continuous Conduction Mode (CCM) / Multi-mode (CrM-CCM) Power Factor Correction Controller;
| 型号： | NCP1681ABD2R2G |
| 厂家： | 
ONSEMI |
| 描述： | Totem Pole Continuous Conduction Mode (CCM) / Multi-mode (CrM-CCM) Power Factor Correction Controller |
| 文件： | 总42页 (文件大小：2218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Totem Pole Power Factor
Correction Controller
NCP1681
The NCP1681 is an innovative Multi−Mode (MM) and Continuous
Conduction Mode (CCM) Power Factor Correction (PFC) controller
IC designed to drive the bridgeless totem pole PFC topology. The
bridgeless totem pole PFC consists of two totem pole legs: a fast−
switching leg driven at the PWM switching frequency and a second
leg that operates at the AC line frequency. This topology eliminates
the diode bridge present at the input of a conventional PFC circuit,
allowing significant improvement in efficiency and power density.
The NCP1681 is available as a Fixed Frequency (NCP1681Ax) or
Multi−Mode (NCP1681Bx) device.
SOIC−20
NARROW BODY
CASE 751EZ
MARKING DIAGRAM
20
NCP1681xxG
AWLYWW
General Features
1
• Totem Pole PFC Topology Eliminates Input Diode Bridge Enabling
Very High Efficiency & Compact Design
• AC Line Monitoring Circuit & AC Phase Detection
• Brownout Detection
xx
A
WL
Y
WW
G
= AA, AB or BA
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Digital Loop Compensation
• Novel Current Sensing Scheme Providing Inductor Current Upslope
and Downslope Sensing
• PFCOK Indicator
PIN CONNECTIONS
• Skip/Standby Mode for Optimizing Light Load Performance
• Near−Unity Power Factor in All Operating Modes
1
20
FAULT
PFCOK
FB
LVSNS2
LVSNS1
Multi−Mode Operation
VM
AGND
CS
AUX
VCC
PWMH
PWML
PGND
POLARITY
• Continuous Conduction Mode (CCM) in Heavy−Load Conditions
• Critical Conduction Mode (CrM) in Light & Medium Load
Conditions
• Optional Fixed Frequency CCM Across Load Range
• Simplified Valley Sensing
ZCD
INVPOL
SRH
SRL
(Top View)
Safety Features
• Soft and Fast Overvoltage Protection
• 2−level Latch Input for OVP & OTP
• Bulk Undervoltage Protection
• Internal Thermal Shutdown
• Cycle−by−cycle Current Limit
ORDERING INFORMATION
See detailed ordering and shipping information on page 4
of this data sheet.
Applications
• Cloud/Server Power Supplies
• High Performance Computing
• 5G/Telecom Power Supplies
• Industrial Power Supplies
• Ultra−High Density (UHD) Power Supplies
• Merchant Power
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
May, 2023 − Rev. 1
NCP1681/D
NCP1681
Figure 1. Typical CCM Application Schematic
Figure 2. Typical Multi−Mode Application Schematic
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2
NCP1681
Figure 3. Block Diagram
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3
NCP1681
Table 1. PIN DESCRIPTIONS
Pin Number
Pin Name
FAULT
Pin Description
1
2
Combined OVP/OTP fault pin.
PFCOK
The PFCOK pin is held low when the PFC output voltage is out of regulation and during fault condi-
tions. The pin becomes active when the PFC output achieves regulation in nominal operation, sourc-
ing a current proportional to the feedback voltage, V
.
FB
The PFCOK pin is bidirectional; it can be used to enable a downstream converter and can be used
by the downstream converter to force the NCP1681 into Skip/Standby Mode operation.
3
4
5
6
FB
This pin senses the PFC output voltage for loop regulation.
Multiplier output. This pin provides the voltage for duty cycle modulation.
Signal ground reference.
V
M
AGND
CS
This pin senses the inductor current upslope through current sense transformers. Upslope signal is
used for cycle−by−cycle current limiting and is summed with the ZCD signal to reconstruct an image
of the inductor current in the IC. The reconstructed inductor current signal is used for generation of
the multiplier voltage for duty cycle modulation in CCM.
7
ZCD
The pin senses the inductor current downslope. It is used to detect demagnetization and control the
synchronous (1−D) switch. The pin voltage is summed with the CS pin voltage to reconstruct an im-
age of the inductor current. The reconstructed inductor current signal is used for generation of the
multiplier voltage for duty cycle modulation in CCM.
8
INVPOL
SRH
Inverted output of the internal AC polarity detection circuit.
Control signal for high side slow leg device.
Control signal for low side slow leg device.
Output of the internal AC polarity detection circuit.
Power ground reference.
9
10
11
12
13
14
15
16
SRL
POLARITY
PGND
PWML
PWMH
VCC
PWM logic level output for control of low side fast leg switch.
PWM logic level output for control of high side fast leg switch.
IC supply pin.
AUX
The pin is used to monitor the switch node resonance on the auxiliary winding and enable valley
turn−on during CrM/DCM operation. For CCM operation (NCP1681Ax devices), the AUX pin must be
tied to GND.
17
18
Removed for creepage distance.
LVSNS1
LVSNS2
Low voltage input for AC line voltage monitoring. LVSNS1 resistor divider should be connected to AC
line side of the boost inductor.
19
20
Removed for creepage distance.
Low voltage input for AC line voltage monitoring. LVSNS2 resistor divider should be connected to the
slow leg bridge node.
Table 2. ORDERING INFORMATION TABLE
V
(V)
ILIM
†
LL / HL
OPN
Operating Mode
CCM
F
CCM
(kHz)
V
(mV)
Package
Shipping
ZCD(ARM)
NCP1681AAD2R2G
NCP1681ABD2R2G
NCP1681BAD2R2G
65
1 / 1
150
SOIC−20
(Pb−Free)
2500 / Tape &
Reel
CCM
95
65
1 / 1
150
300
Multi−Mode
1.4 / 0.84
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP1681
Table 3. MAXIMUM RATINGS (All voltages measured with respect to AGND)
Rating
Supply Input Voltage, V pin
Pin
Symbol
Value
−0.3 to 30
Unit
V
VCC
V
CC
CC(MAX)
CC(MAX)
Maximum Current for V pin
VCC
I
Internally limited
−0.3 to + 0.3
−0.3 to 5.5
mA
V
CC
PGND Maximum Voltage
PGND
PWML
PWML
V
PGND(MAX)
PWML(MAX)
PWML pin Maximum Voltage
PWML pin Maximum Current
V
V
I
−100
mA
PWML(SRC_MAX)
I
+160
PWML(SNK_MAX)
PWMH pin Maximum Voltage
PWMH pin Maximum Current
PWMH
PWMH
V
−0.3 to 5.5
V
PWMH(MAX)
I
−100
mA
PWMH(SRC_MAX)
I
+160
PWMH(SNK_MAX)
SRx, Polarity, INVPOL pin Maximum Voltage
SRx, Polarity, INVPOL pin Maximum Current
SRL, SRH,
V
−0.3 to 14
V
SRx(MAX)
Polarity, INVPOL
SRL, SRH,
Polarity, INVPOL
I
I
−100
+160
mA
SRx(SRC_MAX)
SRx(SNK_MAX)
AUX pin Input Voltage
AUX
AUX
ZCD
ZCD
V
−0.3 to 5.5 (Note 1)
−2 / +5
V
mA
V
AUX
AUX pin Input Current
I
AUX
ZCD pin Input Voltage Range
ZCD pin Maximum Current
Maximum Input Voltage Other Pins
V
−0.3 to 5.5 (Note 1)
−2 / +5
ZCD
ZCD(MAX)
I
mA
V
LVSNS1,
V
MAX
−0.3 to 5.5 (Note 1)
LVSNS2, CS,
VM, FB, FAULT
Maximum Current Other Pins
LVSNS1,
LVSNS2, CS,
VM, FB, FAULT
I
−2 to +5
mA
MAX
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation at T = 70°C
Thermal Resistance Junction−to−Air
(1 Oz Cu, 0.155 Sq Inch Printed Circuit Copper Clad)
P
660
121
mW
°C/W
A
D
R
q
JA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
T
150
−40 to +125
−60 to +150
3.5
°C
°C
°C
kV
kV
J(MAX)
ESD Capability, HBM model (Note 2)
ESD Capability, CDM model (Note 2)
1.25
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V ZENER diode. More positive and negative voltages
can be applied if the pin current stays within the −2 mA / +5 mA range.
2. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,
Charged Device Model 1250 V per JEDEC Standard JESD22−C101E.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1681
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V
= 1.2 V, V
SRH
= 0 V, V = 2.4 V, V
= open, C
CC
LVSNS1
LVSNS2
FB
FAULT POLARITY
= 100 pF, V
= 0 V, V
= 0 V, V = 0 V, C
= 100 nF, C
= C
= 100 pF, C
= C
= 100 pF, for typical values T =
AUX
ZCD
CS
VCC
SRL
PWML
PWMH J
25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
START−UP & SUPPLY CIRCUITS
Supply Voltage
V
Startup Threshold
V
increasing
decreasing
decreasing
decreasing
V
V
9.75
8.2
1.2
2.5
10.5
8.8
1.7
4
11.25
9.4
−
CC
CC
CC
CC
CC(on)
CC(off)
Minimum Operating Voltage
V
V
V
V
Hysteresis (V
– V
)
V
CC
CC(on)
CC(off)
CC(HYS)
CC(reset)
Internal Latch / Logic Reset Level
V
6
Supply Current
Before Startup
Fault or Latch
Operational, Switching at 100 kHz
Operational, Skipping
mA
V
= 9.5 V
FLT
I
I
I
I
−
−
−
−
1.8
1.8
2.2
2.2
4
CC
CC1
CC2
CC3
CC4
V
= 0 V
All DRVs Open
= 0 V
3.3
V
0.54
0.9
PFCOK
AC ZERO CROSSING MANAGEMENT
Recommended External Divider
Ratio
K
−
100
100
−
L_DIV
Main PWM Drive Control
PWM Zero Crossing Blanking
Thresholds
Threshold to stop PWML/H pulses
mV
V
= |V
− V
|
ZCB_STOP
LVSNS1
LVSNS2
V
Decreasing, V
= 0 V;
= 4 V;
V
V
−
−
LVSNS1
LVSNS2
Increasing, V
LVSNS2
ZCB_STOP1(LL)
ZCB_STOP2(LL)
V
LVSNS1
Threshold to start PWML/H pulses
V
= |V
− V
LVSNS2
LVSNS2
|
ZCB_START
LVSNS1
LVSNS2
V
Increasing, V
= 0 V;
= 4 V
V
V
V
+
LVSNS1
LVSNS1
ZCB_START1(LL)
ZCB_START2(LL)
ZCB_STOPx(LL)
V
Decreasing, V
20
Zero Crossing Blanking Filter
Polarity Detection Control
Polarity Detection Filter
t
−
−
20
25
ms
FILT(ZCB)
t
200
−
ms
POL_FILTER
Polarity Detection Threshold
V
= V
− V
LVSNS2
mV
POL_DETx
LVSNS1
V
V
Decreasing, V
= 0 V;
= 4 V;
V
V
−55
−20
−15
20
55
LVSNS1
LVSNS2
LVSNS2
POL_DET1
POL_DET2
V
Increasing, V
15
LVSNS1
Slow Leg (SR) Drive Control
Slow Leg Zero Crossing Blanking
Thresholds
Threshold to stop SRx pulses
mV
mV
V
V
= |V
− V
LVSNS2
LVSNS2
|
SR_STOP
LVSNS1
LVSNS2
Decreasing, V
= 0 V;
= 4 V;
V
−
180
−
LVSNS1
SR_STOP1(LL)
V
SR_STOP2(LL)
V
Increasing, V
LVSNS1
Threshold to start SRx pulses
V
= |V
− V
LVSNS2
LVSNS2
|
SR_START
LVSNS1
LVSNS2
= 0 V;
= 4 V
V
Increasing, V
V
V
V
+
LVSNS1
LVSNS1
SR_START1(LL)
SR_START2(LL)
SR_STOPx(LL)
V
Decreasing, V
20
Synchronous (1 – d) Drive Control
Sync Zero Crossing Blanking
Thresholds
Threshold to stop Sync pulses
V
V
= |V
− V
|
SYNC_STOP
LVSNS1
LVSNS2
= 0 V;
= 4 V;
Decreasing, V
V
V
−
200
−
LVSNS1
LVSNS2
Increasing, V
LVSNS2
SYNC_STOP1(LL)
SYNC_STOP2(LL)
V
LVSNS1
Threshold to start Sync pulses
V
= |V
− V
LVSNS2
LVSNS2
|
SYNC_START
LVSNS1
LVSNS2
= 0 V;
= 4 V
V
Increasing, V
V
V
V
SYNC_STOPx(LL)
LVSNS1
LVSNS1
SYNC_START1(LL)
SYNC_START2(LL)
V
Decreasing, V
+ 20
BROWN−OUT, LINE SAG AND LINE RANGE DETECTION
Line Sag and Brown−Out Detection
Upper Threshold
|V
− V
| Increasing
V
BO(START)
1.02
1.10
1.18
LVSNS1
LVSNS2
Line Sag and Brown−Out Detection
|V
|V
− V
| Decreasing
V
0.92
60
1.00
100
1.08
V
LVSNS1
LVSNS2
BO(STOP)
Lower Threshold
Brown−Out Detection Hysteresis
− V
| Increasing
V
BO(HYS)
−
mV
LVSNS1
LVSNS2
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NCP1681
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V
= 1.2 V, V
SRH
= 0 V, V = 2.4 V, V
= open, C
CC
LVSNS1
LVSNS2
FB
FAULT POLARITY
= 100 pF, V
= 0 V, V
= 0 V, V = 0 V, C
= 100 nF, C
= C
= 100 pF, C
= C
= 100 pF, for typical values T =
AUX
ZCD
CS
VCC
SRL
PWML
PWMH J
25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
BROWN−OUT, LINE SAG AND LINE RANGE DETECTION
Line Sag Detection Blanking Timer
|V
|V
− V
| < V
t
20
25
30
ms
ms
V
LVSNS1
LVSNS2
BO(STOP);
SAG(blank)
Delay to Soft Stop Enable
Brown−Out Detection Blanking
Timer
− V | < V
;
t
520
2.20
650
2.36
780
2.52
LVSNS1
LVSNS2
BO(STOP)
BO(blank)
Delay to Polarity Disable
High−Line Level Detection
Threshold
|V
− V
| Increasing
V
HL
LVSNS1
LVSNS2
Low−Line Level Detection Threshold
|V
|V
− V
| Decreasing
V
2.07
100
20
2.22
140
25
2.37
−
V
LVSNS1
LVSNS2
LL
Line Range Select Hysteresis
− V
| Increasing
V
mV
ms
LVSNS1
LVSNS2
LR(HYS)
blank(LL)
High to Low Line Mode Selector
Timer
|V
− V
| < V
t
30
LVSNS1
LVSNS2
LL
Low to High Line Mode Selector
Timer Filter
|V
|V
− V
| > V
t
200
400
300
500
400
600
ms
LVSNS1
LVSNS2
HL
filter(HV)
Lockout Timer for Low to High Line
Mode Transition
Low Line Mode;
− V | > V
t
ms
line(lockout)
LVSNS1
LVSNS2
HL
AC LINE FREQUENCY MONITORING
Line Frequency Upper Threshold
Line Frequency Lower Threshold
Device Enable Counter
t
t
66
37
−
72
41
4
78
45
−
Hz
Hz
LINE(65)
LINE(45)
N
DRV_EN
Slow Leg Disable Counter
N
−
1
−
SR_DIS
LINEFREQ(DLY)
Line Frequency2 Timer
Delay to PWM Disable
t
60
100
165
ms
VALLEY DETECTION CIRCUIT (NCP1681Bx Only)
Valley Detection Thresholds in
Positive Half Line Cycle
V
= 1.2 V, V
AUX
= 0 V;
mV
LVSNS1
LVSNS2
V
rising (Arm)
V
150
50
200
100
250
150
VD1_TH(rising)
VD1_TH(falling)
V
falling (Trigger)
V
AUX
Valley Detection Hysteresis in
Positive Half Line Cycle
V
50
100
−
mV
ns
VD1(HYS)
Propagation Delay of Valley Detec-
tion in Positive Half Line Cycle
Step V
1.5 V to −0.2 V;
T
VD1
−
50
80
AUX
Time to PWML = 2.5 V
Valley Detection Thresholds in
Negative Half Line Cycle
V
= 0 V, V = 1.2 V;
mV
LVSNS1
LVSNS2
V
falling (Arm)
V
50
150
100
200
150
250
AUX
VD2_TH(falling)
VD2_TH(rising)
V
rising (Trigger)
V
AUX
Valley Detection Hysteresis in
Negative Half Line Cycle
V
50
100
−
mV
ns
VD2(HYS)
Propagation Delay of Valley Detec-
tion in Negative Half Line Cycle
Step V
0 V to 1.5 V;
T
VD2
−
45
75
AUX
Time to PWMH = 2.5 V
Minimum AUX pulse width
T
−
95
1
155
2
ns
SYNC
AUX pin bias current, V
VD1_TH(rising)
=
=
I
I
0.5
mA
AUX
AUX(bias1)
V
AUX pin bias current, V
VD1_TH(falling)
0.5
1
2
mA
AUX
AUX(bias2)
V
FAST LEG DRIVE SIGNALS (PWML & PWMH)
PWMx Rise Time,
x = L, H
V
= 10% to 90% of 5 V
PWMx
T
−
−
−
95
30
15
−
−
ns
ns
W
PWMx
PWMx(rise)
C
= 1 nF
PWMx Fall Time
V
PWMx
= 90% to 10% of 5 V
= 1 nF
T
PWMx(fall)
C
PWMx
Source Resistance
ROH
25
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NCP1681
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V
= 1.2 V, V
SRH
= 0 V, V = 2.4 V, V
= open, C
CC
LVSNS1
LVSNS2
FB
FAULT POLARITY
= 100 pF, V
= 0 V, V
= 0 V, V = 0 V, C
= 100 nF, C
= C
= 100 pF, C
= C
= 100 pF, for typical values T =
AUX
ZCD
CS
VCC
SRL
PWML
PWMH J
25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
FAST LEG DRIVE SIGNALS (PWML & PWMH)
Sink Resistance
ROL
−
−
5
10
W
Peak Source Current
(guaranteed by design)
V
V
= 0 V
= 5 V
I
100
−
mA
PWMx
PWMx(SRC)
Peak Sink Current
(guaranteed by design)
I
−
160
−
mA
PWMx
PWMx(SNK)
PWMx Clamp Voltage
R
= 10 kW
V
4.5
90
5
5.5
V
PWMx
PWMx(high)
Non−overlap time between falling
edge of PWM(d) & rising edge of
PWM(1−d)
V
= 0.5 V
T
DT1
130
170
ns
ZCD
Non−overlap time between falling
edge of PWM(1−d) rising edge of
PWM(d)
V
ZCD
= 0.5 V
T
DT2
110
150
190
ns
SLOW LEG DRIVE SIGNALS (SRL & SRH)
SRx Rise Time
x = LO, HI
V
= 10% to 90% of 12 V
PWMSRx
T
−
−
185
125
−
−
ns
ns
PWMSRx
PWMSRx(rise)
C
= 1 nF
SRx Fall Time
V
= 90% to 10% of 12 V
T
PWMSRx(fall)
PWMSRx
C
= 1 nF
PWMSRx
Source Resistance
Sink Resistance
ROH2
ROL2
−
−
−
45
30
85
60
−
W
W
SRx Peak Source Current
(guaranteed by design)
V
= 0 V
= 12 V
= 10 kW
I
100
mA
PWMSRx
PWMSRx(SRC)
SRx Peak Sink Current
(guaranteed by design)
V
I
−
160
12
9
−
14
−
mA
V
PWMSRx
PWMSRx(SNK)
SRx Clamp Voltage
R
R
V
10
7.8
PWMSRx
PWMSRx(high)
PWMSRx(MIN)
V
CC
= 30 V
SRx Minimum Drive Voltage
= 10 kW
+ 100 mV
V
V
PWMSRx
= V
CC(off)
V
CC
POLARITY & INVPOL OUTPUT
POLARITY Rise Time
V
V
= 10% to 90% of 12 V
POLARITY
T
−
−
185
125
−
−
ns
ns
POLARITY
POLARITY(rise)
C
= 1 nF
POLARITY Fall Time
= 10% to 90% of 12 V
T
POLARITY(fall)
POLARITY
C
= 1 nF
POLARITY
Source Resistance
Sink Resistance
ROH3
ROL3
−
−
−
45
30
85
60
−
W
W
POLARITY Peak Source Current
(guaranteed by design)
V
= 0 V
I
100
mA
POLARITY
POLARITY(SRC)
POLARITY Peak Sink Current
(guaranteed by design)
V
= 12 V
I
−
10
7.8
−
160
12
−
14
−
mA
V
POLARITY
POLARITY(SNK)
POLARITY Clamp Voltage
POLARITY Minimum Drive Voltage
INVPOL Rise Time
R
= 10 kW
= 30 V
V
POLARITY
POLARITY(high)
V
CC
R
= 10 kW
+ 100 mV
V
9
V
POLARITY
POLARITY(MIN)
V
= V
CC
CC(off)
V
= 10% to 90% of 12 V
T
185
125
45
−
ns
ns
W
INVPOL
INVPOL(rise)
C
= 1 nF
INVPOL
INVPOL Fall Time
V
= 90% to 10% of 12 V
= 1 nF
T
−
−
INVPOL
INVPOL(fall)
C
INVPOL
Source Resistance
ROH4
−
85
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NCP1681
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V
= 1.2 V, V
SRH
= 0 V, V = 2.4 V, V
= open, C
CC
LVSNS1
LVSNS2
FB
FAULT POLARITY
= 100 pF, V
= 0 V, V
= 0 V, V = 0 V, C
= 100 nF, C
= C
= 100 pF, C
= C
= 100 pF, for typical values T =
AUX
ZCD
CS
VCC
SRL
PWML
PWMH J
25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
J
Characteristics
POLARITY & INVPOL OUTPUT
Sink Resistance
Conditions
Symbol
Min
Typ
Max
Unit
ROL4
−
−
30
60
W
INVPOL Peak Source Current
(guaranteed by design)
V
= 0 V
= 12 V
= 10 kW
I
100
−
mA
INVPOL
PINVPOL (SRC)
INVPOL Peak Sink Current
(guaranteed by design)
V
I
−
160
12
9
−
14
−
mA
V
INVPOL
INVPOL (SNK)
INVPOL Clamp Voltage
R
R
V
V
10
7.8
INVPOL
V
INVPOL (high)
= 30 V
CC
INVPOL Minimum Drive Voltage
PWM CONTROL CIRCUIT
= 10 kW
CC(off)
V
INVPOL
INVPOL (MIN)
V
CC
= V
+ 100 mV
CCM Switching Frequency
NCP1681AA, BA
NCP1681AB
F
CCM
kHz
60.4
88.3
65
95
69.6
101.7
Switching Frequency Jitter Range
R
−
−
8.9
2.4
−
−
%
JIT
Switching Frequency Jitter
Modulation Rate
F
JIT
kHz
Maximum duty cycle in CCM
Operation
NCP1681AA, BA
NCP1681AB
V
M
= 0 V
D
%
MAX
92.7
92.2
95.1
94.7
97.5
97.2
PWM Ramp Peak Voltage
V
3.5
3.75
17.1
4
V
RAMP,PK
Maximum On Time in CrM
NCP1681BA
V
< V
T
on, max,CrM
13.8
20.3
ms
FB
REF;
LSNS2
V
LVSN1
= 1.20V, V
= 0V
Maximum Frequency Clamp
NCP1681BA Only
F
−
130
−
kHz
clamp1
On−Time Below Which Frequency
Foldback is Engaged, NCP1681BA
Only
Low line
High Line
(t
)
−
−
3.84
1.92
−
−
ms
ON,FF LL
(t
ON,FF)HL
Minimum Frequency Clamp
F
25
200
−
30.5
260
36
320
−
kHz
ns
MIN
Minimum On−Time
V
FB
> V
; C
= Open;
T
REF
PWMx
on, min
on, max,DCM
Maximum On Time in DCM
NCP1681BA Only
T
30.2
ms
REGULATION BLOCK
Feedback Voltage Reference:
@ 25°C
Over the temperature range
V
REF
V
2.475
2.44
2.50
2.50
2.525
2.56
Ratio for DRE Enable (V
Detect Lower Threshold / V
(guaranteed by design)
Low
REF
V
decreasing
increasing
increasing
V
L / V
REF
95.0
97.5
2
95.5
98.0
2.5
96.0
98.5
−
%
%
%
OUT
FB
DRE
)
Ratio for DRE Disable (V
Detect Higher Threshold / V
(guaranteed by design)
Low
V
V
DRE
H / V
OUT
FB
FB
REF
)
REF
Ratio (V
REF
Low Detect Hysteresis /
V
H
/ V
DRE
OUT
REF
V
) (guaranteed by design)
ZCD PIN
ZCD Arming Threshold
NCP1681AA, AB
NCP1681BA
V
ZCD
increasing
V
mV
ZCD(ARM)
−
−
150
300
−
−
www.onsemi.com
9
NCP1681
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V
= 1.2 V, V
SRH
= 0 V, V = 2.4 V, V
= open, C
CC
LVSNS1
LVSNS2
FB
FAULT POLARITY
= 100 pF, V
= 0 V, V
= 0 V, V = 0 V, C
= 100 nF, C
= C
= 100 pF, C
= C
= 100 pF, for typical values T =
AUX
ZCD
CS
VCC
SRL
PWML
PWMH J
25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
ZCD PIN
ZCD Trigger Threshold
NCP1681AA, AB
NCP1681BA
V
ZCD
decreasing
V
mV
ZCD(TRG)
−
−
30
50
−
−
Threshold for Inrush Current
Protection
NCP1681AA, AB
NCP1681BA
V
mV
ZCD(INRUSH)
−
−
30
50
−
−
Propagation delay to (1−D) Drive
Step V
Step V
0 V to V
+ 250 mV;
T
ZCD(ARM)
−
45
75
ns
ns
mA
ZCD
ZCD(ARM)
Pulse
Time to PWMx = 2.5 V
Propagation delay (1−D) Drive Ter-
mination
1 V to V − 250 mV;
T
ZCD(TRG)
−
45
75
ZCD
ZCD(TRIG)
Time to PWMx = 2.5 V
ZCD Pullup Current Source
V
ZCD
= 0 V
I
0.7
0.7
1
1
1.3
1.3
ZCD
ZCD
V
= 2.7 V
CrM/CCM DETECTION FOR NCP1681Bx
Switching Frequency Ratio for CCM
Detection
F
CrM
Decreasing; F
/ F
CrM
R
CCM
−
111
360
262
350
25
−
%
ms
ms
mV
%
CCM
Blanking Time for CCM Mode End
Detection
T
288
210
325
−
432
314
375
−
CCMend
CrM(Min)
Minimum Operating Time in CrM
Mode after CCM ³ CrM Transition
T
Threshold Minimum V for CCM
V
CS_CCM−H
CS
Detection
Ratio Minimum V for CCM Detec-
K
CCM−H
CS
tion to Current Limit Threshold
Threshold Minimum V for CCM
V
185
−
210
15
235
−
mV
%
CS
CS_CCM−L
Confirmation
Ratio Minimum V for CCM Confir-
K
CS
CCM−L
mation to Current Limit Threshold
MULTIPLIER CIRCUIT
Multiplier Voltage in CrM/DCM
NCP1681BA Only
V
2
2.5
3
V
M(CrM)
V
M
Current capability in CrM/DCM
I
450
700
−
mA
VM
NCP1681BA Only
V
V
Pin Source Current
Pin Source Current
V
= 2 V, V = 1 V
I
I
30.4
−
35.7
17.5
0.49
41
−
mA
mA
M
M
FB
CS
M1,LL
V
FB
= 2 V, V = 0.5 V
CS
M2,LL
Low Line Current Ratio
(I
/ I
)
K
0.44
0.54
M2,LL M1,LL
M1,LL
M1,HL
V
M
Pin Source Current High Line
NCP1681AA, AB
NCP1681BA
V
FB
= 2 V, V = 1 V
I
mA
mA
CS
−
−
35.7
150.1
−
−
Ratio of High Line Current to Low
Line Current
(I
/ I
)
K
M1,HL M1,LL
M1,HL
NCP1681AA, AB
NCP1681BA
0.97
3.85
1
4.2
1.03
4.55
V
M
Pin Source Current High Line
NCP1681AA, AB
NCP1681BA
V
FB
= 2 V, V = 0.5 V
I
CS
M2,HL
−
−
17.5
73.9
−
−
High Line Current Ratio
NCP1681AA, AB
NCP1681BA
(I
/ I
)
K
M2,HL
M2,HL M1,LL
0.44
1.8
0.49
2.1
0.54
2.4
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10
NCP1681
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V
= 1.2 V, V
SRH
= 0 V, V = 2.4 V, V
= open, C
CC
LVSNS1
LVSNS2
FB
FAULT POLARITY
= 100 pF, V
= 0 V, V
= 0 V, V = 0 V, C
= 100 nF, C
= C
= 100 pF, C
= C
= 100 pF, for typical values T =
AUX
ZCD
CS
VCC
SRL
PWML
PWMH J
25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
J
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
MULTIPLIER CIRCUIT
V
Pin Source Current, 50% Duty
V
FB
= 2 V, V = V
M
= 1 V,
I
M3,LL
−
35.7
1
−
mA
M
CS
ZCD
V
= 1.875 V; Low Line
Low Line Current Ratio, 50% Duty
(I
/ I
)
K
M3,LL
0.99
1.01
M3,LL M1,LL
CURRENT SENSE BLOCK (CS PIN)
Low−Line Current Limit Threshold
NCP1681AA, AB
V
V
V
ILIMIT1(LL)
ILIMIT1(HL)
0.95
1.33
1
1.05
1.47
NCP1681BA
1.4
High−Line Current Limit Threshold
NCP1681AA, AB
NCP1681BA
|V
− V | = 3
V
LS1
LS2
0.95
0.8
1
0.84
1.05
0.88
Over−Current Protection (OCP)
Delay
Step V 0 V to V
+ 250 mV;
T
OCP1
−
45
75
ns
CS
ILIMIT1
Time to PWMx = 2.5 V
OCP Leading Edge Blanking
T
150
220
290
ns
V
OCP1(LEB)
Threshold for Abnormal Current
Detection
V
= 1.5 * V
V
ILIMIT2
ILIMIT2
ILIMIT1(LL)
NCP1681AA, AB
NCP1681BA
1.425
1.995
1.5
2.1
1.575
2.205
Abnormal Overstress Timer
T
710
815
4
950
ms
WDG(OS)
Consecutive Abnormal Over Current
Events to disable controller
N
−
−
CS(LIM2)
Abnormal Over−Current Protection
Step V 0 V to V
+ 250 mV;
T
OCP2
−
45
75
ns
ns
CS
ILIMIT2
Delay
Time to PWMx = 2.5 V
Abnormal OCP Leading Edge
Blanking
T
85
110
135
OCP2(LEB)
CS Pullup Current Source
V
= V
I
CS
0.7
45
1
1.3
95
mA
CS
ILIMIT2
Minimum Current Threshold for THD
Enhancer Enable (NCP1681BA)
V
CS
increasing
V
70
mV
CS(MIN)
CS Minimum Current Ratio
(NCP1681BA)
K
= V
/V
K
−
5
−
%
CS(MIN)
CS(MIN) ILIM1(LL)
CS(MIN)
CS Protection Test Current
I
180
100
1
235
150
−
−
200
−
mA
mV
kW
CS(TEST)
CS Protection Voltage Threshold
Recommended CS Filter Resistance
V
CS(TEST)
R
CS(FILT)
UNDERVOLTAGE & OVERVOLTAGE PROTECTION
UVP Threshold
V
FB
V
FB
decreasing
decreasing
V
R
−
0.3
12
−
V
UVP
Ratio (UVP Threshold) over V
8
16
%
REF
UVP
(V
/V
)
UVP REF
UVP Hysteresis
V
increasing
increasing
increasing
V
−
−
50
100
−
mV
V
FB
FB
FB
UVP(HYST)
Soft OVP Threshold
V
V
2.625
105
softOVP
softOVP
Ratio (soft OVP Threshold) over
(V /V
V
R
104
106
%
V
REF
)
softOVP REF
Ratio (soft OVP Hysteresis) over
REF
V
FB
decreasing
R
1.5
2
2.5
%
softOVP(H)
V
Fast OVP Threshold
V
increasing
increasing
V
−
2.7
−
V
FB
fastOVP
Ratio (Fast OVP Threshold) over
(soft OVP Upper Threshold)
V
FB
R
102.4
103
103.4
%
fastOVP1
(V
/V
)
fastOVP softOVP
www.onsemi.com
11
NCP1681
Table 4. ELECTRICAL CHARACTERISTICS (V = 12 V, V
= 1.2 V, V
SRH
= 0 V, V = 2.4 V, V
= open, C
CC
LVSNS1
LVSNS2
FB
FAULT POLARITY
= 100 pF, V
= 0 V, V
= 0 V, V = 0 V, C
= 100 nF, C
= C
= 100 pF, C
= C
= 100 pF, for typical values T =
AUX
ZCD
CS
VCC
SRL
PWML
PWMH J
25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
J
Characteristics
UNDERVOLTAGE & OVERVOLTAGE PROTECTION
Ratio (Fast OVP Threshold) over
Conditions
Symbol
Min
Typ
Max
Unit
V
increasing
decreasing
R
106.5
−
108
2.575
250
109.5
−
%
V
FB
fastOVP2
V
(V /V
)
REF
fastOVP REF
FB Threshold for Recovery from a
Soft or Fast OVP
V
FB
V
OVPrecover
FB bias Current @ V =V
(I )
B FB
50
450
nA
FB
softOVP
and V =V
FB
UVP
PFCOK & BUV PROTECTION
PFCOK voltage in OFF mode
PFCOK current
PFCOK pin sink current = 1 mA
= 2.5 V, V = 1 V
V
−
−
100
27
mV
mA
V
PFCOK(low)
V
FB
I
23
25
PFCOK
PFCOK
BUV threshold
V
FB
decreasing
V
T
1.95
400
2.0
500
2.05
600
BUV
BUV delay during which operation is
disabled
ms
BUV
STATIC OVP
Duty ratio
V
FB
= 3 V
D
−
−
0
%
MIN
SOFT SKIP CIRCUIT
V
Threshold Voltage to Enter Skip
V
1.2
56
1.5
1.8
V
M
SKIP(th)
Mode (NCP1681BA Only)
Minimum pulse duration for SKIP
detection
V
M
< V
T
−
−
ms
SKIP(th)
SKIP1
PFCOK SKIP Threshold
V
0.4
10
0.5
30
0.6
50
V
SKIP2
Minimum PFCOK negative pulse du-
ration for SKIP detection
T
SKIP2
ms
V
lower value at the end of a soft
(R
V
)
92.5
94
95.5
%
FB
FB recover
skip cycle burst defined as a V
percentage
REF
V
FB
Restart Level in Skip Cycle
−
400
−
2.35
500
400
−
600
−
V
RESTART
Blanking time for operation recovery
Skip Confirmation Window
T
ms
ms
recover
V
M
T
WINDOW
FAULT PROTECTION
OTP Fault Threshold
V
decreasing
V
0.38
43
0.40
46
0.42
49
V
mA
ms
ms
V
Fault
FLT(OTP)
OTP Fault Source Current
OTP Detection Filter Delay
OTP Blanking During Startup
OTP Fault Recovery Threshold
OVP Fault Threshold
V
= V
+ 200 mV
I
Fault
FLT(OTP)
FLT
V
Fault
decreasing
t
22.5
4
30
37.5
6
OTP(DLY)
t
5
OTP(BLANK)
V
increasing
increasing
increasing
V
V
0.874
2.88
22.5
1.15
1.32
0.92
3
0.966
3.12
37.5
2.25
1.78
Fault
Fault
Fault
FLT(REC)
FLT(OVP)
OVP(DLY)
V
V
V
OVP Detection Filter Delay
Fault Clamp Voltage
t
30
ms
V
V
= open
V
R
1.7
1.55
Fault
FLT(CLAMP)
FLT(CLAMP)
Fault Clamp Resistance
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
kW
Temperature increasing
Temperature decreasing
T
SHDN
−
−
150
50
−
−
°C
°C
T
SHDN(HYS)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
12
NCP1681
Totem Pole Theory of Operation
Figure 4. Totem Pole PFC Circuit
The Totem Pole PFC (TPFC) circuit is shown in Figure 4.
In Figure 4 the fast leg switches are represented as
MOSFETs, but Wide Bandgap (WBG) transistors are
generally recommended for NCP1681 applications. WBG
devices, whether Silicon Carbide (SiC) or Gallium Nitride
The topology consists of two half−bridge configurations;
one half bridge, commonly referred to as the “Fast Leg”
switches at the PWM frequency and the other, commonly
referred to as the “Slow Leg” switches at the AC line
frequency. The fast leg switches perform the role of the
switch and the diode in a classical boost PFC, that is these
switches function to regulate the output voltage and shape
the input current to provide high power factor and low
harmonic distortion. The slow leg switches perform the role
of the diode bridge in a classical boost PFC. Active switches
with low ON resistance are utilized instead of diodes
resulting in improved efficiency. Also, as will be described
in the discussion below, the TPFC operates with only one
slow leg and one fast leg device in the conduction path
whereas the conventional boost PFC operates with two
bridge diodes and one active switch or boost diode in the
conduction path. Fewer devices in the conduction path and
active switches replacing bridge diodes allow the TPFC
topology to achieve higher system efficiency and power
density than the classical boost PFC.
(GaN), offer excellent Q *R
figure of merit and
g
ds(on)
virtually no reverse recovery charge, Q , making them
rr
optimal devices for the TPFC fast leg, particularly when
operating in continuous conduction mode (CCM). The
PWM drive signals produced by the NCP1681 are logic
level signals so an external gate driver IC must be used to
properly drive the fast leg switches. A galvanically isolated
gate driver, such as NCP51561, is recommended due to the
noise induced by the hard switching that occurs in CCM.
The TPFC operates with bidirectional current flow in the
inductor and the command of the fast and slow leg switches
changes depending on the polarity of the AC line cycle.
Operation of the TPFC during the positive and negative half
line cycles is illustrated in Figure 5 and Figure 6,
respectively.
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13
NCP1681
Positive Half Cycle Operation
Figure 5. Positive Half Cycle Operation
During the positive AC line cycle the PWML signal is
fast leg device does not need to conduct for proper PFC
operation, however the PWMH signal can toggle high to
turn on the high side device, providing enhanced system
efficiency at higher loads. Throughout the positive half line
cycle current is flowing left to right through the inductor and
always returning to the source through the low side slow leg
device, hence the SRL signal will toggle high to turn on the
respective slow leg device for optimum converter
efficiency.
responsible for performing pulse width modulation or duty
cycle control of the converter. PWML toggles high turning
on the low side fast leg device, allowing current to charge
and store energy in the inductor, as shown by the solid blue
line in Figure 5. When the PWML signal toggles low the
inductor current diverts through the high side fast leg switch,
transferring energy from the inductor to the load, as shown
by the dashed blue line. In this half line cycle the high side
www.onsemi.com
14
NCP1681
Negative Half Cycle Operation
Figure 6. Negative Half Cycle Operation
During the negative AC line cycle the PWMH signal is
high voltage startup, the bias supply will have to come from
an external source such as a dedicated auxiliary supply or
from a downstream converter. Additionally, the controller
must have sufficient input voltage (BONOK cleared) and
validation that the ac line frequency is within the expected
responsible for performing pulse width modulation or duty
cycle control of the converter. PWMH toggles high
commanding the high side fast leg device to conduct,
allowing current to charge and store energy in the inductor,
as shown by the solid red line in Figure 6. When the PWMH
signal toggles low the inductor current diverts through the
low side fast leg switch, transferring energy from the
inductor to the load, as shown with the dashed red line. In
this half line cycle the low side fast leg device does not need
to conduct for proper PFC operation, however the PWML
signal can toggle high to turn on the low side device,
providing enhanced system efficiency at higher loads.
Throughout the negative half line cycle current is flowing
right to left through the inductor and always returning to the
source through the high side slow leg device, hence the SRH
signal will toggle high to turn on the respective slow leg
device for optimum converter efficiency.
operating range (N
≥ 4), then the control can power
DRV_EN
up on the next rising polarity edge, synchronizing the startup
to a positive half line cycle. The startup requirements are
summarized:
• Brown−out protection, BONOK, is cleared
• V > V
CC
CC(ON)
• N
≥ 4
DRV_EN
• Polarity rising edge
If the supply voltage is in the hysteresis band, i.e. if V
CC(OFF)
< V < V
then the controller will not start up. This
CC
CC(ON)
is done to ensure that the minimum specified hysteresis
between V and V of 1.2 V, is available for the
CC(ON)
CC(OFF)
device so that the increased current consumption at startup
doesn’t pull V below V , typically 8.8 V. Once the
VCC Management and Startup Sequence
The NCP1681 controller requires a supply bias of at least
CC
CC(OFF)
device has been enabled then the V voltage can fall to as
CC
V , typically 10.5 V, to enable and begin normal
CC(ON)
low as V
without disabling but for startup the V
CC(OFF)
CC
operation. Since the controller does not include an internal
voltage must exceed and remain above V
.
CC(ON)
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15
NCP1681
Line Voltage Sensing
interface with the low frequency node of the main boost
inductor, L , and the LVSNS2 pin is intended to
Figure
7
shows the recommended application
BOOST
configuration for the line voltage sensing scheme. External
resistor dividers are required to divide down two high
voltage nodes to perform differential line sensing. The
recommended divide down factor for universal input
interface with the bridge voltage of the slow leg power
switches. The internal Line Detector circuit is designed with
substantially high input impedance allowing for large
external resistors to minimize the power dissipation in the
dividers, enabling the application to achieve low no load
consumer applications is K , typically 100; i.e.
L_DIV
power consumption. Typical values for R
can be in
RLOWERx
LOWERx ) RUPPERx
UPPERx
1
ǒR
Ǔ +
(eq. 1)
the range of 5 – 10 MW while R
can be 50 – 100 kW.
LOWERx
KL_DIV
In practice the upper portion of the resistor divider should
consist of at least two 1206 components connected in series
to withstand the voltage drop.
such that the low voltage signals which interface to the
NCP1681 are approximately 1% of the high voltage signals
that are being monitored. The LVSNS1 pin is intended to
Figure 7. Line Sensing Configuration
In the Totem Pole topology, the AC line voltage floats
with respect to the controller ground. This necessitates a
differential measurement technique to determine the AC
line voltage magnitude. The NCP1681 employs differential
voltage detection and rectification to reconstruct a
sensing will additionally be responsible for determining the
polarity (i.e. positive or negative half−line cycle) of the AC
voltage and for measuring the frequency of the AC line
voltage. In total, the line sense will be utilized for the
following functions –
waveform equal to |V
– V
|. For simplicity
a. Polarity detection,
LVSNS1
LVSNS2
|V
LVSNS1
– V
| will be referred to as V . The key
b. AC Line Frequency Monitoring,
LVSNS2
LINE
waveforms are shown in Figure 8. The reconstructed
waveform is utilized to perform functions such as
brown−out and line level detection where it is necessary to
measure the amplitude of the line voltage. The line voltage
c. Brownout protection feature,
d. Line level detection,
e. AC zero crossing drive management
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NCP1681
Figure 8. Line Sense Waveforms
Polarity Detection
capacitance may be added to improve noise immunity of the
polarity detection circuitry; the recommend time constant of
the RC filter is about 20 – 200 ms, enough to provide noise
immunity from the switching frequency of the power supply
but not such a large time constant to introduce significant lag
in the line sense signals.
Figure 9 shows a simplified diagram of the polarity
detection circuitry. The two line sense signals are compared
directly against each other to determine when they intersect.
The intersection or crossover of the two signals indicates
that the AC line voltage has changed polarity. External filter
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NCP1681
Figure 9. Polarity Detection Diagram
Additionally, the output of the polarity sense comparison
from high to low (or vice versa) but does not remain in that
state for a time greater than T , then the output
will remain in its previous logic state and the timer will
effectively reset. In Figure 10, time durations t1, t2, t3 and
circuit is passed through a digital glitch filter which will
provide additional immunity if the comparison circuit is
toggling repeatedly. The glitch filter has a timer,
POL_FILTER
T
, of 200 ms. The behavior of the filter is shown
POL_FILTER
t5, t6, t7 are all less than T
and hence the output
POL_FILTER
below in Figure 10. The input to the filter must remain at a
logic state (high or low) for greater than the filter’s timer for
the output to transition to that state. If the input transitions
of the filter remains unchanged. Time durations t4 and t8 are
greater than T , causing the output to transition to
POL_FILTER
the new state.
Figure 10. Polarity Glitch Filter Operation
AC Line Frequency Monitoring
The NCP1681 controller comes with an optional line
frequency monitoring circuit. The NCP1681 utilizes timers
operation is shown in Figure 11. Practically the controller
measures the time between every edge transition of the
filtered polarity signal. If one timing interval, such as t ,
1
& counters to monitor the AC line frequency (T
)
measures outside of the expected frequency range then the
controller will disable the slow leg drive signals, SRL and
LINEFREQ
to ensure that the polarity comparator output toggles at a rate
consistent with the mains frequency specification of 45 –
65 Hz. A timing diagram of the AC line frequency monitor
SRH, and start a 100 ms timer, t
. If a timing
LINEFREQ(DLY)
interval within the specification is measured prior to
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NCP1681
t
expiring, then t
is reset and
active, performing continuous time interval measurements
of the polarity signal. The device will auto−recover from the
fault mode once the device detects 4 consecutive polarity
edges that are within the line frequency specification, same
as a new startup. The thresholds for the AC line frequency
LINEFREQ(DLY)
LINEFREQ(DLY)
slow leg drive pulses are again enabled. This is shown with
timing interval t and t .
Should the polarity toggles continue to measure outside of
the mains frequency specification and the timer expires then
the controller will disable fast leg drive pulses and enter fault
2
3
monitor are given by t , nominally 72 Hz, and
LINE(65)
mode as shown after t . Note that throughout timing interval
t , nominally 42 Hz. These thresholds are designed to
LINE(45)
5
t the slow leg pulses are disabled. While in fault mode the
polarity signal and the line frequency monitor will remain
provide some margin so that under worst case tolerance the
AC line frequency can always operate from 45 – 65 Hz.
5
Figure 11. Line Frequency Faults Timing Diagram
th
As previously mentioned, startup of the NCP1681
controller is synchronized to the rising edge of the filtered
polarity signal and requires at least 4 consecutive half−line
on the rising edge of the 4 consecutive polarity toggle with
valid time duration. The rising edge of the polarity signal
indicates that the AC line is entering a positive half line cycle
which is the preferred conduction angle for starting up the
application because the low−side fast leg device will be the
duty cycle controlled device.
cycles (polarity toggles) to be within the valid T
LINEFREQ
duration. The controller enable counter is denoted as
in the electrical table. Line Frequency operation
N
DRV_EN
is shown in Figure 12 where the Line Freq OK flag is set high
Figure 12. Polarity Startup Timing Diagram
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NCP1681
Brown−Out and Line Sag Protection
disabling drive pulses when the line voltage falls below the
threshold, typically 1 V, for a given timer duration.
Considering that the LVSNSx inputs are recommended to be
1% of the AC line voltage, this translates to a nominal enable
The NCP1681 feature set includes line voltage
Brown−out (BO) and Line sag (SAG) detection. These
detection circuits function collaboratively as a line voltage
UVLO, enabling drive pulses when the peak line voltage
V
BO(stop)
threshold of ~ 110 V, or ~ 78 V , and a nominal disable
AC
exceeds the V
threshold, typically 1.1 V, and
threshold of ~ 100 V, or ~ 71 V
.
BO(start)
AC
Figure 13. BO/SAG Detection Circuit
Figure 13 is a representative schematic of the NCP1681
BO/SAG detection circuitry. The circuitry monitors the line
are the same, with the difference between the two features
being the timing after which the respective output is set high,
and the action taken by the controller after each of the
respective outputs. Figure 14 illustrates the controller
response during a line sag and brownout.
voltage, V , generated by the NCP1681’s internal
LINE
differential line sensing. V
is compared against the two
LINE
V
BO
thresholds. Both the BO and SAG voltage thresholds
Figure 14. Line Sag and Brownout Timing Diagram
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NCP1681
The 25 ms SAG timer, t
, allows the application
controller from oscillating between low line and high line
mode. The transition thresholds of 2.36 and 2.22 V typically
SAG(blank)
to sustain a line voltage dropout for a single AC line cycle
while the NCP1681 continues to deliver drive pulses. If the
SAG timer expires, the controller will enter a soft stop
period where the internal control voltage is slowly
discharged to 0 V and the pulse width of the PWM is
gradually narrowed, reducing the power delivery of the
application. After the soft stop period the polarity signal
remains active and the controller will be ready for
immediate restart should the line voltage exceed the
translate to line voltages of 167 and 157 V , respectively,
AC
which are intermediate voltages that do not correspond to
any national standard for AC mains, leaving little likelihood
that the input voltage to the application will operate near the
transition thresholds. Further, the transition thresholds have
a minimum hysteresis, V
, of 100 mV to act as
LR(HYS)
another protection against the device oscillating back and
forth between low and high line.
V
threshold. If the 650 ms brown−out timer expires,
The purpose of line range detection is that the controller
modifies the gain of the internal digital compensator in order
to optimize performance and operation of the PFC for
universal, wide−input mains applications. Specifically, the
loop gain of the digital compensator is reduced by a factor
of 4 when the device detects that it is in the high line range.
BO(start)
the NCP1681 will disable the polarity detection circuit and
reset the device, including any latching faults. When the
application restarts from a BO the controller functions as it
would for an initial power up.
Line Range Detection
The NCP1681 features input voltage range detection,
AC Zero Crossing Management
which distinguishes between high line (nominally 230 V
)
AC zero crossing management is the feature in the
NCP1681 that determines when to enable and disable the
various drive signals at the beginning and end of each of the
half line cycles. This feature is critical to the robustness and
performance of the Totem pole topology. The NCP1681
features 6 drive signals that can be divided into three classes:
1) The primary or duty−cycle controlled PWM drive signal;
2) The synchronous (sync) PWM drive signal that occurs
during the (1 − d) portion of the switching period; and 3) The
slow leg “rectifier” or SR drive signal that switches once per
half line cycle. Each drive signal has a respective stop and
start threshold, which is a function of the line voltage
AC
and low line (nominally 115 V ) input voltages. The input
AC
voltage range is detected based on the peak voltage
measured with the reconstructed V
signal. By default,
LINE
the controller will power up into low line mode. If V
LINE
exceeds the high line threshold, V , typically 2.36 V, for a
HL
duration longer than t , typically 300 ms, the
filter(HV)
controller transitions to high line mode. Once in high line
mode the peak line voltage must fall below V , typically
LL
2.22 V, for a duration longer than t
, typically 25 ms,
blank(LL)
to enter back into the low line mode. The blanking duration,
, is set long enough to allow the controller to remain
t
blank(LL)
in high line mode in the event of a single line cycle dropout.
Should the controller transition from high line to low line
amplitude, V
previously mentioned.
, where V
= |V
– V
| as
LINE
LINE
LVSNS1
LVSNS2
mode, a lockout timer t
, typically 500 ms, is
Figure 15 illustrates the zero crossing management
thresholds for the primary PWM drive, denoted as PWMd.
The same stop and start principle applies to the Synchronous
PWM and SR drives, although with different thresholds.
line(lockout)
enabled. The lockout timer blocks the controller from
transitioning back to high line immediately after a low line
transition for the duration of the timer, preventing the
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NCP1681
Figure 15. AC Zero Crossing Management Thresholds
Figure 15 shows a full AC line cycle beginning with a
Zero crossing management of the synchronous PWM and
SR drives follows the same principle as that used to manage
the primary PWM drive, however the thresholds are higher
as the primary PWM switches for a greater portion of the
positive half−line cycle, i.e. conduction angle between 0 –
180°. In the positive half−line cycle the voltage at the
LVSNS2 pin is pulled to 0 V and the voltage at LVSNS1 is
increasing proportional to the AC line amplitude. When the
half line cycle. For the slow leg SR drive, V
SR_START1(xL)
AC line amplitude exceeds the threshold V
,
is typically 200 mV and V
is typically 180 mV
ZCB_START1(xL)
SR_STOP1(xL)
typically 120 mV, the controller begins issuing drive signals
to the duty−controlled device, PWML in this case. As the
and because operation is symmetric the start and stop
thresholds in negative half line cycle are the same. For the
conduction angle approaches 180°, V
will eventually
threshold, typically 100 mV,
sync drive, the start threshold, V
, is
LINE
SYNC_START1(xL)
fall below the V
typically 220 mV and the stop threshold is typically 200 mV.
All the thresholds in the AC zero crossing management
block include hysteresis to ensure stable operation without
repeated enabling and disabling should noise corrupt the
LVSNS signals. Also, all the drive signals are disabled
before the AC line voltage reaches its true zero crossing.
While this can lead to a small amount of increased zero
crossing distortion, the benefit of disabling all drives is to
create a quite environment to ensure the precision and
robustness of the polarity signal which is critical to
guarantee that the PWM and SR drive signals are directed to
the proper device during the respective half line cycle.
ZCB_STOP1(xL)
and the controller will blank drive pulses to the
duty−controlled device.
In the negative half line cycle the zero crossing
management works largely the same as positive half line
cycle with the controller processing the different LVSNS
signals that are unique to negative half line cycle operation.
In this half line cycle LVSNS2 is pulled up to a voltage
proportional to about 1% of the PFC bulk voltage, and the
LVSNS1 decreases in amplitude relative to the controller
GND pin, but increases in amplitude relative to the LVSNS2
signal. The controller’s differential line sensing reconstructs
V
= |V
– V
| so that V
is symmetrical
LINE
LVSNS1
LVSNS2
LINE
Open Loop Drive Pulses
in positive and negative half line cycle and the zero crossing
management can use the same comparison thresholds for
both half line cycles. The V
Another critical feature of the NCP1681 is the open loop
drive pulses that are issued immediately following a polarity
transition. After the AC line zero crossing, the slow leg
bridge maintains a residual voltage charge from the previous
half line cycle and must be transitioned from V
(or vice versa) during the upcoming half line cycle.
threshold is
ZCB_START2(xL)
120 mV, and the V
threshold is 100 mV, same
ZCB_STOP2(xL)
as the start and stop thresholds in positive half line cycle,
ensuring that the zero crossing management is symmetric
across a full AC line cycle.
to 0 V
BULK
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NCP1681
Considering that PWM−controlled drive pulses near an AC
Table 5. OPEN LOOP DRIVE PULSES
line zero crossing would typically operate with a high duty
cycle, using these pulses to transition the slow bridge
voltage can result in excessively high current spikes in the
inductor; hence it is beneficial to use shorter drive pulses
with a smaller, fixed duty cycle to initiate the slow leg bridge
node transition. The ON time of the main duty−controlled
FET is gradually increased during this phase to assist the
slow leg bridge node voltage in transitioning between the
bulk voltage and ground. The OFF time of the main
duty−controlled FET is also gradually increased during this
phase to maintain the same duty ratio. During the open loop
drive pulses, the slow leg drive and (1−d) drives are held low,
and the current sense input is blanked. The duration and
period of the open loop drive pulses is captured in Table 5.
Ton (ms)
Toff (ms)
Period (ms)
1st pulse
2nd pulse
3rd pulse
4th pulse
1
2
4
6
3
6
4
8
12
18
16
24
52
total
Figure 16 provides an annotated timing diagram of a zero
crossing transition including the open loop drive pulses. For
simplicity, the sync PWM (1−D) drive signals are not shown
in this figure.
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NCP1681
Figure 16. Zero Crossing Timing Diagram
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NCP1681
Operating Modes
Event (A) – When the sensed line voltage falls below
, the ‘D’ drive signal is disabled.
The NCP1681 is available in two versions: The “A”
version operates at a fixed switching frequency with
predictive current mode control, making it well suited for
high power (> 1 kW) CCM applications where full load
efficiency and low harmonic distortion are critical design
requirements. The “B” version is a Multi−Mode (MM)
device which can operate in fixed frequency CCM at high
power, Frequency Clamped Critical Conduction Mode
(FCCrM) at medium loads, and discontinuous conduction
mode (DCM) with reduced switching frequency at lighter
loads. The MM device is best suited for applications where
the output power requirement is ~ 300 W – 1 kW or where
light load efficiency and THD must be optimized.
Additionally, the MM control algorithm enables higher
power density for the boost inductor when compared to
typical CCM applications.
V
ZCB_STOP2(xL)
Event (B) – When the sensed line voltage falls below
, the slow leg drive signal is disabled. Events
(A) & (B) can occur at the same instant or event (A) slightly
before or after event (B).
V
SR_STOP2(xL)
Event (C) – The two sense nodes cross over, representing the
actual AC phase reversal instant.
Event (D) – The polarity edge after the filter.
Event (E) – Open Loop Drive pulses issued on the low side
M2 (PWML) drive during the negative to positive half line
cycle transition or on the high side M1 (PWMH) drive
during the positive to negative half line cycle transition.
Event (F) – The open loop drive pulses assist the slow leg
switch node transition from 400 V to 0 V or from 0 V to
400 V.
Event (G) – Settling of the slow leg switch node voltage.
Multi−Mode Operation
The “B” version of the NCP1681 controller is designed
for Multi−Mode operation where the converter can operate
in fixed frequency CCM at heavy loads, Frequency Clamped
Critical Conduction Mode (FCCrM) at medium loads, and
discontinuous conduction mode with valley switching at
light loads. Transitioning between the different operating
modes is dependent on the duration of the inductor current
conduction period. This is illustrated in Figure 17.
Event (H) – Low side slow leg M4 is enabled if the line
voltage exceeds V
.
SR_START1(xL)
Event (I) – Fast leg drive M2 is enabled if the line voltage
exceeds V . Note that Event(H) doesn’t
ZCB_START1(xL)
necessarily occur before Event(I); based on the selected
options it is possible that Event(I) will occur first.
Event (J) – The current sense used for CCM duty cycle
modulation (V generation) is blanked/shorted during
M
event (E)/(F). This ensures that the control loop does not
respond to this interval.
T
PERIOD
T
PERIOD
T
T
PERIOD
PERIOD
T
PERIOD
Figure 17. Multi−Mode Operating Modes
In FCCrM, the controller operates in variable frequency
critical conduction mode (CrM) if the switching frequency
remains below the frequency clamp threshold of 130 kHz.
Once the switching frequency exceeds the clamp frequency
the controller transitions into discontinuous conduction
mode (DCM) with turn−on of the next switching cycle
synchronized to the valley of the switch node resonance. At
medium loads, transitions between CrM and DCM can occur
within half of the AC line cycle. Often, the controller will
operate in CrM near the peak of the AC line where the
inductor conduction period is longer and switching
frequency is lower, and transition to DCM as the AC line
voltage approaches zero and the inductor conduction period
reduces.
As the load reduces the converter may operate in DCM
across the entire AC half−line cycle, switching in different
valleys throughout. With further reduction in load the
controller enters a switching frequency reduction mode
where the switching frequency is pushed to lower
frequencies the lighter the load. The frequency reduction in
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NCP1681
DCM is achieved by a novel ramp modulation circuit that
period. There is no valley synchronization for turn−on even
if the inductor has completed demagnetization and the
switch node is resonating.
The criteria to exit CCM are intended to provide some
hysteresis in output power so that the controller does not
continuously oscillate between CrM and CCM operation. To
exit CCM, the PFC output power must have reduced enough
that the following exit conditions are met:
• The inductor current conduction period must not
exceed 112% of the CCM switching period for at least
8 consecutive switching cycles.
• The peak upslope current measured at the CS pin must
be continuously below a minimum value equal to 15%
of the CS peak current limit. This threshold,
forces longer switching periods, and more resonant valleys
as the load is decreasing. As the load decreases towards 0,
the controller clamps the switching frequency to a
minimum, F
, typically ~ 30 kHz, to mitigate audible
MIN
noise. All the transitions with FCCrM are determined
exclusively based on the inductor conduction period and the
controller performs these transitions seamlessly causing no
discontinuity in operation while maintaining good power
factor.
Fixed frequency CCM operation is obtained in heavy
loads when the inductor conduction period regularly
exceeds 112% of the CCM switching period, T
. In
CCM
NCP1680BA the CCM switching frequency is 65 kHz so the
inductor conduction period must exceed ~ 17.2 ms (1.12 /
V , is nominally 210 mV.
CS_CCM−L
F ). In addition to the switching frequency threshold,
CCM
• Either of the two criteria listed above must continue for
a period of at least T , nominally 360 ms.
there are multiple conditions that must be met for the
controller to transition to CCM operation. These conditions
are summarized here:
CCMend
Fixed Frequency PWM Operation
• The inductor current conduction period must exceed
112% of the CCM switching period for at least 8
consecutive switching cycles.
In fixed frequency operation the NCP1681 incorporates a
predictive average current mode control scheme to
accomplish power factor correction and output voltage
regulation. This control method utilizes a transconductance
multiplier, illustrated in Figure 18, which senses the inductor
current and produces an output current proportional to the
inductor current. The multiplier receives three input signals:
(A) 2 V voltage reference, (B) the reconstructed inductor
current as a sum of two signals – the upslope current sensed
by the CS pin and downslope current sensed by the ZCD pin,
and (C) the control voltage from the output of the digital
compensator. The multiplier output current is fed into an
• The peak upslope current measured at the CS pin must
exceed a minimum value equal to 25% of the low line
CS peak current limit. This threshold, V
nominally 350 mV.
, is
CS_CCM−H
• The controller cannot transition back into CCM
immediately following a transition to CrM. A CCM ³
CrM transition requires at least 260 ms of CrM
operation before the controller allows a transition back
to CCM.
external resistor, R , that sets the multiplier voltage, V ,
M
M
Once the controller has transitioned to fixed frequency CCM
operation it will remain in this operating mode until meeting
the criteria to exit CCM. In this operating mode the PFC will
switch at a fixed frequency across the entire AC line cycle
regardless of the duration of the inductor current conduction
which is then used for duty cycle modulation. A capacitor to
ground in parallel with R is needed to filter the switching
M
ripple present on V . The recommended time constant for
M
the multiplier filter is 50 – 100 ms.
Figure 18. Multiplier Architecture
2 @ V
The voltage generated at the output of the multiplier is
VM
+
CSZCD @ GVM @ RM
VCTRL
(eq. 2)
shown in Equation 2 where G
is the transconductance of
VM
the multiplier, nominally 75 mA/V.
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NCP1681
This voltage is utilized in the PWM drive control logic to
command the switching duty cycle of the PWM controlled
current shaping is achieved by multiplier voltage control of
the duty cycle.
switch. The switching duty cycle, d, and complement, d’, are
The multiplier resistance, R , impacts the loop dynamics
M
determined by the following equations where V
nominally 3.75 V:
is
and controls the maximum power capability of the PFC.
Equation 5 should be used to calculate the maximum value
RAMP,PK
of R . This calculation should be done at the lowest RMS
input voltage for the application. In Equation 5 the
maximum control voltage of 4.2 V should be used for
M
VM
VRAMP,PK
d + 1 *
(eq. 3)
VM
VRAMP,PK
V , and the value of K
CTRL
is the scaling factor of the
ZCD
dȀ +
(eq. 4)
inductor current to ZCD voltage, typically equal to the R
resistor value established later in the datasheet.
ZCD
To achieve good power factor and low harmonic
distortion, PFC converters must control the amplitude of the
inductor current so that the inductor current effectively
follows the waveshape of the AC input voltage throughout
AC voltage line cycle. This is typically accomplished by
compensating the PFC with a suitably low bandwidth (<
20 Hz) and having a control algorithm which sets the
inductor current to be directly proportional to the input
voltage. In the NCP1681, the loop bandwidth requirement
is accomplished by the digital compensator and the inductor
h @ V2 IN @ VRAMP,PK @ VCTRL
R
M t
(eq. 5)
2 @ VO @ PO @ GVM @ KZCD
On Time Modulation Block
While in FCCrM the NCP1681Bx operates with a
constant on−time control algorithm. The on time of the main
PWM switch is controlled by the control voltage and a
modulating ramp as shown in Figure 19.
Figure 19. On Time Modulation
The circuitry for the on−time modulator is internal to the
NCP1681; the compensation voltage is generated by the
internal digital compensator and translated into the analog
domain, and the timing components for the modulator ramp
are also internal. In CrM the slope of the modulating ramp
Ǹ
2
V
O * 2 @ VIN
h @ VIN
1.12
(eq. 6)
L + ǒ Ǔ@ ǒ Ǔ@
ǒ Ǔ
FCCM
2 @ PTRAN
VO
As long as the application remains in CrM operation the
average input current to the PFC is approximately equal to
half of the peak inductor current, i.e., and a modulating ramp
with a fixed slope will continue to achieve good power
factor. However, when the application transitions to DCM
operation the inductor current remains at zero for some
portion of the switching cycle and the input current will
begin to distort unless that portion of the switching cycle is
compensated out. Figure 20 shows a sample inductor current
in DCM operation and the associated dead time that occurs
prior to the next drive pulse.
is fixed and the maximum on time, T , occurs when
on,max,CrM
the compensation voltage has railed to V
4.2 V.
of
CTRL(MAX)
Designing for MM operation requires designing the
inductor to switch below the CCM switching frequency at a
given line voltage and power level. Equation 6 can be used
to approximate the inductor value needed to achieve the
desired transition point at a given output power, P
. For
TRAN
example, to transition from CrM to CCM at P
= 250 W
TRAN
with an input voltage of 90 V, an inductance of ~ 180 mH is
needed.
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NCP1681
Figure 20. DCM Operation and Dead Time Compensation
T
ON ) TOFF
In DCM the average input current is now a function of the
dead time, specifically
kDT
+
.
TSW
IL,PK
2
T
ON ) TOFF
Multiplying the slope of the modulating ramp by a factor of
increases the on−time inversely proportionally to k
Iin
+
@
,
TSW
k
DT
DT
compensating out the effects of the inductor current dead
time and allowing the application to maintain good power
factor performance across CrM and DCM operation.
and the input current will begin to distort if the on−time
generator continues using a modulating ramp with a fixed
slope. The NCP1681 dead time compensation mitigates
input current distortion, retaining good power factor across
all operating modes, by adjusting the slope of the
modulating ramp by a factor equal to
Output Voltage Regulation Block
Figure 21. FB and Regulation Architecture
The general structure of the feedback and regulation
architecture is shown in Figure 21. The bulk voltage is
divided down via a resistor divider and input to a sample and
hold circuit which passes the sensed voltage to the input of
the error amplifier where it is compared against a 2.5
reference voltage.
The NCP1681 is internally compensated with a digital
error amplifier and a control voltage ripple cancellation
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NCP1681
circuit. The “Digital Error Amplifier and Compensator”
block performs the compensation generating the error
voltage, and the “Regulation Signal
Generation” block performs additional processing of the
error voltage, including the ripple voltage cancellation, to
This compensator provides greater than 50° of phase
boost at 2 Hz, over 70° of phase boost between 5 – 10 Hz,
and the mid−band gain measures at 13.4 dB. For most PFC
applications, having a mid−band gain between 10 – 15 dB
will ensure a loop crossover frequency in the range of 5 –
10 Hz, hence the NCP1681 compensator is designed to
satisfy a 5 – 10 Hz loop bandwidth with > 60° of phase
margin.
V
,
CONTROL
generate the V
signal. Practically, in FFCrM operation
REGUL
the V
signal is the digital domain version of V
REGUL
CTRL
signal from Figure 19 which dictates the on−time of the
application.
Additionally, the V
voltage is passed through an
CONTROL
The compensation in NCP1681 is equivalent to a Type−II
analog compensator as shown in Figure 22 with the
optional line frequency ripple cancellation circuit which is
designed to eliminate the AC ripple present on the
following component values: G
= 200 mS, R = 24 kW,
V
voltage. High amplitude AC ripple on the
OTA
Z
CONTROL
control voltage can increase harmonic distortion of the AC
line current, hence the desire to eliminate this ripple
component. However, a side effect of the ripple cancellation
circuit is that it behaves as another filter in the control loop,
degrading the phase boost provided by the compensator.
Figure 23 provides a Bode plot of the transfer function from
C = 4.62 mF, C = 97.24 nF. Based on these values the key
characteristics of the compensator are the following:
Z
P
• Mid−band gain = 20*log10(R *G ) = ~ 13.6 dB
Z
OTA
• Compensation zero location = 1/(2*p*R *C ) =
Z
Z
~1.44 Hz
• High frequency pole location = 1/(2*p*R *C ) = ~
Z
P
FB to V
including the effects of sampling,
REGUL
68.2 Hz
compensation, and ripple cancellation. The overall
compensation loop is optimized for a crossover point of ~
5 Hz where 60° phase margin can be achieved, and
bandwidths up to ~ 14 Hz can be designed with an acceptable
45° phase margin.
Figure 22. Equivalent Analog Compensator
Figure 23. Bode Plots with Ripple Cancellation Filter
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NCP1681
Output Voltage Protection Features
ǒ
Ǔ
L
Vout,softSKIP + 94% @ Vout,nom
The NCP1681 features multiple protection and
enhancement features for improved performance and
robustness of the application. The soft OVP, UVP and DRE
comparators monitor the sampled FB pin voltage. Based on
the typical value of their parameters and if (V
output voltage nominal value (e.g., 395 V), we can deduce
the following levels:
V
is the regulation reference (2.5 V typically) and R
FB1
REF
and R
are the feedback resistors per Figure 21; k is the
FB2
FB
scale down factor of the feedback resistors
) is the
out,nom
RFB2
FB1 ) RFB2
ǒk
Ǔ.
+
FB
R
V
is the internal threshold for the bulk under−voltage
• Output Regulation Level:
BUV
protection (BUV). Its typical value is 2 V. The BUV
protection thus typically trips when the output voltage drops
to 80% of its nominal level.
VREF
kFB
Vout,nom
+
• Output soft OVP Level:
Vout,SOVP + 105% @ Vout,nom
(V
) and (V
) are the levels between
out,softSKIP H
out,softSKIP L
which the output voltage swings when in soft−SKIP mode
(see the “Soft−SKIP Mode” section).
The soft−OVP trips when the feedback voltage exceeds
• Output Fast OVP Level:
Vout,FOVP + 108% @ Vout,nom
105% of V
and remains in this mode until V drops
REF
FB
below 103% of V . When the soft−OVP trips, it reduces
the power delivery down to zero in 4 steps as shown in
Figure 24.
REF
• Output UVP Level:
Vout,UVP + 12% @ Vout,nom
• Step 1: V
drops to 75% of the V
drops to 50% of the V
drops to 25% of the V
value
value
value
REGUL
for 400 ms
CONTROL
CONTROL
CONTROL
• Output DRE Level:
Vout,DRE + 95.5% @ Vout,nom
• Step 2: V
REGUL
for 400 ms
• Output BUV Level:
V
VREF
• Step 3: V
Vout,BUV
+
BUV @ Vout, nom + 80% @ Vout,nom
REGUL
for 400 ms
• Step 4: V
drops to 0 until the soft−OVP fault is
over, that is, when the output voltage drops below
103% of its regulation level.
• Output Upper Soft−SKIP Level:
REGUL
ǒ
Ǔ
Vout,softSKIP + Vout,nom
H
• Output Lower Soft−SKIP Level:
Figure 24. Soft−OVP Timing Diagram
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30
NCP1681
Auxiliary Winding and Valley Detection Block
The fast OVP comparator is analog and directly monitors
the feedback pin voltage for immediate blanking of the drive
pulses. The Fast OVP comparator trips when the feedback
The TPFC topology presents a unique challenge to the use
of an auxiliary winding for valley detection in FCCrM.
Unlike the classical bridged CrM boost PFC, the TPFC
operates differently in the positive and negative AC line
cycles. The PWM−controlled switch changes from the low
side switch to the high side switch, the inductor current
voltage exceeds 108% of V
and does not allow drive
REF
pulses until the feedback voltage falls below 103% of V
.
REF
The dynamic response enhancer circuit functions to
firmly contain undershoot of the output by increasing the
gain of the control loop in response to the bulk voltage
falling below a percentage of the desired regulation voltage.
Practically when the FB pin voltage falls below 95.5% of
st
rd
changes from 1 to 3 quadrant operation, and the “valley”
of the switch node does not always occur when the auxiliary
winding voltage approaches zero. Specifically, in negative
half line cycle, the “valley” is really a peak and the desired
turn−on of the PWM switch occurs when the switch node
voltage is approaching the bulk voltage. This is illustrated in
Figure 25 where the switch node voltage is depicted in both
positive and negative half line cycles.
V , the DRE speeds up the charge of the compensation
REF
network until the FB pin voltage exceeds 98% of V
.
REF
The FB pin also features a small 250−nA sink current for
protection against an open FB pin, in which case V will be
FB
pulled below the V
(300 mV typically) threshold
UVP
tripping the UVP protection. The UVP feature further works
as a protection in the case of a FB pin that is shorted to GND.
Figure 25. Switch Node Voltage in Positive (left) and Negative (right) Half Line Cycles
To adapt to the changing operation of the TPFC, while
maintaining the use of a single low−cost auxiliary winding,
the NCP1681 implements a novel “valley” sensing scheme
combining edge detection with threshold detection. The
NCP1681 accomplishes this by changing the “Arming” and
“Triggering” thresholds depending on the polarity of the AC
line. During positive half line cycle, the valley detection
arms when the aux voltage goes above 200 mV, and triggers
when the aux voltage falls below 100 mV. During negative
half line cycle the opposite occurs, namely the valley
detection arms when the aux voltage goes below 100 mV
and triggers when the aux voltage comes back above
200 mV. By reusing the same comparators and thresholds,
and only changing the function of the thresholds, the
NCP1681 effectively combines edge and threshold
detection to achieve a robust, low−cost solution that
overcomes the bidirectional operation of the TPFC.
Figure 26. Valley Detection in DCM. Positive Line Cycle on Left, Negative on Right
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31
NCP1681
Figure 26 shows waveforms demonstrating the valley
Figure 27 is an example of valley detection in CrM
operation. The switch node voltage is again shown on
channel 4 and although there is no image of the auxiliary
winding voltage, it can be seen that the turn−on of the
PWML (Ch.2) on the left, and PWMH (Ch.3) on the right are
coordinated to the “valley” of the switch node enabling very
low turn−on voltage for optimized efficiency.
detection implementation of the NCP1681 in DCM
operation. The waveforms show the switch node voltage
(Ch.4) and the auxiliary winding voltage (Ch.3) as its image
traversing through 5 valleys before the respective PWM
signal sets high. In both positive and negative half line cycle
the turn on occurs on the correct edge of the auxiliary
winding voltage.
Figure 27. Valley Detection in CrM. Positive Half Line Cycle on Left, Negative on Right
The recommended auxiliary winding connection is shown
in Figure 28. To optimize the symmetry of the valley
detection between positive and negative half line cycles, a
recommended to protect the AUX pin voltage from going
too far below ground when the auxiliary winding voltage
goes negative. Finally, a capacitor to ground, C
, can be
AUX
resistance, R
, with no series blocking diode is
used to tune the valley detection for optimizing valley
switching and efficiency in the fast leg.
It should be noted that the AUX winding detection is only
needed for multi−mode operation. For the NCP1681Ax
which employs only CCM operation, the AUX pin should be
connected directly to ground.
AUX1
recommended between the auxiliary winding and the AUX
pin. A pulldown resistance at the pin, R , helps divert
current to ground when the auxiliary winding voltage
swings high, reducing the current into the ESD protection of
AUX2
the valley detect circuit. A Schottky diode, D
, is
AUX
Figure 28. Recommended Auxiliary Winding Circuit
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NCP1681
Inductor Current Sensing
In CCM the NCP1681 implements predictive current
mode control that requires the controller to receive an
accurately sensed image of the inductor current. This is a
challenge with the TPFC topology because the inductor and
each of the fast leg switches conduct current bidirectionally,
as shown in Figure 29. Depending on the line cycle polarity,
st
rd
the inductor current flows in either the 1 or 3 quadrant
while the duty−controlled fast leg device conducts current
from drain to source, and the (1−d) fast leg device conducts
current from source to drain.
Figure 29. Current Flow in Positive and Negative Half Line Cycles
Current Transformer Blanking Circuits
The NCP1681 incorporates a novel current sensing
scheme utilizing two inputs – one for sensing inductor
current during the duty−controlled portion of the switching
cycle and one for sensing inductor current during the (1−d)
portion of the switching cycle. These two signals are
summed together inside the controller to reconstruct an
image of the inductor current. The current sense
configuration used in a typical application is illustrated in
Figure 30.
Each of the CTs is active during the half line cycle when
the respective switch is duty controlled. When the respective
switch is (1−d) controlled then the blanking circuit is active,
and the CT secondary is shunted to ground. In Figure 30 the
blanking circuits are shown as generic blocks with 3 ports as
there are different discrete circuit implementations that will
meet the operational requirements for these blanking
circuits. The CT is active when current flows drain to source
in the respective switch. During this portion of the switching
cycle current flows out of the secondary dot, into the anode
of the diode and eventually through the current sense
resistor. To avoid disrupting the CS signal the blanking
circuit must block voltage across ports A−B shown in
Figure 30, parallel to the CT secondary winding, but the
breakdown voltage that must be held off is just a diode drop
above the current sense limit.
Current Sense (CS) Input
The CS input senses the inductor current during the
duty−controlled portion of the switching cycle. This can be
referred to as the inductor current upslope. The
recommended scheme for the CS input requires two current
sense transformers (CTs), one in series with each of the fast
leg switches, a diode OR’ed output from the CT secondaries,
a single current sense resistor, and an RC filter to mitigate
noise pickup on the sense circuit. Additionally, a “blanking”
circuit is needed across each secondary to selectively shunt
the CT output to ground.
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33
NCP1681
meaning that the blanking circuit is conducting when the
POL/INVPOL signal is low and non−conducting when
POL/INVPOL signal is high.
POL/INVPOL
Figure 31. CT Blanking Circuit
Overload and Peak Current Limit Protection
The CS pin is also utilized for cycle−by−cycle peak
current limiting and overload protection. This function helps
protect the application from destructive damage due to
inductor saturation, output power overload, or thermal
overstress, by immediately terminating the duty−controlled
drive pulse when the peak current limit threshold is reached.
To calculate the CS resistor value needed for peak current
limiting, one must first calculate the maximum peak
inductor current in the application using Equation 7 where
Figure 30. NCP1681 Current Sensing Scheme
When the CT is active it develops magnetizing current
during the duty portion of the switching cycle that must then
be reset during the (1−d) period. During the (1−d) period the
magnetizing current in the secondary flows through the reset
resistor and appears at the secondary dot as a negative
voltage with respect to ground. The blanking circuit is then
required to block the reset voltage across ports B−A. The
two secondary diodes used in the ORing circuit and the
blanking circuit have a minimum breakdown voltage equal
to this reset voltage.
The blanking circuit is required to be active/conducting
whenever the primary current is flowing in the direction of
source to drain. In this case the secondary side current would
be flowing into the dot, hence the blanking circuit must be
able to conduct current across ports B−A to successfully
short the secondary. The current carrying capability should
match the capability of the diodes and the effective
impedance across port B−A should be an order of magnitude
lower than the current sense resistor to ensure that the
secondary can be shorted without generating substantial
magnetizing current.
The blanking circuit also requires a control port to switch
the circuit between its conducting and non−conducting state.
The circuit will switch at a frequency equal to the AC line
frequency and the NCP1681 features two outputs, Polarity
and Inverted Polarity (INVPOL), which can be used to drive
the control port. A circuit configuration that features all the
necessary requirements is shown in Figure 31. This
configuration consisting of two PMOS transistors with a
common source/cathode connection can block voltage
bidirectionally and conduct current bidirectionally,
behaving much like an ideal switch. The control port
requires a capacitive charge pump for driving the PMOS
transistors, and the drive logic for this circuit is inverting,
P is output power, h is efficiency, V is the RMS input
O
AC
voltage, L is the inductance of the boost choke, F is the
SW
CCM switching frequency, and D is duty cycle at the peak
PK
AC line voltage. Once the maximum peak current is
determined, Equation 8 is used to find an upper limit on the
CS resistor based on the CS current limit threshold,
V
, and the turns ratio of the current sense
ILIMIT(xL)
transformers. This calculation should be done at the
minimum AC input voltage, usually 90 V , and may also
AC
need to be repeated at the minimum high line voltage in the
application, typically 180
V , depending on the
AC
application’s output power requirements.
The NCP1681Ax utilizes a 1 V current limit threshold in
both low line and high line to accommodate applications that
may require more output power capability at high line when
compared to low line. The NCP1681Bx has a low line peak
current threshold of 1.4 V and implements a 60% reduction
of the current limit at high line, as the multi−mode version
of the device is more likely to be utilized in applications that
have a consistent power output requirement at all line
voltages. If the calculation is needed at both low and high
line, the user should choose the lower of the two calculated
values.
Ǹ
Ǹ
2 @ PO
2 @ Vac @ DPK
2 @ L @ FSW
(eq. 7)
IL,PK
+
)
h @ Vac
VILIMIT(xL)
IL,PK
R
CS t NS @
(eq. 8)
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NCP1681
THD Enhancer
reduces, and the CS voltage will spend longer durations
below this minimum threshold resulting in larger on−time
extensions. Note that the THD enhancer feature is only
actively utilized for on−time control in CrM/DCM, hence
this feature is only active in the NCP1681Bx version of the
device. The THD enhancer working in conjunction with the
dead time compensation circuit allows the NCP1681Bx to
optimize THD performance across line and load.
Another feature of the NCP1681 that is derived from the
CS voltage is the THD enhancer, which produces a small
on−time extension proportional to the time duration that the
CS voltage is less than the V
threshold. This is
CS(MIN)
shown in Figure 32 where the orange block represents the
time duration that the THD enhancer integrates to produce
an on−time extension. Typically, at lighter loads and near the
AC zero crossings the amplitude of the inductor current
Figure 32. THD Enhancer Diagram
Current Sense Open/Short Protection
controller outputs a 230 mA test current out of the CS pin
during the prestart phase when the controller is awaiting the
line frequency monitor to clear 4 consecutive AC line cycles
within the timing threshold. The 230 mA test current should
The CS pin is critical for performance and robustness of
the application so it is necessary to ensure an active sensing
circuit is present and the CS pin has not been left open or
accidentally shorted to ground as this would inhibit the
ability of the NCP1681 to provide protection against
overload or inductor saturation.
flow through the filter resistor, R , which interfaces the
FILT
current sense resistor to the CS pin. The controller measures
the minimum voltage generated externally and inhibits
operation if the voltage is less than 150 mV. To meet this
To protect against an open CS pin, the NCP1681 features
an internal 1 mA pull−up current and a second level current
limit comparator. The second level current limit threshold is
nominally 1.5 times that of the peak current limit threshold.
If the CS pin is open the pull−up current source pulls the pin
voltage above the comparator threshold causing the drive
pulse to terminate. Following a trip of the second level
comparator the controller also implements an overstress
timer, typically 800 ms, before initiating a new drive pulse.
The overstress timer is beneficial for limiting thermal stress
in case the second level comparator trips due to a failed
transistor in the fast leg. If the second level comparator is
tripped on 4 consecutive switching cycles, then the
controller shuts off all drive pulses and requires a complete
power−on reset before allowing more drive pulses.
requirement, it is recommended that R
have a minimum
FILT
resistance of 1 kW. The recommended time constant for the
filter is 50 – 150 ns.
Zero Current Detection (ZCD) Input
The ZCD input senses the inductor current during the
(1−d) portion of the switching cycle. This can be referred to
as the inductor current downslope or demagnetization. The
recommended sensing element for the ZCD input is either a
high power, low inductance, current sense resistor; or a
current transformer circuit like what is used for inductor
upslope detection. For ZCD the CT circuit does not require
a blanking mechanism because the current through the ZCD
sensing element is unidirectional and the CT remains active.
Figure 33 shows the two recommended sense circuit
configurations.
To protect against a CS pin that may be shorted to ground,
the NCP1681 employs a one−time impedance check of the
external circuitry connected to the pin. Specifically, the
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NCP1681
Figure 33. ZCD Sense Circuits
ZCD Resistor Calculation
gating of the device is necessary for optimizing efficiency
and ensuring robustness in the application. A diagram of the
sync control methodology is shown in Figure 34. First, the
The NCP1681 takes the CS and ZCD inputs and sums
them together to provide the internal multiplier with a signal
representative of the inductor current. This inductor current
signal is critical to optimizing THD performance in the
application and therefore the relative signal amplitude of
these two inputs should be approximately equal.
NCP1681 employs a dead time, T , typically 130 ns,
DT1
following the falling edge of the PWM duty−controlled
drive to prevent cross conduction. After the dead time has
expired the controller looks for the ZCD voltage to exceed
If the ZCD sensing element is a high−power current sense
resistor then Equation 9 should be used to calculate the
resistor value that ensures equal signal amplitude between
the CS and ZCD inputs. In case that the application designer
chooses a CT circuit for the ZCD input then the value for
the V
threshold to enable the sync drive. In lighter
ZCD(ARM)
loads, the ZCD voltage may never exceed this V
ZCD(ARM)
threshold, and the sync device will never enable. This is
done to prevent switching of the sync device at light loads
where the associated switching losses could negatively
impact the overall efficiency of the application.
R
ZCD
and the number of turns for CT3 should be identical
to what is used for the CS sensing circuitry. Like the CS
input, additional RC filtering is recommended at the ZCD
input to mitigate noise pickup from switching events. It is
recommended that the filter values at the ZCD input match
At increasing loads, the ZCD voltage will exceed the
arming threshold and the sync drive will remain enabled
until the ZCD falls below the V
threshold. The
ZCD(TRIG)
trigger threshold has been set close to 0 to keep the sync
conduction period as long as possible but without letting the
inductor current reverse polarity. Should the sync device
remain on for too long the inductor current would reverse
polarity and begin cycling energy from the bulk capacitance.
This would lead to increased RMS currents in the system and
could diminish overall efficiency.
the R
and C
values used for CS.
FILT
FILT
RCS
NS
RZCD
+
(eq. 9)
Synchronous PWM Drive Control
The synchronous PWM or (1−d) device in the TPFC
topology enables higher efficiency performance but proper
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NCP1681
Figure 34. Synchronous PWM Drive Control
In CrM operation it is required that the ZCD voltage fall
below the V threshold before the start of the next
PWM drive pulse, but in CCM this may not be the case as the
PWM drive pulse is set based on the internal oscillator.
Therefore, when the NCP1681 operates in CCM, the device
• In CCM operation there is an additional dead time,
, which terminates the sync pulse 150 ns (typical)
ZCD(TRIG)
t
DT2
before the start of the new switching period if the ZCD
voltage remains above the V
threshold.
ZCD(TRIG)
Skip/Standby Mode
implements an additional dead time, t , which shuts off
DT2
The NCP1681 features a Skip/Standby mode which
enables the application to achieve very good no load and
light performance. The device must be externally
commanded to enter the Skip mode by pulsing of either the
PFCOK or V pins, however because the V pin is used for
duty cycle modulation in CCM mode it is highly
recommended that the user utilize the PFCOK pin for skip
mode control. When the device enters the Skip mode, it
the sync drive pulse 150 ns prior to the start of a new
switching period. This additional dead time feature allows
the sync drive to remain high for most of the (1−d)
conduction period enabling better system efficiency while
still preventing cross conduction of the two switches.
Summarizing, the sync (1−d) pulses are gated by the
following criteria:
M
M
• A delay, t , of 125 ns (typical) after the PWM(d)
DT1
sheds much of its functionality except for FB and V
CC
turn−off – This prevents cross conduction
monitoring, and the internal consumption of the device is
• ZCD voltage crosses the V
threshold – This
ensures sync pulses are enabled only at higher loads for
efficiency improvement across all load conditions.
ZCD(ARM)
reduced to I , typically 540 mA. While in Skip mode the
CC4
output voltage decays to 94% of the regulation voltage
allowing for a long period, sometimes up to 1 minute, of
inactivity. When the output voltage reaches 94% of its
nominal value, the device exists Skip mode for a brief burst
period during which drives are enabled and the output
voltage is pushed back up to the nominal regulation value.
Provided that the NCP1681 continues to receive Skip
command pulses from an external source, the device will
continue to operate in this Skip−burst−skip mode
indefinitely. A timing diagram of the Skip operation is
shown in Figure 35.
• V
voltage crossing 220 mV which is 22 V on the
AC line with a 100:1 divider – This avoids premature
enabling of the sync pulses and enhances efficiency
LINE
• PFCOK sets high – To avoid reverse currents during
startup
• In CrM/DCM operation, the sync pulse is terminated by
the V
threshold. The device will not allow a
ZCD(TRIG)
new drive PWM pulse if this threshold has not been in
crossed.
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NCP1681
Figure 35. Skip Operation Timing Diagram
Skip Command Pulses
the PFCOK pin must be pulled below the V
,
SKIP2(th)
The PFCOK pin is typically utilized for communication
to a downstream converter, acting as an enable or UVLO. In
this case it may be necessary for the PFCOK pin to remain
high during the skip mode so that the downstream converter
does not shutdown. For that reason, the command pulse
logic for the PFCOK pin is optimized for a pulse train, where
typically 0.5 V, for a duration greater than T
, typically
SKIP2
30 ms. The frequency of the PFCOK pulse train needs to be
faster than the burst frequency of the PFC. Figure 36 shows
a sample schematic and timing diagram for the interface
between the downstream converter and the PFCOK pin of
the NCP1681.
Figure 36. PFCOK Schematic and Timing Diagram
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38
NCP1681
PFCOK Operation
output of the pin is a current source proportional to the FB
pin voltage with a gain of 10 mA/V. A resistor to ground
placed at the pin will give the downstream converter an
image of the bulk voltage for use as a UVLO or as a logic
enable.
The PFCOK pin is intended to control operation of a
downstream DC−DC converter by acting as an enable or
UVLO signal. The pin output is high when the application
is in nominal operation and low when the application is in
startup or when the device detects a fault condition. The
Figure 37. PFCOK Schematic
A logic diagram detailing the PFCOK pin operation is
shown in Figure 37. Worth noting is that at startup of the
application the PFCOK pin remains pulled to ground until
Fault Pin and Fault Matrix
Fault Pin
The NCP1681 includes a dedicated fault input accessible
via the Fault pin. The controller can be latched by pulling the
pin up above the upper fault threshold, V
the V voltage reaches 98% of V . Once the FB voltage
FB
REF
exceeds 98% of V
the internal PFCOK flag goes high
REF
, typically
FLT(OVP)
which enables the sync PWM and slow leg SR drive pulses.
Sync PWM and slow leg SR pulses are also gated by other
criteria but prior to achieving regulation, they are
completely disabled. The PFCOK flag also gates skip mode
operation and the bulk undervoltage (BUV) fault so that the
device is unable to enter skip mode or declare a BUV fault
until having first achieved regulation.
3.0 V. The controller is disabled if the Fault pin voltage,
, is pulled below the lower fault threshold, V
V
Fault
,
FLT(OTP)
typically 0.4 V. The lower threshold is normally used for
detecting an overtemperature fault. The controller operates
normally while the Fault pin voltage is maintained within
the upper and lower fault thresholds. Figure 38 shows the
architecture of the Fault input.
Figure 38. Fault Pin Schematic
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39
NCP1681
The lower fault threshold is intended to be used to detect
an overtemperature fault using an NTC thermistor. A pull up
devices used to drive either the fast of slow leg transistors
often have V pins rated only up to 20 V so a simple Zener
CC
current source I , (typically 46 mA) generates a voltage
diode connected between VCC and the FAULT pin can
protect those external devices. The controller is latched once
FLT
drop across the thermistor. The resistance of the NTC
thermistor decreases at higher temperatures resulting in a
lower voltage across the thermistor. The controller detects a
V
Fault
exceeds V
. Both of the Fault signals include
FLT(OVP)
internal filtering to prevent noise from triggering the fault
detectors. Upper and lower fault detector blanking delays,
fault once the thermistor voltage drops below V
.
FLT(OTP)
The OTP fault is an auto−recoverable fault so the NCP1681
t
and t
are both typically 30 ms. A fault is
OVP(DLY)
OTP(DLY)
will enable switching once the fault pin voltage exceeds the
detected if the fault condition is asserted for a period longer
than the blanking delay. Some external capacitance is also
recommended at the FAULT pin to provide additional noise
immunity.
V
threshold, typically 0.92 V. The OTP fault also
FLT(REC)
includes a 5 ms blanking circuit, t , which
OTP(BLANK)
prevents the OTP fault from being asserted when the device
first powers up. The blanking period is needed to allow any
external pin capacitance to be charged up above the OTP
threshold.
A clamp circuit prevents the Fault pin voltage from
reaching the upper latch threshold if the pin is left open. To
reach the upper threshold, the external pull−up current must
be higher than the pull−down capability of the clamp (set by
Fault Matrix
The NCP1681 has an extensive suite of fault handling
capabilities designed to enable a robust application design
utilizing the Totem Pole PFC topology. Although much of
the fault handling has been described in some detail
throughout the datasheet, Table 6 is provided as a Fault
Handling Matrix summarizing the key protection features
including the conditions needed to set the fault, reset the
fault, and the specific action taken by the controller for the
given fault.
R
at V
. The upper fault threshold can
FLT(CLAMP)
FLT(CLAMP)
be used for V over−voltage protection in the application,
CC
particularly for protecting external gate drivers. The
NCP1681 V
pin is rated for 30 V, however external
CC
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NCP1681
Table 6. NCP1681 FAULT HANDLING MATRIX
Fault
Set
Reset
Controller Action
− Begin soft stop sequence
Line SAG
(V
< V
SAG(blank)
) +
V
> V
LINE
BO(STOP)
LINE
LINE
BO(START)
t
expires
− PWM and SR drives disabled after soft stop
− PFCOK pulled low if StaticOVP or BUV
(OFF Mode)
− Cancels T
BUV
BO Fault
(V
LINE
< V
BO(blank)
) +
V
> V
− Resets Controller
− Polarity signal disabled
− PFCOK pulled low if StaticOVP (OFF Mode)
BO(STOP)
BO(START)
t
expires
Line Frequency1
Line Frequency2
t
< t
LINE(65)
or >
t
< t
< t
− SR drives disabled
LINE
LINE(45)
LINE(45)
LINE
LINE(65)
t
− Starts t
timer
LINEFREQ(DLY)
t
timer
N
= 4: t
<
− PWM Drive disables
− Polarity signal remains active
LINEFREQ(DLY)
DRV_EN
LINE(45)
expires
t
< t
for 4
LINE
LINE(65)
consecutive polarity toggles − PFCOK pulled low (OFF Mode)
UVP
V
FB
< V
V
FB
> V
+ V
UVP(HYS)
− PWM and SR drives disabled
− Polarity signal remains active
− PFCOK pulled low (OFF Mode)
UVP
UVP
Bulk Under−Voltage (BUV)
PFCOK high &
(V < V
T
BUV
expires
− PWM and SR drives disabled
− Polarity signal remains active
− PFCOK pulled low (OFF Mode)
)
BUV
FB
− Automatic restart after T
BUV
Soft OVP
V
> V
V
< V
< V
− Begin soft OVP sequence
− PWM Drive disables after soft OVP sequence
− Polarity & SR remain active
FB
FB
softOVP
FB
OVPrecover
Hard OVP
V
> V
V
FB
− PWM Drive disables immediately
− Polarity & SR remain active
hardOVP
OVPrecover
Over−Current Protection (OCP)
V
CS
> V
Cycle−by−Cycle,
No Reset Required
− PWM Drive terminates immediately
− Polarity & SR remain active
ILIMIT1(xL)
Abnormal/Short Circuit
Protection (SCP)
V
CS
> V
Cycle−by−Cycle,
No Reset Required
− PWM Drive terminates immediately
WDG(OS)
− Polarity & SR remain active
ILIMIT2
− New PWM delayed for T
N
N
> 4
CS(LIM2)
Master Reset
Master Reset
Master Reset
− PWM and SR drives disabled
− Polarity signal remains active
− PFCOK pulled low (OFF Mode)
CS(LIM2)
CS Short to GND
Open PGND
V
< V
− PWM Drive disables
− Polarity signal remains active
− PFCOK pulled low (OFF Mode)
CS
CS(TEST)
V
> V
− PWM Drive disables
− Polarity signal remains active
− PFCOK pulled low (OFF Mode)
PGND
CS(TEST)
CC(OFF)
V
CC
UVLO
V
CC
< V
V
CC
> V
− PWM and SR drives disabled
− Polarity signal disabled
− PFCOK pulled low (OFF Mode)
CC(ON)
Fault OTP
Fault OVP
TSD
t
expires
FLT(OTP)
V
> V
− PWM and SR drives disabled
− Polarity signal remains active
− PFCOK pulled low (OFF Mode)
OTP(BLANK)
FLT
t
FLT
FLT(REC)
+V
< (V
+
)
OTP(DLY)
V
> V
+
Master Reset
− PWM and SR drives disabled
− Polarity signal remains active
− PFCOK pulled low (OFF Mode)
FLT
FLT(OVP)
OVP(DLY)
t
)
T > T
J
T < (T
–
)
− PWM and SR drives disabled
− Polarity signal remains active
− PFCOK pulled low (OFF Mode)
SHDN
J
T
SHDN
SHDN(HYS)
www.onsemi.com
41
NCP1681
PACKAGE DIMENSIONS
SOIC20 NB LESS PIN 17 & 19
CASE 751EZ
ISSUE O
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