NCP1854FCCT1G [ONSEMI]
电池充电器，开关，2.5 A，带外部功率路径控制和 USB-OTG 升压稳压器;
| 型号： | NCP1854FCCT1G |
| 厂家： | 
ONSEMI |
| 描述： | 电池充电器，开关，2.5 A，带外部功率路径控制和 USB-OTG 升压稳压器 电池 开关 稳压器 |
| 文件： | 总29页 (文件大小：696K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1854
2.5 A Fully Integrated Li-Ion
Switching Battery Charger
with Power Path
Management and USB
On-The-Go Support
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The NCP1854 is a fully programmable single cell Lithium−ion
switching battery charger optimized for charging from a USB
compliant input supply and AC adaptor power source. The device
integrates a synchronous PWM controller, power MOSFETs, and the
entire charge cycle monitoring including safety features under
software supervision. An optional battery FET can be placed between
the system and the battery in order to isolate and supply the system.
The NCP1854 junction temperature is monitored during charge cycle
MARKING
DIAGRAM
1854
AYWW
G
25 BUMP
FLIP−CHIP
CASE 499BN
1854 = Specific Device Code
2
and both current and voltage can be modified accordingly through I C
A
Y
= Assembly Location
= Year
setting. The charger activity and status are reported through a
dedicated pin to the system. The input pin is protected against
overvoltages.
WW = Work Week
G = Pb−Free Package
The NCP1854 also provides USB OTG support by boosting the
battery voltage as well as providing overvoltage protected power
supply for USB transceiver.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
Features
• 2.5 A Buck Converter with Integrated Pass Devices
• Input Current Limiting to Comply to USB Standard
• Automatic Charge Current for AC Adaptor Charging
• High Accuracy Voltage and Current Regulation
• Input Overvoltage Protection up to +28 V
• Factory Mode
• 1000 mA Boosted Supply for USB OTG Peripherals
• Reverse Leakage Protection Prevents Battery Discharge
• Protected USB Transceiver Supply Switch
• Dynamic Power Path with Optional Battery FET
• Silicon Temperature Supervision for Optimized Charge Cycle
• Safety Timers
• Flag Output for Charge Status and Interrupts
2
• I C Control Bus up to 3.4 MHz
• Small Footprint 2.2 x 2.55 mm CSP Package
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• Smart Phone
• Handheld Devices
• Tablets
• PDAs
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
September, 2014 − Rev. 4
NCP1854/D
NCP1854
R
2.2 mH
SNS
L
X
33 mW
SW
IN
C
C
IN
OUT
C
BOOT
NCP1854
SYSTEM
22 mF
1 mF
10 nF
CBOOT
SENSP
SENSN
WEAK
FET
CAP
C
CAP
4.7 mF
VBUS
D+
CORE
TRANS
C
CORE
Q
(*)
BAT
D−
ID
GND
2.2 mF
BAT
+
C
TRS
0.1 mF
USB PHY
ILIM1
ILIM2
OTG
FLAG
SCL
SDA
AGND
SPM
FTRY
PGND
Figure 1. Typical Application Circuit
PIN CONNECTIONS
1
2
3
4
5
A
B
C
D
E
IN
IN
SPM
SDA
SCL
FLAG
FTRY
FET
CAP
SW
CAP
SW
OTG
AGND
SENSP
ILIM2
ILIM1
PGND
CBOOT
PGND
TRANS
SENSN
WEAK
CORE
BAT
(Top View)
Figure 2. Package Outline CSP
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2
NCP1854
Table 1. PIN FUNCTION DESCRIPTION
Pin
A1
A2
A3
A4
Name
IN
Type
POWER
Description
Battery Charger Input. These two pins must be decoupled by at least 1 mF capacitor and
connected together.
IN
POWER
SPM
SDA
DIGITAL INPUT
System Power Monitor input.
2
DIGITAL
BIDIRECTIONAL
I C data line
2
A5
B1
B2
B3
SCL
CAP
CAP
OTG
DIGITAL INPUT
POWER
I C clock line
CAP pin is the intermediate power supply input for all internal circuitry. Bypass with at
least 4.7 mF capacitor. Must be tied together.
POWER
DIGITAL INPUT
Enables OTG boost mode.
OTG = 0, the boost is powered OFF
OTG = 1 turns boost converter ON
2
B4
B5
ILIM2
FLAG
DIGITAL INPUT
Automatic charge current / Input current limiter level selection (can be defeated by I C).
OPEN DRAIN
OUTPUT
Charging state active low. This is an open drain pin that can either drive a status LED or
connect to interrupt pin of the system.
C1
C2
C3
SW
SW
ANALOG OUTPUT
ANALOG OUTPUT
ANALOG GROUND
Connection from power MOSFET to the Inductor.
These pins must be connected together.
AGND
Analog ground / reference. This pin should be connected to the ground plane and must
be connected together.
2
C4
C5
ILIM1
FTRY
DIGITAL INPUT
DIGITAL INPUT
Input current limiter level selection (can be defeated by I C).
Factory mode pin. Refer to section “Factory mode and no battery operation”. Internally
pulled up to CORE pin.
D1
D2
D3
PGND
PGND
SENSP
POWER GND
POWER GND
ANALOG INPUT
Power ground. These pins should be connected to the ground plane and must be
connected together.
Current sense input. This pin is the positive current sense input. It should be connected to
the R
resistor positive terminal.
SENSE
D4
SENSN
ANALOG INPUT
Current sense input. This pin is the negative current sense input. It should be connected
to the R resistor negative terminal. This pin is also voltage sense input of the volt-
SENSE
age regulation loop when the FET is present and open.
D5
E1
FET
ANALOG OUTPUT
ANALOG IN/OUT
Battery FET driver output. When not used, this pin must be directly tied to ground.
CBOOT
Floating Bootstrap connection. A 10 nF capacitor must be connected between CBOOT
and SW.
E2
TRANS
ANALOG OUTPUT
Output supply to USB transceiver. This pin can source a maximum of 50 mA to the
external USB PHY or any other IC that needs +5 V USB. This pin is Overvoltage
protected and will never be higher than 5.5 V. This pin should be bypassed by a 100 nF
ceramic capacitor.
E3
CORE
ANALOG OUTPUT
5 V reference voltage of the IC. This pin should be bypassed by a 2.2 mF capacitor.
No load must be connected to this pin.
E4
E5
WEAK
BAT
ANALOG OUTPUT
ANALOG INPUT
Weak battery charging current source input.
Battery connection
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NCP1854
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
IN (Note 1)
V
IN
−0.3 to +28
−0.3 to +28
−0.3 to +24
−0.3 to +7.0
−0.3 to +7.0
−0.3 to +7.0
CAP (Note 1)
V
CAP
V
Power balls: SW (Note 1)
IN pin with respect to VCAP
CBOOT with respect to SW
V
PWR
V
V
V
IN_CAP
CBOOT_CAP
V
V
Sense/Control balls: SENSP, SENSN, VBAT, FET, TRANS, CORE,
FLAG, INTB and WEAK. (Note 1)
V
CTRL
V
Digital Input: SCL, SDA, SPM, OTG, ILIM, FTRY (Note 1)
Input Voltage
Input Current
V
−0.3 to +7.0 V
20
V
DG
I
mA
DG
Storage Temperature Range
T
−65 to +150
−40 to +TSD
Level 1
°C
°C
STG
Maximum Junction Temperature (Note 4)
Moisture Sensitivity (Note 5)
T
J
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. OPERATING CONDITIONS
Symbol
Parameter
Operational Power Supply
Digital input voltage level
Ambient Temperature Range
FLAG sink current
Conditions
Min
3.6
0
Typ
Max
Unit
V
V
IN
V
INOV
V
DG
5.5
V
T
A
−40
25
+85
10
°C
I
mA
mF
SINK
C
Decoupling input capacitor
Decoupling Switcher capacitor
Decoupling core supply capacitor
Decoupling system capacitor
Switcher Inductor
1
IN
C
4.7
2.2
22
2.2
33
70
25
mF
CAP
C
mF
CORE
C
mF
OUT
L
X
mH
mW
°C/W
°C
R
Current sense resistor
SNS
R
Thermal Resistance Junction to Air
Junction Temperature Range
(Notes 4 and 6)
q
JA
J
T
−40
+125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. With Respect to PGND. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) 200 V per JEDEC standard: JESD22−A115 for all pins.
3. Latch up Current Maximum Rating: 100 mA or per 10 mA JEDEC standard: JESD78 class II.
4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation. See Electrical Characteristics.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
6. The R
is dependent on the PCB heat dissipation. Board used to drive this data was a 2s2p JEDEC PCB standard.
q
JA
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NCP1854
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T between −40°C to +85°C and T up to +125°C for V between 3.9 V to 7 V (Unless otherwise noted).
A
J
IN
Typical values are referenced to T = + 25°C and V = 5 V (Unless otherwise noted).
A
IN
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
INPUT VOLTAGE
V
Valid input detection threshold
USB under voltage detection
USB over voltage detection
Valid input high threshold
V
rising
falling
falling
3.8
3.55
4.3
50
3.85
3.6
3.9
3.65
4.5
V
V
INDET
IN
IN
IN
V
V
V
V
4.4
V
BUSUV
Hysteresis
rising
100
5.65
75
150
5.75
125
7.3
mV
V
V
IN
5.55
25
BUSOV
Hysteresis
rising
mV
V
V
V
IN
7.1
200
7.2
INOV
Hysteresis
300
400
mV
INPUT CURRENT LIMITING
Input current limit
I
V
IN
= 5 V
Maximum Current range
100
70
2000
100
0
mA
mA
%
INLIM
Default value
85
Accuracy
−15
from 500 mA to 2000 mA
2
I C Programmable granularity
(From 500 mA to 2000 mA)
100
mA
INPUT SUPPLY CURRENT
VBUS supply current
I
No load, Charger active state
Charger not active
15
mA
Q_SW
I
700
mA
OFF
CHARGER DETECTION
V
Charger detection threshold
voltage
V
– V
, V rising
50
15
110
30
180
50
mV
mV
CHGDET
IN
SENSN
, V falling
SENSN IN
IN
V
IN
– V
REVERSE BLOCKING CURRENT
leakage current
I
V
BAT
Battery leakage, V
= 4.2 V, V = 0 V,
5
mA
LEAK
BAT
IN
SDA = SCL = 0 V
R
Input RBFET On resistance (Q1)
Charger active state, Measured between
−
45
75
mW
RBFET
IN and CAP, V = 5 V
IN
BATTERY AND SYSTEM VOLTAGE REGULATION
2
V
CHG
Output voltage range
Programmable by I C
3.3
4.5
V
V
Default value
3.6
25
Voltage regulation accuracy
Constant voltage mode, T = 25°C
−0.5
−1
0.5
1
%
A
%
2
I C Programmable granularity
mV
BATTERY VOLTAGE THRESHOLD
V
Safe charge threshold voltage
V
V
rising
rising
2.1
2.15
2.8
2.2
V
V
SAFE
BAT
V
Conditioning charge threshold
voltage
2.75
2.85
PRE
BAT
V
End of weak charge threshold
voltage
V
BAT
rising
Voltage range
3.1
−2
3.6
2
V
FET
Default value
Accuracy
3.4
%
mV
%
2
I C Programmable granularity
100
97
V
Recharge threshold voltage
Relative to V setting register
RECHG
CHG
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NCP1854
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T between −40°C to +85°C and T up to +125°C for V between 3.9 V to 7 V (Unless otherwise noted).
A
J
IN
Typical values are referenced to T = + 25°C and V = 5 V (Unless otherwise noted).
A
IN
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BATTERY VOLTAGE THRESHOLD
Overvoltage threshold voltage
V
V
BAT
rising, relative to V setting register, measured
CHG
115
5
%
V
BUCKOV
on SENSN or SENSP, Q
close or no Q
BAT
BAT
Q
open.
BAT
CHARGE CURRENT REGULATION
2
I
Charge current range
Programmable by I C
450
950
−50
2500
1050
50
mA
mA
mA
mA
mA
mA
mA
CHG
Default value
1000
Charge current accuracy
2
I C Programmable granularity
Pre−charge current
100
450
40
I
V
BAT
< V
400
30
500
50
PRE
PRE
I
Safe charge current
V < V
BAT SAFE
SAFE
I
Weak battery charge current
BATFET present,
IWEAK[1:0] = 01
IWEAK[1:0] = 10
IWEAK[1:0] = 11
80
100
200
300
120
220
330
WEAK
V
< V
FET
<
SAFE
BAT
180
270
V
CHARGE TERMINATION
Charge current termination
I
V
BAT
≥ V
RECHG
Current range
Default value
100
−25
275
25
mA
EOC
150
25
Accuracy, I
< 200 mA
EOC
2
I C Programmable granularity
FLAG
V
FLAG output low voltage
Off−state leakage
I
= 10 mA
0.5
1
V
FOL
FLAG
I
V
= 5 V
mA
ms
FLEAK
FLAG
T
Interrupt request pulse duration
Single event
150
1.2
200
500
250
FLGON
DIGITAL INPUT (V
)
DG
V
High−level input voltage
Low−level input voltage
Pull up resistor (FRTY pin)
Pull down resistor (others pin)
Input current
V
V
IH
V
0.4
0.5
IL
R
kW
DG
I
V
= 0 V
−0.5
mA
DLEAK
DG
2
I C
2
V
CAP pin supply voltage
High level at SCL/SCA line
SCL, SDA low input voltage
SCL, SDA high input voltage
I C registers available
2.5
1.7
V
V
V
V
SYSUV
2
V
5
I CINT
2
V
0.4
I CIL
2
V
0.8*
I CIH
2
V
I CINT
2
V
SCL, SDA low output voltage
I
= 3 mA
0.3
3.4
V
I COL
SINK
2
F
SCL
I C clock frequency
MHz
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NCP1854
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T between −40°C to +85°C and T up to +125°C for V between 3.9 V to 7 V (Unless otherwise noted).
A
J
IN
Typical values are referenced to T = + 25°C and V = 5 V (Unless otherwise noted).
A
IN
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
JUNCTION THERMAL MANAGEMENT
T
Thermal shutdown
Rising
Falling
125
140
115
−7
150
°C
°C
°C
°C
°C
SD
T
T
Hot temp threshold 2
Hot temp threshold 1
Thermal warning
Relative to T
H2
SD
Relative to T
−11
−15
H1
SD
SD
T
Relative to T
WARN
BUCK CONVERTER
F
Switching Frequency
Switching Frequency Accuracy
Max Duty Cycle
−
1.5
−
MHz
%
SWCHG
−10
+10
T
Average
99.5
3
%
DTYC
I
Maximum peak inductor current
Low side Buck MOSFET
A
PKMAX
R
Measured between PGND and SW, V = 5 V
−
−
70
110
85
mW
ONLS
IN
R
(Q3)
DSON
R
High side Buck MOSFET
(Q2)
Measured between CAP and SW, V = 5 V
55
5
mW
ONHS
IN
R
DSON
PROTECTED TRANSCEIVER SUPPLY
V
Voltage on TRANS pin
TRANS current capability
Short circuit protection
V
IN
≥ 5 V
5.5
V
TRANS
TRMAX
TROCP
I
I
50
mA
mA
150
TIMING
T
Watchdog timer
USB timer
32
2048
3
s
s
h
WD
T
USB
T
CHG1
Charge timer
Safe−charge or pre−charge or weak−safe or
weak−charge state.
T
CHG2
CC state
1
2
h
h
CV state
TIMER_SEL = 0 (default)
TIMER_SEL = 1
1
h
T
Wake−up timer
64
32
127
s
WU
T
Charger state timer,
Minimum transition time from
states to states
From Weak−Charge to Full−Charge State
s
ST
From wait−state to safe−charge and from
weak−wait to weak−safe
ms
All others state
16
15
ms
ms
ms
ms
T
Deglitch time for end of charge
voltage detection
V
BAT
rising
falling
rising
VRCHR
V
BAT
127
15
T
Deglitch time for input voltage
detection
V
IN
INDET
T
Deglitch time for signal
Rising and falling edge
Rising and falling edge
15
1
ms
ms
DGS1
crossing I
, V
thresholds
, V
,
EOC
PRE
SAFE
V
CHGDET
T
DGS2
Deglitch time for signal
crossing V , V
,
FET BUSUV
V
thresholds
BUSOV
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NCP1854
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T between −40°C to +85°C and T up to +125°C for V between 3.9 V to 7 V (Unless otherwise noted).
A
J
IN
Typical values are referenced to T = + 25°C and V = 5 V (Unless otherwise noted).
A
IN
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BOOST CONVERTER AND OTG MODE
V
Boost minimum input
operating range
Boost start−up
Boost running
3.1
2.9
4.4
3.2
3
3.3
3.1
4.6
V
V
V
IBSTL
V
IBSTH
Boost maximum input
operating range
4.5
V
Boost Output Voltage
DC value measured on CAP pin, no load
5.00
−3
5.1
5.15
3
V
OBST
V
Boost Output Voltage accuracy
Measured on CAP pin Including line and load
regulation
%
OBSTAC
I
Output current capability
Configured Mode
1000
150
mA
mA
MHz
A
BSTMX
Un−configured Mode
F
Switching Frequency
Maximum peak inductor current
Boost overload
1.35
1.5
3
1.65
SWBST
I
BPKM
V
V
Voltage on CAP pin, falling
4.5
4.3
4.6
4.4
4.65
4.5
32
V
OBSTOL1
OBSTOL2
Un−configured Mode, falling, Voltage on IN pin
T
Boost start−up time
From OTG enable to VIN > V
ms
OBSTOL
OBSTOL
I
Boost Pre−charge current
Un−configured Mode, Measured on IN pin
350
mA
BSTPRE
RLOAD = 29 W, CLOAD = 10 mF
Configured Mode, Measured on IN pin
RLOAD = 5.1 W, CLOAD = 10 mF
1.1
4
A
T
Boost Rise time
Configured Mode,
RLOAD = ∞,
0.3
ms
BSTPRE
Measured on
VIN, VIN rising
(see Figure 3)
CLOAD = 1 mF
RLOAD = 5.1 W,
CLOAD = 10 mF
V
Overvoltage protection
V
rising
5.55
25
5.65
75
5.75
125
V
OBSTOV
IN
Hysteresis
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
VIN
T
BSTPRE
RLOAD
CLOAD
V
IN
90%
10%
Figure 3. Boost Test Schematic
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NCP1854
BLOCK DIAGRAM
μF
4.7
CCAP
CAP
VCAP
IN
VBUS
D+
D−
GND
CBOOT
+
CIN
μF
IINREG
Q1
Amp
Charge
Pump
−
IINLIM
VCORE
1
CBOOT
10nF
Drv
Q2
VCAP
+
Drv
−
VINOVLO
IINREG
+
+
+
5V
reference
VREG
VTJ
SW
Current,
Voltage,
and Clock
Reference
IBUCKREG
VCORE
CCORE
CORE
VBUCKREG
Q3
VCORE
LX
−
μF
2.2
Drv
μF
2.2
TRANS
CTRS
PGND
+
IEOC
VBAT
VTJ
−
IBAT
SENSP
+
RSNS
μF
0.1
+
−
+
−
−
TSD
IBAT
ICHG
+
Amp
IBUCKREG
VBATOV
Amp
SENSN
WEAK
+
−
33mW
USB PHY
−
+
−
TH2
TH1
VRECHG
+
−
+
−
VCORE
VFET
+
−
QBAT(*)
−
+
VCHG
+
−
TWARN
VBUCKREG
Amp
VPRE
ILIM2
+
−
VSAFE
ILIM1
OTG
BAT
FET
I2C &
DIGITAL
CONTROLER
BATFET detection
& Drive
VIN
VINDET
VCORE
+
−
FTRY
SPM
+
VBUSUV
−
+
+
VBUSOV
−
AGND
+
−
VINOV
FLAG
VBAT
+
−
+
SCL
SDA
VCHGDET
Figure 4. Block Diagram
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NCP1854
CHARGING PROCESS
CHARGER ACTIVE:
WEAK CHARGE MODE
CHARGER NOT ACTIVE MODE
WEAK WAIT
V
< V
or
BAT
SAFE
− BUCK: ON
− IWEAK: OFF
− ISAFE: OFF
− FLAG: LOW
− QFET: OFF
V
> V
SYSUV
CAP
FTRY_MOD
−V < V
or
OFF
IN
INDET
− Charger OFF IQ < IOFF
− I2C available
−V − V
< V
IN
BAT CHGDET
not
FTRY_MOD
FTRY_MOD
ANY STATE
−V > V
and
WEAK SAFE
IN
INDET
−V − V
IN
> V
CHGDET
− BUCK: ON
BAT
− IWEAK: OFF
− ISAFE: ON
− FLAG: LOW
− QFET: OFF
Batfet present
and V < V
BAT
FET
and SPM = 0
REG_RST = 1
CONFIG
and CHR_EN = 1
− Power−up
− NTC and BATFET detection
− Q1: ON
V
I
> V
and
BAT
SAFE
≥ 500 mA
INLIM
WEAK CHARGE
−V > V
or
IN
INOV
− BUCK: ON
− IWEAK: ON
− ISAFE: OFF
− FLAG: LOW
− QFET: OFF
−V
BAT
> V
or
BUCKOV
Power−up and
detection done
−Timeout or
−Power fail or
−T > T or
J
SD
−CHR_EN = 0
Fault removed
WAIT
FAULT
and CHR_EN = 1
− BUCK: OFF
− IWEAK: OFF
− ISAFE: OFF
− FLAG: LOW
− QFET: ON
− BUCK: OFF
− IWEAK: OFF
− ISAFE: OFF
− FLAG: HIGH
− QFET: ON
−Timeout
−T > T or
J
SD
−V > V
or
INOV
IN
−Timeout
−T > T or
V
> V
FET
−V
BAT
> V
or
BAT
BATOV
J
SD
−CHR_EN = 0
−V > V or
INOV
IN
−V
BAT
> V
BUCKOV
or
FULL CHARGE
−CHR_EN = 0
− BUCK: ON
− IWEAK: OFF
− ISAFE: OFF
− FLAG: LOW
− QFET: ON
−T > T or
J
SD
−V > V
or
IN
INOV
−V
BAT
< V
RECHG
−CHR_EN = 0
END OF CHARGE
− BUCK: OFF*
− IWEAK: OFF
− ISAFE: OFF
− FLAG: HIGH
− QFET: ON*
V
> V
PRE
BAT
−V
−I
> V
and
BAT
RECHG
< I
EOC
V
< V
PRE
BAT
BAT
PRE CHARGE
−V
SENSN
< V
and
RECHG
−V
> V
< I
EOC
and
BAT
RECHG
− BUCK: ON (precharge)
− IWEAK: OFF
− ISAFE: OFF
−pwr_path = 1
−I
BAT
− FLAG: LOW
− QFET: ON
DPP
− BUCK: ON
−V
BAT
< V
RECHG
− IWEAK: OFF
− ISAFE: OFF
− FLAG: HIGH
− QFET: ON
V
> V
SAFE
BAT
V
< V
SAFE
BAT
Timeout
SAFE CHARGE
− BUCK: OFF
− IWEAK: OFF
− ISAFE: ON
− FLAG: LOW
− QFET: ON
(V
> V
FET
or SPM = 1 or no batfet) and CHR_EN = 1
BAT
CHARGER ACTIVE:
FULL CHARGE MODE
(*) see Power Path Management section
Figure 5. Detailed Charging Process
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NCP1854
TYPICAL CHARACTERISTICS
Figure 6. VBUS Insertion
Figure 7. Charger Mode Efficiency
Figure 9. Dynamic Power Path
Figure 11. Over Voltage Protection
Figure 8. Automatic Charge Current
Figure 10. Boost Mode: Power−Up
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NCP1854
CHARGE MODE OPERATION
2
Overview
The NCP1854 is fully programmable through I C
interface (see Registers Map section for more details). All
registers can be programmed by the system controller at any
The NCP1854 is a fully programmable single cell
Lithium−ion switching battery charger optimized for
charging from a USB compliant input supply. The device
time during the charge process. The charge current (I
),
CHG
integrates
a synchronous PWM controller; power
charge voltage (V
), and input current (I
) are
INLIM
CHG
MOSFETs, and monitoring the entire charge cycle including
safety features under software supervision. An optional
battery FET can be placed between the system and the
battery in order to isolate and supply the system in case of
weak battery. The NCP1854 junction temperature and
battery temperature are monitored during charge cycle and
current and voltage can be modified accordingly through
controlled by a dynamic voltage and current scaling for
disturbance reduction. Is typically 10 ms for each step.
NCP1854 also provides USB OTG support by boosting
the battery voltage as well as an over voltage protected
power supply for USB transceiver.
Charge Profile
2
In case of application without Q , the NCP1854
FET
I C setting. The charger activity and status are reported
provides 4 main charging phases as described below.
Unexpected behaviour or limitations that can modify the
charge sequence are described further (see Charging Process
section).
through a dedicated pin to the system. The input pin is
protected against overvoltages.
V
BAT
I
BAT
V
CHG
V
RECHG
I
CHG
I
PRE
V
V
PRE
I
EOC
I
SAFE
SAFE
Safe
Charge
Pre
Charge
Constant
Current
Constant
Voltage
End of
Charge
Figure 12. Typical Charging Profile of NCP1854
Safe Charge:
current. The battery stays in preconditioning until the V
BAT
With a disconnected battery or completely empty battery,
voltage is lower than V
threshold.
PRE
the charge process is in safe charge state, the charge current
Constant Current (full charge):
In the constant current phase (full charge state), the
DC−DC convertor is enabled and an I current is
delivered to the load. As battery voltage could be sufficient,
the system may be awake and sink an amount of current. In
this case the charger output load is composed of the battery
is set to I
in order to charge up the system’s capacitors
SAFE
or the battery. When the battery voltage reaches V
threshold, the battery enters in pre−conditioning.
SAFE
CHG
Pre Conditioning (pre−charge):
In preconditioning (pre charge state), the DC−DC
convertor is enabled and an I current is delivered to the
and the system. Thus I
current delivered by the
PRE
CHG
battery. This current is much lower than the full charge
NCP1854 is shared between the battery and the system:
= I + I
I
.
BAT
CHG
SYS
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12
NCP1854
System
awake
V
BAT
V
CHG
V
RECHG
I
CHG
V
BAT
I
BAT
I
BAT
I
PRE
I
SYS
V
V
PRE
I
EOC
I
SAFE
SAFE
Safe
Charge
Pre
Charge
Constant
Current
Constant
Voltage
End of
Charge
Figure 13. Typical Charging Profile of NCP1854 with System Awake
I
current is programmable using I2C interface
In order to prevent battery discharge and overvoltage
protection, Q1 (reverse voltage protection) and Q2 (high
side N−MOSFET of the DC−DC converter) are mounted in
a back−to−back common drain structure while Q3 is the low
side N MOSFET of the DC−DC converter. Q2 gate driver
circuitry required an external bootstrap capacitor connected
between CBOOT pin and SW pin.
CHG
(register IBAT_SET − bits ICHG[3:0] and ICHG_HIGH).
Constant Voltage (full charge):
The constant voltage phase is also a part of the full charge
state. When the battery voltage is close to its maximum
(V
), the charge circuit will transition from a constant
CHG
current to a constant voltage mode where the charge current
will slowly decrease (taper off). The battery is now voltage
controlled. V
An internal current sense monitors and limits the
maximum allowable current in the inductor to I
value.
PEAK
voltage is programmable using I2C
CHG
interface (register VBAT_SET− bits CTRL_VBAT[5:0]).
Charger Detection, Start−up Sequence and System Off
The start−up sequence begins upon an adaptor valid
End of Charge:
voltage plug in detection: V > V
and V − V
>
The charge is completed (end of charge state) when the
IN
INDET
IN
BAT
V
(off state).
battery is above the V
threshold and the charge current
CHGDET
RECHG
Then, the internal circuitry is powered up and the presence
below the I
level. The battery is considered fully charged
EOC
of BATFET is reported (register STATUS – bit BATFET).
When the power−up sequence is done, the charge cycle is
automatically launched. At any time and any state, the user
can hold the charge process and transit to fault state by
setting CHG_EN to ‘0’ (register CTRL1) in the I C register.
The I2C registers are accessible without valid voltage on
and the battery charge is halted. Charging is resumed in the
constant current phase when the battery voltage drops below
the V
threshold. I
current is programmable using
RECHG
EOC
I2C interface (register IBAT_SET− bits IEOC[2:0]).
2
Power Stage Control
NCP1854 provides
a fully−integrated 1.5 MHz
V
IN
if V
> V
(i.e. if V is higher than V
BAT SYSUV
CAP
SYSUV
step−down DC−DC converter for high efficiency. For an
optimized charge control, 3 feedback signals control the
PWM duty cycle. These 3 loops are: maximum input current
+ voltage drop across Q2 body diode).
At any time, the user can reset all register stacks (register
CTRL1 – bit REG_RST).
(I
), maximum charge current (I
INLIM
) and, maximum
CHG
Weak Battery Support
charge voltage (V
). The switcher is regulated by the first
CHG
An optional battery FET (Q ) can be placed between
BAT
loop that reaches its corresponding threshold. Typically
during charge current phase (V < V < V ), the
the application and the battery. In this way, the battery can
be isolated from the application and so−called weak battery
operation is supported.
PRE
BAT
RECHG
measured input current and output voltage are below the
programmed limit and asking for more power. But in the
same time, the measured output current is at the
programmed limit and thus regulates the DC−DC converter.
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13
NCP1854
Typically, when the battery is fully discharged, also
Weak wait
referred to as weak battery, its voltage is not sufficient to
supply the application. When applying a charger, the battery
first has to be pre−charged to a certain level before operation.
During this time; the application is supplied by the DC−DC
converter while integrated current sources will pre−charge
the battery to the sufficient level before reconnecting.
Weak wait state is entered from wait state (see Charging
process section) in case of BATFET present, battery voltage
lower than V
and host system in shutdown mode (SPM
FET
= 0). The DCDC converter from VIN to SW is enabled and
set to V while the battery FET Q is opened. The
CHG
BAT
system is now powered by the DC−DC. The internal current
source to the battery is disabled.
The pin FET can drive a PMOS switch (Q ) connected
BAT
between BAT and WEAK pin. It is controlled by the charger
state machine (Charging process section). The basic
behaviour of the FET pin is that it is always low. Thus the
PMOS is conducting, except when the battery is too much
discharged at the time a charger is inserted under the
condition where the application is not powered on. The FET
Weak safe
The voltage at V , is below the V
weak safe state, the battery is charged with a linear current
source at a current of I . The DC−DC converter is
enabled and set to V
opened. In case the ILIM pin is not made high or the input
current limit defeated by I C before timer expiration, the
state is left for the safe charge state after a certain amount of
time (see Wake up Timer section). Otherwise, the state
machine will transition to the weak charge state once the
threshold. In
BAT
SAFE
SAFE
while the battery FET Q
is
CHG
BAT
pin is always low for BAT above the V
threshold. Some
2
FET
exceptions exist which are described in the Charging process
and Power Path Management section. The V threshold
FET
is programmable (register MISC_SET – bit CTRL_VFET).
Batfet detection
battery is above V
.
SAFE
The presence of a PMOS (Q ) at the FET pin is verified
BAT
Weak charge
by the charging process during its config state. To distinguish
the two types of applications, in case of no battery FET the
pin FET is to be tied to ground. In the config state an attempt
will be made to raise the FET pin voltage slightly up to a
detection threshold. If this is successful it is considered that
a battery FET is present. The batfet detection is completed
for the whole charge cycle and will be done again upon
The voltage at V , is above the V
DC−DC converter is enabled and set to V
is initially charged at a charge current of I
threshold. The
BAT
SAFE
. The battery
CHG
supplied by
WEAK
a linear current source from WEAK pin (i.e. DC−DC
converter) to BAT pin. I value is programmable
WEAK
(register MISC_SET bits IWEAK). The weak charge timer
(see Wake up Timer section) is no longer running. When the
unplug condition (V
< V
or V − V
<
BAT
INDET
IN
BAT
battery is above the V
threshold (programmable), the
FET
V ) or register reset (register CTRL1– bit REG_RST).
CHGDET
state machine transitions to the full charge state thus
BATFET Q
is closed.
BAT
I
V
V
OUT
BAT
CHG
I
CHG
V
RECHG
V
BAT
V
SYS
I
BAT
I
V
WEAK
FET
I
BAT
I
SYS
V
BAT
I
EOC
I
SAFE
V
SAFE
Weak
Wait
Weak
Safe
Weak
Charge
Constant
Current
Constant
Voltage
End of
Charge
Figure 14. Weak Charge Profile
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NCP1854
Weak Charge Exit
Charge Timer
In some application cases, the system may not be able to
start in weak charge states due to current capability
limitation or/and configuration of the system. If so, in order
to avoid unexpected “drop and retry” sequence of the buck
output, the charge state machine allows only 3 system
power−up sequences based on SPM pin level: If SPM pin
level is toggled 3 times during weak charge states, the
system goes directly to safe charge state and a full charge
mode sequence is initiated (“Power fail” condition in
Charging process section).
A charge timer T
is running that will make that the
CHG
overall charge to the battery will not exceed a certain amount
of energy. The charge timer is running during charger active
states and halted during charger not active states (see
Charging process section). The timer can also be cleared any
2
time through I C (register CTRL1 – bit TCHG_RST). The
state machine transitions to fault state when the timer
expires. This timer can be disabled (Register CTRL2 bit
CHGTO_DIS).
USB Timer
A USB charge timer T
states while halted in the charger non active states. The timer
keeps running as long as the lowest input current limit
remains selected either by ILIM pin or I C (register I_SET
– bit IINLIM and IINLIM_EN and register IINLIM_SET
bits IINLIM_TA). This will avoid exceeding the maximum
allowed USB charge time for un−configured connections.
When expiring, the state machine will transition to fault
state. The timer is cleared in the off state or by I C command
(register CTRL1 – bit TCHG_RST).
is running in the charger active
USB
Power Path Management
Power path management can be supported when a battery
FET (Q
) is placed between the application and the
BAT
2
battery. When the battery is fully charged (end of charge
state), power path management disconnects the battery from
the system by opening Q , while the DC−DC remains
BAT
active. This will keep the battery in a fully charged state with
the system being supplied from the DC−DC. If a load
transient appears exceeding the DC−DC output current and
2
thus causing V
to fall below V
, the FET Q
RECHG BAT
SENSEN
Wake up Timer
is instantaneously closed to reconnect the battery in order to
provide enough current to the application. The FET Q
Before entering weak charge state, NCP1854 verifies if
the input current available is enough to supply both the
application and the charge of the battery. A wake−up timer
BAT
remains closed until the end of charge state conditions are
reached again. The power path management function is
2
T
verifies if ILIM pin is raised fast enough or application
enabled through the I C interface (register CRTL2 bit
WU
powered up (by monitoring register I_SET – bit IINLIM and
IINLIM_EN and register IINLIM_SET bits IINLIM_TA)
after a USB attachment. The wake up timer is running in
weak wait state and weak safe state and clears when the input
current limit is higher than 100 mA.
PWR_PATH=1).
Safety Timer Description
The safety timer ensures proper and safe operation during
charge process. The set and reset condition of the different
safety timer (Watchdog timer, Charge timer, Wakeup timer
and USB timer) are detailed below. When a timer expires
(condition “timeout” in Charging process section), the
charge process is halted.
Input Current Limitation
In order to be USB specification compliant, the input
current at V is monitored and could be limited to the
IN
I
threshold. The input current limit threshold is
INLIM
Watchdog Timer
selectable through the ILIMx pin. When low, the one unit
Watchdog timer ensures software remains alive once it
has programmed the IC. The watchdog timer is no longer
USB current is selected (I ≤ 100 mA), where when made
IN
high 5 units are selected (I ≤ 500 mA). In addition, this
2
2
IN
running since I C interface is not available. Upon an I C
write, automatically a watchdog timer T is started. The
2
current limit can be programmed through I C (register
WD
MISC_SET bits IINLIM and register IINLIM_SET bits
IINLIM_TA) therefore defeating the state of the ILIMx pin.
In case of non−limited input source, current limit can be
disabled (register CTRL2 bit IINLIM_EN). The current
limit is also disabled in case the input voltage exceeds the
watchdog timer is running during charger active states and
fault state. Another I C write will reset the watchdog timer.
When the watchdog times out, the state machine reverts to
fault state and reported through I C interface (register
CHINT2– bit WDTO). Also used to time out the fault state.
This timer can be disabled (Register CTRL2 bit
WDTO_DIS).
2
2
V
threshold.
BUSOV
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NCP1854
I
V
BAT
BAT
V
V
CHG
RECHG
I
CHG
I
PRE
V
V
PRE
I
EOC
I
SAFE
SAFE
Safe
Charge
Pre
Charge
Constant
Current
Constant
Voltage
End of
Charge
Figure 15. Typical Charging Profile of NCP1854 with Input Current Limit
Input Voltage Based Automatic Charge Current
If the input power source capability is unknown,
automatic charge current will automatically increase the
Between
T
and
T
threshold, a junction
SD
WARN
temperature management option is available by setting 1 to
TJ_WARN_OPT bit (register CONTROL). In this case, if
charge current step by step until the V drops to V
.
the die temperature hits T
threshold, an interrupt is
IN
BUSUV
M1
Upon V
being triggered, the charge current I
is
generated again but NCP1854 will also reduce the charge
current I by two steps or 200 mA. This should in most
BUSUV
CHG
immediately reduced by 1 step and stays constant until V
IN
CHG
drops again to V
I C register value (register IBAT_SET, bits ICHG). This
unique feature is enabled when the pins ILIM1 = 0 and
ILIM2 = 1 or through I C register (register CRTL2 bit
AICL_EN).
. The ICHG current is clamped to the
cases stabilize the die temperature because the power
dissipation will be reduced by approximately 50 mW. If the
BUSUV
2
die temperature increases further to hit T , an interrupt is
M2
2
generated and the charge current is reduced to its lowest
level or 400 mA. The initial charge current will be
re−established when the die temperature falls below the
ILIM1
ILIM2
Input Current Limit
100 mA
T
again.
WARN
0
0
1
1
0
1
0
1
If bit TJ_WARN_OPT = 0 (register CTRL1), the charge
current is not automatically reduced, no current changes
actions are taken by the chip until T
Automatic Charge Current
500 mA
.
SD
Regulated Power Supply (Trans pin)
900 mA
NCP1854 has embedded a linear voltage regulator
(V
) able to supply up to I
to external loads.
TRANS
TRMAX
Junction Temperature Management
During the charge process, NCP1854 monitors the
temperature of the chip. If this temperature increases to
This output can be used to power USB transceiver. Trans pin
is enabled if a V valid is connected on input pin
BUS
2
(V
< V < V
) and can be disabled through I C
BUSUV
IN
BUSOV
T
, an interrupt request (described in section Charge
WARN
(bit TRANS_EN_REG register CTRL2).
status reporting) is generated and bit TWARN_SNS is set to
‘1’ (register TEMP_SENSE). Knowing this, the user is free
to halt the charge (register CTRL − bit CHG_EN) or reduce
the charge current (register I_SET − bits ICHG). When chip
temperature reaches T
automatically halted.
value, the charge process is
SD
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NCP1854
Charge Status Reporting
Sense and Status Registers
At any time the system processor can know the status of
all the comparators inside the chip by reading VIN_SNS,
VBAT_SNS, and TEMP_SNS registers (read only). These
bits give to the system controller the real time values of all
the corresponding comparators outputs (see BLOCK
DIAGRAM).
FLAG pin
FLAG pin is to used to report charge status to the system
processor and for interruption request.
During charger active states and wait state, the pin FLAG
is low in order to indicate that the charge of the battery is in
progress. When charge is completed or disabled or a fault
occurs, the FLAG pin is high as the charge is halted.
Battery Removal
STATUS and CONTROL Registers
During normal charge operation the battery may bounce
or be removed. The state transition of the state machine only
occurs upon deglitched signals which allow bridging any
battery bounce. True battery removal will last longer than
the debounce times. The NCP1854 handles battery removal
if a BATFET is present and power path option is enable
(register CRTL2 bit PWR_PATH=1)
If the battery removal appears during the charge cycle, the
NCP1854 will behave normally and charge up very quickly
the equivalent capacitor seen on VSENSN and/or VBAT
(from tens to hundreds of milliseconds). The state machine
will automatically end up in end of charge / dpp state while
the DCDC is still enabled and the system still supplied.
The status register contains the current charge state,
BATFET connection as well as fault and status interrupt
(bits FAULTINT and STATINT in register STATUS). The
charge state (bits STATE in register STATUS) is updated on
the fly and corresponds to the charging state described in
Charging process section. An interruption (see description
below) is generated upon a state change. In the config state,
hardware detection is performed on BAFTET pins. From
wait state, their statuses are available (bit BATFET in
register STATUS). STATINT bit is set to 1 if an interruption
appears on STAT_INT register (see description below).
FAULTINT bit is set to 1 if an interruption appears on
registers CH1_INT, CH1_INT or BST_INT. Thanks to this
register, the system controller knows the chip status with
Factory Mode and No Battery Operation
2
During factory testing no battery is present in the
application and a supply could be applied through the
bottom connector to power the application. The state
machine will support this mode of operation if a BATFET is
present and if the application processor can configure
NCP1854 within 32 seconds. In factory mode condition, the
NCP1854 is locked in weak wait state (DCDC enable and no
weak charge). The factory mode is enabled through the
only one I C read operation. If a fault appears or a status
change (STATINT bits and FAULTINT), the controller can
read corresponding registers for more details.
Interruption
Upon a state or status change, the system controller is
informed by sensing FLAG pin. A T
pulse is
FLAGON
generated on this pin in order to signalize an event. The level
of this pulse depends on the state of the charger (see
Charging process section):
• When charger is in charger active states and wait state
the FLAG is low and consequently the pulse level on
FLAG pin is high.
2
FTRY pin or through I C (Register CTRL1 Bit
FCTRY_MOD_REG) according to the following logic
table.
FTRY_MODE
(Factory mode)
FTRY Pin
FCTRY_MOD_REG
• In the other states, the pulse level is low as the FLAG
stable level is high.
0
0
1
1
0
1
0
1
Enable
Charge state transition even and all bits of register
STAT_INT, CH1_INT, CH2_INT, BST_INT generate an
interrupt request on FLAG pin and can be masked with the
corresponding mask bits in registers STAT_MSK,
CH1_MSK, CH2_MSK and BST_MSK. All interrupt
signals can be masked with the global interrupt mask bit (bit
INT_MASK register CTRL1). All these bits are read to
clear. The register map (see REGISTERS MAP section)
indicated the active transition of each bits (column “TYPE”
in see REGISTERS MAP section).
Disable
Disable
Enable
Remark: The charge current loop (ICHG) and input current
loop are disabled in factory mode so full power is available
for the system.
2
Through I C the device is entirely programmable so the
controller can configure appropriate current and voltage
threshold for handle factory testing.
If more than 1 interrupt appears, only 1 pulse is generated
while interrupt registers (STAT_INT, CH1_INT, CH2_INT,
BST_INT) will not fully clear.
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NCP1854
BOOST MODE OPERATION
Boost Over−Load Indication (Un−configured mode)
In un−configured mode, the load on IN can exceed
The DC−DC Converter can also be operated in a Boost
mode where the application voltage is stepped up to the input
I
. In that case, the system indicated to the user (bit
BSTPRE
V
IN
for USB OTG supply. The converter operates in a
V
register BST_INT) that a more than 1 unit load
1.5 MHz fixed frequency PWM mode or in pulse skipping
mode under low load condition. In this mode, where CAP is
the regulated output voltage, Q3 is the main switch and Q2
is the synchronous rectifier switch. While the boost
converter is running, the Q1 MOSFET is conducting.
OBSTOL2
is connected to the NCP1854.
This indicator can also be used to detect a device attached
upon a hot plug on VIN.
Battery Out of Range Protection
During boost mode, when the battery voltage is lower than
Boost Start−up Sequence
The boost mode is enabled through the OTG pin or I C
2
the battery under voltage threshold (V
< V ), or
IBSTL
BAT
higher than the overvoltage threshold (V
> V
), the
(register CTRL1 − bit OTG_EN). Upona turn on request, the
BAT
IBSTH
IC turns off the PWM converter. A fault is indicated to the
system controller (bit VBAT_NOK register BST_INT)
A toggle on OTG pin or OTG_EN bit (register CTRL1) is
needed to start again a boost operation.
converter regulates CAP pin to V
by smoothly boost up
OBST
(DVS) the battery voltage while Q1 MOSFET is maintained
open. The rest of the startup sequence depends on the
accessory configuration:
• Un−Configured USB port (USB_CFG = 0)
According to USB Spec, the maximum load that can be
placed at the downstream end of a cable is 10 mF in
Boost Status Reporting
STATUS and CTRL Registers
The status register contains the boost status. Bits STATE
in register STATUS gives the boost state to the system
controller. Bits FAULTINT and STATINT in register
STATUS are also available in boost mode. If a fault appears
or a status changes (STATINT bits and FAULTINT) the
processor can read corresponding registers for more details.
parallel with 29 W. In that case, the I
current
BSTPRE
source will precharge the IN pin to the operating
voltage.
• Configured USB port (USB_CFG = 1)
A configured USB OTG port should be able to provide
5 units (650 mA DC). End user can program the
NCP1854 to provide the maximum current during start
up in case of specific USB dual role application
(register CTRL1 − bit USB_CFG). A soft start circuitry
of Q1 MOSFET will control the inrush current
Interruption
In boost mode, valid interrupt registers are STAT_INT and
BST_INT while CH1_INT and CH2_INT are tied to their
reset value. Upon a state or status changes, the system
controller is informed by sensing FLAG pin. Like in charge
mode, T
pulse is generated on this pin in order to
Boost Running
FLAGON
signalize the event. The pulse level is low as the FLAG level
is high in boost mode. Charge state transition even and all
signals of register BST_INT can generate an interrupt
request on FLAG pin and can be masked with the
corresponding mask bits in register BST_MSK. All these
bits are read to clear. The register map (see Registers Map
section) indicates the active transition of each bits (column
“TYPE” in see Registers Map section). If more than 1
interrupt appears, only 1 pulse is generated while interrupt
registers (listed just above) will not fully clear.
When running, user can change from Un−configured to
configured mode on the fly and vise versa thanks to
USB_CFG bit.
Boost Over−Voltage Protection
The NCP1854 contains integrated over−voltage
protection on the V line. During boost operation (V
IN
IN
supplied), if an over−voltage condition is detected (V
>
IN
V
), the controller turns off the PWM converter and
OBSTOV
a fault is indicated to the system controller (bit VBUSOV
register BST_INT).
Sense and Status Registers
At any time the system controller can know the status of
all the comparator inside the chip by reading VIN_SNS and
TEMP_SNS registers (read only). These bits give to the
controller the real time values of all the corresponding
comparators outputs (see Block Diagram).
Boost Over−Current Protection
The NCP1854 contains over current protection to prevent
the device and battery damage when V is overloaded.
When the CAP voltage drops down to V
determine an over−current condition is met, so Q1 MOSFET
and PWM converter are turned off. A fault is indicated to the
IN
, NCP1854
OBSTOL1
system controller (bit V
register BST_INT).
OBSTOL1
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18
NCP1854
Table 5. REGISTERS MAP
RST
Value
Bit
STATUS REGISTER − Memory location : 00
7−4 R No_Reset
Type
Reset
Name
Function
STATE[3:0]
0000
Charge mode:
−0000 : OFF
−0001 : WAIT + STBY
−0010 : SAFE CHARGE
−0011 : PRE CHARGE
−0100 : FULL CHARGE
−0101 : VOLTAGE CHARGE
−0110 : CHARGE DONE
−0111 : DPP
−1000 : WEAK WAIT
−1001 : WEAK SAFE
−1010 : WEAK CHARGE
−1011 : FAULT
Boost mode:
−1100 : OTG SET UP
−1101 : OTG UNCONFIGURED
−1110 : OTG CONFIGURED
−1111 : OTG FAULT
3
R
No_Reset
BATFET
0
Indicate if a batfet is connected:
0 : No BATFET is connected
1 : BATFET is connected.
2
1
R
R
No_Reset
No_Reset
RESERVED
STATINT
0
0
Status interrupt:
0 : No status interrupt
1 : Interruption flagged on STAT_INT register
0
R
No_Reset
FAULTINT
0
Fault interrupt:
0 : No status interrupt
1 : interruption flagged on CHRIN1, CHRIN2
or BST_INT register
CTRL1 REGISTER − Memory location : 01
7
6
5
RW
RW
RW
OFF STATE, POR,
REG_RST
REG_RST
CHG_EN
OTG_EN
0
1
0
Reset:
0 : No reset
1 : Reset all registers
OFF STATE, POR,
REG_RST
Charge control:
0 : Halt charging (go to fault state) or OTG operation
1 : Charge enabled / Charge resume
OFF STATE, POR,
REG_RST, CHGMODE
On the go enable:
0 : no OTG operation
1 : OTG operation (set by I2C or OTG pin)
4
3
RW
RW
OFF STATE, POR,
REG_RST, OTGMODE
FCTRY_MOD_REG
TJ_WARN_OPT
1
0
Factory mode (See Section Factory mode and No
battery operation)
OFF STATE, POR,
REG_RST
Enable charge current vs Junction temperature
0: No current change versus junction temperature
1: Charge current is reduced when TJ is too high.
2
RW
OFF STATE, POR,
REG_RST
USB_CFG
1
0 : OCP between CAP and IN after boost start up
done
1 : R
between CAP and IN after boost start
RBFET
up done
1
0
RW
RW
OFF STATE, POR,
REG_RST, TRM_RST
TCHG_RST
INT_MASK
0
1
Charge timer reset:
0 : no reset
1 : Reset and resume charge timer(tchg timer)
(self clearing)
OFF STATE, POR,
REG_RST
global interrupt mask
0 : All Interrupts can be active.
1 : All interrupts are not active
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19
NCP1854
Table 5. REGISTERS MAP
RST
Value
Bit
Type
Reset
Name
Function
CTRL2 REGISTER − Memory location : 02
7
6
5
4
RW
RW
RW
RW
OFF STATE, POR,
REG_RST, OTGMODE
WDTO_DIS
0
Disable watchdog timer
0: Watchdog timer enable
1: Watchdog timer disable
OFF STATE, POR,
REG_RST, OTGMODE
CHGTO_DIS
PWR_PATH
0
0
1
Disable charge timer
0: Charge timer enable
1: Charge timer disable
OFF STATE, POR,
REG_RST, OTGMODE
Power Path Management:
0: Power Path disable
1: Power Path enable
OFF STATE, POR,
REG_RST
TRANS_EN_REG
Trans pin operation enable:
0 : Trans pin is still off
1 : Trans pin is supply
3
2
R
Reserved
RW
OFF STATE, POR,
REG_RST, OTGMODE
IINSET_PIN_EN
IINLIM_EN
1
1
0
Enable input current set pin:
0: Input current limit and AICL control by I C
1: Input current limit and AICL control by pins ILIMx
2
1
0
RW
RW
OFF STATE, POR,
REG_RST, OTGMODE
Enable input current limit:
0: No input current limit
1: Input current limit is IINLIM[3:0]
OFF STATE, POR,
AICL_EN
Enable automatic charge current:
REG_RST, OTGMODE
0: No AICL
1: AICL
STAT_INT REGISTER − Memory location : 03
7−6
5
R
No_Reset
RESERVED
TWARN
RCDual
OFF STATE, POR,
REG_RST
0
0
0
0
0 : Silicon temperature is below TWARN threshold
1 : Silicon temperature is above TWARN threshold
4
3
2
RCDual
RCDual
RCDual
OFF STATE, POR,
REG_RST
TM1
TM2
TSD
0 : Silicon temperature is below T1 threshold
1 : Silicon temperature is above T1 threshold
OFF STATE, POR,
REG_RST
0 : Silicon temperature is below T2 threshold
1 : Silicon temperature is above T2 threshold
OFF STATE, POR,
REG_RST
0 : Silicon temperature is below TSD threshold
1 : Silicon temperature is above TSD threshold
1
0
R
No_Reset
RESERVED
VBUSOK
0
0
RCDual
OFF STATE,
REG_RST,
POR, OTGMODE
0: charger not in USB range
1: charger in USB charging range VBUSUV < VIN
< VBUSOV
CH1_INT REGISTER − Memory location : 04
7−5
4
R
No_Reset
RESERVED
VINLO
0
0
RCDual
OFF STATE,
REG_RST,
VIN changer detection interrupt:
1: VIN − VBAT > VCHGDET and VIN < VINDET
POR, OTGMODE
3
RCDual
OFF STATE,
REG_RST,
VINHI
0
VIN over voltage lock out interrupt:
1: VIN > VINOV
POR, OTGMODE
2
1
R
No_Reset
RESERVED
BUCKOVP
0
0
RCDual
OFF STATE,
REG_RST,
VBAT over voltage interrupt:
1: VBAT > VOVP
POR, OTGMODE
0
R
No_Reset
CHINT2
0
charger related interrupt (CH2_INT register)
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20
NCP1854
Table 5. REGISTERS MAP
RST
Value
Bit
Type
Reset
Name
Function
CH2_INT REGISTER − Memory location : 05
7
6
5
4
3
R
No_Reset
No_Reset
No_Reset
No_Reset
RESERVED
RESERVED
RESERVED
RESERVED
WDTO
0
0
0
0
0
R
R
R
RCSingle
OFF STATE, POR,
REG_RST, TRM_RST,
OTGMODE
watchdog timeout expires interrupt:
1: 32s timer expired.
2
1
0
RCSingle
RCSingle
R
OFF STATE, POR,
REG_RST, TRM_RST,
OTGMODE
USBTO
CHGTO
CHINT1
0
0
0
usb timeout expires interrupt:
1: 2048s timer expired
OFF STATE, POR,
REG_RST, TRM_RST,
OTGMODE
charge timeout expires interrupt:
1: 3600s timer expired
No_Reset
charger related interrupt (CH1_INT register)
BST_INT REGISTER − Memory location : 06
7−4
3
R
No_Reset
RESERVED
VOBSTOL2
0000
0
RCDual
OFF STATE, BOOST
START UP STATE,
POR, REG_RST,
CHGMODE
vbus overload interrupt:
1: Vbus voltage < V
OBSTOL2
2
1
0
RCSingle
RCDual
RCDual
OFF STATE, POR,
REG_RST, CHGMODE
VOBSTOL1
VBUSOV
0
0
0
vbus overload interrupt:
1: VCAP voltage < V
OBSTOL1
OFF STATE, POR,
REG_RST, CHGMODE
vbus overvoltage interrupt:
1: Vbus voltage < VBUSOV
OFF STATE, POR,
REG_RST, CHGMODE
VBAT_NOK
vbat out of range interrupt:
1: V
< Vbat voltage < VIBSTL
IBSTH
VIN_SNS REGISTER − Memory location : 07
7
R
No_Reset
VINOVLO_SNS
0
VIN over voltage lock out comparator
1: VIN > VINOV
6
5
R
R
No_Reset
No_Reset
RESERVED
0
0
VBUSOV_SNS
VIN not is USB range comparator
1: VIN > VBUSOV
4
3
2
1
0
R
R
R
R
R
No_Reset
No_Reset
No_Reset
No_Reset
No_Reset
VBUSUV_SNS
VINDET_SNS
VCHGDET_SNS
VOBSTOL2_SNS
RESERVED
0
0
0
0
0
VIN not is USB range comparator
1: VIN < VBUSUV
VIN voltage detection comparator
1: VIN > VINDET
VIN changer detection comparator
1: VIN − VBAT > VCHGDET
VIN OTG under voltage comparator
1: Vbus voltage < V
OBSTOL2
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21
NCP1854
Table 5. REGISTERS MAP
RST
Value
Bit
Type
Reset
Name
Function
VBAT_SNS REGISTER − Memory location : 08
7
6
R
R
No_Reset
No_Reset
RESERVED
0
0
VBAT_OV_SNS
VBAT over voltage comparator
1: VBAT > VOVP
5
4
3
2
1
0
R
R
R
R
R
R
No_Reset
No_Reset
No_Reset
No_Reset
No_Reset
No_Reset
VRECHG_OK_SNS
VFET_OK_SNS
VPRE_OK_SNS
VSAFE_OK_SNS
IEOC_OK_SNS
RESERVED
0
0
0
0
0
0
VBAT recharge comparator
1: VBAT > VRECHG
VBAT weak charge comparator
1: VBAT > VFET
VBAT precharge comparator
1: VBAT > VPRE
VBAT safe comparator
1: VBAT > VSAFE
End of charge current comparator
1: ICHARGE > IEOC
TEMP_SNS REGISTER − Memory location : 09
7
6
5
4
3
R
R
R
R
R
No_Reset
No_Reset
No_Reset
No_Reset
No_Reset
RESERVED
RESERVED
RESERVED
RESERVED
TSD_SNS
0
0
0
0
0
Chip thermal shut down comparator
1: Chip Temp > TSD
2
1
0
R
R
R
No_Reset
No_Reset
No_Reset
TM2_SNS
TM1_SNS
TWARN
0
0
0
Chip thermal shut down comparator
1: Chip Temp > tm2
Chip thermal shut down comparator
1: Chip Temp > tm1
Chip thermal shut down comparator
1: Chip Temp > twarn
STAT_MSK REGISTER − Memory location : 0A
7
6
5
R
R
No_Reset
No_Reset
RESERVED
RESERVED
0
0
0
RW
OFF STATE,
POR, REG_RST
TWARN_MASK
TWARN interruption mask bit.
TM1 interruption mask bit.
TM2 interruption mask bit.
TSD interruption mask bit.
4
3
2
RW
RW
RW
OFF STATE,
POR, REG_RST
TM1_MASK
TM2_MASK
TSD_MASK
0
0
0
OFF STATE,
POR, REG_RST
OFF STATE,
POR, REG_RST
1
0
R
No_Reset
RESERVED
0
0
RW
OFF STATE, POR,
REG_RST, OTGMODE
VBUSOK_MASK
VBUSOK interruption mask bit.
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22
NCP1854
Table 5. REGISTERS MAP
RST
Value
Bit
Type
Reset
Name
Function
CH1_MSK REGISTER − Memory location : 0B
7−5
4
R
No_Reset
RESERVED
0
0
RW
OFF STATE, POR,
REG_RST, OTGMODE
VINLO_MASK
VINLO interruption mask bit.
VINHI interruption mask bit.
3
RW
OFF STATE, POR,
VINHI_MASK
0
REG_RST, OTGMODE
2
1
R
No_Reset
RESERVED
0
0
RW
OFF STATE, POR,
REG_RST, OTGMODE
BUCKOVP_MASK
BUCKOVP interruption mask bit.
0
RW
OFF STATE, POR,
REG_RST, OTGMODE
STATECHG_MASK
0
State transition interruption mask bit.
CH2_MSK REGISTER − Memory location : 0C
7−4
3
R
No_Reset
RESERVED
0000
1
RW
OFF STATE, POR,
REG_RST, OTGMODE
WDTO_MASK
WDTO interruption mask bit.
USBTO interruption mask bit.
CHGTO interruption mask bit.
2
1
0
RW
RW
R
OFF STATE, POR,
REG_RST, OTGMODE
USBTO_MASK
CHGTO_MASK
RESERVED
1
1
0
OFF STATE, POR,
REG_RST, OTGMODE
No_Reset
BST_MSK REGISTER − Memory location : 0D
7−5
4
R
No_Reset
RESERVED
0
1
RW
OFF STATE, POR,
REG_RST, OTGMODE
VOBSTOL2_MASK
3
2
1
0
RW
RW
RW
RW
OFF STATE, POR,
REG_RST, OTGMODE
VOBSTOL1_MASK
VBUSOV_MASK
1
1
1
1
OFF STATE, POR,
REG_RST, OTGMODE
OFF STATE, POR,
REG_RST, OTGMODE
VBAT_NOK_MASK
STATEOTG_MASK
OFF STATE, POR,
REG_RST, OTGMODE
STATEOTG interruption mask bit.
VBAT_SET REGISTER − Memory location : 0E
7−6
5−0
R
No_Reset
RESERVED
00
RW
OFF STATE, POR,
REG_RST, OTGMODE
CTRL_VBAT [5:0]
001100
000000: 3.3 V
001100: 3.6 V
110000: 4.5 V
Step: 0.025 V
IBAT_SET REGISTER − Memory location : 0F
7
RW
OFF STATE, POR,
REG_RST, OTGMODE
ICHG_HIGH
IEOC[2:0]
0
Output current MSB:
0, ICHG[] = ICHG
1, ICHG[] = 1.6A + ICHG
6−4
RW
OFF STATE, POR,
REG_RST, OTGMODE
010
000: 100 mA
010: 150 mA
111: 275 mA
Step: 25 mA
3−0
RW
OFF STATE, POR,
REG_RST, OTGMODE
ICHG[3:0]
0110
Output range current programmable range:
0000: 450 mA
1111: 1.9 A
Step: 100 mA
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23
NCP1854
Table 5. REGISTERS MAP
RST
Value
Bit
Type
Reset
Name
Function
MISC_SET REGISTER − Memory location : 10
7
R
Reserved
6−5
RW
OFF STATE, POR,
REG_RST, OTGMODE
IWEAK[1:0]
01
Charge current during weak battery states:
00: Disable
01: 100 mA
10: 200 mA
11: 300 mA
4−2
1−0
RW
RW
OFF STATE, POR,
REG_RST, OTGMODE
CTRL_VFET[2:0]
011
Battery to system re−connection threshold:
000: 3.1 V
001: 3.2 V
010: 3.3 V
011: 3.4 V
100: 3.5 V
101: 3.6 V
OFF STATE, POR,
REG_RST, OTGMODE
IINLIM[2:0]
00
Input current limit range:
00: 100 mA
01: 500 mA
10: 900 mA
11: 1500 mA
IINLIM_SET REGISTER − Memory location : 11
7−4
RW
OFF STATE, POR,
REG_RST, OTGMODE
IINLIM_TA[3:0]
0000
Input current limit range:
0000: IINLIM
0001: 600 mA
1111: 2000 mA
Step: 100 mA
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24
NCP1854
Application Information
Bill of Material
2.2 mH
L
X
R
SNS
33 mW
SW
IN
C
OUT
C
IN
C
BOOT
SYSTEM
NCP1854
22 mF
1 mF
10 nF
CBOOT
SENSP
SENSN
WEAK
FET
CAP
CORE
C
CAP
4.7 mF
VBUS
D+
D−
C
CORE
Q
BAT
(*)
ID
GND
2.2 mF
BAT
+
TRANS
ILIM1
C
TRS
0.1 mF
USB PHY
FLAG
SCL
ILIM2
OTG
SDA
AGND
SPM
PGND
FTRY
Figure 16. Typical Application Example
Item
Part Description
Ref
Value
1 mF
PCB Footprint
0603
Manufacturer
MURATA
MURATA
MURATA
MURATA
MURATA
AVX
Manufacturer Reference
GRM188R61E105K
GRM21BR61E475KA12L
GRM155R60J225M
GRM155R60J104K
GRM155R60J103K
08056D226MAT2A
SPM3012T-2R2M
1
2
3
4
5
6
7
8
9
Ceramic Capacitor 25 V X5R
Ceramic Capacitor 25 V X5R
Ceramic Capacitor 6.3 V X5R
Ceramic Capacitor 6.3 V X5R
Ceramic Capacitor 10 V X5R
Ceramic Capacitor 6.3 V X5R
SMD Inductor
C
IN
C
4.7 mF
2.2 mF
0.1 mF
10 nF
22 mF
2.2 mH
33 mW
18 mW
0805
CAP
C
0402
CORE
C
0402
TRS
C
0402
BOOT
C
0805
OUT
L
X
3012
SPM3012T-2R2M
YAGEO
SMD Resistor 0.25 W, 1%
Power channel P-MOSFET
R
0805
RL0805FR-7W0R033L
NTLUS3A18PZ
SNS
Q
UDFN 2*2 mm
ONSEMI
BAT
PCB Layout Consideration
Particular attention must be paid with C
capacitor as
The high current charge path through IN, CAP, SW,
inductor L1, Resistor R1, optional BAFTET, and battery
pack must be sized appropriately for the maximum charge
current in order to avoid voltage drops in these traces. An
IWEAK current can flow through WEAK and BAT traces
witch defines the appropriate track width.
It’s suggested to keep as complete ground plane under
NCP1854 as possible. PGND and AGND pin connection
must be connected to the ground plane.
CORE
it’s decoupling the supply of internal circuitry including gate
driver. This capacitor must be placed between CORE pin
and PGND pin with a minimum track length.
The high speed operation of the NCP1854 demands
careful attention to board layout and component placement.
To prevent electromagnetic interference (EMI) problems,
attention should be paid specially with components L ,
X
C
, and C
as they constitute a high frequency current
CAP
OUT
loop area. The power input capacitor C , connected from
CAP to PGND, should be placed as close as possible to the
Care should be taken to avoid noise interference between
PGND and AGND. Finally it is always good practice to keep
the sensitive tracks such as feedbacks connections (SENSP,
SENSN, BAT) away from switching signal connections by
laying the tracks on the other side or inner layer of PCB.
CAP
NCP1854. The output inductor L and the output capacitor
X
C
OUT
connected between R
and PGND should be placed
SNS
close to the IC. C capacitor should also be place as close
IN
as possible to IN and PGND pin as well.
http://onsemi.com
25
NCP1854
IN
DC Power path
Q1
Q2
Swithing Power Path
CORE
CAP
C
IN
2.2 mH
L
X
R
33 mW
SNS
C
SW
CORE
1 mF
2.2 mF
Q3
+
22 mF
C
CAP
C
4.7 mF
SYS
NCP1854
Ground
Plane
PGND
PGND
Ground
Plane
Figure 17. Power Path
It’s suggested to use multiple layers (usually 2) under the power balls of the IC to reduce thermal heating to due to contact
resistance between CSP and PCB.
Figure 18. Layout Example
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26
NCP1854
ORDERING INFORMATION
Device Order Number
NCP1854FCCT1G
2
†
I C address
Marking
Shipping
6C
1854
3000 / Tape & Reel
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27
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
25 Pin Flip−Chip, 2.55x2.20
CASE 499BN
ISSUE A
DATE 26 OCT 2011
SCALE 4:1
D
A
B
E
NOTES:
PIN A1
REFERENCE
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A3
A2
MILLIMETERS
DIM
A
A1
A2
A3
b
D
E
e
MIN
−−−
0.17
MAX
0.60
0.23
0.36 REF
0.04 REF
0.24 0.29
2.55 BSC
2.20 BSC
0.40 BSC
2X
0.10
0.10
C
2X
C
DETAIL A
TOP VIEW
A2
DETAIL A
GENERIC
0.10
C
MARKING DIAGRAM*
A
XXXXXX
AYWW
G
0.05
C
SEATING
PLANE
NOTE 3
C
A1
SIDE VIEW
XXXXXX= Specific Device Code
A
Y
WW
G
= Assembly Location
= Year
= Work Week
e
25X
b
0.05
0.03
C A B
E
C
e
= Pb−Free Package
D
C
B
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
A
RECOMMENDED
SOLDERING FOOTPRINT*
1
2
3
4
5
BOTTOM VIEW
PACKAGE
OUTLINE
A1
0.40
PITCH
25X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON54510E
25 PIN FLIP−CHIP, 2.55X2.20
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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