NCP1927DR2G_技术文档

NCP1927

Combination Power Factor

Correction Controller and

Flyback Controller for Flat

Panel TVs

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MARKING DIAGRAM

This combination IC integrates the primary side control blocks −

power factor correction (PFC) and flyback controllers with

sequencing circuitry − necessary to implement a compact highly

efficient Flat Panel TV Switched Mode Power Supply.

The PFC controller exhibits near−unity power factor while

operating in Critical Conduction Mode (CrM) with an internal

frequency clamp. The circuit incorporates all the features necessary

for building a robust and compact PFC stage while minimizing the

number of external components.

The fixed−frequency current−mode flyback controller features a

proprietary Soft−Skip™ mode combined with frequency foldback

enabling excellent efficiency during light load conditions while

achieving very low standby power consumption. Soft−Skip

dramatically reduces the risk of acoustic noise, therefore enabling the

use of inexpensive transformers and capacitors in the clamping

network. Frequency jittering and ramp compensation make this

controller an excellent fit for converters where ruggedness and

component cost are the key constraints.

POVUV

PFB

IENABLE

PSKIP

PDRV

VCC

Shutdown

PControl

PCT

FDRV

GND

PZCD

PCS

FFB

SOIC−16

CASE 751B

GTS

FCS

A

= Assembly Location

WL = Wafer Lot

= Year

WW = Work Week

Y

G

= Pb−Free Package

ORDERING INFORMATION

Common General Features

• Wide V Range from 10 V to 30 V

†

CC

Device

NCP1927DR2G

Package

Shipping

• Very Low Startup Current Consumption

(v 20 mA MAX)

SOIC−16 2500 / Tape & Reel

(Pb−Free)

• Inverter Enable Output

• Shutdown Pin to Disable IC

• Go To Standby Input

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

• This is a Pb−Free Device

PFC Controller Features

Flyback Controller Features

• Critical Conduction Mode (CrM) with Constant On

Time Control

• Internal Frequency Clamp

• Skip Mode Operation During Light Load Conditions

• Fast Line / Load Transient Compensation

• Accurate and Programmable Maximum On Time

Control

• Negative Current Sensing

• Programmable Overvoltage/Undervoltage Protection

• 800 mA Source / 1200 mA Sink Gate Drive

• 65 kHz Fixed−Frequency Operation with Built−In

Ramp Compensation

• Frequency Jittering for Softened EMI Signature

• Frequency Foldback then Soft−Skip for Improved

Performance in Standby

• Timer−Based Overload Protection with Auto−Recovery

• Protection Against Winding Short−Circuit

• 4 ms Soft−Start Timer

• 800 mA Source / 1200 mA Sink Gate Drive

1

Publication Order Number:

June, 2011 − Rev. 0

NCP1927/D

NCP1927

Figure 1. Typical Application Example

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2

NCP1927

V

DD

Flyback_OVLD

Latch

I

Shutdown

GOS Timer

GTS Timer

Shutdown

30 ms

Filter

Shutdown

GTS

30 ms

TSD

R

GTS

Filter

V

SHDN

V

standby

FFAULT

30 ms

Filter

V

CC

V

Reg

DD

CS_STOP

V

CC(on)

UVP

V

30 ms

Filter

POVUV

OVP_int

5V Reg

V

CC(off)

I

UVP

SS_enable

V

OVP

FFAULT

START_DELAY

PFAULT

PFC_OK

V

IENABLE

CC(reset)

V

disable

30 ms

Filter

R

Q

R

S

V

FFB(open)

V

DD

Saw In

Soft−Skip

Saw

R

FFB

Reset

I

PControl(boost)

Timer

PFC_OK

FFB

V

Skip Out

FSKIP

B5

FFAULT

Timer

0.955*V

FFAULT

REF

Reset

PFB

ILIM

10 ms

Filter

V

REF

0 mA

Detect

Flyback_OVLD

PControl

LEB

FCS

PFAULT

SS_enable

SS_end

Soft−Start

Timer

R

V

DD

9*R

I

CS_STOP

V

ILIM

PSKIP

V

CS(stop)

LEB

PSKIP

START_DELAY

FFAULT

R

ramp

PFC_OK

V

Saw

V

CC

Latch

DD

Clamp

Shutdown

I

PCT(charge)

t

ON(MAX)

Timer

R

Q

FDRV

PCT

PCS

S

Frequency

Foldback

PDRV

PFM

SQUARE

OSC

FFB

V

Jittering

S AW

Saw

SS_end

FM

CC

R

Q

Clamp

I

> I

PCS OCP

START_DELAY

S

PDRV

GND

S

R

Q

OVP_int

PFAULT

DRVCLK

ZCD

PDRV

V

ZCD(rising)

PDRV

Reset

WDT

S

R

Q

PDRV

Frequency Clamp

PZCD

V

ZCD(falling)

* Values are typical values

* All latches are Reset Dominant

Figure 2. Internal Block Diagram

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3

NCP1927

PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

POVUV

PFB

Pin Description

is below V (300 mV typ) or above V

1

2

The gate drive is disabled while V

(2.5 V typ).

OVP

POVUV

UVP

This pin receives a portion of the pre−converter output voltage. This information is used for the

regulation and the “output low” detection that speeds up the loop response when the output voltage

drops below 95.5% (typ) of the programmed level.

3

4

Shutdown

PControl

Pull this pin above 1.0 V (typ) to disable the part. Ground this pin when not in use.

The error amplifier output is available on this pin. The capacitor connected between this pin and

ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve a high power

factor. This pin is internally grounded when the circuit is off so that when it starts operation, the power

increases gradually (soft−start).

5

PCT

The PCT pin sources a 210 mA (typ) current to charge an external timing capacitor. The circuit

controls the power switch on time by comparing the PCT voltage to an internal voltage derived from

the regulation block.

6

7

8

9

PZCD

PCS

GTS

FCS

The voltage of an auxiliary winding is applied to this pin to detect when the inductor is demagnetized

for operation in critical conduction mode.

This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the

maximum coil current and protect the PFC stage during overload conditions.

Pull this pin low to disable the PFC controller during standby mode. Standby mode can also be

entered by monitoring the feedback voltage of the flyback stage with an external resistor divider.

This pin senses the primary current for current−mode operation of the flyback stage. Ramp

compensation can be added with an external resistor.

10

11

12

13

14

15

FFB

GND

FDRV

Connecting this pin to ground through an optocoupler allows regulation of the flyback stage.

This is the the controller ground.

This is the driver’s output to an external MOSFET gate of the flyback power stage.

This pin is connected to an external auxiliary voltage.

V

CC

PDRV

PSKIP

This is the driver’s output to an external MOSFET gate of the PFC power stage.

To adjust the power level below which the PFC stage will enter skip mode, connect a resistor between

this pin and ground. To disable skip mode, connect this pin directly to ground.

16

IENABLE

This pin voltage is high (5 V) when the output of the PFC stage is in steady state regulation and low

at all other times. This signal serves to “inform” the backlight inverter that the PFC output is ready and

that it can start operation. It can also be used as a stable 5 V reference.

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4

NCP1927

MAXIMUM RATINGS (Note 1)

Rating

Symbol

Value

Unit

Supply Pin (pin 13) (Note 2)

Voltage Range

Current Range

V

−0.3 to 30

$30

V

mA

CC(MAX)

I

PFC Drive Pin (pin 14) (Note 2)

Voltage Range

Current Range

V

−0.3 to 20

−800, +1200

V

mA

PDRV(MAX)

I

Flyback Drive Pin (pin 12) (Note 2)

Voltage Range

Current Range

V

−0.3 to 20

−800, +1200

V

mA

FDRV(MAX)

I

Inverter Enable Pin (pin 16) (Note 2)

Voltage Range

Current Range

V

−0.3 to 6

$20

V

mA

IENABLE(MAX)

I

Control Pin (pin 4) (Note 2)

Voltage Range

Current Range

V

−0.3 to 6

$10

V

mA

PControl(MAX)

I

PFC Current Sense Pin (pin 7) (Note 2)

Voltage Range

Current Range

V

−0.3 to 3

$10

V

mA

PCS(MAX)

I

ZCD Pin (pin 6) (Note 2)

Voltage Range

Current Range

V

−0.9 to 12

$10

V

mA

PZCD(MAX)

I

All Other Pins (Note 2)

Voltage Range

Current Range

V

−0.3 to 10

$10

V

mA

MAX

I

Thermal Resistance

R

140

°C/W

θ

JA

2

Junction−to−Air, 100 mm Single Layer of 1 oz Copper

Temperature Range

°C

Storage Temperature

T

−60 to 150

−25 to 125

JSTRG(MAX)

J(MAX)

Operating Junction Temperature

T

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Charged Device Model 2000 V per JEDEC Standard JESD22-C101D

Human Body Model 2000 V per JEDEC Standard JESD22−A114E

Machine Model 200 V per JEDEC Standard JESD22−A115A

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

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5

NCP1927

ELECTRICAL CHARACTERISTICS (V = 12 V, V

= 2.4 V, V

= 2.3 V, V

= 4 V, V

= 0 V, V

=

CC

= 0 V, V

PFB

POVUV

PControl

PZCD

PCS

GTS

1 V, V

= 0 V, V

= 2.4 V, V

= 0 V, V

= open, C

= 1 nF, C

= 1 nF, for typical

PSKIP

FFB

FCS

Shutdown

IENABLE

PCT

PDRV

FDRV

values T = 25°C, for min/max values, T is − 25°C to 125°C, unless otherwise noted)

J

Characteristics

Test Condition

Symbol

Min

Typ

Max

Unit

SUPPLY CIRCUIT

Supply Voltage

V

Startup Threshold

V

increasing, dV/dt = 1.25 mV/ms

decreasing, dV/dt = 125 mV/ms

V

16

8

5.0

17

9

6.5

18

10

8.0

CC

CC(on)

CC(off)

Minimum Operating Voltage

Internal latch reset level

V

decreasing

CC(reset)

CC

Supply Current

PFC is switching at 70kHz

Flyback Switching, PFC is in GTS

C

= open, C

= open

I

2.4

3.8

1.0

3.3

5.1

1.5

4.2

6.4

2.0

mA

FDRV

PDRV

CC1

CC2

CC3

V

= V

− 0.2 V, C

FCS

= open,

FFB

fold

V

FDRV

= 0.8 V

During Faults

Startup

I

1.0

−

1.5

−

2.5

20

mA

CC4

CC5

V

= V

− 0.2 V

CC

CC(on)

FLYBACK FEEDBACK

Equivalent Internal Pull−Up Resistor

R

K

14

20

31

kW

FFB

V

FFB

to Internal Current Setpoint

4.8

5.0

5.2

FFB

Division Ratio

Overload Detection Filter

Flyback Fault Timer

t

−

10

80

−

ms

V

delay(FOVLD)

V

FFB

= 4.5 V to FDRV turn−off

t

60

4.5

100

5.5

FOVLD

FFB Pin Voltage

V

FFB

= open

V

5.0

FFB(open)

FLYBACK CURRENT SENSE

Current Sense Voltage Threshold

Leading Edge Blanking Duration

V

FFB

= 4.5 V

V

0.655

190

0.700

250

0.725

310

V

ILIM

t

ns

LEB

Propagation Delay

Step V

0 V to 2 V, to FDRV

FCS

Current Sense Voltage Threshold

Immediate Fault Protection

falling edge

t

−

80

110

ns

delay(ILIM)

CS(stop)

t

Immediate Fault Protection Threshold

Leading Edge Blanking Duration for

V

FFB

= 3 V, V

dV/dt = 500 mV/ms

V

0.95

90

1.05

120

1.15

150

V

FCS

CS(stop)

t

ns

LEB(stop)

I

CS(stop)

Input Bias Current

V

= V

I

−1

−

+1

mA

FCS

ILIM

FCS(bias)

Current Sourced by the FCS Pin

FLYBACK SOFT−START

Soft−Start Period

V

= 0 V, 80% Duty Ratio

I

100

150

200

FCS

ramp(MAX)

st

1

FDRV pulse to V

= V

t

SSTART

2.8

4.0

5.2

ms

FCS

ILIM

OSCILLATOR

Base Oscillator Frequency

Maximum Duty Ratio

f

60

76

−

65

80

70

84

−

kHz

%

OSC

D

MAX

MOD

Frequency Modulation in Percentage of

f

$6

%

f

OSC

Frequency Modulation Frequency

f

−

125

−

Hz

%

jitter

Oscillator Frequency Voltage Stability

V

< V < V

CC(MAX)

f

−1

−

+1

CC(MIN)

CC

OSC(VSTAB)

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6

NCP1927

ELECTRICAL CHARACTERISTICS (V = 12 V, V

= 2.4 V, V

= 2.3 V, V

= 4 V, V

= 0 V, V

=

CC

= 0 V, V

PFB

POVUV

PControl

PZCD

PCS

GTS

1 V, V

= 0 V, V

= 2.4 V, V

= 0 V, V

= open, C

= 1 nF, C

= 1 nF, for typical

PSKIP

FFB

FCS

Shutdown

IENABLE

PCT

PDRV

FDRV

values T = 25°C, for min/max values, T is − 25°C to 125°C, unless otherwise noted)

J

Characteristics

Test Condition

Symbol

Min

Typ

Max

Unit

FLYBACK GATE DRIVE

FDRV Impedance

Sink

V

= 10 V

= 2 V

R

−

12.5

14

−

W

FDRV

FDRV(SNK)

FDRV(SRC)

Source

V

FDRV Rise Time (10% to 90%)

FDRV Fall Time (90% to 10%)

FDRV Low Voltage

t

15

12

−

30

25

80

70

0.5

1

ns

V

FDRV(r)

t

FDRV(f)

I

= 0 mA

V

0.06

−

FDRV

FDRV(low)

FDRV Voltage Drop

V

CC

= V

R

+ 0.2 V,

V

−

V

CC(off)

FDRV(drop)

= 33 kW

FDRV

FDRV Clamp Voltage

V

CC

= 30 V, I

= 0 mA

V

FDRV(clamp)

11

13.5

16

V

FDRV

FLYBACK SKIP MODE/FREQ FOLDBACK

Skip Threshold

V

Decreasing

V

630

65

700

100

1.40

26

770

135

140

1.54

31

mV

ms

FFB

FSKIP

V

FSKIP(HYS)

Skip Comparator Hysteresis

Soft−Skip Duration

st

1

Pulse to V

= V /K

t

SSKIP

50

FCS

fold FFB

Frequency Foldback Threshold

Minimum Switching Frequency

Maximum On Time

V

Decreasing, dV/dt = 500 mV/ms

V

1.26

21

V

FFB

fold

OSC(MIN)

V

= V

+ 150 mV

f

kHz

ms

FFB

FSKIP

Frequency Foldback or Skip Mode

t

10.0

13.0

16.0

on(MAX)

PFC CURRENT SENSE

PCS Pin Voltage

R

= 2.5 kW, I

= 265 mA

V

−20

230

−

0

20

mV

mA

ns

PCS

OCP

Overcurrent Protection Threshold

Propagation Delay

R

= 2.5 kW

I

t

250

100

265

210

PCS

step I

OCP

0 mA to 400 mA

PCS

I

to PDRV falling edge

R

= 1 kW

PCS

PFC RAMP CONTROL

PCT Charge Current

V

= 1.5 V

I

189

210

231

500

mA

PCT

PCT(charge)

C

Discharge Time

V

= open, C

= 10 nF

t

CPCT(discharge)

−

ns

PCT

PControl

PCT

PControl

V

= V

−100 mV to

600 mV

PCT(MAX)

Maximum PCT Level Before PDRV

Switches Off

= open, C

= 10 nF

V

PCT(MAX)

4.7

−

5.0

150

385

5.3

200

440

V

PControl

Propagation Delay of the PWM

Comparator

step V

from 3.5 V to 5.0 V

t

ns

PCT

PWM

PFC Frequency Clamp

f

330

kHz

clamp

PFC GATE DRIVE

PDRV Impedance

Sink

V

= 10 V

= 2 V

R

−

12.5

14

−

W

PDRV

PDRV(SNK)

PDRV(SRC)

Source

V

PDRV Rise Time (10 % to 90 %)

PDRV Fall Time (90 % to 10 %)

PDRV Low Voltage

t

15

12

−

30

25

80

70

0.5

1

ns

V

PDRV(r)

t

PDRV(f)

I

= 0 mA

V

0.06

−

PDRV

PDRV(low)

PDRV Voltage Drop

V

CC

= V

R

+ 0.2 V,

V

−

V

CC(off)

PDRV(drop)

= 33 kW

PDRV

PDRV Clamp Voltage

V

CC

= 30 V, I

= 0 mA

V

PDRV(clamp)

11

13.5

16

V

PDRV

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7

NCP1927

ELECTRICAL CHARACTERISTICS (V = 12 V, V

= 2.4 V, V

= 2.3 V, V

= 4 V, V

= 0 V, V

=

CC

= 0 V, V

PFB

POVUV

PControl

PZCD

PCS

GTS

1 V, V

= 0 V, V

= 2.4 V, V

= 0 V, V

= open, C

= 1 nF, C

= 1 nF, for typical

PSKIP

FFB

FCS

Shutdown

IENABLE

PCT

PDRV

FDRV

values T = 25°C, for min/max values, T is − 25°C to 125°C, unless otherwise noted)

J

Characteristics

Test Condition

Symbol

Min

Typ

Max

Unit

PFC ZERO CURRENT DETECTION

Zero Current Detection Threshold

V

Rising

Falling

V

1.12

0.56

1.40

0.70

1.68

0.84

ZCD(rising)

ZCD(falling)

V

Hysteresis on Voltage Threshold

Propagation Delay

V

− V

V

ZCD(HYS)

560

700

100

840

170

mV

ns

V

ZCD(rising)

ZCD(falling)

Step V

from 2 V to 0 V

t

−

PZCD

ZCD

Clamp Voltage

Upper Clamp

I

= 3 mA

= −2 mA

V

8

−0.9

10

−0.7

12

0

PZCD

CL(POS)

CL(NEG)

Negative Clamp

I

V

PZCD

Minimum detectable ZCD pulse width

Maximum Off Time

t

−

70

100

300

ns

SYNC

PDRV off = 10% to PDRV on = 90%

t

75

180

ms

start

Input Bias Current

V

PZCD

= 5 V

I

−2

−

2

mA

PZCD

PZCD(bias)

V

= −0.2 V

I

PFC SKIP MODE

Skip Pin Internal Current Source

I

27

10

30

12

33

16

mA

PSKIP

Hysteresis of the skip cycle detection

level

V

PSKIP

= 1 V

V

%

PSKIP(HYS)

PFC REGULATION BLOCK

Voltage Reference

V

REF

2.463

2.500

2.537

V

Error Amplifier Current Capability

Maximum Source Current

Maximum Sink Current

V

PFB

V

PFB

= 2.4 V, V

= 2.6 V, V

= 3 V

I

EA(SRC)

EA(SNK)

16

20

24

mA

POVUV

I

Error Amplifier Transconductance

V

PFB

= V

POVUV

$ 100 mV,

gm

100

200

300

mS

REF

V

= 3 V

PFB Bias Current

V

= 2.5 V

I

−0.5

−

0.5

6.1

mA

PFB

PFB(bias)

Maximum EA Output Voltage

V

= 2 V

V

5.05

5.6

V

PFB

PControl(MAX)

V

= open, C

= 10 nF

PControl

Minimum EA Output Voltage

V

= 3 V

V

0.35

0.6

0.8

V

PFB

PControl(MIN)

= open, C

PControl

EA Output Regulation Voltage Swing

V

− V

DV

PControl

4.7

5.0

5.3

V

PControl(MAX)

PControl(MIN)

Ratio (V Low Detect Threshold /

REF

V

/V

95.0

95.5

96.0

%

out

OLOW REF

V

)

V

out

Low Detect / V

Hysteresis

V /

OLOW(HYS)

−

1.0

%

REF

V

REF

Source Current During V

Detect

Low

I

190

240

290

mA

OUT

PControl(boost)

GO TO STANDBY (GTS)

Internal Pull−Down Resistor

Standby Threshold

R

80

270

85

200

300

100

320

330

125

kW

mV

GTS

V

GTS

Decreasing

V

standby

Standby Hysteresis

V

standby(HYS)

Go To Standby Timer

Step V

from 1 V to 0 V

from 0 V to 1 V

t

37.5

30

50.0

50

62.5

70

ms

GTS

GTS(off)

GTS(on)

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8

NCP1927

ELECTRICAL CHARACTERISTICS (V = 12 V, V

= 2.4 V, V

= 2.3 V, V

= 4 V, V

= 0 V, V

=

CC

= 0 V, V

PFB

POVUV

PControl

PZCD

PCS

GTS

1 V, V

= 0 V, V

= 2.4 V, V

= 0 V, V

= open, C

= 1 nF, C

= 1 nF, for typical

PSKIP

FFB

FCS

Shutdown

IENABLE

PCT

PDRV

FDRV

values T = 25°C, for min/max values, T is − 25°C to 125°C, unless otherwise noted)

J

Characteristics

Test Condition

Symbol

Min

Typ

Max

Unit

PFC FAULT PROTECTION

Overvoltage Protection Threshold

Overvoltage Protection Hysteresis

Overvoltage Protection Filter Delay

Undervoltage Protection Threshold

Undervoltage Protection Hysteresis

Undervoltage Protection Filter Delay

UVP Pull Down Current Source

V

2.450

20

2.500

40

2.550

60

V

OVP

V

mV

ms

OVP(HYS)

delay(OVP)

t

−

30

−

V

285

20

300

40

315

60

mV

ms

UVP

V

UVP(HYS)

delay(UVP)

t

−

30

−

I

0.7

99.5

1.0

1.3

100.5

mA

%

UVP

Ratio Between V

and V

(Note 3)

V

/V

100.0

OVP

REF

OVP REF

INVERTER ENABLE/REFERENCE

Disable Threshold

V

1.809

1.865

30

1.921

V

disable

Disable Filter Delay

t

−

ms

delay(disable)

Voltage Reference

I

= 8 mA

V

4.5

4.7

−

5.0

60

5.4

120

V

mV

IENABLE(SRC)

IENABLE(high)

IENABLE(low)

= 1 mA

I

= 250 mA

V

IENABLE(SNK)

Reference Pin Decoupling Capacitor

THERMAL PROTECTION

Thermal Shutdown

C

0

−

1

mF

REF

T

−

150

30

−

°C

ms

TSHDN

Thermal Shutdown Delay

SHUTDOWN PIN

t

delay(TSHDN)

Shutdown Threshold

V

Increasing

V

0.90

−

1.00

30

1.10

−

V

Shutdown

SHDN

Shutdown Filter Delay

t

ms

mA

Shutdown

delay(SHDN)

Pull Up Current Source

3. Guaranteed by design

I

2.3

3.3

4.3

Shutdown

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9

NCP1927

DETAILED OPERATING DESCRIPTION

INTRODUCTION

When V reaches V

(typically 6.5 V), a Power

CC

CC(reset)

The NCP1927 is a combination power factor correction

(PFC) and flyback controller optimized for use in Flat Panel

TVs. This device includes all the features needed to

implement a highly efficient and compact power supply. It

integrates a critical conduction mode (CrM) PFC controller

and a fixed−frequency current mode flyback controller with

proper sequencing for simplified system design.

This device includes frequency jittering, a shutdown

input, an inverter enable output, a go to standby input, and

a dedicated pin for under/overvoltage protection.

On Reset occurs. This resets all logic states on the device. As

continues to rise, the IC bias current remains at I

V

CC

CC5

until V

reaches V (typically 17 V). Once V

CC(on) CC

CC

reaches V , the flyback controller is enabled and the IC

CC(on)

bias current increases to I

(1.5 mA typical). However,

CC3

the total I current is greater than this due to the gate charge

CC

load at the flyback drive output (FDRV). Once the flyback

is in regulation, the PFC controller can be enabled. When the

PFC is enabled, the I current increases further due to the

CC

gate charge load at the PFC drive output (PDRV). The

increase in I per MOSFET is calculated using Equation 2.

CC

SUPPLY SEQUENCING

The flyback controller of the NCP1927 is enabled once

I

_CC(x)+ f_OSC@ Q_G(x)

(eq. 2)

V

reaches V

, provided it is not in thermal shutdown

CC

CC(on)

where, f

is the switching frequency and Q

is the gate

OSC

G(X)

and has not been latched off or shutdown. Once the flyback

controller is enabled, a soft−start timer is activated, and it

begins switching. The soft−start timer provides a ramp

charge of the external MOSFET X.

C

VCC

must be sized such that a V voltage greater than

CC

V

CC(off)

(9 V typical) is maintained while the auxiliary

signal that increases over t

(typically 4.0 ms). This

SSTART

supply voltage increases during startup. If C

is too small,

VCC

ensures that the peak current gradually increases to

minimize power component stress and limit output voltage

overshoot. Frequency jittering is disabled while the

soft−start timer is running.

Once the flyback controller detects regulation on the

output (it is no longer in overload), the PFC controller can

be enabled. As soon as the PFC controller is enabled, the

error amplifier begins to source its maximum output current,

V

CC

falls below V

and the controller turns off before

CC(off)

the auxiliary winding powers up the controller. The total I

current after the flyback controller is enabled (I

CC

plus

CC3

I

) must be considered to correctly size C

. It is

VCC

CC(FDRV)

often useful to connect a small V capacitor (C1) directly

CC

to the V pin, while a larger capacitor (C2) is connected to

CC

the V pin through a diode and charged by the aux winding.

CC

This allows minimum startup time while providing enough

I

, (typically 20 mA) to linearly charge the PControl

EA(MAX)

V

CC

capacitance to operate during light load conditions.

pin capacitor (C

charges. An internal grounding switch on the PControl pin

is turned on each time the PFC controller is disabled, and

). Soft−start is achieved as C

PControl

This implementation is shown in Figure 3 and the startup

sequence is shown in Figure 4.

turned off when it is enabled. This ensures that C

is

PControl

always fully discharged at the beginning of soft−start.

As the PFC stage approaches regulation on the output, the

error amplifier output current, I , gradually reduces to

EA

0 mA. Once the output is in regulation and I reaches 0 mA,

EA

the IENABLE pin is set to V

(typically 5 V).

IENABLE(high)

V_CCMANAGEMENT

When power is initially applied to the application, the V

CC

capacitor (C ) begins charging through a resistor

VCC

connected to the high voltage line (V ). The resistor value

in

must be chosen so that the charging current is greater than

the IC bias current during startup. The maximum value for

the startup resistor is calculated using Equation 1.

V_in

(eq. 1)

R_start

+

I_CC5

where V is the rectified dc input voltage and I

is the IC

in

CC5

bias current during startup (20 mA maximum).

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10

NCP1927

V

Fault

Occurs

Device

Restarts

in

VCC

ON

R

start

VCC

OFF

D1

D2

C2

Fault is Reset

Aux Winding

+

C1

time

I

DRV

CC

V

CC

ICC

2

ICC

4

NCP1927

ICC

5

time

Figure 5. V_CCDuring a V_CCHiccup

Figure 3. Operation with Dual V_CCCapacitors

SHUTDOWN PIN

The Shutdown pin allows for external disabling of the

NCP1927. When V is pulled above the shutdown

Shutdown

V

CC

threshold, V

(typically 1.0 V), both the flyback and

SHDN

V

PFC drive outputs are immediately turned off, and a V

CC(on)

CC

hiccup occurs (see Figure 5). When V reaches V

,

CC

CC(on)

V

CC(off)

the cycle repeats unless the NCP1927 is taken out of

shutdown. This is achieved when V becomes less

Shutdown

V

CC(reset)

than V . The NCP1927 leaves shutdown mode and will

SHDN

start when V reaches V

power−on sequence. The V behavior during shutdown

according to the initial

CC

CC(on)

0 V

DRV

Time

CC

mode is shown in Figure 6.

PDRV

FDRV

Time

I

CC

I

+I

CC1 CC(FDRV) CC(PDRV)

I

+

CC3 ICC(FDRV)

I

CC5

Figure 4. Startup Sequence of the NCP1927

FAULT MANAGEMENT

When the NCP1927 detects a non−latching fault

(Shutdown Mode, TSD, and Flyback Overload), the drivers

are disabled, and V falls towards V

internal current consumption. Once V

due to the IC

falls below

CC

CC(off)

CC

V , the fault is reset and the IC internal current

CC(off)

consumption is reduced to the startup current, I . V

CC5

CC

begins to rise as if power was initially applied and the device

resumes normal operation once V reaches V . This

CC

CC(on)

cycle between V

and V

is commonly referred to

CC(on)

CC(off)

as a V hiccup and is shown in Figure 5.

CC

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11

NCP1927

(125 Hz typical). The frequency jittering is fully disabled

during soft−start and frequency foldback. Figure 7 depicts

the jittering operation.

f

OSC

f

+ f

MOD

OSC

Nominal f_OSC

- f

f

OSC MOD

Time

8 ms

(125 Hz)

Figure 7. Frequency Jittering

Current Sensing

NCP1927 is a current−mode controller, which means that

the feedback voltage sets the peak current flowing in the

transformer and the MOSFET. This is done through the

PWM comparator. The switch current is sensed across a

resistor and the resulting voltage is applied to the FCS pin.

It is then applied to one input of the PWM comparator

through a 250 ns leading edge blanking (LEB) block. On the

Figure 6. V_CCBehavior During Shutdown Mode

THERMAL SHUTDOWN

When the junction temperature exceeds T

(140°C

TSHDN

other input, the feedback voltage divided by K

(typically

minimum), a temperature sensing circuit disables the gate

drives and a V hiccup occurs (see Figure 5). When V

FFB

5) sets the current limit threshold. When the current reaches

this threshold, the output driver is turned off. A dedicated

comparator monitors the current sense voltage, and if it

CC

reaches V , the cycle repeats unless the junction

CC(on)

temperature drops below T

.

TSHDN

reaches the maximum value, V

(typically 0.7 V), the

ILIM

CLAMPED DRIVERS

The NCP1927 includes two powerful MOSFET drivers

capable of sourcing 800 mA and sinking 1200 mA each.

output driver is turned off immediately. This occurs even if

the limit imposed by the feedback voltage is higher than

V . Figure 8 shows the schematic of the current sense

ILIM

Since V is rated at 30 V (maximum), each driver output

CC

circuit.

V

is internally clamped to 16 V (maximum) to allow the use of

20 V MOSFETs.

FFB(open)

R

FFB

FLYBACK CONTROLLER

FFB

FCS

The NCP1927 flyback stage implements a standard

current mode architecture where the switch−off event is

dictated by the peak current setpoint.

K

÷

FFB

V

CC

Oscillator with Maximum Duty Ratio and Frequency

Jittering

The NCP1927 flyback controller includes an oscillator

that sets the switching frequency with an accuracy of

$7.7%. The maximum duty ratio of the FDRV pin is 80%

(typical).

FDRV

t

Q

R

S

LEB

f

(OSC)

V

ILIM

In order to improve the EMI signature, the switching

Figure 8. Current Sense Block Schematic

frequency jitters at f

($6% typical) around its nominal

MOD

value, with a triangle−wave shape and at a frequency of f

jitter

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12

NCP1927

Short−Winding Protection

soft−start is applied when V reaches V

. The current

CC(on)

CC

Under some conditions, like a transformer winding or

output diode short−circuit, the primary current increases

limit threshold is linearly increased from 0 until it reaches

(in 4.0 ms), or until the feedback loop imposes a

setpoint lower than the one imposed by the soft−start (the 2

comparator outputs are OR’ed together). Figure 10 shows a

typical startup sequence.

V

ILIM

above V

before the LEB timer expires. To prevent

ILIM

dangerously high current from flowing, an additional

comparator senses when V reaches V . Once this

FCS

CS(stop)

comparator toggles, the controller immediately latches off.

The effect of latching off the IC is identical to shutdown

VFB

mode, however, the V cycle repeats indefinitely until the

CC

input power is removed and C

is allowed to discharge

VCC

below V

. When input power is reapplied, the

CC(reset)

NCP1927 operates according to the initial power−on

sequence. The V behavior during short winding

protection is shown in Figure 9.

CC

Time

VFB takes

Soft−start ramp

over soft−start

V_ILIM

Short

Winding

Detected

FCS Pin

V_CS(stop)

Time

t_SSTART

CS Setpoint

time

V_CC

V_CC(on)

V_ILIM

V_CC(off)

Time

time

DRV

Figure 10. Soft−Start Timing

Ramp Compensation

Ramp compensation is a known method for preventing

subharmonic oscillations. These oscillations take place at

half the switching frequency and occur only during

continuous conduction mode (CCM) when the duty ratio is

greater than 50%. To prevent these oscillations, one

typically lowers the current loop gain by injecting between

50% and 75% of the inductor downslope. This is done by

I_CC

I_CC2

I_CC4

I_CC6

time

Figure 9. V_CCBehavior During Short Winding

Protection

inserting a resistor (R ) between the FCS pin and the

SCOMP

current sense resistor. Figure 11 shows an example of this.

The ramp signal is disconnected from the FCS pin during the

off time.

Feedback

The ratio from the feedback voltage to the current limit

threshold, K (typically 5), determines the peak current

I

ramp(MAX)

FFB

0 mA

ON

limit threshold. This means that the feedback voltage when

the current limit threshold equals V is 3.5 V (typical).

ILIM

The FFB pin is connected to the internal V rail through

a resistor divider. To ease system design, the FFB pin is

represented by a Thevenin equivalent circuit containing a

DD

FDRV

Reset

I

ramp

R

SCOMP

+

−

L.E.B.

voltage source and series resistor, V

(typically 5 V)

FFB(open)

FCS

and R

(typically 20 kW).

FFB

R

sense

from FFB Setpoint

Soft−Start

The NCP1927 flyback controller features an internal

soft−start circuit. Every time the controller starts (i.e. the

controller was off and starts, or restarts due to a fault), a

Figure 11. Inserting a Resistor

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13

NCP1927

Overcurrent

applied

Fault

disappears

When calculating the proper value for R

, it is

SCOMP

Output Load

Max Load

necessary to express the internal ramp signal in terms of its

slope (dI /dt). This is done using Equation 3.

OSC

I

_ramp(MAX)@ f_OSC

time

dl_OSC

dt

Fault Flag

(eq. 3)

+

D_MAX

Fault

timer

starts

The inductor downslope (dV

current sense resistor (R

Equation 4.

/dt) projected across the

P(off)

V_CC

) is then calculated using

sense

Restart

V_CC(on)

At V

CC(on)

N

S

V_CC(off)

ǒ

Ǔ

@

V

_out) V_D

Fault is

reset

dV_P(off)

N

(eq. 4)

P

time

+ R_sense

@

DRV

dt

L_P

Controller

stops

where V is the forward drop of the output rectifier, N /N

P

D

S

is the turns ratio, and L is the primary inductance.

P

Fault Timer

80 ms

Using the results from Equations 3 and 4, R

calculated using Equation 5.

can be

SCOMP

dV

time

P(off)

t_FOVLD

a @

dt

(eq. 5)

R_SCOMP

+

Figure 12. Operation During Overload

dI

OSC

dt

where a is the percentage of dV /dt to be injected.

P(off)

Frequency Foldback

In order to improve the efficiency at light load conditions,

the frequency of the internal oscillator is linearly reduced

Overload Protection with Fault Timer

When an overload occurs on the output of the power

supply, the feedback loop asks for more power than the

controller can deliver, and the current limit threshold

from its nominal value down to f

(typically

OSC(MIN)

26 kHz). The frequency foldback starts when the voltage on

the FFB pin goes below V , and is completed before V

fold

FFB

reaches V . When this event occurs, a fault timer

ILIM

reaches V . The current−mode control remains active

FSKIP

(t

) is enabled.

FOVLD

while the oscillator frequency decreases. This is shown in

Figure 13.

When the timer expires, FDRV pulses are stopped, the

PFC is disabled, and a V hiccup occurs. When V

CC

reaches V

, the controller starts according to the initial

CC(on)

Oscillator Frequency

f_OSC

power−on sequence. If the overload is still present, the fault

timer continues to run and the cycle repeats when it expires.

The fault timer is reset if the current limit threshold goes

Skip

back below V

. A short delay, t , is added to

ILIM delay(FOVLD)

f_OSC(MIN)

prevent the fault timer from resetting due to noise. This

autorecovery operation is depicted in Figure 12.

FFB

V_FSKIP

V_fold

Figure 13. Switching Frequency as V_FFBDecreases

Skip Cycle Mode with Soft−Skip

When the feedback voltage reaches V

while

FSKIP

decreasing, skip mode is activated and the driver stops

switching. While the driver is disabled, V begins to rise.

FFB

As soon as V

rises above V

+ V

, the

FFB

FSKIP

FSKIP(HYS)

driver starts to switch again, but the duty ratio is gradually

increased from nearly 0% over a short Soft−Skip duration

(t

). This is accomplished by comparing the current

SSKIP

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14

NCP1927

sense signal to an internal ramp generated by the Soft−Skip

mode instead of current mode. Once the CS signal reaches

the feedback voltage, the controller resumes normal

operation in current mode. The skip mode block diagram is

shown in Figure 14. The ramp timing and overall timing

diagrams are shown in Figures 15 and 16.

timer instead of the feedback voltage. Since the LEB of the

FCS Pin prevents operation at nearly 0% duty ratio, the

controller instead compares the soft−skip ramp to an internal

sawtooth signal generated by the oscillator (not subjected to

LEB). This causes the controller to operate briefly in voltage

Soft−skip ramp

Sawtooth

t

Reset

SSKIP

Oscillator

D

MAX

V

FSKIP

S

Q

FDRV stage

R

K

FFB

FCS

+

−

+

t

LEB

Figure 14. Skip Cycle with Soft−Skip Architecture

V_FFB

V_fold

V_FSKIP(HYS)

V_FSKIP

During the Soft−Skip duration if the feedback voltage

goes above V , the Soft−Skip ends instantaneously

fold

allowing the controller to operate in current mode.

This transient load detection feature avoids large output

drops if a load transient occurs while the controller is in skip

mode.

Time

Enters

Soft−Skip

FDRV

Exits

Soft−Skip

Time

CS Setpoint

Soft−Skip

Time

Figure 15. Skip Cycle with Soft−Skip Timing Diagram

Figure 16. Soft−Skip Timing Diagram

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15

NCP1927

PFC CONTROLLER

ideal choice for medium power PFC boost stages because it

combines the lower peak currents of CCM operation with

the zero current switching of DCM operation. The operation

and waveforms in a PFC boost converter are illustrated in

Figure 17.

The PFC stage operates in critical conduction mode

(CrM). CrM occurs at the boundary between discontinuous

conduction mode (DCM) and continuous conduction mode

(CCM). In CrM, the driver on time is initiated when the

boost inductor current reaches zero. CrM operation is an

Diode Bridge

I

L

V

drain

in

I

L

+

L

+

V

out

−

The power switch is ON

The power switch is OFF

The coil current flows through the diode. The coil voltage is (V

The power switch being about zero, the input voltage

is applied across the coil. The coil current linearly

−

out

V ) and the coil current linearly decays with a (V − V )/L slope.

in

out

in

increases with a (V /L) slope.

in

Coil

Current

(V − V )/L

Critical Conduction Mode:

Next current cycle starts as

soon as the core is reset.

out

in

V /L

in

I

L(peak)

time

V

drain

V

out

V

in

If next cycle does not

start then V rings

drain

towards V

in

time

Figure 17. Schematic and Waveforms of an Ideal CrM Boost Converter

When the switch is closed, the inductor current increases

linearly to its peak value. When the switch opens, the

inductor current linearly decreases to zero. At this point, the

constant on time CrM control in a cost−effective and robust

manner.

drain voltage of the switch (V

) begins to drop. If the next

drain

V (t)

in

V

switching cycle does not start, the voltage rings with a

dampened frequency around Vin. A simple derivation of

equations (such as those found in AND8123) leads to the

result that good power factor correction in CrM operation is

achieved when the on time is constant across a single ac

cycle. Equation 6 shows the relationship between on time

and system operating conditions.

in(peak)

I

L(peak)

I (t)

L

I

in(peak)

I (t)

in

2 @ P_out@ L

time

(eq. 6)

t_on

+

h @ Vac²

ON

where P is the output power, L is the boost inductor

inductance and h is the system efficiency.

out

MOSFET

OFF

A plot of the MOSFET on/off time over an ac line cycle

is illustrated in Figure 18. The MOSFET off time varies

based on the instantaneous line voltage, but the on time is

Figure 18. Inductor Waveform During CrM Operation

constant. This causes the peak inductor current (I

) to

L(peak)

follow the ac line voltage. The NCP1927 implements

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16

NCP1927

Output Regulation

where I

is the resistor divider current.

divider

The NCP1927 error amplifier (EA) consists of an

operational transconductance amplifier (OTA) with the

inverting input connected to the PFB pin and the output

connected to the PControl pin to regulate the output voltage.

It features a typical transconductance (gm) of 200 mS and a

Using R

, R

is calculated with Equation 9.

PFB1 PFB2

R

_PFB1@ V_REF

_out* V_REF

(eq. 9)

R_PFB2

+

V

Compensation

maximum output (I

and I ) of $20 mA

EA(SNK)

EA(SRC)

A compensation network must be connected between the

PControl pin and ground due to the nature of an active PFC

circuit. The PFC stage generates a sinusoidal current from

the ac line voltage and provides the load with a power that

matches the average demand. When the input voltage is at

its peak, the PFC stage delivers more power than the load

requires, and the output capacitor charges. Conversely,

when the input voltage is at a valley, the load requires more

power than the PFC stage can deliver, and the output

capacitor discharges. The situation is depicted in Figure 20.

(typical). The non−inverting input is connected internally to

a voltage reference (V ) with a typical value of 2.5 V

REF

$1.5% over process and temperature. During normal

operation, the voltage on the PControl pin varies between

V

(typically 0.6 V) and V

PControl(MIN)

PControl(MAX)

(typically 5.6 V). A simplified diagram of the OTA circuit

is shown in Figure 19.

V (t)

in

I (t)

in

time

C

PControl

P (t)

in

P

out

(t)

Figure 19. Error Amplifier and On Time Regulation

Circuits

time

V

out

(t)

A resistor divider from the boost output to the PFB pin

provides a scaled−down representation of the output voltage

(V ) to the EA. When V is in regulation, V equals

out

PFB

V

. If V drops below regulation, the feedback voltage

REF

out

Figure 20. Output Voltage Ripple for a Constant

Output Power

(V ) drops and the EA sources current until V

towards V . This increases the control voltage (V

returns

PFB

)

REF

PControl

and the on time of the driver (t ), which in turn increases the

on

This creates a ripple on the output with frequency equal to

power delivered to the load and brings V back into

out

twice the line frequency (f ). Since the on time must

line

regulation. Alternatively, if V (and also V ) is too high,

out

PFB

remain constant during each ac line cycle to maintain good

power factor correction, the EA must reject the output

ripple. This is commonly achieved by setting the regulation

bandwidth below 20 Hz. A type 1 compensation network is

typically used for simplicity, as it only requires a single

the EA sinks current and V

decreases, thus

PControl

shortening t until V returns to regulation. The output

on

out

voltage is calculated using Equation 7.

R

_PFB1) R_PFB2

(eq. 7)

V

_out+ V_REF@

R_PFB2

capacitor (C

) connected between the PControl pin

PControl

and ground (see Figure 19). For a type 1 network, C

is calculated using Equation 10.

PControl

where R

is the upper resistor of the resistor divider, and

PFB1

R

PFB2

is the lower resistor.

gm

The impedance of the feedback network determines its

noise immunity and power dissipation. While a lower

impedance provides better noise immunity, it also increases

power dissipation. Once the divider current is chosen, R

is determined using Equation 8.

(eq. 10)

C_PControl

+

2p @ f_c

where gm is the transconductance of the EA (typically

PFB1

200 ^mS), and f is the desired crossover frequency (typically

c

less than 20 Hz).

V_out

(eq. 8)

R_PFB1

+

I_divider

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NCP1927

Transient Load Detection

bulk capacitor voltage ripple, the on time remains constant

over the entire ac line cycle.

The maximum on time of the controller occurs when

Due to the low bandwidth of the regulation loop, fast load

transients may result in output voltage over and undershoots.

Overshoots are limited by the overvoltage protection (see

OVP section). To control the undershoots, an internal

comparator monitors the ratio between V

When it is lower than V

V

is at its maximum value. Therefore, C must be

PControl

t

sized to ensure that the required on time can be achieved at

maximum output power and minimum input voltage. The

maximum on time is calculated using Equation 11.

and V

(95.5% typical),

.

PFB

REF

/V

OLOW REF

I

(240 mA typical) is connected to the PControl

PControl(boost)

C_t@ V_PCT(MAX)

pin to speed up the charging of C

. This has the effect

PControl

(eq. 11)

t_on(MAX)

+

I_PCT(charge)

of increasing the EA gain by a factor of approximately 13.

The transient load detection circuit is disabled during the

startup sequence of the PFC stage to prevent it from

interfering with the operation of the soft−start circuit.

where V

= 5 V (typical) and I

= 210 mA

PCT(MAX)

PCT(charge)

(typical).

Combining Equation 11 with Equation 6, results in

Equation 12.

On Time Control

Since the NCP1927 is designed to control a CrM boost

converter, the switching pattern consists of constant on

times and variable off times. The on time is set via an

2 @ P_out@ L @ I_PCT(charge)

(eq. 12)

C_t+

h @ Vac_LL²@ V_PCT(MAX)

external capacitor (C ) connected to the PCT pin. At the

t

Where, Vac is the minimum ac rms input voltage.

LL

beginning of each switching cycle, C is charged linearly by

t

I

(210 mA typical). An internal comparator

PCT(charge)

Off Time Control

monitors the voltage on the PCT pin (V ) and compares

The off time varies with the instantaneous line voltage and

is adjusted every cycle so that the inductor is demagnetized

before the next switching cycle begins. The inductor is

demagnetized once its current reaches zero. When this

happens, the drain voltage begins to drop. This is detected

by sensing the voltage across an inductor auxiliary winding.

This winding, commonly known as a zero crossing detection

(ZCD) winding, provides the NCP1927 with a scaled

version of the inductor voltage. Figure 22 shows a typical

ZCD winding arrangement.

PCT

it to an internal regulation limit set by V

. The internal

down by a voltage

PControl

limit is determined by shifting V

PControl

equal to one diode drop (0.6 V typical) to account for the

offset of the control voltage range. Once this level is

exceeded, the drive is turned off. C is then discharged within

t

(maximum 500 ns) and held low until the

CPCT(discharge)

beginning of the next switching cycle. This sequence is

shown in Figure 21.

V

PControl

V

DD

PWM

−

I

PCT(charge)

PCT

Ct

+

t

on

PDRV

Figure 22. ZCD Winding Implementation

V

PCT

V

− 0.6 V

While the switch is on, a negative voltage appears at the

PZCD pin. When the switch turns off, the ZCD voltage

swings positive, arming the ZCD detector. The ZCD voltage

remains positive until the inductor current falls to zero and

the inductor is demagnetized. The voltage then drops to 0 V

and triggers the ZCD detector to begin the next switch cycle.

The arming threshold of the ZCD detector is typically 1.4 V

PControl

t

on

PDRV

(V

) and the triggering threshold is typically 0.7 V

ZCD(rising)

).

ZCD(falling)

The PZCD pin is internally clamped to V

CL(POS)

Figure 21. On Time Generation

(typically 10 V) and V

(typically −0.7 V). A resistor

CL(NEG)

in series with the PZCD pin is required to limit the current

Since V

varies with the RMS line voltage and

into the pin and prevent it from exceeding 3 mA at V

PControl

CL(POS)

output load, this naturally satisfies Equation 6. If the values

of compensation components are sufficient to filter out the

or −2 mA at V

waveforms.

. Figure 23 shows typical ZCD

CL(NEG)

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18

NCP1927

V

protection keeps the output voltage within an acceptable

range.

While traditional PFC controllers often use one single pin

PDRV

time

for both under/overvoltage protections and feedback, the

NCP1927 uses a dedicated pin for undervoltage protection

(UVP) and OVP. This configuration allows the

implementation of two separate feedback networks as

shown in Figure 24.

V

drain

V

out

V

out

V

PZCD

V

CL(POS)

ZCD(rising)

ZCD(falling)

R

POVUV1

POVUV2

PFB1

PFB2

V

PFB

V

CL(NEG)

ZCD Winding

ZCD(off)

POVUV

V

time

V

ZCD(on)

Figure 23. Voltage Waveforms for Zero Current

Detection

Figure 24. Configuration with Two Separate

Feedback Networks

During startup, there are no ZCD transitions to enable the

The double feedback configuration provides an increased

level of safety, as it protects the PFC stage even if there is a

failure of one of the two feedback arrangements.

PFC switch. A watchdog timer, t , enables the PFC driver

start

when no switch pulses are detected before it times out

(180 ms typical). The watchdog timer is also useful while

operating at light load because the amplitude of the ZCD

signal may be too small to cross the ZCD thresholds.

A 1 mA (typical) current source, I , pulls the POVUV

UVP

pin voltage below the UVP threshold if the pin is left floating

to ensure the PFC stage will be protected.

A comparator connected to the POVUV pin provides the

OVP protection. The output voltage that activates the OVP

fault detection is calculated using Equation 13.

Frequency Clamp

Since the NCP1927 operates in CrM mode over the ac line

half cycle, the switching frequency naturally increases as the

line voltage approaches zero. In order to minimize the PFC

inductor size, the NCP1927 features an internal oscillator

that clamps the maximum switching frequency to f

(typically 385 kHz).

R

) R

POVUV2

POVUV1

R

V

+ V

@

) I

@ R

UVP

POVUV1

out(OVP)

OVP

POVUV2

clamp

(eq. 13)

where V

is the peak value of the output voltage

out(OVP)

Overvoltage/Undervoltage Protection

including ripple and V

typical).

When the OVP comparator is activated, the PFC driver is

immediately turned off. Once the feedback voltage drops

is the OVP threshold (2.5 V

OVP

The low bandwidth of the PFC stage feedback network

causes it to have a slow transient response. This increases the

risk of overshoots during transient conditions (startup, load

steps, etc.). For safe operation, overvoltage protection

(OVP) is utilized to prevent the output voltage from rising

too high and overstressing the power stage components. The

below the hysteresis of V

(V

), the PFC driver

OVP

OVP(HYS)

is re−enabled. This helps to limit overshoots on the output

during startup and transient loads. Figure 25 depicts the

operation of the OVP circuitry, while Figure 26 shows the

internal block diagram.

NCP1927 detects high V levels and disables the driver

out

until the output voltage returns to nominal levels. This

http://onsemi.com

19

NCP1927

V

out

power path to the bulk capacitor (i.e. the capacitor is unable

to charge up) or if the controller is unable to sense the output

voltage (i.e. the POVUV Pin is floating). The output voltage

that causes a UVP fault is calculated using Equation 14.

V

out(nom)

time

R

) R

POVUV2

POVUV1

R

V

+ V

@

) I

@ R

UVP

out(UVP)

UVP

POVUV1

(eq. 14)

PDRV

POVUV2

Overcurrent Protection (OCP)

The NCP1927 contains an OCP circuit to protect the PFC

stage by limiting the coil current. A current sense resistor

OVP

(R

sense

) is inserted in the return path to generate a negative

voltage proportional to the coil current (V

) as

Rsense

portrayed by Figure 27. The circuit uses V

to detect

Rsense

when the coil current exceeds its maximum permissible

level. To do so, the circuit incorporates an operational

amplifier that sources the current necessary to maintain the

Figure 25. OVP Timing Diagram

PCS pin at zero volts. A resistor (R ) inserted between the

PCS

PCS pin and R

allows the current sourced by the PCS

sense

pin (I ) to be adjusted via Equation 15.

V

PCS

out

OVP

UVP

ǒ

Ǔ

₎ǒ_R

Ǔ _{+ 0}

_PCS@ I_PCS

(eq. 15)

− R_sense@ I_L

R

where I is the current flowing through the boost inductor.

POVUV1

L

Rearranging Equation 15 allows I

using Equation 16.

to be calculated

PCS

POVUV

R_sense

I_PCS

+

@ I_L

R

(eq. 16)

POVUV2

R_PCS

If I

exceeds I

(typically 250 mA), an OCP

PCS

OCP

condition is detected and the driver is turned off. The driver

remains off until I falls below I , and the next ZCD

Figure 26. POVUV Pin Block

PCS

OCP

transition occurs or the watchdog timer expires. The

The NCP1927 detects a UVP fault when the output

voltage falls below the UVP limit. During a UVP fault, the

drive output and error amplifier (EA) are disabled, and

maximum coil current (I ) is calculated with

L(MAX)

Equation 17.

R_PCS

C

is discharged. It is important to note that the PFC

(eq. 17)

I_L(MAX)

+

@ I_OCP

PControl

R_sense

stage does not start if V

is lower than V . This

POVUV

UVP

protects the application when there is a problem with the

where I

is the OCP threshold current.

OCP

V

DD

I

PCS

To PDRV disable

I

> I

OCP

PCS

−

+

I

R

PCS

R

sense

I

L

Figure 27. Current Sense Block

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20

NCP1927

Skip Mode Operation

V_PSKIP

P_skip(lower)

+

@ P_out(MAX)

The NCP1927 automatically skips switching cycles when

the power demand drops below a given level. This is

accomplished by monitoring the internal offset PControl

voltage. This voltage is compared to the PCT ramp to control

the power level in a particular design. During normal

operation, the circuit generates the input line current

necessary for matching the load power demand. If the need

for power decreases, the regulation loop lowers the

regulation voltage to reduce the power delivery accordingly.

When the regulation voltage goes below a programmable

pre−set level, the PFC stage stops switching. This causes the

output voltage to decrease, and the regulation voltage to

increase. When the regulation voltage exceeds the skip

threshold, switching resumes.

2

(eq. 18)

(eq. 19)

Vac

LL

_{5 V @}ǒ Ǔ

Vac

V_PSKIP

P_skip(upper)

+

@ P_out(MAX)

2

Vac

LL

_{4.5 V @}ǒ Ǔ

Vac

where V

is the voltage applied to the PSKIP pin, Vac

is the minimum ac line voltage, Vac is the operating line

voltage, and P is the maximum output power.

The skip pin voltage is adjusted through a resistor to

ground using Equation 20.

PSKIP

LL

out(MAX)

V

_PSKIP+ I_PSKIP@ R_PSKIP

(eq. 20)

This operation allows the PFC stage to deliver 10% power

for 10% of the time, as opposed to 1% power for 100% of the

time. This skip cycle mode, also called controlled burst

operation, is much more efficient than a continuous power

flow since it drastically reduces the number of switching

pulses and their associated switching losses. To ensure

stability, hysteresis is added.

The PSKIP pin provides the possibility to adjust these

levels by connecting it through a single resistor to ground.

Since the skip threshold power levels can vary with line

voltage, they are calculated using Equations 18 and 19.

where I

(30 mA typical) and R

to ground.

is the value of the internal current source

PSKIP

is the external resistor connected

PSKIP

If desired, skip mode can be easily disabled by connecting

the PSKIP pin directly to ground. If the PSKIP pin is left

floating, V

and disable the drive. Since the PControl Pin is low during

startup, the PFC skip mode is disabled until the PFC output

reaches regulation and the IENABLE Pin is high. A

simplified schematic of the PSKIP pin is shown in

Figure 28.

will rise towards the internal voltage rail

PSKIP

OTA Output

PControl

To PWM Comparator

R

PFAULT

9*R

V

DD

PSKIP

R

PSKIP

SKIP

PFC_OK

Figure 28. Schematic for PSKIP Pin

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21

NCP1927

R

Go To Standby Pin

limit

GTS

VCC_AUX

The Go To Standby (GTS) pin is used to disable the PFC

stage during system standby based on the flyback stage load

condition. This can be done by connecting it to the flyback

stage feedback pin (FFB) through a resistor divider or by

directly driving the pin with an optocoupler. These

implementations are shown in Figures 29 and 30.

C

GTS

from secondary side

Figure 30. GTS Implementation with Optocoupler

The GTS pin contains an internal pull down resistor, R

GTS

(typically 200 kW), for use with an optocoupler and to

ensure the PFC is disabled if the pin is floating.

IENABLE Pin

The IENABLE pin is designed to drive an optocoupler

that enables the Flat Panel TV backlight inverter once the

PFC stage reaches regulation. The NCP1927 achieves this

by monitoring the current sourced by the EA. Once this

current drops to 0 mA, the IENABLE pin voltage switches

GTS

FFB

R

GTS1

GTS2

to V

(typically 5.0 V). This operation is shown

IENABLE(high)

in Figure 31.

V_out

V_out(MAX)

V_out(NOM)

V_out(MIN)

C

GTS

Undershoot from Inverter

Load

time

I_EA(out)

Figure 29. GTS Implementation with Feedback Pin

0 μA

The resistor divider from the FFB pin is used to setup the

−20 μA

GTS power level threshold. When V

is brought below

GTS

the GTS threshold, V

switching and enter standby mode. It remains in standby

, the PFC controller stops

standby

time

V_IENABLE

5 V

until V

is brought above the hysteresis of V

GTS

standby

(V

). A timer is included on the GTS pin to ensure

standby(HYS)

Inverter

Starts

transients on the flyback converter do not trigger GTS.

However, the PFC must come out of standby as soon as

possible if there is a request to turn on the TV. Therefore, the

timer is bypassed when coming out of standby. The FFB

voltage at which the PFC enters GTS is expressed using

Equation 21.

0 V

time

Figure 31. IENABLE Pin Timing

A separate comparator on the PFB pin is used to protect

the inverter from undervoltage conditions by detecting

when the PFB voltage falls below V

R

_GTS1) R_equiv

(eq. 21)

V

_FFB(GTS)+ V_GTS@

. When this occurs,

R_equiv

disable

the IENABLE pin voltage switches to V

the result from Equation 7, the output threshold that sets the

IENABLE pin low can be calculated with Equation 23.

. Using

IENABLE(low)

where R

is the parallel resistor combination of R

and

equiv

GTS

R

GTS2

and is calculated using Equation 22.

R

_GTS@ R_GTS2

V

_out@ V_disable

(eq. 22)

R_equiv

+

(eq. 23)

V_out(disable)

+

R

_GTS) R_GTS2

V_REF

If direct control of the PFC standby mode is desired, the

GTS pin can instead be driven with an optocoupler from the

secondary side to force the PFC stage in and out of standby

where V

is the disable threshold (1.865 V typical).

disable

The IENABLE pin can also be used as a voltage reference.

To filter noise, a decoupling capacitor (C ) may be

connected to the pin.

REF

mode. A resistor (R ) is placed in series with the

limit

optocoupler to limit the current into the GTS pin.

http://onsemi.com

22

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

DATE 29 DEC 2006

SCALE 1:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−A−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

16

9

8

−B−

P 8 PL

M

S

B

0.25 (0.010)

1

MILLIMETERS

INCHES

MIN

0.386

DIM MIN

MAX

0.393

0.157

0.068

0.019

0.049

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00

G

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

F

R X 45

K

_

G

J

1.27 BSC

0.050 BSC

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

K

M

P

R

C

7

0

_

−T−

SEATING

PLANE

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

J

M

D

16 PL

M

S

A

0.25 (0.010)

T B

STYLE 1:

STYLE 2:

STYLE 3:

STYLE 4:

PIN 1. COLLECTOR

2. BASE

3. EMITTER

4. NO CONNECTION

5. EMITTER

6. BASE

7. COLLECTOR

8. COLLECTOR

9. BASE

10. EMITTER

11. NO CONNECTION

12. EMITTER

13. BASE

PIN 1. CATHODE

2. ANODE

3. NO CONNECTION

4. CATHODE

5. CATHODE

6. NO CONNECTION

7. ANODE

8. CATHODE

9. CATHODE

10. ANODE

11. NO CONNECTION

12. CATHODE

13. CATHODE

14. NO CONNECTION

15. ANODE

PIN 1. COLLECTOR, DYE #1

2. BASE, #1

3. EMITTER, #1

4. COLLECTOR, #1

5. COLLECTOR, #2

6. BASE, #2

PIN 1. COLLECTOR, DYE #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. COLLECTOR, #3

6. COLLECTOR, #3

7. COLLECTOR, #4

8. COLLECTOR, #4

9. BASE, #4

10. EMITTER, #4

11. BASE, #3

12. EMITTER, #3

13. BASE, #2

7. EMITTER, #2

8. COLLECTOR, #2

9. COLLECTOR, #3

10. BASE, #3

11. EMITTER, #3

12. COLLECTOR, #3

13. COLLECTOR, #4

14. BASE, #4

SOLDERING FOOTPRINT

14. COLLECTOR

15. EMITTER

16. COLLECTOR

14. EMITTER, #2

15. BASE, #1

16. EMITTER, #1

15. EMITTER, #4

16. COLLECTOR, #4

8X

6.40

16. CATHODE

16X

1.12

STYLE 5:

STYLE 6:

STYLE 7:

PIN 1. SOURCE N‐CH

PIN 1. DRAIN, DYE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. DRAIN, #3

6. DRAIN, #3

7. DRAIN, #4

8. DRAIN, #4

9. GATE, #4

PIN 1. CATHODE

2. CATHODE

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

7. CATHODE

8. CATHODE

9. ANODE

2. COMMON DRAIN (OUTPUT)

3. COMMON DRAIN (OUTPUT)

4. GATE P‐CH

5. COMMON DRAIN (OUTPUT)

6. COMMON DRAIN (OUTPUT)

7. COMMON DRAIN (OUTPUT)

8. SOURCE P‐CH

1

16

16X

0.58

9. SOURCE P‐CH

10. SOURCE, #4

11. GATE, #3

12. SOURCE, #3

13. GATE, #2

14. SOURCE, #2

15. GATE, #1

16. SOURCE, #1

10. ANODE

11. ANODE

12. ANODE

13. ANODE

14. ANODE

15. ANODE

16. ANODE

10. COMMON DRAIN (OUTPUT)

11. COMMON DRAIN (OUTPUT)

12. COMMON DRAIN (OUTPUT)

13. GATE N‐CH

14. COMMON DRAIN (OUTPUT)

15. COMMON DRAIN (OUTPUT)

16. SOURCE N‐CH

1.27

PITCH

8

9

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB42566B

SOIC−16

PAGE 1 OF 1

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


型号：	NCP1927DR2G
厂家：	ONSEMI
描述：	PFC and Flyback Controller for Flat Panel TVs 功率因数校正电视
文件：	总24页 (文件大小：613K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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