NCP252163MNTWG [ONSEMI]
Integrated Driver and MOSFET;
| 型号： | NCP252163MNTWG |
| 厂家： | 
ONSEMI |
| 描述： | Integrated Driver and MOSFET |
| 文件： | 总20页 (文件大小：1026K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Integrated Driver and
MOSFET
PQFN31 5X5, 0.5P
CASE 483BR
NCP252163
The NCP252163 integrates a MOSFET driver, high−side MOSFET
and low−side MOSFET into a single package.
MARKING DIAGRAM
The driver and MOSFETs have been optimized for high−current
DC−DC buck power conversion applications. The NCP252163
integrated solution greatly reduces package parasitics and board space
compared to a discrete component solution.
Pin 1
NCP
252163
AWLYYWWG
G
Features
• Capable of Average Currents up to 60 A
• Capable of Switching at Frequencies up to 2 MHz
• Compatible with 3.3 V or 5 V PWM Input
• Responds Properly to 3−Level PWM Inputs
• Option for Zero Cross Detection with 3−Level PWM
• Internal Bootstrap Diode
NCP252163
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Undervoltage Lockout
(Note: Microdot may be in either location)
®
• Supports Intel Power State 4
ORDERING INFORMATION
• Thermal Warning Output
• Thermal Shutdown
†
Device
Package
Shipping
• This is a Pb−Free Device
NCP252163MNTWG
PQFN31
3000 /
(Pb−Free)
Tape & Reel
Applications
• Desktop and All−in−One Computers, V−Core and Non−V−Core
DC−DC Converters
• High−Current DC−DC Point−of−Load Converters
• Small Form−Factor Voltage Regulator Modules
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
5 V
VIN
VCCD VCC
VIN
THWN
BOOT
Zero Current Detect Enable
DRVON from Controller
ZCD_EN
DISB#
PWM from Controller
SMOD from Controller
PWM
VOUT
SMOD#
CGND
VSW
PGND
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
June, 2022 − Rev. 0
NCP252163/D
NCP252163
BLOCK DIAGRAM
VCCD 29
5
BOOT
8−11
VIN
3
VCC
LEVEL
SHIFT
UVLO
16−26
VSW
AGND
DEAD
TIME
CONTROL
7
PHASE
2
SMOD#
SHUTDOWN
WARNING
TEMP
SENSE
PWM
1
DISB#
31
LEVEL
SHIF
28
PGND
PGND
30
12−15
THWN
27
33
GL
GL
ZCD
CONTROL
32
AGND
4
CGND
Figure 2. Block Diagram
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2
NCP252163
PINOUT DIAGRAM
31 DISB#
30 THWN
29 VCCD
28 PGND
27 GL
VIN 9
VIN 10
VIN 11
32
AGND
33
GL
PGND 12
PGND 13
PGND 14
PGND 15
26 VSW
25 VSW
24 VSW
Figure 3. Pinout Diagram
Table 1. PIN LIST AND DESCRIPTION
Pin No.
Symbol
Description
1
PWM
PWM Control Input and Zero Current Detection Enable: When DISB# = Low, the internal resistor
divider will always be disconnected regardless SMOD# status.
2
SMOD#
Skip Mode pin. 3−state input (see Table 6):
SMOD# = High ³ State of PWM determine whether the NCP252163 performs ZCD or not.
SMOD# = Mid ³ Connects PWM to internal resistor divider placing a bias voltage on PWM pin.
Otherwise, logic is equivalent to SMOD# in the high state.
SMOD# = Low ³ Placing PWM into mid−state pulls GH and GL low without delay.
There is an internal pull−up resistor to VCC on this pin
Control Power Supply Input
3
4, 32
5
VCC
CGND, AGND
BOOT
NC
Signal Ground (pin 4 and pad 32 are internally connected)
Bootstrap Voltage
6
Open pin (not used)
7
PHASE
VIN
Bootstrap Capacitor Return
8−11
12−15, 28
16−26
27, 33
29
Conversion Supply Power Input
PGND
VSW
Power Ground
Switch Node Output
GL
Low Side FET Gate Access (pin 27 and pad 33 are internally connected)
Driver Power Supply Input
VCCD
THWN
30
Thermal warning indicator. This is an open−drain output. When the temperature at the driver die
reaches T
, this pin is pulled low.
THWN
31
DISB#
Output disable pin. When this pin is pulled to a logic high level, the driver is enabled. There is an
internal pull−down resistor on this pin.
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NCP252163
Table 2. ABSOLUTE MAXIMUM RATINGS (Electrical Information − all signals referenced to PGND unless noted otherwise.)
Pin Name / Parameter
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−5
Max
6.5
25
Unit
V
VCC, VCCD
VIN
V
BOOT (DC)
30
V
BOOT (< 20 ns)
BOOT to PHASE (DC)
VSW, PHASE (DC)
VSW, PHASE (< 20 ns)
All Other Pins
35
V
6.5
25
V
V
30
V
−0.3
V
VCC
+ 0.3
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
12.4
Unit
°C/W
°C/W
°C
Thermal Resistance (under onsemi Thermal Board)
q
JA
q
1.8
−
J
PCB
Operating Junction Temperature Range (Note 1)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Moisture Sensitivity Level
T
J
−40 to +150
−40 to +125
−55 to +150
1
T
A
°C
T
STG
°C
MSL
1. The maximum package power dissipation must be observed.
2. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM.
3. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM.
Table 4. RECOMMENDED OPERATING RANGES
Parameter
Supply Voltage Range
BOOT to PHASE
Pin Name
Conditions
Min
4.5
4.1
4.5
−
Typ
5.0
4.6
12
Max
5.5
5.1
16
Unit
VCC, VCCD
V
V
V
A
V
−
BOOT PHASE
Conversion Voltage
Continuous Output Current
VIN
F
= 1 MHz, V = 12 V,
−
55
SW
OUT
IN
V
= 1.0 V, T = 25°C
A
F
= 300 kHz, V = 12 V,
−
−
60
A
SW
IN
V
= 1.0 V, T = 25°C
OUT
A
Peak Output Current
Junction Temperature
Duration = 5 ms, Period = 10 ms
−
−
−
85
A
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 5. ELECTRICAL CHARACTERISTICS
(V
VCC
= V
= 5.0 V, V
= 12 V, V
= 2.0 V, C
= C
= 0.1 F unless specified otherwise) Min/Max values are valid for the
VCCD
VIN
DISB#
VCCD
VCC
temperature range −40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
VCC SUPPLY CURRENT
Operating
Symbol
Conditions
Min
Typ
Max
Unit
DISB# = 5 V, PWM = 400 kHz
DISB# = 5 V, PWM = 0 V
DISB# = 0 V, SMOD# = VCC
DISB# = 0 V, SMOD# = GND
VCC rising
−
−
1
−
2
2
mA
mA
mA
mA
V
No switching
Disabled
−
0.4
6
1
−
15
3.37
−
UVLO Start Threshold
UVLO Hysteresis
V
UVLO
2.89
150
−
−
mV
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NCP252163
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(V = V = 5.0 V, V = 12 V, V = 2.0 V, C = C = 0.1 F unless specified otherwise) Min/Max values are valid for the
VCC
VCC
VCCD
VIN
DISB#
VCCD
temperature range −40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
VCCD SUPPLY CURRENT
Enabled, No Switching
Disabled
Symbol
Conditions
Min
Typ
Max
Unit
DISB# = 5 V, PWM = 0 V
DISB# = 0 V
−
−
−
175
0.4
−
300
1
mA
mA
Operating
DISB# = 5 V, PWM = 400 kHz
30
mA
DISB# INPUT
Input Resistance
Upper Threshold
Lower Threshold
Hysteresis
To Ground
−
−
467
−
−
2.0
−
kW
V
V
UPPER
V
0.8
200
−
−
V
LOWER
V
− V
−
−
mV
ms
UPPER
LOWER
Enable Delay Time
Time from DISB# transitioning HI to
when VSW responds to PWM.
−
50
Disable Delay Time
Time from DISB# transitioning LOW
to when both output FETs are off.
−
21
50
ns
SMOD# INPUT
SMOD# Input Voltage High
SMOD# Input Voltage Mid−state
SMOD# Input Voltage Low
SMOD# Input Resistance
V
2.65
1.4
−
−
−
−
2.0
0.7
−
V
V
SMOD_HI
V
SMOD#_MID
V
−
V
SMOD_LO
R
Pull−up resistance to VCC
−
455
34
kW
ns
SMOD#_DOWN
SMOD# Propagation Delay,
Falling
T
SMOD# = Low to GL = 90%,
PWM = MID
−
42
SMOD#_PD_F
SMOD# Propagation Delay,
Rising
T
SMOD# = High to GL = 10%,
PWM = MID
−
22
30
ns
SMOD#_PD_R
PWM INPUT
Input Voltage High
V
2.65
1.4
−
−
−
−
2.1
0.7
−
V
V
PWM_HI
Input Mid−State Voltage
Input Low Voltage
V
PWM_MID
V
−
V
PWM_LO
Input Resistance
R
SMOD# = V
SMOD# = V
SMOD# = V
or V
10
−
−
MW
kW
V
PWM_HIZ
SMOD#_LO
SMOD#_HI
Input Resistance
R
68
1.7
13
−
PWM_BIAS
SMOD#_MID
SMOD#_MID
PWM Input Bias Voltage
Non−overlap Delay, Leading Edge
V
−
−
PWM_BIAS
T
T
GL Falling = 1 V to Gh−VSW
Rising = 1 V
−
−
ns
NOL_L
Non−overlap Delay, Trailing Edge
GH−VSW Falling = 1 V to GL
Rising = 1 V
−
12
−
ns
NOL_T
PWM Propagation Delay, Rising
PWM Propagation Delay, Falling
T
PWM = High to GL = 90%
−
−
−
13
47
14
35
52
25
ns
ns
ns
PWM,PD_R
T
PWM = Low to SW = 90%
PWM = Mid−to−Low to GL = 10%
PWM,PD_F
Exiting PWM Mid−state
Propagation Delay, Mid−to−Low
T
PWM_EXIT_L
Exiting PWM Mid−state
Propagation Delay, Mid−to−High
T
PWM = Mid−to−High to SW = 10%
−
13
25
ns
PWM_EXIT_H
ZCD FUNCTION
Zero Cross Detect Threshold
ZCD Blanking + Debounce Time
THERMAL WARNING
V
−
−
−6
−
−
mV
ns
ZCD
t
330
BLNK
Thermal Warning Temperature
Thermal Warning Hysteresis
Thermal Shutdown Temperature
T
Temperature at Driver Die
Temperature at Driver Die
−
−
−
150
15
−
−
−
°C
°C
°C
THWN
T
THWN_HYS
T
180
THDN
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NCP252163
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(V = V = 5.0 V, V = 12 V, V = 2.0 V, C = C = 0.1 F unless specified otherwise) Min/Max values are valid for the
VCC
VCC
VCCD
VIN
DISB#
VCCD
temperature range −40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
Parameter
THERMAL WARNING
Thermal Shutdown Hysteresis
THWM Open Drain Current
BOOST STRAP DIODE
Forward Voltage
Symbol
Conditions
Min
Typ
Max
Unit
T
−
−
25
−
°C
THDN_HYS
I
−
5
mA
THWN
Forward Bias Current = 2.0 mA
−
300
−
mV
LOW−SIDE DRIVER
Output Impedance, Sourcing
Output Impedance, Sinking
GL Rise Time
R
Source Current = 100 mA
Sink Current = 100 mA
GL = 10% to 90%
−
−
−
−
0.9
0.4
27
−
−
−
−
W
W
SOURCE_GL
R
SINK_GL
T
R_GL
ns
ns
GL Fall Time
T
F_GL
GL = 90% to 10%
13
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 6. LOGIC TABLE
INPUT TRUTH TABLE
DISB#
PWM
X
SMOD# (Note 4)
GH (not a pin)
GL
L
X
L
H
L
L
L
L
H
H
H
H
H
X
L
L
X
H or MID
L
H
MID
MID
ZCD (Note 5)
L (Note 6)
4. PWM input is driven to mid−state with internal divider resistors when SMOD# is driven to mid−state and PWM input is undriven externally.
5. GL goes low following 80 ns de−bounce time, 250 ns blanking time and then SW exceeding ZCD threshold.
6. There is no delay before GL goes low.
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NCP252163
TYPICAL PERFORMANCE CHARACTERISTICS
(Test Conditions: V = 12 V, V = P
= 5 V, V
= 1 V, L = 250 nH, T = 25°C and natural convection cooling,
OUT A
IN
CC
VCC
OUT
unless otherwise noted)
Figure 4. Safe Operating Area with 12 VIN
Figure 5. Safe Operating Area with 16 VIN
Figure 6. Power Loss vs. Output Current with 12
VIN
Figure 7. Power Loss vs. Output Current with 16
VIN
Figure 8. Power Loss vs. Switching Frequency
Figure 9. Power Loss vs. Input Voltage
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NCP252163
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(Test Conditions: V = 12 V, VCC = P
= 5 V, V
= 1 V, L = 250 nH, T = 25°C and natural convection cooling,
OUT A
IN
VCC
OUT
unless otherwise noted)
Figure 10. Power Loss vs. Driver Supply Voltage
Figure 11. Power Loss vs. Output Voltage
Figure 12. Power Loss vs. Output Inductor
Figure 13. Driver Supply Current vs. Switching
Frequency
Figure 14. Driver Supply Current vs. Driver Supply
Voltage
Figure 15. Driver Supply Current vs. Output
Current
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NCP252163
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(Test Conditions: V = 12 V, VCC = P
= 5 V, V
= 1 V, L = 250 nH, T = 25°C and natural convection cooling,
OUT A
IN
VCC
OUT
unless otherwise noted)
Figure 16. UVLO Threshold vs. Temperature
Figure 17. PWM Threshold vs. Driver Supply
Voltage
Figure 18. PWM Threshold vs. Temperature
Figure 19. SMOD Threshold vs. Driver Supply
Voltage
Figure 20. FCCM Threshold vs. Temperature
Figure 21. FCCM Pull−Up Current vs. Temperature
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NCP252163
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(Test Conditions: V = 12 V, VCC = P
= 5 V, V
= 1 V, L = 250 nH, T = 25°C and natural convection cooling,
OUT A
IN
VCC
OUT
unless otherwise noted)
Figure 22. Body Diode Forward Voltage vs.
Temperature
Figure 23. Driver Shutdown vs. Temperature
Figure 24. Driver Quiescent Current vs. Temperature
Theory of Operation
High−Side Driver
The NCP252163 is an integrated driver and MOSFET
module designed for use in a synchronous buck converter
topology. The NCP252163 supports numerous application
control definitions including ZCD (Zero Current Detect)
and alternately PWM Tristate control. A PWM input signal
is required to control the drive signals to the high−side and
low−side integrated MOSFETs.
The high−side driver drives an internal, floating
low−R N−channel MOSFET. The gate voltage for the
DS(on)
high side driver is developed by a bootstrap circuit
referenced to Switch Node (VSW and PHASE) pins.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor and resistor. When the
NCP252163 is starting up, the VSW pin is at ground,
allowing the bootstrap capacitor to charge up to VCCD
through the bootstrap diode (See Figure 1). When the PWM
input is driven high, the high−side driver turns on the
high−side MOSFET using the stored charge of the bootstrap
capacitor. As the high−side MOSFET turns on, the voltage
Low−Side Driver
The low−side driver drives an internal, ground−
referenced low−R
N−Channel MOSFET. The voltage
DS(on)
supply for the low−side driver is internally connected to the
VCCD and PGND pins.
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NCP252163
Zero Current Detect
at the VSW and PHASE pins rises. When the high−side
MOSFET is fully turned on, the switch node settles to VIN
and the BST pin settles to VIN + VCCD − Vdiode (excluding
parasitic ringing).
The Zero Current Detect PWM (ZCD_PWM) mode is
enabled when SMOD# is HIGH or MID (see Tables 6 & 8).
With PWM set to > VPWM_HI, GL goes low and GH
goes high after the non−overlap delay. When PWM is driven
to < VPWM_HI and to > VPWM_LO, GL goes high after
the non−overlap delay, and stays high for the duration of the
ZCD blanking timer (TZCD_BLANK) and an 80 ns
de−bounce timer. Once this timer expires, VSW is
monitored for zero current detection, and GL is pulled low
once zero current is detected. The threshold on VSW to
determine zero current undergoes an auto−calibration cycle
every time DISB# is brought from low to high. This
auto−calibration cycle typically takes 25 ms to complete.
Bootstrap Circuit
The bootstrap circuit relies on an external charge storage
capacitor (CBST) and an integrated diode to provide current
to the HS Driver. A multi−layer ceramic capacitor (MLCC)
with a value greater than 100 nF should be used as the
bootstrap capacitor. A 1 to 5 W resistor in series with the
bootstrap capacitor can be used to decrease the VSW
overshoot.
Power Supply Decoupling
The NCP252163 sources relatively large currents into the
MOSFET gates. In order to maintain a constant and stable
supply voltage (VCCD) a low−ESR capacitor should be
placed near the power and ground pins. A multi−layer
ceramic capacitor (MLCC) between 1 mF and 4.7 mF is
typically used.
A separate supply pin (VCC) is used to power the analog
and digital circuits within the driver. A 1 mF ceramic
capacitor should be placed on this pin in close proximity to
the NCP252163. It is good practice to separate the VCC and
VCCD decoupling capacitors with a resistor (2 − 10 W
typical) to avoid coupling driver noise to the analog and
digital circuits that control the driver function (See
Figure 1). It is recommended to connect the supply to
VCCD and then VCC through the filter.
PWM Input
The PWM Input pin is a tri−state input used to control the
HS MOSFET ON/OFF state. It also determines the state of
the LS MOSFET. See Table 6 for logic operation. The PWM
in some cases must operate with frequency programming
resistances to ground. These resistances can range from
10 kW to 300 kW depending on the application. When
SMOD# is set to > VSMOD#_HI or to < VSMOD#_LO, the
input impedance to the PWM input is very high in order to
avoid interferences with controllers that must use
programming resistances on the PWM pin.
If SMOD# is set to < VSMOD#_HI and > VSMOD#_LO
(Mid−State), the PWM pin undriven default voltage is set to
Mid−State with internal divider resistances.
Disable Input (DISB#)
Safety Timer and Overlap Protection Circuit
The DISB# pin is used to disable the GH to the High−Side
FET to prevent power transfer. The pin has a pull−down
resistance to force a disabled state when it is left
unconnected. DISB# can be driven from the output of a logic
device or set high with a pull−up resistance to VCC.
It is important to avoid cross−conduction of the two
MOSFETS which could result in a decrease in the power
conversion efficiency or damage to the device.
The NCP252163 prevents cross−conduction by
monitoring the status of the MOSFETs and applying the
appropriate amount of non−overlap (NOL) time (the time
between the turn−off of one MOSFET and the turn−on of the
other MOSFET). When the PWM input pin is driven high,
the gate of the low−side MOSFET (LSGATE) goes low after
a propagation delay (TPWM_PD_R). The time it takes for
the low−side MOSFET to turn off is dependent on the total
charge on the low−side MOSFET gate.
The NCP252163 monitors the gate voltage of both
MOSFETs and the switch node voltage to determine the
conduction status of the MOSFETs. Once the low−side
MOSFET is turned off an internal timer delays the turn−on
of the high−side MOSFET. When the PWM input pin goes
low, the gate of the high−side MOSFET (HSGATE) goes
low after the propagation delay (TPWM_PD_F). The time
to turn off the high−side MOSFET is dependent on the total
gate charge of the high−side MOSFET. A timer is triggered
once the high−side MOSFET stops conducting, to delay the
turn−on of the low−side MOSFET.
Table 7. UVLO/DISB# LOGIC TABLE
UVLO
DISB#
Driver State
Disabled (GH = GL = 0)
Disabled (GH = GL = 0)
Enabled (See Table 1)
Disabled (GH = GL = 0)
L
H
H
H
X
L
H
Open
VCC Undervoltage Lockout
The VCC pin is monitored by an Undervoltage Lockout
Circuit (UVLO). A VCC voltage above the rising threshold
enables the NCP252163.
Thermal Warning
The THWN pin is an open drain output. When the
temperature of the driver exceeds T
pulled low indicating a thermal warning. At this point, the
, the THWN pin is
THWN
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NCP252163
part continues to function normally. When the temperature
drops T below T , the THWN pin goes high.
enables the low side synchronous MOSFET to operate
independently of the internal ZCD function. When the
SMOD# pin is set low while PWM is in the mid−state, the
low side MOSFET can be disabled to allow discontinuous
mode operation.
THWN_HYS
THWN
If the driver temperature exceeds T
, the part enters
THDN
thermal shutdown and turns off both MOSFETs. Once the
temperature falls T below T , the part
THDN_HYS
THDN
resumes normal operation.
The NCP252163 has the capability of internally
connecting a resistor divider to the PWM pin. To engage
ZCD, SMOD# needs to be placed into mid−state or high.
While in SMOD# mid−state, the IC logic is equivalent to
SMOD# being in the high state.
Skip Mode Input (SMOD#)
The SMOD# tri−state input pin has an internal pull−up
resistance to VCC. When driven low, the SMOD# pin
Inductor
Current
Inductor
Current
ZCD Waits
until Times
Expire
ZCD
Detected
PWM
GH
PWM
GH
GL
GL
250 ns
250 ns
80 ns De−Bounce
80 ns De−Bounce
ZCD Blanking
Timer
ZCD Blanking
Timer
Timer
Timer
NOTE: If the Zero Current Detect circuit detects zero current after the ZCD Wait timer period, the GL is driven low by the Zero Current
Detect signal.
If the Zero Current Detect circuit detects zero current before the ZCD Wait timer period expires, the Zero Current detect signal is
ignored and the GL is driven low at the end of the ZCD Wait timer period.
Inductor
Current
PWM
GH
SMOD#
Triggered
GL
SMOD#
NOTE: If the SMOD# input is driven low at any time after the GL has been driven high, the SMOD# Falling edge triggers the GL to go
low.
If the SMOD# input is driven low while the GH is high, the SMOD# input is ignored.
Figure 25. SMOD# Timing Diagram
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NCP252163
For Use with Controllers with 3−State PWM and
No Zero Current Detection Capability:
Table 8. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH NO ZCD
PWM
SMOD#
H or MID
H or MID
H or MID
GH (Not a Pin)
GL
OFF
ZCD
ON
H
M
L
ON
OFF
OFF
This section describes operation with controllers that are
capable of 3 states in their PWM output and relies on the
NCP252163 to conduct zero current detection during
discontinuous conduction mode (DCM).
The SMOD# pin needs to either be set to 5 V or left
disconnected. The NCP252163 has an internal pull−down
resistor that connects to VCC that sets SMOD# to the logic
high state if this pin is disconnected.
and low states. To enter into DCM, PWM needs to be
switched to the mid−state.
Whenever PWM transitions to mid−state, GH turns off
and GL turns on. GL stays on for the duration of the
de−bounce timer and ZCD blanking timers. Once these
timers expire, the NCP252163 monitors the SW voltage and
turns GL off when SW exceeds the ZCD threshold voltage.
By turning off the LS FET, the body diode of the LS FET
allows any positive current to go to zero but prevents
negative current from conducting.
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
(HIGH)/(MID)
SMOD#
(HIGH)
ZCD_EN
Zero
Current
Detected
Inductor
Current
0
PWM
GH
GL
T
+
T
+
T
+
T
+
ZCD_BLANK
ZCD_BLANK
ZCD_BLANK
ZCD_BLANK
T
T
T
T
DEBOUNCE
DEBOUNCE
DEBOUNCE
DEBOUNCE
Figure 26. Timing Diagram − 3−state PWM Controller, No ZCD
www.onsemi.com
13
NCP252163
For Use with Controllers with 3−State PWM
Controllers Detection Capability:
Table 9. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH ZCD
PWM
SMOD#
GH (Not a Pin)
GL
OFF
OFF
ON
H
M
L
L
L
L
ON
OFF
OFF
This section describes operation with controllers that are
capable of 3 PWM output levels and have zero current
detection during discontinuous conduction mode (DCM).
The SMOD# pin needs to be pulled low (below
and low states. During DCM, the controller is responsible
for detecting when zero current has occurred, and then
notifying the NCP252163 to turn off the LS FET. When the
controller detects zero current, it needs to set PWM to
mid−state, which causes the NCP252163 to pull both GH
and GL to their off states without delay.
V
).
SMOD#_LO
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
SMOD# = Low
SMOD# 0 V
IL 0 A
PWM
Controller Detects Zero Current → Sets PWM to Mid−State
PWM in Mid−State Pulls GL Low
GH
GL
Figure 27. Timing Diagram − 3−state PWM Controller, with ZCD
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14
NCP252163
Figure 28. Top Copper Layer
Figure 29. Bottom Copper Layer
www.onsemi.com
15
NCP252163
RECOMMENDED PCB FOOTPRINT
(OPTION 1)
Figure 30. Recommended PCB Footprint (Option 1)
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16
NCP252163
RECOMMENDED PCB FOOTPRINT
(OPTION 2)
Figure 31. Recommended PCB Footprint (Option 2)
Intel and the Intel logo are trademarks of Intel Corporation or its subsidiaries.
www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN31 5X5, 0.5P
CASE 483BR
ISSUE D
DATE 13 FEB 2023
SCALE 2.5:1
MILLIMETERS
DIM
MIN.
0.70
0.00
0.15
0.20
0.13
4.90
3.70
0.75
1.88
1.22
0.45
NOM.
0.75
MAX.
0.80
0.05
0.25
0.30
0.30
5.10
3.90
0.95
2.08
1.42
0.65
A
A1
A3
b
−
0.20
0.25
b1
D
0.18
5.00
D2
D3
D4
D5
D6
D7
E
3.80
0.85
1.98
1.32
0.55
0.38 REF
5.00
4.90
1.82
0.93
0.93
0.93
0.20
5.10
2.02
1.13
1.13
1.13
0.40
E2
E3
E4
E5
E6
E7
e
1.92
1.03
1.03
1.03
0.30
0.22 REF
0.50 BSC
0.25 BSC
0.25 BSC
0.75 BSC
0.25 BSC
0.40 REF
0.45 REF
0.40 REF
0.30 REF
0.55 REF
0.50 REF
0.40 REF
0.40
e/2
e/3
e/4
e/5
k1
k2
k3
k4
k5
k6
k7
L
C.L.
C.L.
16 17 181920
2122
23
16 17 181920
2122
23
15
14
13
12
24
25
26
27
28
29
30
31
15
14
13
24
25
26
27
28
29
30
31
12
33
33
C.L.
C.L.
11
10
9
11
10
9
32
32
0.30
0.30
0.15
0.50
0.50
0.35
L1
L2
m
0.40
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0.25
0.15 REF
0.80 REF
2.28 REF
2.38 REF
0.80 REF
0.625 REF
n
p
q
r
z
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13680G
PQFN31 5X5, 0.5P
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN31 5X5, 0.5P
CASE 483BR
ISSUE D
DATE 13 FEB 2023
8
1
31
9
11
12
32
33
27
26
15
24
16
23
8
1
9
11
12
31
32
33
33
27
26
15
24
16
23
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
A
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
G
= Pb−Free Package
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13680G
PQFN31 5X5, 0.5P
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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