NCP303160MNTWG [ONSEMI]
Integrated Driver and MOSFET with Integrated Current Monitor, 60A;
| 型号： | NCP303160MNTWG |
| 厂家： | 
ONSEMI |
| 描述： | Integrated Driver and MOSFET with Integrated Current Monitor, 60A |
| 文件： | 总24页 (文件大小：1384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Integrated Driver and
MOSFET with Integrated
Current Monitor
NCP303160
Description
The NCP303160 integrates a MOSFET driver, high−side MOSFET
and low−side MOSFET into a single package.
PQFN39
MN SUFFIX
CASE 483BF
The driver and MOSFETs have been optimized for high−current
DC−DC buck power conversion applications. The NCP303160
integrated solution greatly reduces package parasitics and board space
compared to a discrete component solution.
MARKING DIAGRAM
NCP
Features
303160
AWLYYWW
• Capable of Average Currents up to 60 A
• Capable of 80 A (10 ms) Peak Current
• 80 A Packaged−level UIS Tested to Improve Robustness
• High−Performance, Universal Footprint, Copper−Clip 5 mm x 6 mm
PQFN Package in Wettable Flank
NCP303160 = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
WL
YY
WW
= Work Week
• Capable of Switching at Frequencies up to 1 MHz
• Compatible with 3.3 V or 5 V PWM Input
• Responds Properly to 3−level PWM Inputs
• Precise Current Monitoring
ORDERING INFORMATION
†
Device
NCP303160MNTWG
Package
Shipping
• Option for Zero Cross Detection with 3−level PWM
• Internal Bootstrap Diode
PQFN39
3000 / Tape &
Reel
(Pb−Free)
• Catastrophic Fault Detection
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
♦ Thermal Flag (OTP) for Over−Temperature Condition
♦ Over−Current Protection FAULT (OCP)
♦ Under−Voltage Lockout (UVLO) on VCC and PVCC
♦ Under−Voltage Protection FAULT on Boot−SW
• These Devices are Pb−Free and are RoHS Compliant
Applications
• Desktop & Notebook Microprocessors
• Graphic Cards
• Routers and Switches
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
April, 2023 − Rev. 6
NCP303160/D
NCP303160
DIAGRAMS
R
VCC
V
5V
V
IN
C
VIN
I
IN
C
PVCC
C
VCC
VIN
BOOT
P
PWM
VCC
R
BOOT
VCC
PWM from
controller
CBOOT
DRVON from
controller
DISB#
PHASE
SW
I
OUT
TMON/FLT
TMON/FLT
V
OUT
L
OUT
C
OUT
ZCD_EN
ZCD_EN
IMON
Current
sense
RefIN
REFIN
Voltage
A
GND
PGND
Figure 1. Application Schematic
PVCC
BOOT
3.3 V
flag on FAULT
THERMAL
WARNING
TMON/
FLT
FAULT
LATCH
EN_PWM
VIN
IMON
IMON
FAULT LOGIC
REFIN
PHASE
1 V / 2.4 V
LEVEL
SHIFT
DISB#
VCC
HDRV
REN_DOWN
SW
STARTUP
(POR)
EN/UVLO
VCC
LDRV
EN_PWM
EN_POR
EN_POR
RPWM_UP
PWM INPUT
STAGE
PWM
GL
RPWM_DOWN
EN_POR
VCC
ZCD_EN
ZCD
CONTROL
PGND
AGND
Figure 2. Block Diagram
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2
NCP303160
PINOUT DIAGRAM
5.0 mm
39
38
37
36
35
34
33
32
31
30
1
2
3
4
5
6
N/C
AGND
VCC
29
28
VIN
VIN
40
27
26
VIN
VIN
PVCC
PGND
GL
25 VIN
GL
41
PGND
24
PGND
PGND
23
22
PGND
PGND
7
8
9
21 PGND
20
PGND
PGND
18
19
10
11
12
13
14
15
16
17
Figure 3. Top View
Table 1. PIN LIST AND DESCRIPTIONS
Pin No.
Symbol
NC
Description
1
No connect.
2
3
AGND
VCC
Analog Ground for the analog portions of the IC and for substrate.
Power Supply input for all analog control functions
Power Supply input for LS Gate Driver and Boot Diode.
Reserved for PVCC de−coupling capacitor return.
Low−Side Gate Monitor.
4
PVCC
PGND
GL
5, 40
6, 41
7−9, 20−24
10−19
25−30
31
PGND
SW
Power ground connection for Power Stage high current path.
Switching node junction between high−and low−side MOSFETs
Input Voltage to Power Stage.
VIN
NC
No connect.
32
PHASE
BOOT
Return Connection for BOOT capacitor.
33
Supply for high−side MOSFET gate driver. A capacitor from BOOT to PHASE supplies the charge to turn
on the n−channel high side MOSFET. During the freewheeling interval (LS MOSFET on) the high side
capacitor is recharged by an internal diode.
34
35
36
PWM
DISB#
PWM input to gate driver IC.
DISB# = LOW disables most blocks inside IC. DISB# = HIGH enables all blocks inside IC.
TMON/FLT
Temperature and FAULT Reporting Pin. Pin sources a (PTAT) voltage of 0.6 V at 0°C with an 8 mV/°C
slope when no module FAULT is present. In the event of a module FAULT, this pin pulls HIGH to an inter-
nal driver IC rail = 3.0 V typical.
37
38
39
ZCD_EN
IMON
Zero Current Detection Function Enable
Current Monitor Output (output is referenced to REFIN) − 5 mA/A
REFIN
Referenced voltage used for IMON feature. DC input voltage supplied by external source (not generated
on SPS driver IC)
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3
NCP303160
Table 2. ABSOLUTE MAXIMUM RATINGS (Electrical Information − all signals referenced to PGND unless noted otherwise)
Symbol
Parameter
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−5
Max
Unit
V
V
CC
Supply Voltage
Referenced to AGND
6
PV
Drive Voltage
Referenced to AGND
6
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
VCC+0.3
30
V
CC
DISB#
V
Enable / Disable
PWM Signal Input
ZCD Mode Input
Low Gate Test Pin
Current Monitor Output
Referenced Voltage input
Thermal Monitor
Power Input
Referenced to AGND
V
V
PWM
Referenced to AGND
V
V
Referenced to AGND
V
ZCD_EN
V
GL
Referenced to AGND
V
V
IMON
Referenced to AGND
V
V
REFIN
Referenced to AGND
V
V
Referenced to AGND
V
TMON/FLT
V
Referenced to PGND, AGND
Referenced to PGND, AGND (DC Only)
Referenced to PGND, AC < 5 ns
Referenced to PGND, AGND (DC Only)
Referenced to PGND, AC < 5 ns
Referenced to PGND, AGND (DC Only)
Referenced to PGND, AC < 5 ns
Referenced to AGND
V
In
Vin − Phase
V
Vin − PHASE
30
V
36
V
phase
Phase
−0.3
−15
30
V
V
30
V
SW
Switch Node Input
−0.3
−7
28
32
V
BOOT
Bootstrap Supply
−0.3
−0.3
−0.3
32
V
V
V
Boot to PHASE Voltage
DC Only
7
BOOT−PHASE
AC < 5 ns
9
V
T
Maximum Junction Temperature
150
°C
mJ
J
UIS
Unclamped Inductive
Switching
Single−Pulse Avalanche Energy, Highside FET
(T = 25°C, Vcc & Vgs = 5 V, L = 0.5 μH, I = 80 A
−
2.15
)
J
L
Pk
ESD
Electrostatic Discharge
Protection
Human Body Model
2000
1000
V
Charged Device Model, JESD22−C101
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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4
NCP303160
Table 3. THERMAL INFORMATION
Rating
Symbol
(Note 2)
Value
Unit
°C/W
°C/W
°C/W
°C
Thermal Resistance (Note 1)
0.8
13.1
q
J−Lead
q
J−CaseTop
q
16
J−Ambient
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Maximum Power Dissipation
T
A
−40 to +125
−55 to +150
13.5
T
STG
°C
W
Moisture Sensitivity Level
MSL
1
1. Mounted on 2S2P test board with 0 LFM at T = 25°C
A
2. Measured at PGND Pad (Pins 20 – 24)
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameter
Pin Name
VCC, PVCC
VIN
Conditions
Min
4.5
4.5
−
Typ
5.0
19
−
Max
Unit
V
Supply Voltage Range
Conversion Voltage
5.5
20
55
60
80
V
Continuous Output Current
F
SW
F
SW
F
SW
= 1 MHz, V = 19 V, V
= 1.0 V, T = 25°C
A
IN
OUT
A
= 300 kHz, V = 19 V, V
= 1.0 V, T = 25°C
−
−
A
IN
OUT
A
Peak Output Current
Junction Temperature
= 500 kHz, V = 19 V, V
= 1.0 V,
A
−
−
A
IN
OUT
Duration = 10 ms, Period = 1 s, T = 25°C
−40
−
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCP303160
Table 5. ELECTRICAL CHARACTERISTICS
(V = 5.0 V, V = 19 V, V
= 2.0 V, C
= 0.1 mF unless specified otherwise) Min/Max values are valid for the temperature range
CC
IN
DISB#
VCC
−40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
J
Parameter
BASIC OPERATION
Symbol
Conditions
Min
Typ
Max
Unit
No switching
DISB# = 5 V, PWM = 0 V
DISB# = 0 V, SW = 0 V
VCC rising
−
−
8
−
−
mA
mA
V
Disabled
120
4.1
UVLO Threshold
UVLO Hysteresis
POR Delay to Enable IC
V
3.8
−
4.2
−
UVLO
UVLO_
0.17
V
Hyst
T
VCC UVLO rising to internal PWM en-
able
125
ms
−
−
D_POR
DISB# INPUT
Pull−Down Resistance
High−Level Input Voltage
Low−Level Input Voltage
Enable Propagation Delay
−
2.7
−
130
−
−
−
kW
V
V
UPPER
V
−
0.65
32
V
LOWER
PWM=GND, Delay Between EN from
LOW to HIGH to GL from LOW to HIGH
– Slow EN Setting
16
26
ms
Disable Propagation Delay
PWM=GND, Delay Between EN from
HIGH to LOW to GL from HIGH to LOW
– Fast EN setting
−
43
109
ns
PWM INPUT (T = 25°C, V / P
= 5 V, f
= 1 MHz, I
= 10 A)
A
CC
VCC
SW
OUT
Input High Voltage
V
2.35
2.05
0.9
0.65
−
2.45
2.2
1.0
0.75
21
2.55
2.3
1.1
0.85
−
V
V
PWM_HI
Mid−State Voltage Upper Threshold
Mid−State Voltage Lower Threshold
Input Low Voltage
V
TRI_HI
TRI_LO
V
V
V
R
V
PWM_LO
UP_PWM
Pull−Up Impedance
kW
kW
V
Pull−Down Impedance
R
−
10
−
DOWN_PWM
3−State Open Voltage
V
1.4
1.65
7
1.85
PWM_HIZ
Non−overlap Delay, Leading Edge
T
GL <= 0.5 V to SW>1.2 V,
PWM Transition 0→1
ns
−
−
DEADON
Non−overlap Delay, Trailing Edge
PWM Propagation Delay, Rising
PWM Propagation Delay, Falling
T
SW <= 1.2 V to GL>=0.5 V,
6
ns
ns
ns
ns
ns
−
−
−
DEADOFF
PWM Transition 1→0
T
T
PWM Going HIGH to GL Going LOW,
17
26
20
27
20
PD_PHGLL
V
to 90% GL
IH_PWM
PWM Going LOW to GH Going LOW,
to 90% GH
−
−
−
30
30
30
PD_PLGHL
V
IL_PWM
Exiting PWM Mid−state Propagation
Delay, Mid−to−Low
T
PWM (from Tri−State) going LOW to
GL going HIGH, V to 10% GL
PWM_EXIT_L
IL_PWM
Exiting PWM Mid−state Propagation
Delay, Mid−to−High
T
PWM (from Tri−State) going HIGH to
SW going HIGH, V to 10% SW
PWM_EXIT_H
IH_PWM
PWM High to 3−State hold Off Time
PWM Low to 3−State hold Off Time
HS minimal turn on time
T
T
PWM Going High to HS Going Off
PWM Going Low to LS Going Off
SW gate rising 10% to falling 10%
LS gate rising 10% to falling 10%
SW gate falling 10% to rising 10%
LS gate falling 10% to rising 10%
20
20
−
43
36
37
33
31
51
50
50
−
ns
ns
ns
ns
ns
ns
D_HOLDOFF1
D_HOLDOFF2
T
ON_MIN_HS
LS minimal turn on time
T
−
−
ON_MIN_LS
HS minimal turn off time
T
−
−
OFF_MIN_HS
LS minimal turn off time
T
−
−
OFF_MIN_LS
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NCP303160
Table 5. ELECTRICAL CHARACTERISTICS
(V = 5.0 V, V = 19 V, V
= 2.0 V, C
= 0.1 mF unless specified otherwise) Min/Max values are valid for the temperature range
CC
IN
DISB#
VCC
−40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
J
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
FAULT FLAG OUTPUT VOLTAGE/CURRENT
FAULT Report Output Voltage
Fault Report Delay time
IMON
V
2.85
−
−
−
V
FAULT
T
−
100
ns
DFAULT
HS Off to LS On Blanking Stop Time
T
IMON Blanking Time for PWM
−
−
−
−
90
70
5
−
−
−
−
ns
ns
BLANK_HSOFF
transition 1³0
LS Off to HS On Blanking Stop Time
IMON Amplifier Gain BW
T
IMON Blanking Time for PWM
BLANK_HSON
transition 0³1
BW
L = 150 nH, V = 19 V, V
= 1.0 V,
= 1.0 V,
MHz
ns
IMON
IN
OUT
f
= 800 kHz
SW
IMON Propagation Delay Time
T
L = 150 nH, V = 19 V, V
60
DELAY
IN
OUT
f
= 800 kHz, IMON to IL
SW
IMON OPERATING RANGE ( T = T = −405C to 1255C, V = 4.5 V to 5.5 V, V = 4.5 − 20 V)
A
J
CC
IN
Dynamic range at IMON pin
V
0.6
−
2.3
V
IMON
IMON ACCURACY (T = 255C to 1255C, V /P
= 5 V, V = 19 V) (Note 3)
A
CC VCC
IN
I
I
I
I
= −10 A to 40 A
4.75
46.5
5.00
50
5.25
53.5
mA/A
MON_SLOPE
MON_SLOPE
OUT
V
V
V
V
R
= 1 kW
IMON
= 10 A, Voltage is Referenced to
mV
IMON_10A
IMON_20A
IMON_30A
IMON_40A
OUT
resistor placed REFIN Pin
from IMON to
I
= 20 A, Voltage is Referenced to
95
100
150
200
105
157.5
212
mV
mV
mV
REFIN.
Current Monitor
Voltage
OUT
REFIN Pin
I
= 30 A, Voltage is Referenced to
142.5
192
OUT
(V
)
IMON−REFIN
REFIN Pin
I
= 40 A, Voltage is Referenced to
OUT
REFIN Pin
BOOTSTRAP DIODE
Forward Voltage
V
Forward Bias Current = 10 mA
−
350
−
−
mV
V
F
Breakdown Voltage
LOW−SIDE DRIVER
V
R
30
−
Output Impedance, Sourcing
Output Impedance, Sinking
THERMAL MONITOR VOLTAGE
R
Source Current = 100 mA
Sink Current = 100 mA
−
−
0.96
0.29
−
−
W
W
SOURCE_GL
R
SINK_GL
V
Thermal
Monitor Voltage
T = T = 25°C
−
−
−
−
0.800
1.600
8
−
−
−
−
V
V
TMON_25C
A
J
V
T = T = 125°C
A J
TMON_125C
TMON_SLOPE
SOURCE_TMON
V
mV/°C
mA
I
I
TMON Source 5 VCC, 25°C
850
Current
TMON Sink 5 VCC, 25°C
Current
−
40
−
mA
SINK_TMON
OVER−TEMPERATURE WARNING FAULT
Over−Temperature Warning Accuracy
OTW Hysteresis
Driver IC Temperature
Driver IC Temperature
−
−
140
15
−
−
°C
°C
HS CYCLE−BY−CYCLE POSITIVE I−LIMIT
I−limit comparator input−output propa-
t
Input Signal = 380 mV,
dv/dt = 0.2 mV/nsec.
−
60
80
−
ns
A
D_ILimit−COMP
gation delay.
Over−Current Limit
I
74
86
LIM
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NCP303160
Table 5. ELECTRICAL CHARACTERISTICS
(V = 5.0 V, V = 19 V, V
= 2.0 V, C
= 0.1 mF unless specified otherwise) Min/Max values are valid for the temperature range
CC
IN
DISB#
VCC
−40°C ≤ T ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
J
Parameter
Symbol
Conditions
Min
Typ
8
Max
−
Unit
A
HS CYCLE−BY−CYCLE POSITIVE I−LIMIT
OCP Hysteresis
I
LIM_HYS
−
NEGATIVE OVER−CURRENT (NOCP) FAULT
NOCP Trip LOW Level
ZCD_EN INPUT
I
−
−50
−
A
NOCP_LOW
Pull−Up Impedance
R
−
−
21
10
−
kW
kW
V
UP_PWM
Pull−Down Impedance
3−State Open Voltage
ZCD_EN input Voltage High
ZCD_EN input Voltage Mid−state
ZCD_EN input Voltage Low
R
−
DOWN_PWM
V
1.4
2.25
1.4
0.7
1.65
2.4
−
1.85
2.55
2.0
0.95
PWM_HIZ
V
V
ZCD_HI
V
V
ZCD_MID
V
0.8
V
ZCD_LO
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Imon performance is guaranteed by independent ATE testing of High−side and Low−side slope and offset
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NCP303160
TYPICAL CHARACTERISTICS
(Tests at T = 25°C, V = 5 V, V = 19 V, and V = 1 V unless otherwise specified)
A
CC
IN
O
Figure 4. Highside FET Forward Biased Safe
Operating Area
Figure 5. Lowside FET Forward Biased Safe
Operating Area
Figure 6. Highside FET Unclamped Inductive
Switching Capability
Figure 7. Lowside FET Unclamped Inductive
Switching Capability
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NCP303160
TYPICAL CHARACTERISTICS
(Tests at T = 25°C, V = 5 V, V = 19 V, and V = 1 V unless otherwise specified)
A
CC
IN
O
Figure 8. Power Loss vs. Output Current
Figure 10. Power Loss vs. Input Voltage
Figure 12. Efficiency vs. Output Load
Figure 9. Power Loss vs. Switching Frequency
Figure 11. Power Loss vs. Driver Voltage
Figure 13. Driver Supply Current vs. Switching
Frequency
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NCP303160
TYPICAL CHARACTERISTICS
(Tests at T = 25°C, V = 5 V, V = 19 V, and V = 1 V unless otherwise specified)
A
CC
IN
O
Figure 14. Driver Current vs. Driver Voltage
Figure 16. UVLO Threshold vs. Temperature
Figure 18. PWM Threshold vs. Temperature
Figure 15. Driver Current vs. Output Current
Figure 17. PWM Threshold vs. Driver Voltage
Figure 19. Quiescent Current vs. Driver
Voltage
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NCP303160
TYPICAL CHARACTERISTICS
(Tests at T = 25°C, V = 5 V, V = 19 V, and V = 1 V unless otherwise specified)
A
CC
IN
O
Figure 20. Quiescent Current vs. Temperature
Figure 21. EN Threshold vs. Driver Voltage
Figure 22. EN Threshold vs. Temperature
Figure 23. IMON Accuracy vs. Temperature
Figure 24. IMON Accuracy vs. Switching
Frequency
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NCP303160
FUNCTIONAL DESCRIPTION
The SPS NCP303160 is a driver plus MOSFET module
With ZCD_EN set high, if PWM falls to less than
VPWM_HI, but stays above VPWM_LO, GL will go high
after the non−overlap delay, and stay high for the duration of
the ZCD Blanking time. Once this timer has elapsed, VSW
will be monitored for zero current, and GL will be pulled low
when zero current is detected.
With ZCD_EN set mid (open), if the PWM goes to low,
GL will go high after the non−overlap delay, and stay high
for the duration of the ZCD Blanking time. Once this timer
has elapsed, VSW will be monitored for zero current, and
GL will be pulled low when zero current is detected.
optimized for the synchronous buck converter topology. A
PWM input signal is required to properly drive the high−side
and the low−side MOSFETs. The part is capable of driving
speed up to 1 MHz.
DISB# and UVLO
The SPS NCP303160 is enabled by both DISB# pin input
signal and V UVLO. Table 6 summarizes the enable and
CC
disable logics. With DISB# low and VCC UVLO, SPS is
fully shut down. If VCC is ready but DISB# is low, SPS goes
into sleep mode with very low Quiescent current, where only
critical circuitry are alive. The part should also read
fuses/program itself during this state.
PWM
The PWM Input pin is a tri−state input used to control the
HS MOSFET ON/OFF state. It also determines the state of
the LS MOSFET. See Table 7 for logic operation with
ZCD_EN.
There is a minimum PWM pulse width, typical at 37 ns
(SW gate rising 10% to falling 10%), if the PWM input pulse
width is shorter than that, the driver will extend the pulse
width to 37 ns. If the PWM input is shorter than 5 ns, the
driver will ignore it.
Table 6. UVLO AND DRIVER STATE
VCC
UVLO
DISB#
Driver State
0
X
Full driver shutdown (GH, GL=0), requires
40 ms for start−up
1
0
1
Partial driver shutdown (GH, GL=0),
requires 30 ms for startup
1
Enabled (GH/GL follow PWM)
Table 7. LOGIC TABLE
INPUT TRUTH TABLE
X
Open/0 Disabled (GH, GL=0)
NCP303160 needs 40 ms time to go from fully shutdown
mode to power ready mode. The time is 30 ms to go from
partial shutdown mode to power ready mode. Before power
is ready, FAULT pin is strongly pulled low with a 50 W
resistor. As a result, FAULT pin can also be used as a power
ready indicator.
DISB#
ZCD_EN
PWM
X
GH
L
GL
L
L
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
MID
H
L
ZCD
L
L
H
L
Zero Current Detect Enable Input (ZCD_EN)
The ZCD_EN pin is a logic input pin with an internal
voltage divider connected to VCC.
When ZCD_EN is set low, the NCP303160 will operate
in synchronous rectifier (PWM) mode. This means that
negative current can flow in the LS MOSFET if the load
current is less than 1/2 delta current in the inductor. When
ZCD_EN is set high, Zero Current Detect PWM
(ZCD_PWM) mode will be enabled.
L
L
H
L
MID
H
L
L
MID
MID
MID
H
L
L
L
ZCD
L
MID
L
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NCP303160
VIH_PWM
PWM
VIL_PWM
90%
10%
90%
10%
GL
90%
10%
90%
10%
GH−PHASE
BOOT−GND
PVCC −VF_DBOOT−1V
90%
SW
tPD_PHGLL tD_DEADON tRISE_GH
tFALL _GL
tPD_PLGHL tD_DEADOFF tRISE _GL
tFALL _GH
tPD_PHGLL = PWM HI to GL LO , VIH_PWM to 90% GL
tFALL_GL = 90% GL to 10% GL
tPD_PLGLH
tD_DEADON = LS Off to HS On Dead Time , 10% GL to VBOOT−GND <= PVCC −VF_DBOOT−1V or BOOT −GND dip start point
tRISE_GH = 10% GH to 90% GH, VBOOT−GND <= PVCC −VF_DBOOT−1V or BOOT −GND dip start point to GL bounce start point
tPD_PLGHL = PWM LO to GH LO , VIL_PWM to 90% GH or BOOT −GND decrease start point , tPD_PLGLH −tD_DEADOFF −tFALL_GH
tFALL_GH = 90% GH to 10% GH, BOOT−GND decrease start point to 90% VSW or GL dip start point
tD_DEADOFF = HS Off to LS On Dead Time , 90% VSW or GL dip start point to 10% GL
tRISE_GL = 10% GL to 90% GL
tPD_PLGLH = PWM LO to GL HI , VIL_PWM to 10% GL
Figure 25. PWM Timing Diagram
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NCP303160
For Use with Controllers with 3−State PWM and No
Zero Current Detection Capability:
This section describes operation with controllers that are
capable of 3 states in their PWM output and relies on the
NCP303160 to conduct zero current detection during
discontinuous conduction mode (DCM).
turns GL off when the inductor current exceeds the ZCD
threshold. By turning off the LS FET, the body diode of the
LS FET allows any positive current to go to zero but
prevents negative current from conducting.
There are three scenarios:
1. PWM from high to mid,
The ZCD_EN pin needs to either be set to 5 V or left
disconnected. The NCP303160 has an internal voltage
divider connected to VCC that will set ZCD_EN to the logic
mid state if this pin is left disconnected.
Inductor current goes to zero before the ZCD
blanking timer, GL is on and current goes to
negative until the timer expires.
2. PWM from high to mid,
ZCD blanking timer expires before inductor
current goes to zero, GL is on until inductor
current reaches zero.
A. When ZCD_EN is set to high.
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
and low states. To enter into DCM, PWM needs to be
switched to the mid−state. Whenever PWM transitions to
mid−state, GH turns off and GL turns on. GL stays on for the
duration of the ZCD blanking timers. Once this timer
expires, the NCP303160 monitors the inductor current and
3. PWM from mid to low to mid,
ZCD blanking timer starts when PWM goes from
mid to low, GL turns on. After PWM goes back to
mid, driver will wait for the timer to expire to turn
off GL.
Figure 26. Timing Diagram − 3−state PWM Controller, No ZCD (a)
B. When ZCD_EN is set to mid (open).
With this setting, NCP303160 monitors the inductor
current when PWM goes from high to low and turns off the
GL when the inductor current exceeds the ZCD threshold.
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NCP303160
Figure 27. Timing Diagram − 3−state PWM Controller, No ZCD (b)
For Use with Controllers with 3−State PWM and Zero
Current Detection Capability:
and low states. During DCM, the controller is responsible
for detecting when zero current has occurred, and then
notifying the NCP303160 to turn off the LS FET. When the
controller detects zero current, it needs to set PWM to
mid−state, which causes the NCP303160 to pull both GH
and GL to their off states without delay.
This section describes operation with controllers that are
capable of 3 PWM output levels and have zero current
detection during discontinuous conduction mode (DCM).
The ZCD_EN pin needs to be pulled low.
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
Figure 28. Timing Diagram − 3−state PWM Controller, with ZCD
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16
NCP303160
Power Sequence
Dead−Times
NCP303160 requires four (4) input signals to conduct
normal switching operation: VIN, VCC, PWM, and DISB#.
All combinations of power sequences are available. The
below example of a power sequence is for a reference
application design:
The driver IC design ensures minimum MOSFET dead
times, while eliminating potential shoot−through
(cross−conduction) currents. To ensure optimal module
efficiency, body diode conduction times must be reduced to
the low nano−second range during CCM and DCM
operation. Delay circuitry is added to prevent gate overlap
during both the low−side MOSFET off to high−side
MOSFET on transition and the high−side MOSFET off to
low−side MOSFET on transition.
• From no input signals
−> VCC On: Typical 5 VDC
−> DISB# HIGH: Typical 5 VDC
−> VIN On: Typical 19 VDC
−> PWM Signaling: 3.3 V HIGH/ 0 V LOW
Boot Capacitor Refresh
The VIN pins are tied to the system main DC power rail.
The DISB# pin can be tied to the VCC rail with an external
pull−up resistor and it will maintain HIGH once the VCC rail
turns on. Or the DISB# pin can be directly tied to the PWM
controller for other purposes.
NCP303160 monitors the low Boot−SW voltage. If
DISB# and VCC are ready, but the voltage across the boot
capacitor voltage is lower than 3.1 V, NCP303160 ignores
the PWM input signal and starts the boot refresh circuit. The
boot refresh circuit turns on the low side MOSFET with a
100 ns~200 ns narrow pulse in every 7~14 ms until
Boot−SW voltage is above 3.6 V.
High−Side Driver
The high−side driver (HDRV) is designed to drive a
floating N−channel MOSFET (Q1). The bias voltage for the
high−side driver is developed by a bootstrap supply circuit,
consisting of the internal Schottky diode and external
Current Monitor (IMON)
The SPS current monitor accurately senses high−side and
low−side MOSFET currents. The currents are summed
together to replicate the output filter inductor current. The
signal is reported from the SPS module in the form of a
bootstrap capacitor (C ). During startup, the SW node
BOOT
is held at PGND, allowing C
to charge to VCC through
BOOT
the internal bootstrap diode. When the PWM input goes
HIGH, HDRV begins to charge the gate of the high−side
MOSFET (internal GH pin). During this transition, the
5 mA/A current signal (I
). The IMON signal
IMON−REFIN
will be referenced to an externally supplied signal (REFIN)
and differentially sensed by an external analog/ digital
PWM controller.
The motivation for the IMON feature is to replace the
industry standard output filter DCR sensing, or output
current sense using an external precision resistor. Both
techniques are lossy and lead to reduced system efficiency.
Inductor DCR sensing is also notoriously inaccurate for low
value DCR inductors. Figure 29 shows a comparison
between conventional inductor DCR sensing and the unique
IMON feature.
The accuracy on IMON signal is 5% from 10 A to 40 A
output current. For the SPS module, parameters that can
affect IMON accuracy are tightly controlled and trimmed at
the MOSFET/IC production stage. The user can easily
incorporate the IMON feature and accuracy replacing the
traditional current sensing methods in multi−phase
applications.
charge is removed from the C
and delivered to the gate
BOOT
of Q1. As Q1 turns on, SW rises to V , forcing the BOOT
IN
pin to V + V
, which provides sufficient V
IN
BOOT
GS
enhancement for Q1. To complete the switching cycle, Q1
is turned off by pulling HDRV to SW. C is then
BOOT
recharged to VCC when the SW falls to PGND. HDRV
output is in phase with the PWM input. The high−side gate
is held LOW when the driver is disabled or the PWM signal
is held within the 3−state window for longer than the 3−state
hold−off time, t
.
D_HOLD−OFF
Low−Side Driver
The low−side driver (LDRV) is designed to drive the
gate−source of a ground referenced low RDS(ON) N−channel
MOSFET (Q2). The bias for LDRV is internally connected
between VCC and PGND. When the driver is enabled, the
driver’s output is 180° out of phase with the PWM input.
When the driver is disabled, LDRV is held LOW.
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NCP303160
Figure 29. DrMOS with Inductor DCR Sensing vs. SPS with IMON
Fault Flag (FAULT)
temperature. Driver still responds to PWM commands.
Once the IC falls below 125°C, fault flag is cleared
internally by driver IC.
The TMON / FAULT pin on NCP303160 is a thermal
monitor output in normal operation. Before power is ready,
TMON pin is strongly pulled low with a 50 ohm resistor. As
a result, it can be used as a power ready indicator. Also, this
pin is used as a module FAULT flag pin if there is OCP,
Boot/PH UVLO, or OTP.
The TMON pin output is a Proportional to Absolute
Temperature (PTAT) voltage sourced signal referenced to
AGND when no module FAULT is present. It will typically
output 0.6 V at 0°C and 1.8 V at 150°C with 8 mV / °C typical
slope.
TMON pins from multiple SPS modules (used in
multi−phase topologies) can be tied together to share a
common thermal bus. Operating with this configuration will
force the thermal bus signal to report the highest voltage
output TMON signal to the controller (highest temperature).
The TMON output has a low output impedance when
sourcing current and a high output impedance when sinking
current.
The TMON signal reported from the module pin is a
buffered version of an internal TMON signal. Configuring
the SPS module to share a common thermal bus will still
permit each module to safely monitor its own temperature
since the internal TMON signal is unaffected by the
common thermal bus configuration.
Over−Current Protection (OCP)
The NCP303160 has cycle−by−cycle over−current
protection. If current exceeds the OCP threshold, HS FET is
gated off regardless of PWM command. HS FET cannot be
gated on again until the current is less than the OCP
threshold with a hysteresis.
Fault flag will be pulled HIGH after 10 consecutive
cycle−by−cycle OCPs are detected. Fault flag will clear once
OCP is NOT detected. Module never shuts down nor does
it disable HDRV/LDRV (but driver will still truncate HS on
time when PWM=HIGH and ILIM is detected).
Negative−OCP
The NCP303160 can detect large negative inductor
current and protect the low side MOSFET. Once this
Negative current threshold is detected the driver module
takes control and truncates LS on−time pulse (LS FET is
gated off regardless of PWM command). The driver will
stay in this state till one of two things happen 1) 200 ns
expires in which case if the PWM pin is commanding the
driver to turn on LS, the driver will respond and NOCP will
again be monitored 2) PWM commands HS on in which case
the driver will immediately turn on HS regardless of the
200 ns Timer.
An over temperature event is considered catastrophic in
nature. OTW raises fault flag HIGH once it exceeds 140°C
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NCP303160
APPLICATION INFORMATION
Decoupling Capacitor for VCC
be sized properly to not generate excessive heating due to
high power dissipation.
For the supply input (VCC pin), local decoupling
capacitor is required to supply the peak driving current and
to reduce noise during switching operation. Use at least 0.68
~ 2.2 mF/ 0402 ~ 0603/ X5R ~ X7R multi−layer ceramic
capacitor for the power rail. Keep this capacitor close to the
VCC pin and AGND copper planes. If it needs to be located
on the bottom side of board, put through−hole vias on each
pad of the decoupling capacitor to connect the capacitor pad
on bottom with VCC pin on top.
Decoupling capacitor on VCC and BOOT capacitor
should be placed as close as possible to the VCC ~ AGND
and BOOT ~ PHASE pin pairs to ensure clean and stable
power supply. Their routing traces should be wide and short
to minimize parasitic PCB resistance and inductance.
The board layout should include a placeholder for
small−value series boot resistor on BOOT ~ PHASE. The
boot−loop size, including series R
and C , should
BOOT
BOOT
The supply voltage range on VCC is 4.5 V ~ 5.5 V,
typically 5 V for normal applications.
be as small as possible.
A boot resistor may be required and it is effective to
control the high−side MOSFET turn−on slew rate and SW
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
voltage overshoot. R
can improve noise operating
BOOT
margin in synchronous buck designs that may have noise
issues due to ground bounce or high positive and negative
(C ). A bootstrap capacitor of 0.1 ~ 0.22 mF/ 0402 ~
BOOT
0603/ X5R ~ X7R is usually appropriate for most switching
applications. A series bootstrap resistor may be needed for
specific applications to lower high−side MOSFET switching
speed. The boot resistor is required when the SPS is
V
SW
ringing. Inserting a boot resistance lowers the SPS
module efficiency. Efficiency versus switching noise must
be considered. R values from 4.2 W to 6.0 W are
BOOT
typically effective in reducing V overshoot.
SW
switching above 15 V V ; when it is effective at controlling
IN
The VIN and PGND pins handle large current transients
with frequency components greater than 100 MHz. If
possible, these pins should be connected directly to the VIN
and board GND planes. The use of thermal relief traces in
series with these pins is not recommended since this adds
extra parasitic inductance to the power path. This added
inductance in series with either the VIN or PGND pin
degrades system noise immunity by increasing positive and
V
overshoot. RBOOT value from 4.2 to 6 W is typically
SW
recommended to reduce excessive voltage spike and ringing
on the SW node. A higher R value can cause lower
efficiency due to high switching loss of high−side MOSFET.
Do not add a capacitor or resistor between the BOOT pin
and GND.
It is recommended to add a PCB place holder for a small
size 1 nF ~ 1 mF capacitor close to the REFIN pin and AGND
to reduce switching noise injection.
It is also recommended to add a small 10 ~ 47 pF capacitor
in parallel with the IMON resistor from IMON to REFIN.
This capacitor can help reduce switching noise coupling
onto the IMON signal. The place of the IMON resistor and
cap should be close to the controller, not the SPS to improve
the sensing accuracy.
BOOT
negative V ringing.
SW
PGND pad and pins should be connected to the GND
copper plane with multiple vias for stable grounding. Poor
grounding can create a noisy and transient offset voltage
level between PGND and AGND. This could lead to faulty
operation of gate driver and MOSFETs.
Ringing at the BOOT pin is most effectively controlled by
close placement of the boot capacitor. Do not add any
additional capacitors between BOOT to PGND. This may
lead to excess current flow through the BOOT diode,
causing high power dissipation.
Put multiple vias on the VIN and VOUT copper areas to
interconnect top, inner, and bottom layers to evenly
distribute current flow and heat conduction. Do not put too
many vias on the SW copper to avoid extra parasitic
inductance and noise on the switching waveform. As long as
efficiency and thermal performance are acceptable, place
only one SW node copper on the top layer and put no vias on
the SW copper to minimize switch node parasitic noise. Vias
should be relatively large and of reasonably low inductance.
PCB Layout Guideline
All of the high−current paths; such as VIN, SW, VOUT,
and GND coppers; should be short and wide for low parasitic
inductance and resistance. This helps achieve a more stable
and evenly distributed current flow, along with enhanced
heat radiation and system performance.
Input ceramic bypass capacitors must be close to the VIN
and PGND pins. This reduces the high−current power loop
inductance and the input current ripple induced by the power
MOSFET switching operation.
An output inductor should be located close to the
NCP303160 to minimize the power loss due to the SW
copper trace. Care should also be taken so the inductor
dissipation does not heat the SPS.
Critical high−frequency components; such as R
, C
,
BOOT BOOT
RC snubber, and bypass capacitors; should be located as
close to the respective SPS module pins as possible on the
top layer of the PCB. If this is not feasible, they can be placed
on the board bottom side and their pins connected from
bottom to top through a network of low−inductance vias.
®
PowerTrench MOSFETs are used in the output stage and
are effective at minimizing ringing due to fast switching. In
most cases, no RC snubber on SW node is required. If a
snubber is used, it should be placed close to the SW and
PGND pins. The resistor and capacitor of the snubber must
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NCP303160
PCB Layout Guideline (Continued)
Figure 30. Layout Example – Top View
Figure 31. Layout Example – Bottom Layer
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NCP303160
Evaluation Board Information
The NCP303160 evaluation board (EVB) is 70 mm x 70 mm with 6 total layers. All layers have a 2−oz. copper finish.
Figure 32. EVB Top Layer
Figure 33. EVB Inner Layer 1
Figure 34. EVB Inner Layer 2
Figure 35. EVB Inner Layer 3
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NCP303160
Evaluation Board Information
The NCP303160 evaluation board (EVB) is 70 mm x 70 mm with 6 total layers. All layers have a 2−oz. copper finish.
Figure 36. EVB Inner Layer 4
Figure 37. EVB Bottom Layer
Figure 38. EVB Silkscreen Top
Figure 39. EVB Bottom Layer
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC.
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NCP303160
PACKAGE DIMENSIONS
PQFN39 5X6, 0.45P
CASE 483BF
ISSUE B
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NCP303160
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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