NCP3170ADR2G [ONSEMI]
Synchronous PWM Switching Converter; 同步PWM开关转换器
| 型号： | NCP3170ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Synchronous PWM Switching Converter |
| 文件： | 总26页 (文件大小：684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP3170
Synchronous PWM
Switching Converter
The NCP3170 is a flexible synchronous PWM Switching Buck
Regulator. The NCP3170 operates from 4.5 V to 18 V, sourcing up to
3 A and is capable of producing output voltages as low as 0.8 V. The
NCP3170 also incorporates current mode control. To reduce the
number of external components, a number of features are internally set
including soft start, power good detection, and switching frequency.
The NCP3170 is currently available in an SOIC−8 package.
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SOIC−8 NB
CASE 751
Features
• 4.5 V to 18 V Operating Input Voltage Range
• 90 mW High-Side, 25 mW Low-Side Switch
• FMEA Fault Tolerant During Pin Short Test
• 3 A Continuous Output Current
• Fixed 500 kHz and 1 MHz PWM Operation
• Cycle-by-Cycle Current Monitoring
• 1.5% Initial Output Accuracy
• Internal 4.6 ms Soft-Start
MARKING DIAGRAM
8
3170x
ALYW
G
1
3170x = Specific Device Code
• Short-Circuit Protection
x
A
L
Y
W
G
= A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
• Turn on Into Pre-bias
• Power Good Indication
• Light Load Efficiency
• Thermal Shutdown
• These are Pb-Free Devices
PIN CONNECTIONS
Typical Applications
V
• Set Top Boxes
PGND
SW
V
IN
PG
• DVD/Blu−rayt Drives and HDD
• LCD Monitors and TVs
• Cable Modems
AGND
FB
EN
COMP
(Top View)
• PCIe Graphics Cards
• Telecom/Networking/Datacom Equipment
• Point of Load DC/DC Converters
ORDERING INFORMATION
†
Device
Package
Shipping
V
IN
NCP3170ADR2G
SOIC−8
2,500/Tape & Reel
(Pb−Free)
C1
22 mF
VIN
L1 4.7 mH
NCP3170BDR2G
SOIC−8
(Pb−Free)
2,500/Tape & Reel
VSW
EN
3.3 V
NCP3170
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
R1
R2
PG
C2, C3
22 mF
COMP
FB1
C
C
AGND
PGND
R
C
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
April, 2013 − Rev. 3
NCP3170/D
NCP3170
VIN
VDD
EN
Power
Control
(PC)
UVLO
POR
Driver
Voltage
Clamp
VCV
VCL
Soft Start
Reference
Slope
Compensation
0.030 V/A
Current
Sense
S
ORing
Circuit
Pulse by
Pulse
Current
Limit
SET
Oscillator
S
Q
Q
+
FB
R
CLR
+
−
−
VIN
COMP
Soft Start
Complete
Logic
HS
PDRV
+
VSW
VCW
VCL
−
998 mV
+
867 mV
728 mV
−
+
−
LS
NDRV
PG
VSW
Over
Zero
Temperature
Protection
Current
Detection
AGND
PGND
Figure 2. NCP3170 Block Diagram
Description
Table 1. PIN FUNCTION DESCRIPTION
Pin
Pin Name
1
PGND
The power ground pin is the high current path for the device. The pin should be soldered to a large copper
area to reduce thermal resistance. PGND needs to be electrically connected to AGND.
2
3
VIN
The input voltage pin powers the internal control circuitry and is monitored by multiple voltage comparators.
The VIN pin is also connected to the internal power PMOS switch and linear regulator output. The VIN pin
has high di/dt edges and must be decoupled to ground close to the pin of the device.
AGND
The analog ground pin serves as small-signal ground. All small-signal ground paths should connect to the
AGND pin and should also be electrically connected to power ground at a single point, avoiding any high
current ground returns.
4
5
FB
Inverting input to the OTA error amplifier. The FB pin in conjunction with the external compensation serves to
stabilize and achieve the desired output voltage with current mode compensation.
COMP
The loop compensation pin is used to compensate the transconductance amplifier which stabilizes the
operation of the converter stage. Place compensation components as close to the converter as possible.
Connect a RC network between COMP and AGND to compensate the control loop.
6
7
EN
PG
Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the device. Do not leave
it open.
Power good is an open drain 500 mA pull down indicating output voltage is within the power good window. If
the power good function is not used, it can be connected to the VSW node to reduce thermal resistance. Do
not connect PG to the VSW node if the application is turning on into pre-bias.
8
VSW
The VSW pin is the connection of the drains of the internal N and P MOSFETS. At switch off, the inductor will
drive this pin below ground as the body diode and the NMOS conducts with a high dv/dt.
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NCP3170
Table 2. ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 3, unless otherwise noted)
Rating
Symbol
V
V
Unit
V
MAX
MIN
Main Supply Voltage Input
V
IN
20
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.7
−5
Voltage between PGND and AGND
PWM Feedback Voltage
Error Amplifier Voltage
V
PAG
0.3
V
F
B
6
V
COMP
EN
6
V
Enable Voltage
V
V
V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 10 V
V
IN
IN
IN
PG Voltage
PG
V
VSW to AGND or PGND
VSW to AGND or PGND for 35ns
Junction Temperature (Note 1)
Operating Ambient Temperature Range
Storage Temperature Range
V
SW
V
V
SWST
V
V
IN
T
J
+150
°C
°C
°C
T
A
−40 to +85
T
stg
− 55 to +150
Thermal Characteristics (Note 2)
SOIC−8 Plastic Package
Maximum Power Dissipation @ T = 25°C
P
q
RqJC
1.15
87
37.8
W
°C/W
°C/W
A
D
JA
Thermal Resistance Junction-to-Air
Thermal Resistance Junction-to-Case
R
Lead Temperature Soldering (10 sec):
Reflow (SMD Styles Only) Pb-Free (Note 3)
RF
260 peak
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The maximum package power dissipation limit must not be exceeded.
TJ(max) * TA
PD
+
RqJA
2. The value of qJA is measured with the device mounted on 2in x 2in FR−4 board with 2oz. copper, in a still air environment with T = 25°C.
A
The value in any given application depends on the user’s specific board design.
3. 60−180 seconds minimum above 237°C.
Table 3. RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
4.5
Max
18
Unit
V
Main Supply Voltage Input
Power Good Pin Voltage
Switch Pin Voltage
PG
4.5
18
V
V
SW
−0.3
0
18
V
Enable Pin Voltage
EN
COMP
FB
18
V
Comp Pin Voltage
−0.1
−0.1
−0.1
−40
−40
5.5
5.5
−0.1
125
85
V
Feedback Pin Voltage
Power Ground Pin Voltage
Junction Temperature Range
Operating Temperature Range
V
PGND
V
T
J
°C
°C
T
A
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NCP3170
Table 4. ELECTRICAL CHARACTERISTICS
(T = 25°C, V = V = 12 V, V = 3.3 V for min/max values unless otherwise noted (Note 7))
A
IN
EN
OUT
Characteristic
Conditions
Min
Typ
Max
Unit
Input Voltage Range
(Note 5)
4.5
−
18
V
SUPPLY CURRENT
Quiescent Supply Current
NCP3170A
NCP3170B
V
IN
= EN = 12 V V = 0.8 V
−
−
1.7
1.7
2.0
2.0
mA
FB
(Note 5)
Shutdown Supply Current
UNDER VOLTAGE LOCKOUT
VIN UVLO Threshold
VIN UVLO Threshold
MODULATOR
EN = 0 V (Note 5)
−
13
17
mA
V
Rising Edge (Note 5)
Falling Edge (Note 5)
−
−
4.41
4.13
−
−
V
V
IN
V
IN
Oscillator Frequency
NCP3170A
NCP3170B
Enable = V
450
900
500
550
kHz
%
IN
1000
1100
Maximum Duty Ratio
Minimum Duty Ratio
NCP3170A
NCP3170B
91
90
−
−
96
96
NCP3170A
NCP3170B
V
IN
= 12 V
6.0
4.0
−
−
11
11.5
%
VIN Soft Start Ramp Time
OVER CURRENT
Current Limit
V
FB
= VCOMP
3.5
4.6
6.0
6.0
ms
(Note 4)
4.0
−
A
PWM COMPENSATION
VFB Feedback Voltage
Line Regulation
GM
T = 25°C
0.792
−
0.8
1
0.808
V
%
A
(Note 4)
−
−
−
201
55
mS
dB
MHz
nA
mA
mA
AOL DC gain
(Note 4)
(Note 4)
(Note 4)
40
2.0
−
−
Unity Gain BW (C
= 10 pF)
−
−
OUT
Input Bias Current (Current Out of FB IB Pin)
IEAOP Output Source Current
IEAOM Output Sink Current
ENABLE
−
286
−
V
FB
V
FB
= 0 V
= 2 V
−
20.1
21.3
−
−
Enable Threshold
(Note 5)
−
1.41
−
V
POWER GOOD
Power Good High On Threshold
Power Good High Off Threshold
Power Good Low On Threshold
Power Good Low Off Threshold
Over Voltage Protection Threshold
Power Good Low Voltage
PWM OUTPUT STAGE
−
−
−
−
−
−
875
859
−
−
−
−
−
−
mV
mV
mV
mV
mV
V
712
728
998
V
IN
= 12 V, IPG = 500 mA
0.195
High-Side Switch On-Resistance
V
= 12 V
= 4.5 V
−
−
90
130
150
mW
mW
IN
IN
V
100
Low-Side Switch On-Resistance
V
= 12 V
= 4.5 V
−
−
25
29
35
39
IN
IN
V
THERMAL SHUTDOWN
Thermal Shutdown
Hysteresis
(Notes 4 and 6)
−
−
164
43
−
−
°C
°C
4. Guaranteed by design
5. Ambient temperature range of −40°C to +85°C.
6. This is not a protection feature.
7. The device is not guaranteed to operate beyond the maximum operating ratings.
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NCP3170
TYPICAL PERFORMANCE CHARACTERISTICS
(Circuit from Figure 1, T = 25°C, V = V = 12 V, V = 3.3 V unless otherwise specified)
A
IN
EN
OUT
Figure 3. Light Load (DCM) Operation 1 ms/DIV
Figure 4. Full Load (CCM) Operation 1 ms/DIV
Figure 5. Start−Up into Full Load 1 ms/DIV
Figure 6. Short−Circuit Protection 200 ms /DIV
Figure 7. 50% to 100% Load Transient 100 ms/DIV
Figure 8. 3.3 V Turn on into 1 V Pre−Bias 1 ms /DIV
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NCP3170
TYPICAL PERFORMANCE CHARACTERISTICS
(Circuit from Figure 1, T = 25°C, V = V = 12 V, V
= 3.3 V unless otherwise specified)
A
IN
EN
OUT
30
27
2.1
Input Voltage = 18 V
2.0
1.9
1.8
1.7
1.6
1.5
Input Voltage = 18 V
24
21
18
15
12
9
Input Voltage = 12 V
Input Voltage = 12 V
Input Voltage = 4.5 V
Input Voltage = 4.5 V
6
1.4
1.3
3
0
−50 −30 −10
10
30
50
70
90
110 130
−50 −30 −10
10
30
50
70
90 110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. ICC Shut Down Current vs.
Temperature
Figure 10. NCP3170 Enabled Current vs.
Temperature
806
805
804
803
802
801
800
799
503
502
501
500
499
498
Input Voltage = 18 V
Input Voltage = 18 V
Input Voltage = 4.5 V
Input Voltage = 12 V
Input Voltage = 12 V
Input Voltage = 4.5 V
497
496
798
797
−50 −30 −10
10
30
50
70
90 110 130
−50 −30 −10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Bandgap Reference Voltage vs.
Temperature
Figure 12. Switching Frequency vs.
Temperature
735
730
880
875
Over Voltage Protection Falling
Under Voltage Protection Rising
725
720
715
870
865
Under Voltage Protection Falling
Over Voltage Protection Rising
860
855
710
705
−50 −30 −10
10
30
50
70
90
110 130
−50 −30 −10
10
30
50
70
90 110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Input Under Voltage Protection at
12 V vs. Temperature
Figure 14. Input Over Voltage Protection at
12 V vs. Temperature
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NCP3170
TYPICAL PERFORMANCE CHARACTERISTICS
(Circuit from Figure 1, T = 25°C, V = V = 12 V, V = 3.3 V unless otherwise specified)
A
IN
EN
OUT
130
120
110
40
35
30
25
Input Voltage = 4.5 V
100
90
Input Voltage = 4.5 V
Input Voltage = 12 V, 18 V
Input Voltage = 12 V, 18 V
80
20
15
70
60
−50 −30 −10
10
30
50
70
90 110 130
−50 −30 −10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. High Side MOSFET RDS(on) vs.
Temperature
Figure 16. Low Side MOSFET RDS(on) vs.
Temperature
215
210
1001.5
1001.0
1000.5
1000.0
999.5
Input Voltage = 12 V
Input Voltage = 4.5 V
205
200
195
190
999.0
Input Voltage = 4.5 V
Input Voltage = 18 V
Input Voltage = 18 V
998.5
998.0
997.5
Input Voltage = 12 V
185
180
997.0
996.5
−50 −30 −10
10
30
50
70
90
110 130
−50 −30 −10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Transconductance vs. Temperature
Figure 18. Over Voltage Protection vs.
Temperature
4.45
4.40
Input Under Voltage Protection Rising
4.35
4.30
4.25
4.20
4.15
Input Under Voltage Protection Falling
4.10
4.05
−50 −30 −10
10
30
50
70
90
110 130
TEMPERATURE (°C)
Figure 19. Input Under Voltage Protection vs.
Temperature
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NCP3170
NCP3170A Efficiency and Thermal Derating
100
90
80
70
60
50
40
30
20
10
100
90
80
V = 5 V
o
V = 1.8 V
o
V = 3.3 V
V = 3.3 V
o
o
70
V = 1.2 V
o
V = 1.8 V
o
60
V = 1.2 V
o
50
40
30
20
10
0
12 V, 500 kHz
Efficiency
5 V, 500 kHz
Efficiency
0
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 20. Efficiency (VIN = 12 V) vs. Load
Current
Figure 21. Efficiency (VIN = 5 V) vs. Load Current
Thermal derating curves for the SOIC−8 package part under typical input and output conditions based on the evaluation board.
The ambient temperature is 25°C with natural convection (air speed < 50 LFM) unless otherwise specified.
5
4
3
2
1
0
5
4
3
2
1
0
1.2 V, 1.8 V,
3.3 V
1.2 V, 1.8 V,
3.3 V, 5.0 V
25
35
45
55
65
75
85
25
35
45
55
65
75
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 22. 500 kHz Derating Curves at 5 V
Figure 23. 500 kHz Derating Curves at 12 V
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NCP3170
NCP3170B Efficiency and Thermal Derating
100
90
80
70
60
50
40
30
20
100
90
80
V = 1.8 V
o
V = 3.3 V
V = 3.3 V
o
V = 5 V
o
o
70
V = 1.2 V
o
V = 1.8 V
o
60
50
40
30
20
10
0
V = 1.2 V
o
12 V, 1 MHz
Efficiency
5 V, 1 MHz
Efficiency
10
0
0
1
2
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 24. 12 V, 1 MHz Efficiency
Figure 25. 5 V, 1 MHz Efficiency
Thermal derating curves for the SOIC−8 package part under typical input and output conditions based on the evaluation board.
The ambient temperature is 25°C with natural convection (air speed < 50 LFM) unless otherwise specified.
5
4
3
2
1
0
5
4
3
2
1
0
1.2 V,
1.8 V
1.2 V,
1.8 V
3.3 V
3.3 V
5.0 V
25
35
45
55
65
75
85
25
35
45
55
65
75
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 26. 1 MHz Derating Curves at 5 V Input
Figure 27. 1 MHz Derating Curves at 12 V Input
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NCP3170
DETAILED DESCRIPTION
The NCP3170 is a current-mode, step down regulator
The enable pin can be used to delay a turn on by
connecting a capacitor as shown in Figure 30.
with an integrated high-side PMOS switch and a low-side
NMOS switch. It operates from a 4.5 V to 18 V input voltage
range and supplies up to 3 A of load current. The duty ratio
can be adjusted from 8% to 92% allowing a wide output
voltage range. Features include enable control, Power-On
Reset (POR), input under voltage lockout, fixed internal soft
start, power good indication, over voltage protection, and
thermal shutdown.
4.5 V−18 V
VIN
C1
IN
R
bias
EN
NCP3170
C1
DLY
Enable and Soft-Start
AGND
An internal input voltage comparator not shown in
Figure 28 will force the part to disable below the minimum
input voltage of 4.13 V. The input under voltage disable
feature is used to prevent improper operation of the
converter due to insufficient voltages. The converter can be
turned on by tying the enable pin high and the part will
default to be input voltage enabled. The enable pin should
never be left floating.
Figure 30. Delay Enable
If the designer would like to add hysteresis to the enable
threshold it can be added by use of a bias resistor to the
output. The hysteresis is created once soft start has initiated.
With the output voltage rising, current flows into the enable
node, raising the voltage. The thresholds for enable as well
as hysteresis can be calculated using Equation 1.
4.5 V−18 V
VIN
VINHYS + VINStart * ENTH ) R1UV
C1
IN
(eq. 1)
VOUT * ENTH
ENTH
R2UV
ƪ
ƫ
*
R3UV
EN
NCP3170
ǒ
Ǔ
R1UV R2UV ) R3UV
(eq. 2)
VINStart + ENTH
ƪ
1 )
ƫ
R2UV R3UV
AGND
where:
Figure 28. Input Voltage Enable
EN
= Enable Threshold
TH
VIN
= Input Voltage Start Threshold
= High Side Resistor
= Low Side Resistor
= Hysteresis Bias Resistor
= Regulated Output Voltage
START
If an adjustable Under Voltage Lockout (UVLO)
threshold is required, the EN pin can be used. The trip
voltage of the EN pin comparator is 1.38 V typical. Upon
application of an input voltage greater than 4.41 V, the VIN
UVLO will release and the enable will be checked to
determine if switching can commence. Once the 1.38 V trip
voltage is crossed, the part will enable and the soft start
sequence will initiate. If large resistor values are used, the
EN pin should be bypassed with a 1 nF capacitor to prevent
coupling problems from the switch node.
R1
R2
R3
UV
UV
UV
V
OUT
4.5 V−18 V
C1
VIN
IN
R1
UV
EN
4.5 V−18 V
VIN
NCP3170
R2
R3
UV
UV
C1
IN
AGND
R1
V
OUT
UV
EN
NCP3170
Figure 31. Added Hysteresis to the Enable UVLO
R2
C1
UV
UV
AGND
Figure 29. Input Under Voltage Lockout Enable
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NCP3170
The part can be enabled with standard TTL or high voltage
logic by using the configuration below.
slowly raises and the OTA regulates the output voltage to the
divided reference voltage. In a pre-biased condition, the
voltage at the FB pin is higher than the internal reference
voltage, so the OTA will keep the COMP voltage at ground
potential. As the internal reference is slewed up, the COMP
pin is held low until the FB pin voltage surpasses the internal
reference voltage, at which time the COMP pin is allowed
to respond to the OTA error signal. Since the bottom of the
PWM ramp is at 0.6 V there will be a slight delay between
the time the internal reference voltage passes the FB voltage
and when the part starts to switch. Once the COMP error
signal intersects with the bottom of the ramp, the high side
switch is turned on followed by the low side switch. After the
internal reference voltage has surpassed the FB voltage, soft
start proceeds normally without output voltage discharge.
4.5 V−18 V
VIN
C1
IN
R1
LOG
EN
NCP3170
C1
LOG
R2
LOG
AGND
Figure 32. Logic Turn-on
The enable can also be used for power sequencing in
conjunction with the Power Good (PG) pin as shown in
Figure 33. The enable pin can either be tied to the output
voltage of the master voltage or tied to the input voltage with
a resistor to the PG pin of the master regulator.
Power Good
The output voltage of the buck converter is monitored at
the feedback pin of the output power stage. Two
comparators are placed on the feedback node of the OTA to
monitor the operating window of the feedback voltage as
shown in Figure 34. All comparator outputs are ignored
during the soft start sequence as soft start is regulated by the
OTA since false trips would be generated. Further, the PG
pin is held low until the comparators are evaluated. PG state
does not affect the switching of the converter. After the soft
start period has ended, if the feedback is below the reference
4.5 V−18 V
V
o1
VIN
EN
VSW
FB
PG
voltage of comparator 1 (V < 0.726), the output is
FB
AGND
considered operational undervoltage (OUV). The device
will indicate the under voltage situation by the PG pin
remaining low with a 100 kW pull-up resistance. When the
feedback pin voltage rises between the reference voltages of
V
o1
NCP3170
4.5 V−18 V
V
o2
V
VIN
EN
comparator 1 and comparator 2 (0.726 < V < 0.862),
then the output voltage is considered power good and the PG
pin is released. Finally, if the feedback voltage is greater than
o2
FB
VSW
FB
comparator 2 (V > 0.862), the output voltage is
FB
considered operational overvoltage (OOV). The OOV will
be indicated by the PG pin remaining low. A block diagram
of the OOV and OUV functionality as well as a graphical
representation of the PG pin functionality is shown in
Figures 34 through 36.
AGND
NCP3170
Figure 33. Enable Two Converter Power Sequencing
12 V
Once the part is enabled, the internal reference voltage is
slewed from ground to the set point of 800 mV. The slewing
process occurs over a 4.5 ms period, reducing the current
draw from the upstream power source, reducing stress on
internal MOSFETS, and ensuring the output inductor does
not saturate during start-up.
FB
800 mV
+
SOFT
Start
Complete
100 kW
−
Comp 2
PG
+
−
862 mV
726 mV
+
−
Pre-Bias Start-up
When starting into a pre-bias load, the NCP3170 will not
discharge the output capacitors. The soft start begins with
the internal reference at ground. Both the high side switch
and low side switches are turned off. The internal reference
Comp 1
Figure 34. OOV and OUV System
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NCP3170
Light Load Operation
Light load operation is generally a load that is 1 mA to
300 mA where a load is in standby mode and requires very
little power. During light load operation, the regulator
emulates the operation of a non-synchronous buck converter
and the regulator is allowed to skip pulses. The
non-synchronous buck emulation is accomplished by
detecting the point at which the current flowing in the
inductor goes to zero and turning the low side switch off. At
the point when the current goes to zero, if the low side switch
is not turned off, current would reverse, discharging the
output capacitor. Since the low side switch is shutoff, the
only conduction path is through the body diode of the low
side MOSFET, which is back biased. Unlike traditional
synchronous buck converters, the current in the inductor
will become discontinuous. As a result, the switch node will
oscillate with the parasitic inductances and capacitances
connected to the switch node. The OTA will continue to
regulate the output voltage, but will skip pulses based on the
output load shown in Figure 37.
OOV
Hysteresis = 14 mV
Hysteresis = 14 mV
V
OOV
V
REF
V
OUV
= 862 mV
= 0.8 V
Power Good
OUV
= 726 mV
Figure 35. OOV and OUV Window
0.862 V
0.8 V
0.726 V
FB Voltage
Soft Start Complete
6 ms = 166 kHz
Power Good
2 ms = 50 kHz
Figure 36. OOV and OUV Diagram
Switch
Node
If the power good function is not used, it can be connected
to the VSW node to reduce thermal resistance. Do not
connect PG to the VSW node if the application is turning on
into pre-bias.
0V
Zero Current Point
Inductor
Current
0A
Feedback
Voltage
Switching Frequency
Reference Votlage
Ramp Threshold
COMP
Voltage
The NCP3170 switching frequency is fixed and set by an
internal oscillator. The practical switching frequency could
range from 450 kHz to 550 kHz for the NCP3170A and
900 kHz to 1.1 MHz for the NCP3170B due to device
variation.
Figure 37. Light Load Operation
PROTECTION FEATURES
Over Current Protection
Switch
Current is limited to the load on a pulse by pulse basis.
During each high side on period, the current is compared
against an internally set limit. If the current limit is
exceeded, the high side and low side MOSFETS are shutoff
and no pulses are issued for 13.5 ms. During that time, the
output voltage will decay and the inductor current will
discharge. After the discharge period, the converter will
initiate a soft start. If the load is not released, the current will
build in the inductor until the current limit is exceeded, at
which time the high side and low side MOSFETS will be
shut off and the process will continue. If the load has been
released, a normal soft start will commence and the part will
continue switching normally until the current limit is
exceeded.
Node
13.5 ms Hold Time
Current Limit
Inductor
Current
Figure 38. Over Current Protection
Thermal Shutdown
The thermal limit, while not a protection feature, engages
at 150°C in case of thermal runaway. When the thermal
comparator is tripped at a die temperature of 150°C, the part
must cool to 120°C before a restart is allowed. When thermal
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12
NCP3170
trip is engaged, switching ceases and high side and low side
operating in PWM mode. Figure 41 and 42 below shows the
safe operating area for the NCP3170A and B respectively.
While not shown in the safe operating area graph, the output
voltage is capable of increasing to the 93% duty ratio
limitation providing a high output voltage such as 16 V. If
the application requires a high duty ratio such as converting
from 14 V to 10 V the converter will operate normally until
the maximum duty ratio is reached. For example, if the input
voltage were 16 V and the user wanted to produce the
highest possible output voltage at full load, a good rule of
thumb is to use 80% duty ratio. The discrepancy between the
usable duty ratio and the actual duty ratio is due to the
voltage drops in the system, thus leading to a maximum
output voltage of 12.8 V rather than 14.8 V. The actual
achievable output to input voltage ratio is dependent on
layout, component selection, and acceptable output voltage
tolerance.
MOSFETs are driven off. Further, the power good indicator
will pull low until the thermal trip has been released. Once
the die temperature reaches 120°C the part will reinitiate
soft-start and begin normal operation.
Switch
Node
Output
Voltage
Thermal
Comparator
150°C
120°C
IC
Temperature
Figure 39. Over Temperature Shutdown
Over Voltage Protection
Upon the completion of soft start, the output voltage of the
buck converter is monitored at the FB pin of the output
power stage. One comparator is placed on the feedback node
to provide over voltage protection. In the event an over
voltage is detected, the high side switch turns off and the low
side switch turns on until the feedback voltage falls below
the OOV threshold. Once the voltage has fallen below the
OOV threshold, switching continues normally as displayed
in Figure 40.
1.0 V
Figure 41. NCP3170A Safe Operating Area
0.862 V
0.800 V
0.726 V
FB Voltage
Softstart
Complete
Power
Good
Low Side
Switch
Figure 40. Over Voltage Low Side Switch Behavior
Figure 42. NCP3170B Safe Operating Area
Duty Ratio
Design Procedure
The duty ratio can be adjusted from 8% to 92% allowing
a wide output voltage range. The low 8% duty ratio limit will
restrict the PWM operation. For example if the application
is converting to 1.2 V the converter will perform normally
if the input voltage is below 15.5 V. If the input voltage
exceeds 15.5 V while supplying 1.2 V output voltage the
converter can skip pulses during operation. The skipping
pulse operation will result in higher ripple voltage than when
When starting the design of a buck regulator, it is important
to collect as much information as possible about the behavior
of the input and output before starting the design.
ON Semiconductor has a Microsoft Excel based design
tool available online under the design tools section of the
NCP3170 product page. The tool allows you to capture your
®
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13
NCP3170
design point and optimize the performance of your regulator
based on your design criteria.
DI
ra +
(eq. 6)
IOUT
where:
ąDI
Table 5. DESIGN PARAMETERS
Design Parameter
= Ripple current
= Output current
= Ripple current ratio
Example Value
9 V to 16 V
3.3 V
I
OUT
Input Voltage (V
)
IN
ra
Output Voltage (V
)
OUT
Using the ripple current rule of thumb, the user can
establish acceptable values of inductance for a design using
Equation 6.
Input Ripple Voltage (VCC
)
200 mV
20 mV
RIPPLE
Output Ripple Voltage (V
)
OUTRIPPLE
Output Current Rating (I
Operating Frequency (F
)
3 A
OUT
VOUT
( )
1 * D ³
)
500 kHz
LOUT
+
SW
IOUT ra FSW
(eq. 7)
The buck converter produces input voltage (V ) pulses
that are LC filtered to produce a lower DC output voltage
IN
12 V
( )
1 * 27.5%
4.7 mH +
3.0 A 34% 500 kHz
(V ). The output voltage can be changed by modifying
OUT
the on time relative to the switching period (T) or switching
frequency. The ratio of high side switch on time to the
switching period is called duty ratio (D). Duty ratio can also
where:
D
= Duty ratio
= Switching frequency
= Output current
= Output inductance
= Ripple current ratio
F
SW
be calculated using V , V , the Low Side Switch Voltage
OUT IN
I
OUT
Drop (V
), and the High Side Switch Voltage Drop
LSD
L
OUT
(V
).
HSD
ra
1
(eq. 3)
(eq. 4)
FSW
TON
+
19
T
TOFF
T
17
15
13
11
9
(
)
1 * D +
D +
D +
T
VOUT ) VLSD
VIN * VHSD ) VLSD
[
(eq. 5)
VOUT
VIN
3.3 V
12 V
D +
³ 27.5% +
18 V
where:
D
FSW
T
TOFF
TON
= Duty ratio
7 V
= Switching frequency
= Switching period
= High side switch off time
= High side switch on time
= Input voltage
= High side switch voltage drop
= Low side switch voltage drop
= Output voltage
7
4.7 mH
5
V
IN
3
VHSD
VLSD
VOUT
4.4 V
1
10 13 16 19 22 25 28 31 34 37 40
RIPPLE CURRENT RATIO (%)
Inductor Selection
Figure 43. Inductance vs. Current Ripple Ratio
When selecting an inductor, the designer may employ a
rule of thumb for the design where the percentage of ripple
current in the inductor should be between 10% and 40%.
When using ceramic output capacitors, the ripple current can
be greater because the ESR of the output capacitor is smaller,
thus a user might select a higher ripple current. However,
when using electrolytic capacitors, a lower ripple current
will result in lower output ripple due to the higher ESR of
electrolytic capacitors. The ratio of ripple current to
maximum output current is given in Equation 6.
When selecting an inductor, the designer must not exceed
the current rating of the part. To keep within the bounds of
the part’s maximum rating, a calculation of the RMS current
and peak current are required.
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NCP3170
ra2
12
(
)
VOUT 1 * D
Ǹ1 )
Ǹ1 )
IRMS + IOUT
³
IPP
+
³
LOUT FSW
(eq. 8)
(eq. 11)
34%2
12
(
)
3.3 V 1 * 27.5%
3.01 A + 3 A
³
1.02 A +
4.7 mH 500 kHz
where:
where:
D
I
I
= Output current
= Inductor RMS current
= Ripple current ratio
OUT
= Duty ratio
= Switching frequency
RMS
F
SW
PP
ra
I
= Peak-to-peak current of the inductor
= Output inductance
= Output voltage
L
V
ǒ1 ) raǓ
OUT
IPK + IOUT
³
OUT
2
(eq. 9)
From Equation 11, it is clear that the ripple current
increases as L decreases, emphasizing the trade-off
between dynamic response and ripple current.
3.51 A + 3 A ǒ1 ) 34%Ǔ
OUT
2
where:
The power dissipation of an inductor falls into two
categories: copper and core losses. Copper losses can be
further categorized into DC losses and AC losses. A good
first order approximation of the inductor losses can be made
using the DC resistance as shown below:
I
I
= Output current
= Inductor peak current
= Ripple current ratio
OUT
PK
ra
A standard inductor should be found so the inductor will
be rounded to 4.7 mH. The inductor should support an RMS
current of 3.01 A and a peak current of 3.51 A. A good
design practice is to select an inductor that has a saturation
current that exceeds the maximum current limit with some
margin.
2
LPCU_DC + IRMS DCR ³
(eq. 12)
61 mW + 3.012 6.73 mW
where:
DCR
= Inductor DC resistance
= Inductor RMS current
The final selection of an output inductor has both
mechanical and electrical considerations. From
I
RMS
a
LP
= Inductor DC power dissipation
CU_DC
mechanical perspective, smaller inductor values generally
correspond to smaller physical size. Since the inductor is
often one of the largest components in the regulation system,
a minimum inductor value is particularly important in space
constrained applications. From an electrical perspective, the
maximum current slew rate through the output inductor for
a buck regulator is given by Equation 10.
The core losses and AC copper losses will depend on the
geometry of the selected core, core material, and wire used.
Most vendors will provide the appropriate information to
make accurate calculations of the power dissipation at which
point the total inductor losses can be captured by the
equation below:
LPtot + LPCU_DC ) LPCU_AC ) LPCore
³
VIN * VOUT
(eq. 13)
SlewRateLOUT
+
+
³
LOUT
67 mW + 61 mW ) 5 mW ) 1 mW
(eq. 10)
12 V * 3.3 V
4.7 mH
where:
LP
A
1.85
ms
= Inductor core power dissipation
= Inductor AC power dissipation
= Inductor DC power dissipation
= Total inductor losses
Core
LP
LP
LP
CU_AC
CU_DC
tot
where:
L
= Output inductance
= Input voltage
OUT
V
V
IN
= Output voltage
OUT
Output Capacitor Selection
The important factors to consider when selecting an
output capacitor are DC voltage rating, ripple current rating,
output ripple voltage requirements, and transient response
requirements.
The output capacitor must be able to operate properly for
the life time of a product. When selecting a capacitor it is
important to select a voltage rating that is de-rated to the
guaranteed operating life time of a product. Further, it is
important to note that when using ceramic capacitors, the
capacitance decreases as the voltage applied increases; thus
a ceramic capacitor rated at 100 mF 6.3 V may measure
Equation 10 implies that larger inductor values limit the
regulator’s ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply the load current until the
inductor current reaches the output load current level.
Reduced inductance to increase slew rates results in larger
values of output capacitance to maintain tight output voltage
regulation. In contrast, smaller values of inductance increase
the regulator’s maximum achievable slew rate and decrease
the necessary capacitance at the expense of higher ripple
current. The peak-to-peak ripple current for NCP3170 is
given by the following equation:
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NCP3170
ESL IPP FSW
100 mF at 0 V but measure 20 mF with an applied voltage of
VESLON
+
³
3.3 V depending on the type of capacitor selected.
The output capacitor must be rated to handle the ripple
current at full load with proper derating. The capacitor RMS
ratings given in datasheets are generally for lower switching
frequencies than used in switch mode power supplies, but a
multiplier is given for higher frequency operation. The RMS
current for the output capacitor can be calculated below:
ra
D
(eq. 16)
(eq. 17)
1 nH @ 1.01 A @ 500 kHz
1.84 mV +
27.5%
ESL IPP FSW
VESLOFF
+
³
(
)
1 * D
1 nH 1.1 A 500 kHz
0.7 mV +
(
)
1 * 27.5%
CORMS + I
³
OUT Ǹ
12
where:
D
ESL
(eq. 14)
34%
= Duty ratio
0.294 A + 3.0 A
Ǹ
= Capacitor inductance
= Switching frequency
= Peak-to-peak current
12
F
SW
PP
where:
Co
I
= Output capacitor RMS current
= Output current
RMS
I
The output capacitor is a basic component for fast
response of the power supply. For the first few microseconds
of a load transient, the output capacitor supplies current to
the load. Once the regulator recognizes a load transient, it
adjusts the duty ratio, but the current slope is limited by the
inductor value.
During a load step transient, the output voltage initially
drops due to the current variation inside the capacitor and the
ESR (neglecting the effect of the ESL).
OUT
ra
= Ripple current ratio
The maximum allowable output voltage ripple is a
combination of the ripple current selected, the output
capacitance selected, the Equivalent Series Inductance
(ESL), and Equivalent Series Resistance (ESR).
The main component of the ripple voltage is usually due
to the ESR of the output capacitor and the capacitance
selected, which can be calculated as shown in Equation 14:
DVOUT−ESR + ITRAN COESR
³
(eq. 18)
1
ǒ
Ǔ
VESR_C + IOUT ra COESR
)
³
7.5 mV + 1.5 A 5 mW
8 FSW COUT
where:
(eq. 15)
Co
= Output capacitor Equivalent Series
Resistance
= Output transient current
= Voltage deviation of V
effects of ESR
ESR
1
ǒ5 mW )
Ǔ
10.89 mV + 3 34%
8 500 kHz 44 mF
I
TRAN
ąDV
_
due to the
where:
OUT ESR
OUT
Co
C
F
= Output capacitor ESR
= Output capacitance
= Switching frequency
= Output current
ESR
OUT
SW
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is given by
the following equation:
I
OUT
ra
= Ripple current ratio
= Ripple voltage from the capacitor
V
ESR_C
ǒ
Ǔ2
ITRAN LOUT FSW
The impedance of a capacitor is a function of the
frequency of operation. When using ceramic capacitors, the
ESR of the capacitor decreases until the resonant frequency
is reached, at which point the ESR increases; therefore the
ripple voltage might not be what one expected due to the
switching frequency. Further, the method of layout can add
resistance in series with the capacitance, increasing ripple
voltage.
The ESL of capacitors depends on the technology chosen,
but tends to range from 1 nH to 20 nH, where ceramic
capacitors have the lowest inductance and electrolytic
capacitors have the highest. The calculated contributing
voltage ripple from ESL is shown for the switch on and
switch off below:
DVOUT−DIS
+
³
ǒ
Ǔ
2 FCROSS COUT VIN * VOUT
(eq. 19)
2
(
)
1.5 4.7 mH 500 kHz
138.1 mV +
ǒ
Ǔ
2 50 kHz 44 mF 12 V * 3.3 V
where:
C
OUT
= Output capacitance
= Duty ratio
D
F
F
= Switching frequency
= Loop cross over frequency
= Output transient current
= Output inductor value
= Input voltage
SW
CROSS
TRAN
I
L
OUT
V
V
IN
= Output voltage
OUT
ąDV
_
= Voltage deviation of V
due to the
OUT DIS
OUT
effects of capacitor discharge
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NCP3170
In a typical converter design, the ESR of the output
capacitor bank dominates the transient response. Please note
that DV and DV are out of phase with each
The equation reaches its maximum value with D = 0.5 at
which point the input capacitance RMS current is half the
output current. Loss in the input capacitors can be calculated
with the following equation:
_
OUT DIS
OUT_ESR
other, and the larger of these two voltages will determine the
maximum deviation of the output voltage (neglecting the
effect of the ESL). It is important to note that the converters
frequency response will change when the NCP3170 is
operating in synchronous mode or non-synchronous mode
due to the change in plant response from CCM to DCM. The
effect will be a larger transient voltage excursion when
transitioning from no load to full load quickly.
ǒ
Ǔ2
PCIN + CINESR IinRMS
(eq. 21)
ǒ
Ǔ2
18 mW + 10 mW 1.34 A
where:
CIN
= Input capacitance Equivalent Series
Resistance
ESR
Iin
= Input capacitance RMS current
= Power loss in the input capacitor
RMS
Input Capacitor Selection
P
CIN
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize losses and input voltage
ripple. The RMS value of the input ripple current is:
Due to large di/dt through the input capacitors, electrolytic
or ceramics should be used. If a tantalum capacitor must be
used, it must be surge protected, otherwise capacitor failure
could occur.
Ǹ
( )
D 1 * D ³
IinRMS + IOUT
(eq. 20)
Ǹ
(
)
1.34 A + 3 A 27.5% 1 * 27.5%
where:
D
= Duty ratio
Iin
= Input capacitance RMS current
= Load current
RMS
I
OUT
POWER MOSFET DISSIPATION
where:
Power dissipation, package size, and the thermal
environment drive power supply design. Once the
dissipation is known, the thermal impedance can be
calculated to prevent the specified maximum junction
temperatures from being exceeded at the highest ambient
temperature.
Power dissipation has two primary contributors:
conduction losses and switching losses. The high-side
MOSFET will display both switching and conduction
losses. The switching losses of the low side MOSFET will
not be calculated as it switches into nearly zero voltage and
the losses are insignificant. However, the body diode in the
low-side MOSFET will suffer diode losses during the
non-overlap time of the gate drivers.
I
R
P
= RMS current in the high side MOSFET
= On resistance of the high side MOSFET
= Conduction power losses
RMS_HS
DS(ON)_HS
COND
Using the ra term from Equation 6, I
becomes:
RMS
ra2
ǸD ǒ1 )
Ǔ
(eq. 24)
IRMS_HS + IOUT
12
where:
D
ra
I
I
= Duty ratio
= Ripple current ratio
= Output current
OUT
= High side MOSFET RMS current
RMS_HS
Starting with the high-side MOSFET, the power
dissipation can be approximated from:
The second term from Equation 22 is the total switching
loss and can be approximated from the following equations.
PD_HS + PCOND ) PSW_TOT
(eq. 22)
PSW_TOT + PSW ) PDS ) PRR
(eq. 25)
where:
P
where:
= Conduction losses
= Power losses in the high side MOSFET
= Total switching losses
P
DS
= High side MOSFET drain to source losses
= High side MOSFET reverse recovery
losses
COND
P
P
P
RR
D_HS
SW_TOT
P
P
= High side MOSFET switching losses
= High side MOSFET total switching losses
SW
The first term in Equation 21 is the conduction loss of the
high-side MOSFET while it is on.
SW_TOT
Ǔ2
(eq. 23)
ǒ
PCOND + IRMS_HS RDS(on)_HS
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NCP3170
The first term for total switching losses from Equation 25
are the losses associated with turning the high-side
MOSFET on and off and the corresponding overlap in drain
voltage and current.
Q
= MOSFET gate to drain gate charge
= MOSFET gate resistance
= Drive pull down resistance
= MOSFET fall time
GD
G
R
R
HSPD
FALL
t
V
V
= Clamp voltage
= MOSFET gate threshold voltage
CL
TH
PSW + PTON ) PTOFF
+
(eq. 26)
1
ǒ
Ǔ
ǒ
Ǔ
+
IOUT VIN FSW tRISE ) tFALL
2
Next, the MOSFET output capacitance losses are caused
by both the high-side and low-side MOSFETs, but are
dissipated only in the high-side MOSFET.
where:
F
I
= Switching frequency
= Load current
SW
1
OUT
2
(eq. 29)
PDS
+
COSS VIN FSW
P
= High side MOSFET switching losses
= Turn on power losses
= Turn off power losses
= MOSFET fall time
2
SW
P
P
TON
TOFF
FALL
RISE
where:
C
= MOSFET output capacitance at 0 V
= Switching frequency
= MOSFET drain to source charge losses
= Input voltage
OSS
SW
DS
t
t
F
P
= MOSFET rise time
V
IN
= Input voltage
V
IN
When calculating the rise time and fall time of the high
side MOSFET, it is important to know the charge
characteristic shown in Figure 44.
Finally, the loss due to the reverse recovery time of the
body diode in the low−side MOSFET is shown as follows:
PRR + QRR VIN FSW
(eq. 30)
where:
F
SW
P
RR
= Switching frequency
= High side MOSFET reverse recovery
losses
Q
RR
V
IN
= Reverse recovery charge
= Input voltage
The low-side MOSFET turns on into small negative
voltages so switching losses are negligible. The low-side
MOSFET’s power dissipation only consists of conduction
Vth
loss due to R
periods.
and body diode loss during non-overlap
DS(on)
PD_LS + PCOND ) PBODY
(eq. 31)
where:
P
P
P
= Low side MOSFET body diode losses
= Low side MOSFET conduction losses
= Low side MOSFET losses
BODY
COND
D_LS
Figure 44. High Side MOSFET Total Charge
QGD
IG1
QGD
tRISE
+
+
(eq. 27)
ǒ
Ǔ ǒ
Ǔ
Conduction loss in the low-side MOSFET is described as
VCL * VTH ń RHSPU ) RG
follows:
where:
IG1
ǒ
Ǔ2
= Output current from the high-side gate
drive
= MOSFET gate to drain gate charge
= Drive pull up resistance
= MOSFET gate resistance
= MOSFET rise time
PCOND + IRMS_LS RDS(on)_LS
(eq. 32)
where:
Q
GD
I
= RMS current in the low side
= Low-side MOSFET on resistance
= High side MOSFET conduction losses
RMS_LS
R
HSPU
R
G
R
P
DS(ON)_LS
COND
t
RISE
V
V
= Clamp voltage
= MOSFET gate threshold voltage
CL
TH
ra2
Ǹ
ǒ1 )
Ǔ
(eq. 33)
( )
1 * D
IRMS_LS + IOUT
12
QGD
QGD
where:
D
tFALL
+
+
(eq. 28)
IG2
= Duty ratio
= Load current
ǒ
Ǔ ǒ
Ǔ
VCL * VTH ń RHSPD ) RG
I
I
OUT
where:
IG2
= RMS current in the low side
= Ripple current ratio
RMS_LS
= Output current from the low-side gate
drive
ra
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NCP3170
Compensation Network
The body diode losses can be approximated as:
To create a stable power supply, the compensation
network around the transconductance amplifier must be
used in conjunction with the PWM generator and the power
stage. Since the power stage design criteria is set by the
application, the compensation network must correct the
overall output to ensure stability. The NCP3170 is a current
mode regulator and as such there exists a voltage loop and
a current loop. The current loop causes the inductor to act
like a current source which governs most of the
characteristics of current mode control. The output inductor
and capacitor of the power stage form a double pole but
because the inductor is treated like a current source in closed
loop, it becomes a single pole system. Since the feedback
loop is controlling the inductor current, it is effectively like
having a current source feeding a capacitor; therefore the
pole is controlled by the load and the output capacitance. A
table of compensation values for 500 kHz and 1 MHz is
provided below for two 22 mF ceramic capacitors. The table
also provides the resistor value for CompCalc at the defined
operating point.
ǒ
Ǔ
(eq. 34)
PBODY + VFD IOUT FSW NOLLH ) NOLHL
where:
F
I
= Switching frequency
= Load current
SW
OUT
NOL
= Dead time between the high-side
MOSFET turning off and the low-side
MOSFET turning on, typically 30 ns
= Dead time between the low-side
MOSFET turning off and the high-side
MOSFET turning on, typically 30 ns
= Low-side MOSFET body diode losses
= Body diode forward voltage drop
typically 0.92 V
HL
NOLLH
P
BODY
V
FD
Table 6. COMPENSATION VALUES
VIN
(V)
V
L
R1
R2
Rf
Cf
Cc
Rc
Cp
Resistance for
Current Gain
out
out
(V)
0.8
1.0
1.1
1.2
1.5
1.8
2.5
3.3
5.0
10.68
14.8
0.8
1.0
1.1
1.2
1.5
1.8
2.5
3.3
(mF)
1.8
2.5
2.5
2.5
3.6
3.6
4.7
4.7
7.2
7.2
7.2
1.8
2.5
2.5
2.5
3.6
3.6
3.6
3.6
(kW)
(kW)
(kW)
(pF)
(nF)
(kW)
(pF)
12
12
12
12
12
12
12
12
12
12
18
5
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
NI
NI
1
1
1
1
1
1
1
1
1
1
NI
1
1
1
1
1
1
1
NI
NI
15
10
10
10
10
8.2
6.8
3.9
3.9
6.8
NI
NI
0.825
2
15
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
15
NI
NI
NI
NI
NI
NI
NI
3.6
4
100
66.5
49.9
28.7
20
150
150
150
150
150
150
150
150
150
150
NI
20
20
20
20
25
27
27
30
30
15
28
30
30
30
30
50
50
2
2.49
2.49
3.74
4.99
10
11.8
7.87
4.75
2.05
1.43
NI
10
NCP3170A
6.98
NI
5
100
66.5
49.9
28.7
20
150
150
150
150
150
150
150
15
10
10
10
10
6.8
6.8
0.825
2
5
5
2
5
2.49
2.49
4.99
4.99
5
5
11.8
7.87
5
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19
NCP3170
Table 6. COMPENSATION VALUES (continued)
VIN
(V)
V
L
R1
R2
Rf
Cf
Cc
Rc
Cp
Resistance for
Current Gain
out
out
(V)
1.2
1.5
1.8
2.5
3.3
5.0
10.68
14.8
0.8
1.0
1.1
1.2
1.5
1.8
2.5
3.3
(mF)
1.5
1.8
1.8
2.7
3.3
3.3
1.5
3.3
1.0
1.0
1.0
1.5
1.5
1.5
1.8
1.8
(kW)
(kW)
49.9
28.7
20
(kW)
(pF)
(nF)
(kW)
(pF)
12
12
12
12
12
12
12
18
5
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
1
1
82
82
82
82
82
82
82
82
NI
NI
NI
82
82
82
82
82
2.7
2.7
2.7
1.8
1.5
2.2
2.2
2.2
15
6.04
6.04
6.04
10
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
NI
20
22
22
32
52
52
52
52
20
28
42
55
55
55
55
55
1
11.8
7.87
4.75
2.05
1.43
NI
1
1
12.1
8.25
5.1
1
1
1
5.1
NCP3170B
NI
NI
NI
1
0.499
1.69
3.61
6.04
6.04
10
5
100
66.5
49.9
28.7
20
6.8
3.9
2.7
2.7
1.8
1.8
1.8
5
5
5
1
5
1
5
11.8
7.87
1
10
5
1
10
To compensate the converter we must first calculate the
current feedback
where:
A
= Un-scaled gain
F
I
L
M
V
V
= Switching Frequency
= Output Current
= Output inductor value
= Current feedback
= Input Voltage
SW
F
L
V
OUT
RAMP
SW
M +
) 1 ³
(eq. 35)
OUT
R
VIN
MAP
OUT
500 kHz 4.7 mH 0.33 V
7.299 +
) 1
IN
3.3 V
32
12 V)1.46
1000
ǒ
Ǔ
W 12 V
= Output Voltage
OUT
Next the DC gain of the plant must be calculated.
where:
A
G +
³
RMAP
F
SW
= Switching Frequency
= Output inductor value
= Current feedback
= Input Voltage
= Output Voltage
(eq. 37)
L
OUT
0.339 W
33.016 +
M
Vin
3.3 V
32
12 V)1.46
ǒ
Ǔ
W
V
V
R
OUT
1000
= Slope Compensation Ramp
= Current Sense Resistance
RAMP
MAP
where:
G
A
= DC gain of the plant
= Un−scaled gain
The un-scaled gain of the converter also needs to be
calculated as follows:
The amplitude ratio can be calculated using the following
equation:
1
A +
VOUT
M*0.5*M
0.8 V
VREF
VOUT
IOUT
VIN
Y +
³ 0.242 +
(eq. 38)
)
)
VOUT
LOUT FSW
3.3 V
(eq. 36)
1
where:
Vo
VREF
0.339 W +
3.3 V
12 V
= Output voltage
= Regulator reference voltage
= Amplitude ratio
7.299*0.5*7.299
3.0 A
3.3 V
4.7 mH 500 kHz
Y
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20
NCP3170
The ESR of the output capacitor creates a “zero” at the
determining phase margin. To start the design, a resistor
frequency as shown in Equation 39:
value should be chosen for R from which all other
1
components can be chosen. A good starting value is 24.9 kW.
The NCP3170 allows the output of the DC−DC regulator
to be adjusted down to 0.8 V via an external resistor divider
network. The regulator will maintain 0.8 V at the feedback
pin. Thus, if a resistor divider circuit was placed across the
1
FZESR
+
³
2p COESR COUT
(eq. 39)
1
723 kHz +
2p 5 mW 44 mF
feedback pin to V
voltage proportional to the resistor divider network in order
to maintain 0.8 V at the FB pin.
, the regulator will regulate the output
OUT
where:
CO
= Output capacitor ESR
= Output capacitor
ESR
C
OUT
FZ
= Output capacitor zero ESR frequency
ESR
V
OUT
1
FP
+
³
R1
2p A COUT
FB
(eq. 40)
1
10.664 kHz +
2p 0.339 W 44 mF
R2
where:
A
= Un-scaled gain
= Output capacitor
= Current mode pole frequency
Figure 46. Feedback Resistor Divider
C
OUT
P
F
The relationship between the resistor divider network
above and the output voltage is shown in Equation 41:
The two equations above define the bode plot that the
power stage has created or open loop response of the system.
The next step is to close the loop by considering the feedback
values. The closed loop crossover frequency should be less
than 1/10 of the switching frequency, which would place the
maximum crossover frequency at 50 kHz.
VREF
ǒ
Ǔ
R2 + R1
(eq. 41)
VOUT * VREF
where:
R
R
= Top resistor divider
= Bottom resistor divider
= Output voltage
1
2
Figure 45 shows a pseudo Type III transconductance error
amplifier.
V
OUT
V
REF
= Regulator reference voltage
The most frequently used output voltages and their
associated standard R and R values are listed in the table
below.
1
2
ZIN
CF
R1
R2
IEA
Table 7. OUTPUT VOLTAGE SETTINGS
V
O
(V)
R (kW)
1
R (kW)
2
ZFB
0.8
1.0
1.1
1.2
1.5
1.8
2.5
3.3
5.0
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
24.9
Open
100
CC
RC
CP
+
66.5
49.9
28.7
20
VREF
−
11.8
8.06
4.64
Figure 45. Pseudo Type III Transconductance Error
Amplifier
The compensation network consists of the internal error
amplifier and the impedance networks Z (R , R , and C )
IN
1
2
F
The compensation components for the Pseudo Type III
Transconductance Error Amplifier can be calculated using
the method described below. The method serves to provide
a good starting place for compensation of a power supply.
The values can be adjusted in real time using the
compensation tool CompCalc
and external Z (R , C , and C ). The compensation
FB
C
C
P
network has to provide a closed loop transfer function with
the highest 0 dB crossing frequency to have fast response
and the highest gain in DC conditions, so as to minimize load
regulation issues. A stable control loop has a gain crossing
with −20 dB/decade slope and a phase margin greater than
45°. Include worst-case component variations when
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21
NCP3170
1
The first pole to crossover at the desired frequency should
be setup at FPO to decrease at −20 dB per decade:
RC
+
³
2p CC FP
(eq. 44)
FCROSS
1
2.925 kW +
FPO
+
³
2p 5.12 nF 1.512 kHz
G
(eq. 42)
50 kHz
33.061
where:
1.512 kHz +
³
C
C
F
= Compensation capacitance
= Output capacitance
= Current mode pole frequency
= Compensation resistor
C
OUT
P
where:
F
cross
F
PO
= Cross over frequency
= Pole frequency to meet crossover
frequency
R
C
1
CP
+
³
G
= DC gain of the plant
2p RC FESR
(eq. 45)
The crossover combined compensation network can be
used to calculate the transconductance output compensation
network as follows:
1
75.2 pF +
2p 2.925 kW 723 kHz
where:
y gm
C
P
= Compensation pole capacitor
= Capacitor ESR zero frequency
= Compensation resistor
CC
+
³
2 p FPO
F
ESR
(eq. 43)
R
C
0.242 200 ms
2p 1.512 kHz
5.12 nF +
If the ESR frequency is greater than the switching
frequency, a CF compensation capacitor may be needed for
stability as the output LC filter is considered high Q and thus
will not give the phase boost at the crossover frequency.
Further at low duty cycles due to some blanking and filtering
of the current signal the current gain of the converter is not
constant and the current gain is small. Thus adding CF and
RF can give the needed phase boost.
where:
C
C
= Compensation capacitor
= Pole frequency
= Transconductance of amplifier
= Amplitude ratio
F
PO
gm
y
R1 ) R2
CF
+
³
2p (R1 * RF ) R2 * RF ) R2 * R1) Fcross
(eq. 46)
24.9 kW ) 7.87 kW
456 pF +
2p (24.9 kW * 1 kW ) 7.87 kW * 1 kW ) 7.87 kW * 24.9 kW) 50 kHz
where:
IPK
C
F
= Compensation pole capacitor
= Cross over frequency
F
cross
gm
= Transconductance of amplifier
= Top resistor divider
= Bottom resistor divider
= Feed through resistor
R
1
R
2
R
F
Figure 47. Input Charge Inrush Current
VIN
IICinrush_PK1 +
CINESR
Calculating Input Inrush Current
The input inrush current has two distinct stages: input
charging and output charging. The input charging of a buck
stage is usually controlled, but there are times when it is not
and is limited only by the input RC network, and the output
impedance of the upstream power stage. If the upstream
power stage is a perfect voltage source and switches on
instantaneously, then the input inrush current can be
depicted as shown in Figure 47 and calculated as:
(eq. 47)
12
1.2 kA +
0.01
VIN
5 CINESR CIN
IICinrush_RMS1 +
0.316
Ǹ
tDELAY_TOTAL
CINESR
(eq. 48)
12 V
5 0.01 W 22 mF
12.58 A +
0.316
Ǹ
0.01
1 ms
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NCP3170
3.3 V
where:
C
CIN
= Output capacitor
= Output capacitor ESR
= Total delay interval
= Input Voltage
IN
ESR
t
DELAY_TOTAL
V
IN
Output
Voltage
Once the t
has expired, the buck converter
DELAY_TOTAL
starts to switch and a second inrush current can be
calculated:
ǒ
Ǔ
COUT ) CLOAD VOUT
D
Output
Current
IOCinrush_RMS
+
) ICL D
(eq. 49)
Ǹ
tSS
3
where:
tss
C
C
= Total converter output capacitance
= Total load capacitance
= Duty ratio of the load
= Applied load at the output
= RMS inrush current during start-up
= Soft start interval
OUT
Figure 49. Resistive Load Current
LOAD
D
Alternatively, if the output load has an under voltage
lockout, turns on at a defined voltage level, and draws a
constant current, then the RMS connected load current is:
I
I
t
CL
OCinrush_RMS
SS
VOUT * VOUT_TO
V
OUT
= Output voltage
+ Ǹ
ICL1
IOUT
VOUT
From the above equation, it is clear that the inrush current
is dependent on the type of load that is connected to the
output. Two types of load are considered in Figure 48: a
resistive load and a stepped current load.
(eq. 51)
3.3 V * 2.5 V
492 mA +
Ǹ
1 A
3.3 V
where:
Inrush
Current
I
= Output current
= Output voltage
= Output voltage load turn on
OUT
Load
V
V
OUT
OUT_TO
OR
1.0 V
3.3 V
Output
Voltage
Figure 48. Load Connected to the Output Stage
If the load is resistive in nature, the output current will
increase with soft start linearly which can be quantified in
Equation 50.
Output
Current
VOUT
VOUT
1
ICLR_RMS
+
ICR_PK +
t
Ǹ
ROUT
ROUT
3
tss
(eq. 50)
3.3 V
3.3 V
1
Figure 50. Voltage Enable Load Current
191 mA +
300 mA +
Ǹ
10 W
10 W
3
If the inrush current is higher than the steady state input
current during max load, then an input fuse should be rated
where:
2
I
I
= RMS resistor current
= Peak resistor current
= Output resistance
= Output voltage
accordingly using I t methodology.
CLR_RMS
CR_PK
R
OUT
V
OUT
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NCP3170
THERMAL MANAGEMENT AND LAYOUT
Consideration
In the NCP3170 buck regulator high pulsing current flows
through two loops as shown in the figure below.
VIN
VIN
L1 4.7 mH
VSW
FB1
Input
Current
3.3 V
EN
PG
R1
R2
DRIVE
C2, C3
22 mF
C1
22 mF
C
bypass
0.1 mF
COMP
AGND
C
C
PGND
R
C
Figure 51. Buck Converter Current Paths
The first loop shown in blue activates when the high side
switch turns on. When the switch turns on, the edge of the
current waveform is provided by the bypass capacitor. The
remainder of the current is provided by the input capacitor.
Slower currents are provided by the upstream power supply
which fills up the input capacitor when the high side switch
is off. The current flows through the high side MOSFET and
to the output, charging the output capacitors and providing
current to the load. The current returns through a PCB
ground trace where the output capacitors are connected, the
regulator is grounded, and the input capacitors are grounded.
The second loop starts from the inductor to the output
capacitors and load, and returns through the low side
MOSFET. Current flows in the second loop when the low
side NMOSFET is on. The designer should note that there
are locations where the red line and the blue line overlap;
these areas are considered to have DC current. Areas
containing a single blue line indicate that AC currents flow
and transition very quickly. The key to power supply layout
is to focus on the connections where the AC current flows.
A good rule of thumb is that for every inch of PCB trace,
20 nH of inductance exists. When laying out a PCB,
minimizing the AC loop area reduces the noise of the circuit
and improves efficiency. A ground plane is strongly
recommended to connect the input capacitor, output
capacitor, and PGND pin of the NCP3170. Drawing the real
high power current flow lines on the recommended layout is
important so the designer can see where the currents are
flowing.
Figure 52. Recommended Signal Layout
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24
NCP3170
The NCP3170 is the major source of power dissipation in
5. Create copper planes as short as possible from the
VSW pin to the output inductor, from the output
inductor to the output capacitor, and from the load
to PGND.
the system for which the equations above detailed the loss
mechanisms. The control portion of the IC power
dissipation is determined by the formula below:
6. Create a copper plane on all of the unused PCB
area and connect it to stable DC nodes such as:
PC + IC VIN
(eq. 52)
where:
V , GND, or V
.
IN
OUT
I
= Control circuitry current draw
= Control power dissipation
= Input voltage
CC
7. Keep sensitive signal traces far away from the
VSW pins or shield them.
P
C
V
IN
Once the IC power dissipations are determined, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient temperature. The formula for calculating the
junction temperature with the package in free air is:
TJ + TA ) PD RqJA
(eq. 53)
where:
P
D
= Power dissipation of the IC
R
qJA
= Thermal resistance junction to ambient
of the regulator package
T
A
= Ambient temperature
T
= Junction temperature
J
The thermal performance of the NCP3170 is strongly
affected by the PCB layout. Extra care should be taken by
users during the design process to ensure that the IC will
operate under the recommended environmental conditions.
As with any power design, proper laboratory testing should
be performed to ensure the design will dissipate the required
power under worst case operating conditions. Variables
considered during testing should include maximum ambient
temperature, minimum airflow, maximum input voltage,
maximum loading, and component variations (i.e., worst
Figure 53. Recommend Thermal Layout
case MOSFET R ). Several layout tips are listed below
DS(on)
for the best electric and thermal performance. Figure 53
illustrates a PCB layout example of the NCP3170.
1. The VSW pin is connected to the internal PFET
and NFET drains, which are a low resistance
thermal path. Connect a large copper plane to the
VSW pin to help thermal dissipation. If the PG pin
is not used in the design, it can be connected to the
VSW plane, further reducing the thermal
impedance. The designer should ensure that the
VSW thermal plane is rounded at the corners to
reduce noise.
2. The user should not use thermal relief connections
to the VIN and the PGND pins. Construct a large
plane around the PGND and VIN pins to help
thermal dissipation.
3. The input capacitor should be connected to the
VIN and PGND pins as close as possible to the IC.
4. A ground plane on the bottom and top layers of the
PBC board is preferred. If a ground plane is not
used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin
noise coupling to the AGND pin.
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NCP3170
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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NCP3170/D
相关型号：
NCP3218GMNR2G
SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, QCC48, 6 X 6 MM, 0.40 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, QFN-48
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