NCP347 [ONSEMI]
Positive Overvoltage Protection Controller with Internal Low RON NMOS FET and Status FLAG; 正过压保护控制器，内部低辛烷值的NMOS FET和状态标志
| 型号： | NCP347 |
| 厂家： | 
ONSEMI |
| 描述： | Positive Overvoltage Protection Controller with Internal Low RON NMOS FET and Status FLAG |
| 文件： | 总13页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP347
Positive Overvoltage
Protection Controller with
Internal Low RON NMOS FET
and Status FLAG
http://onsemi.com
The NCP347 is able to disconnect the systems from its output pin
in case wrong input operating conditions are detected. The system is
positive overvoltage protected up to +28 V.
MARKING
DIAGRAM
Due to this device using internal NMOS, no external device is
necessary, reducing the system cost and the PCB area of the
application board.
BAx M
G
WDFN10
MT SUFFIX
CASE 516AA
The NCP347 is able to instantaneously disconnect the output from
the input, due to integrated Low R Power NMOS (65 mW), if the
ON
input voltage exceeds the overvoltage threshold (OVLO) or
undervoltage threshold (UVLO).
At powerup (EN pin = low level), the V turns on 50 ms after the
BAx = Specific Device Code
M
= Date Code
= Pb-Free Package
out
G
V
exceeds the undervoltage threshold.
The NCP347 provides a negative going flag (FLAG) output, which
in
PIN CONNECTIONS
alerts the system that a fault has occurred.
In addition, the device has ESD-protected input (15 kV Air) when
bypassed with a 1.0 mF or larger capacitor.
IN
1
2
10 EN
PAD1
GND
GND
9
NC
Features
•ꢀOvervoltage Protection up to 28 V
FLAG
IN
3
4
5
8
7
6
NC
•ꢀOn-Chip Low R
NMOS Transistor: 65 mW
DS(on)
OUT
OUT
PAD2
IN
•ꢀInternal Charge Pump
IN
•ꢀOvervoltage Lockout (OVLO)
•ꢀUndervoltage Lockout (UVLO)
•ꢀInternal 50 ms Startup Delay
•ꢀAlert FLAG Output
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 12 of this data sheet.
•ꢀShutdown EN Input
•ꢀCompliance to IEC61000-4-2 (Level 4)
ꢁ8.0 kV (Contact)
ꢁ15 kV (Air)
•ꢀESD Ratings: Machine Model = B
Human Body Model = 3
•ꢀ10 Lead WDFN 2.5x2 mm Package
•ꢀThis is a Pb-Free Device
Applications
•ꢀCell Phones
•ꢀCamera Phones
•ꢀDigital Still Cameras
•ꢀPersonal Digital Applications
•ꢀMP3 Players
©ꢀ Semiconductor Components Industries, LLC, 2007
September, 2007 - Rev. 0
1
Publication Order Number:
NCP347/D
NCP347
V
Bat
V
Bat
D3
7011X/SM
NCP1835B
ENABLE / Microprocessor
V2P8
6
3
2
EN
V2P8
VSNS
BAT
CFLG
FAULT
7
9
NCP347
V
Bat
Wall Adapter - AC/DC
10
1
4
5
1
6
7
8
IN
IN
IN
OUT
OUT
NC
V
CC
1 mF
100 nF
ISEL
GND
5
4.7 mF
9
3
8
4
10
NC
V
Bat
Lithium BATTERY
EN
ENABLE /
Microprocessor
270 K
FLAG
2
15 pF
1 M
0
0
Figure 1. Typical Application Circuit
INPUT
OUTPUT
60 mA
Output Impedance = 200 k
Core
Negative
Protection
FLAG
Gate
Driver
Charge
Pump
ESD
Protection
Delay
Generator
ESD
Protection
200 kHz
Power
ON
10 V
Oscillator
LDO
EN
EN
Block
V
REG
V
REG
UVLO
UVLO
OVLO
V
REF
OVLO
ESD
Protection
V
REF
V
REF
DISABLE
Figure 2. Functional Block Diagram
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2
NCP347
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
Description
1
4
5
IN
POWER
Input Voltage Pin.
This pin is connected to the power supply.
The device system core is supplied by this input.
A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND.
The three IN pins must be hardwired to common supply.
2
3
GND
POWER
OUTPUT
Ground
FLAG
Fault Indication Pin.
This pin allows an external system to detect a fault on IN pin.
The FLAG pin goes low when input voltage exceeds OVLO threshold or drop below UVLO threshold.
Since the FLAG pin is open drain functionality, an external pull up resistor to V must be added.
CC
6
7
OUT
OUTPUT
Output Voltage Pin.
This pin follows IN pin when “no fault” is detected.
The output is disconnected from the V power supply when the input voltage is under the UVLO
in
threshold or above OVLO threshold.
The two OUT pins must be hardwired to common supply.
8
9
NC
NC
EN
OPEN
OPEN
INPUT
No Connect
No Connect
Enable Pin.
10
The device enters in shutdown mode when this pin is tied to a high level. In this case the output is
disconnected from the input.
To allow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin.
This pin does not have an impact on the fault detection.
PAD1
PAD2
PAD1, under the device. See PCB recommendations page 10.
Can be shorted to GND.
The PAD2 is electrically connected to the internal NMOS drain and connected to Pins 4 and 5.
See PCB recommendations page 10.
MAXIMUM RATINGS
Rating
Symbol
Vmin
Value
-0.3
Unit
V
Minimum Voltage (IN to GND)
in
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
Vmin
Vmax
-0.3
V
30
V
in
Maximum Voltage (All others to GND)
Vmax
Imax
R
7.0
V
Maximum Current (UVLO<V <OVLO)
IN
2.0
A
Thermal Resistance, Junction-to-Air (Note 1)
Operating Ambient Temperature Range
Storage Temperature Range
280
°C/W
°C
°C
°C
q
JA
T
A
-40 to +85
-65 to +150
150
T
stg
Junction Operating Temperature
T
J
ESD Withstand Voltage (IEC 61000-4-2) (input only) when bypassed with 1.0 mF capacitor
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd
15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity
MSL
Level 1
-
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2
1. The R
is highly dependent on the PCB heat sink area (connected to pad 2). As example R
2
is 268 °C/W with 30 mm (copper 35 mm) and
q
JA
q
JA
189 °C/W with 400 mm .
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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3
NCP347
ELECTRICAL CHARACTERISTICS (Min/Max limits values (-40°C < T < +85°C) and V = +5.0 V. Typical values are T = +25°C,
A
in
A
unless otherwise noted.)
Characteristic
Symbol
Conditions
Min
1.2
2.8
Typ
-
Max
28
Unit
V
Input Voltage Range
V
in
-
Undervoltage Lockout Threshold (Note 4)
UVLO
V
in
falls down UVLO threshold
from 5 V to 2.7 V
2.95
3.1
V
Undervoltage Lockout Hysteresis
UVLO
V
rises up UVLO + UVLO
30
60
90
mV
V
hyst
in
hyst
Overvoltage Lockout Threshold (Note 4)
OVLO
V rises up OVLO threshold
in
NCP347MTAE
NCP347MTAF
NCP347MTAH
5.39
5.63
6.80
5.63
5.90
7.20
5.88
6.17
7.60
Overvoltage Lockout Hysteresis
OVLO
V
in
falls down OVLO + OVLO
hyst
mV
hyst
NCP347MTAE
NCP347MTAF
NCP347MTAH
30
30
50
60
60
70
90
90
100
V
in
versus V Resistance
out
R
DS(on)
V = 5.0 V, EN = GND,
in
Load connected to V
-
65
110
mW
out
Supply Quiescent Current
Idd
No load. EN = 5.0 V
No load. EN = Gnd
-
-
-
-
90
170
60
150
250
-
mA
mA
mA
mV
UVLO Supply Current
Idd
V
IN
= 2.7 V
uvlo
FLAG Output Low Voltage
Vol
1.2 V < V < UVLO
IN
Sink 50 mA on/FLAG pin
20
400
flag
V
> OVLO
Sink 1.0 mA on FLAG pin
-
-
400
mV
IN
FLAG Leakage Current
EN Voltage High
FLAG
FLAG level = 5.0 V
-
1.2
-
1.0
-
-
-
nA
V
leak
Vih
Vol
-
EN Voltage Low
-
-
0.4
-
V
EN Leakage Current
EN
EN = 5.0 V or GND
-
1.0
nA
leak
TIMINGS
Startup Delay
ton
tstart
toff
From V > UVLO to V = 0.3 V
30
30
-
50
50
70
70
ms
ms
ms
in
out
(See Figures 3 & 7)
FLAG Going Up Delay
From V = 0.3 V to FLAG =
out
1.2 V (See Figures 3 & 9)
Output Turn Off Time
From V > OVLO to V < =
out
1.5
5.0
in
0.3 V (See Figures 4 & 8)
increasing from 5.0 V to 8.0 V
at 3.0 V/ms
V
in
Rload connected on V
out
Alert Delay
tstop
tdis
From V > OVLO to FLAG < =
in
0.4 V (See Figures 4 & 10)
-
-
1.0
1.0
-
ms
ms
V
in
increasing from 5.0 V to 8.0 V
at 3.0 V/ms
Rload connected on V
out
Disable Time
From EN > = 1.2 V to
< 0.3 V
Rload = 5.0 W
5.0
V
out
(See Figures 5 & 12)
NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature.
4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor
representativefor availability.
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4
NCP347
TIMING DIAGRAMS
<OVLO
OVLO
UVLO
V
V
V
in
in
t
off
V
out
t
on
V
in
- (R
I)
DS(on)
V
- (R
I)
in
DS(on)
0.3 V
0.3 V
out
t
start
FLAG
t
stop
1.2 V
FLAG
0.4 V
Figure 3. Startup
Figure 4. Shutdown on Overvoltage Detection
1.2 V
EN
1.2 V
EN
V
in
OVLO
UVLO
t
dis
V
out
V
in
- (R
I)
DS(on)
FLAG
0.3 V
100 ms
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
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5
NCP347
TYPICAL OPERATING CHARACTERISTICS
Figure 7. Startup
Vin = Ch1, Vout = Ch3
Figure 8. Output Turn Off Time
Vin = Ch1, Vout = Ch2
Figure 9. FLAG Going Up Delay
Vout = Ch3, FLAG = Ch2
Figure 10. Alert Delay
Vout = Ch1, FLAG = Ch3
Figure 11. Initial Overvoltage Delay
Vin = Ch1, Vout = Ch2, FLAG = Ch3
Figure 12. Disable Time
EN = Ch1, Vout = Ch2, FLAG = Ch3
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6
NCP347
TYPICAL OPERATING CHARACTERISTICS
Figure 13. Inrush Current with Cout = 100 mF,
I charge = 1 A, Output Wall Adaptor Inductance 1 mH
Figure 14. Output Short Circuit
Figure 15. Output Short Circuit (Zoom Fig. 14)
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7
NCP347
CONDITIONS
> OVLO
0 < V < UVLO
V
IN
IN
OUT
IN
And/Or
/EN = 1
VOLTAGE DETECTION
Figure 16. Simplified Diagram
CONDITIONS
/EN = 0
&
IN
OUT
UVLO < V < OVLO
IN
VOLTAGE DETECTION
Figure 17. Simplified Diagram
Operation
overtaking undervoltage UVLO (Figure 3). The NCP347
provides aFLAG output, which alerts the system that a fault
has occurred. A 50 ms additional delay, regarding
available output (Figure 3) is added between output signal
rising up and to FLAG signal rising up. FLAG pin is an open
drain output.
The NCP347 provides overvoltage protection for
positive voltage, up to 28 V. A Low R NMOS FET
DS(on)
protects the systems (i.e.: charger) connected on the Vout
pin, against positive overvoltage. At powerup, with EN pin
= low, the output is rising up 50 ms after the input
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8
NCP347
V
out
= 0
FLAG = Low
Reset Timer
V
V
< UVLO or
> OVLO
in
V
out
= 0
in
FLAG = Low
Timer Count
OVLO > V > UVLO
in
T < 50 ms
Timer Check
T = 50 ms
Reset Timer
V
V
< UVLO or
> OVLO
in
Check V
in
in
FLAG = Low
Timer Count
UVLO < V < OVLO
in
EN = 1
EN = 0
Check EN
V
out
= Open
V = V
out in
V
V
< UVLO or
> OVLO
in
T < 50 ms
in
Timer Check
T = 50 ms
Check EN
UVLO < V < OVLO
in
UVLO < V < OVLO
in
EN = 1
EN = 0
V
out
= V
in
V
out
= Open
FLAG = High
Check V
FLAG = High
Check V
in
in
V
< UVLO or
> OVLO
in
V
in
Figure 18. State Machine
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9
NCP347
Undervoltage Lockout (UVLO)
As example: R
Typical R
= 8.0 W, V = 5.0 V
in
load
To ensure proper operation under any conditions, the
device has a built-in undervoltage lockout (UVLO) circuit.
During V positive going slope, the output remains
= 65 mW, I = 618 mA
out
DS(on)
V
out
= 8 x 0.618 = 4.95 V
in
2
2
NMOS losses = R
x Iout = 0.065 x 0.618 = 25 mW
DS(on)
disconnected from input until V voltage is below 2.92 V,
in
plus hysteresis, nominal. The FLAG output is tied to low as
long as V does not reach UVLO threshold. This circuit has
ESD Tests
in
The NCP347 input pin fully supports the IEC61000-4-2.
1.0 mF (minimum) must be connected between V and
GND, close to the device.
That means, in Air condition, V has a "15 kV ESD
a 60 mV hysteresis to provide noise immunity to transient
condition. Additional UVLO thresholds ranging from
UVLO can be manufactured. (See Selection Guide on page
12) Contact your ON Semiconductor representative for
availability.
in
in
protected input. In Contact condition, V has "8.0 kV
in
ESD protected input.
Please refer to Figure 19 to see the IEC 61000-4-2
electrostatic discharge waveform.
Overvoltage Lockout (OVLO)
To protect connected systems on V
pin from
out
overvoltage, the device has a built-in overvoltage lockout
(OVLO) circuit. During overvoltage condition, the output
remains disabled as long as the input voltage exceeds
5.675 V typical (NCP347MTAE). Additional OVLO
thresholds ranging from OVLO can be manufactured. (See
Selection Guide on page 12) Contact your ON
Semiconductor representative for availability.
FLAG output is tied to low until V is higher than OVLO.
in
This circuit has a 90 mV hysteresis to provide noise
immunity to transient conditions.
FLAG Output
The NCP347 provides a FLAG output, which alerts
external systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded or when the V level is below the UVLO
in
threshold. When V level recovers normal condition,
in
Figure 19. Electrostatic Discharge Waveform
FLAG is held high, keeping in mind that an additional
50ꢂms delay has been added between available output and
FLAG = high. The pin is an open drain output, thus a pull
up resistor (typically 1 MW, minimum 10 kW) must be
PCB Recommendations
The NCP347 integrates a 2 amperes rated NMOS FET,
and the PCB rules must be respected to properly evacuate
the heat out of the silicon. The PAD1 is internally isolated
from the active silicon and should preferably be connected
added to V . Minimum V supply must be 2.5 V. The
bat
bat
FLAG level will always reflects V status, even if the
in
device is turned off (EN = 1).
to ground. The PAD2 of the NCP347 package is connected
to the internal NMOS drain and can be used to increase the
heat transfer if necessary from an applications standpoint.
Depending upon the power dissipated in the application,
one can either use the PCB tracks connected to Pins 4 and
5 to evacuate heat, or make profit of the PAD2 area to add
extra copper surface to reduce the junction temperature
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin,
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal NMOS FET
(See Figure 20). Of course, in any case, this pad shall be not
connected to any other potential. Figure 20 shows copper
The NCP347 includes an internal Low R
NMOS
DS(on)
FET to protect the systems, connected on OUT pin, from
positive overvoltage. Regarding electrical characteristics,
area according to R
and allows the design of the heat
JA
q
transfer plane connected to PAD2.
the R
DS(on)
on V pin.
, during normal operation, will create low losses
out
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10
NCP347
310
290
270
250
230
1 oz C.F.
1 oz Sim
2 oz Sim
2 oz C.F.
1
2
210
190
175
150
0
25 50 75 100 125150175200225 250275 300 325350
2
COPPER HEAT SPREADING AREA (mm )
Figure 21. Demo Board Layout
Figure 20.
INPUT
OUTPUT
1
6
7
IN
IN
IN
OUT
OUT
4
5
C2
100 nF 50 V X7R 0805 not necessary
NCP347
C1
1 mF 25 V X5R 0603
Murata GRM188R61E105KA12D
8
9
NC
NC
FLAG Power
3
10
FLAG
EN
FLAG
GND
2
EN_Power
EN_State
EN
R1
1 M
J2
1
R3
100 k
3 2
1
2
R2
1
GND
F1 F2 F3 F4
100 k
2
FLAG_State
Figure 22. Demo Board Schematic
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11
NCP347
ORDERING INFORMATION
Device
†
Marking
BAL
Package
Shipping
NCP347MTAETBG
NCP347MTAFTBG
NCP347MTAHTBG
WDFN-10
(Pb-Free)
BAM
3000 / Tape & Reel
BAK
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP347 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows:
NCP347MTxxTxG
a b
c
Code
Contents
a
UVLO Typical Threshold
a: A = 2.95 V
b
c
OVLO Typical Threshold
b: E = 5.63 V
b: F = 5.90 V
b: H = 7.20 V
Tape & Reel Type
c: B = 3000
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12
NCP347
PACKAGE DIMENSIONS
WDFN10, 2.5x2, 0.5P
CASE 516AA-01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
D
A
B
E
PIN ONE
REFERENCE
MILLIMETERS
DIM
A
MIN
0.70
0.00
NOM
0.75
MAX
0.80
0.05
2X
0.10
C
A1
A3
b
---
0.20 REF
0.25
0.20
0.30
2X
0.10
C
D
2.50 BSC
1.08
D2
D3
e
0.97
0.57
1.18
0.78
0.68
A3
0.50 BSC
2.00 BSC
0.90
0.10
C
E
E2
G
0.80
1.00
A
0.375 BSC
0.35 BSC
---
G1
K
10X
0.08
C
A1
0.20
0.20
---
L
0.30
0.40
SEATING
PLANE
C
SOLDERING FOOTPRINT*
G1
0.10
0.05
C
A
B
D3
K
C
2.50
10X
0.58
D2
0.95
10X
L
1
5
E2
10X
0.30
1.13
0.50
PITCH
10
6
8X
e
b 10X
0.05
0.10
0.05
C
C
A
B
G
0.10
0.05
C
A
B
NOTE 3
C
0.73
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your loca
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NCP347/D
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