NCP370_11 [ONSEMI]
Positive and Negative Overvoltage Protection;
| 型号： | NCP370_11 |
| 厂家： | 
ONSEMI |
| 描述： | Positive and Negative Overvoltage Protection |
| 文件： | 总11页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP370
Positive and Negative
Overvoltage Protection
with Internal Low RON
N-MOSFETs and Reverse
Charge Control Pin
http://onsemi.com
MARKING
The NCP370 is an overvoltage, overcurrent and reverse control
device. Two main modes are available by setting logic pins. First mode
is Direct Mode from Wall−Adapter to the system. In this mode the
system is both positive and negative over−voltage protected up to
+28 V and down to −28 V. The wall adapter (or AC/DC charger) is
disconnected from the system if the input voltage exceeds the
overvoltage (OVLO) or undervoltage (UVLO) thresholds. At power
DIAGRAM
NCAI
370
1
12 PIN LLGA
MU SUFFIX
CASE 513AK
ALYWG
G
up, the V turns on 30 ms after the V exceeds the undervoltage
threshold.
out
in
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
The second mode (see Tables 1 & 2), called the Reverse Mode,
allows an external accessory to be powered by the system battery or
boost converter. Here the external accessory would be connected to
the device input (bottom connector of system) and the device battery
would be at the device output. In this case overcurrent protection is
activated to prevent accessory faults and battery discharge. Thanks to
the NCP370 using an internal NMOS, the system cost and the PCB
area of the application board are minimized.
(Note: Microdot may be in either location)
1
2
3
4
5
6
12
11
IN
IN
NC
OUT
FLAG
DIR
The NCP370 provides a negative going flag (FLAG) output which
alerts the system that a fault has occurred.
In addition, the device has ESD−protected input (15 kV Air) when
10
9
GND
RES
RES
RES
NCP370
bypassed with a 1 mF or larger capacitor.
8
REV
Ilim
7
Features
• Overvoltage Protection Up to 28 V
• Negative Voltage Protection Down to −28 V
• Reverse Charge Control: REV
• Direct Charge Control: DIR
• Overcurrent Protection
(Top View)
ORDERING INFORMATION
†
Device
Package
Shipping
NCP370MUAITXG LLGA12
2500 / Tape &
Reel
(Pb−Free)
• Thermal Shutdown
• On−chip Low R
NMOS Transistors: Typical 130 mW
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
DS(on)
• Overvoltage Lockout (OVLO)
• Undervoltage Lockout (UVLO)
• Soft−Start
Typical Applications
• Alert FLAG Output
• Cell Phones
• Compliance to IEC61000−4−2 (Level 4)
• Camera Phones
8 kV (Contact)
15 kV (Air)
• Digital Still Cameras
• Personal Digital Applications
• MP3 Players
• ESD Ratings: Machine Model = B
Human Body Model = 2
• 12 Lead TLLGA 3x3 mm Package
• This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
July, 2011 − Rev. 6
NCP370/D
NCP370
10k
Charger
NCP370
Wall Adapter
1
2
3
4
5
6
12
11
10
9
IN
NC
OUT
FLAG
1mF
IN
FLAG
DIR
GND
RES
RES
RES
System
DIR
8
REV
REV
7
Ilim
FLAG
DIR
LI+BATTERY
4.7mF
R
limit
REV
GND
Figure 1. Typical Application Circuit
FUNCTIONAL BLOCK DIAGRAM
INPUT
OUTPUT
Gate Driver and Reverse OCP
Logic
REV
I
lim
VREF
Charge
Pump
Control
Logic
and
EN
Block
UVLO
OVLO
Timer
FLAG
Thermal
Shutdown
GND
DIR
Figure 2. Functional Block Diagram
http://onsemi.com
2
NCP370
PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
1, 2
IN
POWER
Input voltage pins. These pins are connected to the power supply. A 1 mF low ESR ceramic capacitor, or
larger, must be connected between these pins and GND. The two IN pins must be hardwired to common
supply.
3
4
5
6
7
GND
RES
RES
RES
Ilim
POWER
INPUT
Main Ground
Reserved pin. This pin must be connected to GND.
Reserved pin. This pin must be connected to GND.
Reserved pin. This pin must be connected to GND.
INPUT
INPUT
OUTPUT
Current Limit Pin. This pin provides the reference, based on the internal band−gap voltage reference, to
limit the over current, across internal N−MOSFETs, from battery to external accessory. A 1% tolerance,
or better, resistor shall be used to get the highest accuracy of the overcurrent limit.
8
9
REV
DIR
INPUT
INPUT
Reverse Charge Control Pin. In combination with DIR, the internal N−MOSFETs are turned on if Battery
is applied on the OUT pin (See Tables 1 & 2). In reverse mode, the internal overcurrent protection is
activated. When reverse mode is disabled, the NCP370 current consumption, into OUT pin, is drastically
decreased to limit battery discharge.
Direct Mode Pin. In combination with REV, the internal N−MOSFETs are turned on if a wall adapter
AC−DC is applied on the IN pins (See Tables 1 & 2). The device enters in shutdown mode when this pin
is tied to a high level and the REV pin is tied to high. In this case the output is disconnected from input.
The state of this pin does not have an impact on the fault detect of the FLAG pin.
10
11
FLAG
OUT
OUTPUT
OUTPUT
Fault Indication Pin. This pin allows an external system to detect fault condition. The pin goes low when
input voltage exceeds OVLO threshold or drops below UVLO threshold, charge current from battery to
accessory exceeds current limit or internal temperature exceeds thermal shutdown limit. Since the pin is
open drain functionality, an external pull up resistor to VBat must be added (10 kW minimum value).
Output Voltage Pin. This pin follows IN pins when “no input fault” is detected. The output is disconnected
from the V power supply when the input voltage is under the UVLO threshold or above OVLO threshold
IN
or thermal shutdown limit is exceeded.In Reverse Mode, the device is supplied across OUT pin.
12
13
NC
NC
Not Connected
PAD1
POWER
The PAD1 is used to dissipate the internal MOSFET thermal energy and must be soldered to an isolated
PCB area. The area mustn’t be connected to any other potential than complete isolated one. See PCB
recommendations on page 9.
MAXIMUM RATINGS
Rating
Symbol
Vmin
Value
Unit
V
Minimum Voltage (IN to GND)
−30
in
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
Vmin
−0.3
V
Vmax
30
V
in
Maximum Voltage (OUT to GND)
Maximum Voltage (All others to GND)
Thermal Resistance, Junction−to−Air, (Note 1)
Operating Ambient Temperature Range
Storage Temperature Range
Vmax
10
7
V
out
Vmax
R
V
200
°C/W
°C
°C
°C
q
JA
T
A
−40 to +85
−65 to +150
150
T
STG
Junction Operating Temperature
T
J
ESD Withstand Voltage (IEC 61000−4−2)
Human Body Model (HBM), Model = 2, (Note 2)
Machine Model (MM) Model = B, (Note 3)
Vesd
15kV air, 8kV contact
kV
V
V
2000V
200V
Moisture Sensitivity
MSL
Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The R
is highly dependent on the PCB heat sink area (connected to PAD1). See PCB recommendation paragraph.
q
JA
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
http://onsemi.com
3
NCP370
ELECTRICAL CHARACTERISTICS (V = 5 V, Minimum/Maximum limits at −40°C < T < +85°C unless otherwise noted. Typical
in
A
values are at T = +25°C)
A
Characteristics
Input Voltage Range
Symbols
Conditions
Disable, Direct and Enhance Modes, V = 0 V
Min
−28
−24
2.5
Typ
Max
Unit
V
V
in
28
out
Input Voltage
Vin
Disable, Direct and Enhance Modes, V = 4.25V
V
min
out
Output Voltage Range
Undervoltage Lockout Threshold
V
out
Reverse Mode
5.5
2.8
V
UVLO
Vin falls below UVLO Threshold
(Disable, Direct and Enhance Modes)
2.6
2.7
60
V
Undervoltage Lockout Hysteresis
UVLO
V
in
rises above UVLO Threshold + UVLO
hyst
45
75
mV
hyst
Over voltage Lockout Threshold
NCP370MUAITXG
OVLO
V rises above OVLO threshold
in
(Disable and Direct Modes)
6.3
60
6.6
80
6.9
100
8.6
V
mV
V
Overvoltage Lockout Hysteresis
Over System Voltage Lockout
OVLO
V
falls below to OVLO − OVLO
hyst
hyst
in
OVLO
V
in
rises above OVLO Threshold Enhanced
7.9
8.27
00
00
Mode @ 25°C
Overvoltage Lockout Hysteresis
OVLO
V
falls below to OVLO − OVLO @ 25°C
00hyst
80
100
130
145
220
mV
00hyst
in
00
V
in
to V Resistance
R
DS(on)
V
= 5 V, Direct Mode, Load Connected to V
out
mW
out
in
V
= 5 V, Direct Mode,
in
Load Connected to V @ 25°C
130
130
200
220
out
V
out
to V Resistance
R
DS(on)
V = 5 V, Reverse Mode, Accessory
out
mW
in
Connected to V
in
V
out
= 5 V, Reverse Mode, Accessory
130
200
Connected to V @ 25°C
in
Input Standby Current
Input Supply Quiescent Current
Output Standby Current
Reverse Mode current
Minimum DC Current
Idd
No Load. Disable Mode, V connected
140
200
0.02
200
200
280
1.0
mA
mA
mA
mA
A
STD
in
Idd
No Load. Direct Mode
IN
STDOUT
Idd
Idd
Rin = 10 kW, V = 5.5 V, Disable Mode
out
No Accessory, V = 4.2 V, Reverse Mode
315
REV
out
I
Output Load, V = 5.5 V, Direct
1.3
1.3
CHG
in
I
Accessory, V = 5.5 V, Reverse Modes
out
REV
Overcurrent Threshold
Overcurrent Response
FLAG Output Low Voltage
I
V
out
= 4.2 V, Load on V , Reverse Mode, R
1.35
1.75
7.0
30
2.10
A
%
OCP
in
ILIM
= 0 W, 1 A/1 ms
I
Direct Accessory Short, Reverse Mode,
= 4.2 V, I = 1.6 A
acc
V
out
lim
Vol
1.2 V < V < UVLO
400
mV
flag
in
Sink 50 mA on FLAG Pin
V
> OVLO, Sink 1 mA on FLAG Pin
400
400
in
I
> I , Sink 1 mA on FLAG Pin
lim
reverse
FLAG Leakage Current
DIR Voltage High
FLAG
FLAG Level = 5.5 V
1.0
nA
V
leak
V
ihDIR
1.2
1.2
DIR Voltage Low
V
ilDIR
0.55
0.55
V
DIR Leakage Current
DIR
V
or V connected
200
1.0
nA
leak
in
out
V
and V disconnected
in
out
REV Voltage High
REV Voltage Low
REV Leakage Current
V
ihREV
V
V
V
ilREV
REV
V
or V connected
200
1.0
nA
leak
in
out
V
in
and V disconnected
out
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T
150
30
°C
°C
SD
T
SDHYST
http://onsemi.com
4
NCP370
Characteristics
Symbols
Conditions
Min
Typ
Max
Unit
TIMINGS
DIRECT MODE
Start Up Delay
t
From V > UVLO to V w 0.3 V
20
20
30
30
40
40
ms
ms
ms
on
in
out
FLAG Going Up Delay
Turn Off Delay
t
From V > 0.3 V to FLAG = 1.2 V
start
out
t
From V > OVLO to V v 0.3 V
1.5
5.0
off
in
out
V
Increasing from 5 V to 8 V at 3 V/ms
in
Alert Delay
t
From V > OVLO to FLAG v 0.4 V See Figure
1.5
2.5
ms
ms
stop
in
3 and 9 V Increasing from 5 V to 8 V at 3 V/ms
in
Disable Time
t
REV = 1.2 V, From DIR = 0.4 V to 1.2 V to V
dis
out
v 0.3 V
REVERSE MODE
Reverse Start Up Delay
ton
V
out
w 2.5 V, From REV = 1.2 to 0.55 to
0.6
1.2
1.8
ms
REV
V
in
w 0.3 V, Reverse Mode
Reverse FLAG Going Up Delay
Rearming Reverse Delay
Over Current Regulation Time
OCP Delay Time
tstart
From V w 0.3 V FLAG = 1.2 V, Reverse Mode
0.6
20
1.2
30
1.8
40
ms
ms
ms
ms
REV
in
t
t
t
V
> 2.5 V, R = 1 W, Reverse Mode
RRD
out in
V
out
> 2.6, V > 0.3 V, Reverse Mode
0.5
1.2
5
1.8
REG
OCP
in
From I
> I , 1 A/1 ms
lim
reverse
Reverse Disable Time
t
From REV = 0.55 V to 1.2 V, to V < 0.3 V.
200
ms
REVDIS
in
V
= 5 V
out
NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature.
TYPICAL OPERATING CHARACTERISTICS
Operation
Overvoltage Lockout (OVLO)
The NCP370 provides overvoltage protection for positive
and negative voltages, up to 28 V or down to −28 V on
IN pins. At powerup, with DIR pin = low, REV = high, the
output rises 30 ms after the input rises above the UVLO. The
NCP370 provides a FLAG output, which alerts the system
that a fault has occurred. The FLAG signal rises 30 ms after
the output signal rises.
To protect connected systems on Vout pin from
overvoltage, the device has a built−in overvoltage lock out
(OVLO) circuit. During overvoltage condition, the output is
disabled as long as the input voltage exceeds OVLO.
Additional OVLO thresholds can be manufactured
(Please contact your ON Semiconductor representative for
availability).
A Reverse Mode is available when an accessory is
connected on IN pins and the internal battery is applied on
the OUT pin, allowing the accessory to be powered. In this
mode, no supply must be connected on IN pins and REV pin
must be tied to low level. The NCP370 provides overcurrent
protection for the battery from current faults in the
accessory.
FLAG output will be low since V is higher than OVLO.
This circuit has a 80 mV hysteresis to provide noise
immunity to transient conditions.
in
Oversystem Voltage Lockout (OVLO00
)
A second overvoltage comparator is available for
supplying the sytem (output) by the Wall Adaptor (input) by
setting DIR = low and REV = low. The R
will be
DS(on)
higher during this mode allowing to handle few 10 mA
Undervoltage Lockout (UVLO)
.
To ensure proper turn−on operation from AC/DC (or Wall
adapter charging) under any conditions, the device has a
built−in undervoltage lock out (UVLO) circuit. During
This additional comparator allows to put higher input
voltage (OVLO = 8.27 V typical) on the NCP370 during test
production sequence (I.E: One Time Programming of the
cell phone, PDA). This parameter is 25°C guaranteed only.
positive going slope on V , the output remains disconnected
in
from input until V voltage is above UVLO. The FLAG
in
FLAG Output
output will be low as long as V has not reached UVLO
in
The NCP370 provides a FLAG output which alerts that a
fault has occurred. As soon as a fault state is detected by the
NCP370 (see Figure 3), the FLAG pin output goes low,
alerting the micro−controller to take appropriate action.
threshold. This circuit has a 60 mV hysteresis to provide
noise immunity to transient conditions.
In Reverse Mode (REV pin v 0.55 V, DIR w 1.2 V),
UVLO and OVLO comparators are inactivated.
http://onsemi.com
5
NCP370
The FLAG pin goes low as soon the input voltage exceeds
the OVLO threshold or falls below the UVLO threshold.
therefore a pull up resistor (typically 1 MW, minimum
10 kW) must be connected to Battery. The FLAG level will
When the V level recovers normal condition, FLAG goes
always reflect V status, even if the device is turned off (DIR
in
in
high after a time delay, t
(see Figure 3), following the V
= 1 and REV = 1).
start
out
response. The FLAG pin is an open drain output and
V
in
OVLO
UVLO
V
out
FLAG
DIR
t
dis
REV
> 1.2 V
t
on
t
t
off
t
on
t
start
start
t
stop
Figure 3. FLAG Pin in AC/DC Charging Mode
During over thermal condition (T° >T° ), output is
overvoltage condition, overcurrent condition or thermal
shutdown condition.
J
SD
disconnected from input, and FLAG pin goes low.
In Reverse Mode, FLAG pin remains available, allowing
the micro−controller to appropriately process the
http://onsemi.com
6
NCP370
V
in
ton
rev
V
out
Battery
Output
FLAG
DIR
REV
micro−controller
micro−controller
External Accessory ID = 1
Figure 4. FLAG status in Reverse Mode
Table 1. FLAG TABLE
FLAG
Status
DIR
REV
IN
1.5 < V < UVLO or
OUT
Pass Element (Dual NMOS FET)
0
0
Hiz
Low
Open
in
V
> OVLO
in
oo
0
0
0
1
UVLO < V < OVLO
= V −DROPOUT
High
Low
Close
Open
in
oo
in
1.5 < V < UVLO or
Hiz
in
V
in
> OVLO
0
1
1
1
0
1
UVLO < V < OVLO
= V −DROPOUT
High
High
Low
Close
Close
Open
in
in
= V −DROPOUT
V
out
> 2.5 V
Hiz
out
1.5 < V < UVLO or
in
V
in
> OVLO
1
1
UVLO < V < OVLO
Hiz
High
Open
in
DIR Input
Table 2. TABLE SELECTION OF CHARGE MODES
To enable Direct Charge operation (Direct Mode), the
DIR pin shall be forced to low and REV to high. A high level
on the DIR pin disconnects OUT pin from IN pin. DIR does
not over−ride an OVLO or UVLO fault (FLAG status is still
available).
DIR
0
REV
Mode
0
1
0
1
Enhance Mode
Direct Mode
Reverse Mode
Disable Mode
0
1
1
http://onsemi.com
7
NCP370
Negative Voltage and Reverse Current.
The device protects the downstream side from negative
voltage occurring on the IN pin, down to −28 V. When a
negative voltage occurs, the output is disconnected from the
IN pins.
By adding external resistors in series from I to GND,
the OCP value is lowered. The typical overcurrent threshold
can be calculated with the following formula;
lim
R
(kW) = (60 / I ) − 36
OCP
ilim
Reverse Mode
In Reverse Mode, an external accessory plugged into the
bottom connector can be powered by the internal battery of
the system.
To access to the reverse mode, DIR pin must be tied high
(> 1.2) and REV must be tied high to low (< 0.55 V).
In this case, the core of the NCP370 will be supplied by
the battery, with a 2.5 V minimum voltage and 5.5 V
maximum voltage.
In this reverse state, both OCP and thermal modes are
available.
Overcurrent Protection (OCP)
This device integrates the reverse over current protection
function, from battery to external accessory.
That means the current across the internal NMOS is
Figure 5. Reverse Mode Overcurrent Protection vs.
ILIM Resistance, RLIMIT
limited when the value, set by the external R
resistor,
limit
During an overcurrent event, the N−MOSFETs turn off
exceeds I
.
OCP
and FLAG output goes low, allowing the micro−controller
to process the fault event and then disable reverse charge
path.
An internal resistor is placed in series with the I pin
lim
allowing a maximum OCP value when I pin is directly
lim
connected to GND.
http://onsemi.com
8
NCP370
At power up (accessory is plugged on input pins), the
current is limited up to I for 1.2 ms (typical), to allow
After 1 ms following the plug in of the accessory, the OCP
mode is engaged. See Figure 6.
lim
capacitor charge and limit inrush current. If the I
lim
threshold is exceeded over 1.2 ms, the device enters
OCP burst mode until the overcurrent event disappears.
V
out
V
in
ton
REV
tstart
REV
FLAG
t
REG
I
I
lim
REV
REV
ID
t
RRD
Accessory ID
Detection
Drive Current in Accessory
DIR
Figure 6. Overcurrent Protection Sequence
Thermal Shutdown Protection
PCB Recommendations
In case of internal overheating, the integrated thermal
shutdown protection turns off the internal MOSFETs in
order to instantaneously decrease the device temperature.
The thermal threshold has been set at 150°C FLAG then
goes low to inform the MCU.
As the thermal hysteresis is 30°C, the MOSFETs will turn
on as soon the device temperature falls below 120°C.
If the fault event is still present, the temperature increase
engages the thermal shutdown again until the fault event
disappears.
Since the NCP370 integrates the 1. 3A N−MOSFETs,
PCB rules must be respected to properly evacuate the heat
out of the silicon.
From an applications standpoint, PAD1 of the NCP370
package should be connected to an isolated PCB area to
increase the heat transfer if necessary.
In any case, PAD1 should be not connected to any other
potential or GND other than the isolated extra copper
surface.
To assist in the design of the transfer plane connected to
PAD1, Figure 7 shows the copper area required with respect
to R
.
qJA
http://onsemi.com
9
NCP370
250
200
150
100
50
2.5
2
Power Curve with
PCB cu thk 2 oz
1.5
1
Power Curve with
PCB cu thk 1 oz
qJA Curve with
PCB cu thk 2 oz
qJA Curve with
PCB cu thk 1 oz
0.5
0
0
0
100
200
300
400
500
600
700
2
COPPER HEAT SPREAD AREA (mm )
Figure 7. Copper heat Spread Area
ESD Tests
RDS(on) and Dropout
The NCP370 conforms to the IEC61000−4−2, level 4 on
the Input pin. A 1 mF (I.E Murata GRM188R61E105KA12D)
must be placed close to the IN pins. If the IEC61000−4−2 is
not a requirement, a 100 nF/25 V must be placed between IN
and GND.
The above configuration supports 15 kV (Air) and 8 kV
(Contact) at the input per IEC61000−4−2 (level 4).
Please refer to Figure 8 for the IEC61000−4−2
electrostatic discharge waveform.
The NCP370 includes two internal low R
N−MOSFETs to protect the system, connected on OUT pin,
from overvoltage, negative voltage and reverse current
DS(on)
protection. During normal operation, the
characteristics of the N−MOSFETs give rise to low losses on
pin.
R
DS(on)
V
out
As example: R
= 800 mA.
= 8 W, Vin= 5 V. R
= 155 mW. I
out
load
DS(on)
V
= 4.905 V
out
2
2
NMOS Losses = R
x I
= 0.155 x 0.8 = 0.0992 W
DS(on)
out
Figure 8. Ipeak = f(t)/IEC61000−4−2
http://onsemi.com
10
NCP370
PACKAGE DIMENSIONS
LLGA12 3x3, 0.5P
CASE 513AK−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
B
E
A
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
0.60
0.05
0.30
2X
A
A1
b
0.50
0.00
0.20
0.15
C
2X
D
3.00 BSC
D2
E
E2
e
2.60
3.00 BSC
1.90
0.50 BSC
2.80
0.15
C
TOP VIEW
2.10
K
L
0.20
0.25
−−−
0.35
0.10
0.08
C
C
A
12X
SOLDERING FOOTPRINT*
A1
SEATING
PLANE
SIDE VIEW
D2
C
3.30
12X
0.50
1
e
0.50
PITCH
6
1
0.43
2.75
12X K
E2
11X
0.30
2.05
12
7
12X
0.10
0.05
C
C
A
B
DIMENSIONS: MILLIMETERS
12X L
b
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP370/D
相关型号：
NCP372
Positive and Negative Overvoltage Protection Controller with Internal Low Ron NMOS FETs and Status FLAG
ONSEMI
NCP372MUAITXG
Positive and Negative Overvoltage Protection Controller with Internal Low Ron NMOS FETs and Status FLAG
ONSEMI
©2020 ICPDF网 联系我们和版权申明