NCP45495XMNTWG [ONSEMI]
4-Channel Voltage Bus and 4-Channel High-Side Current Shunt Monitor, 26 V;
| 型号： | NCP45495XMNTWG |
| 厂家： | 
ONSEMI |
| 描述： | 4-Channel Voltage Bus and 4-Channel High-Side Current Shunt Monitor, 26 V |
| 文件： | 总19页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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26V, 4-Channel Voltage Bus
and 4-Channel High-Side
Current Shunt Monitor
1
QFN32 4x4
CASE 485CD
NCP45495
MARKING DIAGRAM
The NCP45495 is a high−performance monolithic IC which can be
used to monitor bus voltage and current on four high−voltage power
supplies simultaneously. The HV bus voltages and currents are
translated to a low−voltage power domain and multiplexed onto a
single differential output for measurement externally by common
ADCs. The NCP45495 offers programmable voltage and current gain
settings and requires a minimal amount of external passives for a small
cost saving solution. The device is also configurable to operate either
standalone or as a pair, permitting up to eight separate HV power
supplies to be monitored and measured.
45495
ALYW
G
45495 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
PIN CONFIGURATION
• Translates and Scales Shunt and Bus Voltages up to 26 V
• Single Device Monitors Four Supplies
• May Be Paired for Monitoring Up To Eight Supplies
• Very Low Powerdown Current
• All Channels Individually Gain Programmable via I C Interface
• Fast Settling Time
• Real−Time Bus Voltages Valid Signal
• Adjustable Output Common−Mode Voltage
• RoHS/REACH Compliant Device
2
24 SDA
IN_N1
IN_P1
1
2
3
4
5
6
7
8
23 SCL
BV_IN1
IN_N2
22 ADRS[1]
21 ADRS[0]
33:GND
IN_P2
20 DIFF_OUT_P
19 DIFF_OUT_N
18 BV_REF
BV_IN2
IMON_IN1
IMON_IN2
17 BG_REF_OUT
Applications
• Computers / Notebooks / Graphics Cards
• Power Management / Power Control Loops
• Battery Chargers
(Top View)
ORDERING INFORMATION
†
Device
Package
Shipping
4000 /
Tape & Reel
NCP45495XMNTWG
QFN32
(Green)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
March, 2023 − Rev. 4
NCP45495/D
NCP45495
V
BUS1
IMON_IN1
IMON_IN2
Channel 1 (of up to 4)
BV_IN1
R
BV1
DIFF_OUT_P
DIFF_OUT_N
Diff
MUX
Amp
R
R
BV2
SC1
IN_P1
IN_N1
CM_VREF
Shunt
EN_B
MUX_SEL
SKIP
SDA
Logic
Block
31R
1R
SCL
R
to load 1
SC2
SYNC
CH 1−4
EN
BV_OK
Vref
Generator
R
Vbus Comparators
NCP45495
CM2
CM_VREF
POR
R
CM2
BV_REF
BG_REF_OUT
RGND
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin
Name
IN_Nx
I/O
AI
Function
1,4,13,16
Sense Resistor Sense −, High Voltage
Sense Resistor Sense +, High Voltage
Bus Voltage Input for Voltage monitoring
2,5,12,15
IN_Px
AI
3,6,11,14
7,8
9
BV_INx
IMON_INx
RGND
AI
AI
Current Monitor Channels (High impedance input)
Reference Ground for multiplexer and differential amplifier
Buffered Bandgap Voltage Output
GND
AO
AI
17
BG_REF_OUT
BV_REF
DIFF_OUT_N
DIFF_OUT_P
ADRS[1:0]
SCL
18
BV_OK comparator threshold reference
Differential Output, Negative
19
AO
AO
DI
20
Differential Output, Positive
2
21,22
23
I C Address set bits
2
DI
I C Clock
2
24
SDA
DI/DO
DI
I C Data Signal
25
SKIP
Skip Function control (see description) Mask for BV_OK. High level is V and low level is GND
CC
27
VCC
PWR
DI
Device Power
28
EN_B
Device Enable. When high, places device in low−power state.
Multiplexer Select Input
29
MUX_SEL
BV_OK
SYNC
DI
30
DO
DO
GND
Bus OK output (open−drain; high impedance = BUS OK)
Sync pin outputs a pulse at the beginning of every MUX_SEL sequence
Device Ground
31
33
GND
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2
NCP45495
Table 2. MAXIMUM RATINGS
Rating
Pins
Condition
GND = 0 V
GND = 0 V
GND = 0 V
Symbol
Value
Unit
V
Supply Voltage Range
Bus Input Voltage Range
Digital Input Voltage Range
VCC
V
CC
−0.3 to 5.5
−0.3 to 30
−0.3 to 5.5
BV_INx, IN_Px, IN_Nx
V
BV_IN
V
MUX_SEL, EN_B, SKIP, SCL,
SDA, ADRS[x]
V
LV
V
Low Voltage I/O Range
DIFF_OUT_P, DIFF_OUT_N,
BV_OK, BG_REF_OUT
GND = 0 V
V
LV
−0.3 to 5.5
V
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
R
R
40
5
°C/W
°C/W
θJA
θJC
(V Paddle)
IN
Operating Temperature Range
Functional Temperature Range
Maximum Junction Temperature
Storage Temperature Range
T
−40 to 105
−40 to 125
125
°C
°C
°C
°C
°C
A1
T
A2
T
J
T
STG
−40 to 150
260
Lead Temperature, Soldering (10 sec.)
T
SLD
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. ESD RATINGS
Rating
ESD Capability, Human Body Model (Note 1)
ESD Capability, Charged Device Model (Note 1)
Symbol
Value
>2.0
Unit
kV
ESD
ESD
HBM
CDM
>0.5
kV
1. Tested by the following methods @ T = 25°C
A
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model per JESD22−C101
Table 4. RECOMMENDED OPERATING RANGES
Rating
Symbol
Min
2.8
Max
3.8
26
Unit
V
Supply Voltage Range
V
CC
Bus Input Pin Voltage Range
Digital Input High Voltage Range (Note 2)
Digital Input Low Voltage Range (Note 2)
SKIP Input High Voltage Range
SKIP Input Low Voltage Range
Ambient Temperature
V
V
5
V
IN_PX, IN_Nx
V
0.945
V
IH
V
0.405
3.8
V
IL
SKIP
SKIP
2.8
V
VIH
VIL
0.405
85
V
T
−40
−40
°C
°C
A
Junction Temperature
T
125
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. V and V ranges apply to the EN_B, SCLK, SDA, ADRS[x], and MUX_SEL pins
IL
IH
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NCP45495
Table 5. ELECTRICAL CHARACTERISTICS V
= 15 V, V
= 0 V, Vcc = 3.3 V, unless indicated otherwise. Min and Max
IN_PX
EN_B
values are valid for temperature range −40°C < T < +105°C unless noted otherwise and are guaranteed by test, design, characterization,
J
or statistical correlation. Typical values are referenced to T = 25°C
J
Parameter
AC CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Multiplexer Settling Time (to 9.375 mV)
Multiplexer Settling Time (to 3 mV)
Symbol
Min
Typ
Max
Unit
T
T
100
300
ns
ns
ms
ms
ms
pF
STAB1
STAB2
MUX_SEL Period (normal operation – assuming no timeout set)
MUX_SEL Timeout (from falling edge of MUX_SEL)
Power−up Time (STANDBY or Limited Function to Full Function) (Note 3)
Differential Amplifier Capacitive Load Capability (Note 4)
DC CHARACTERISTICS
T
MSP
0.185
35
39
43
40
82
T
PWR_UP
C
DIFF
Input Impedance (EN_B pin tri−stated)
IMONx Channel Input Leakage Current
BG_REF_OUT Voltage
R
100k
W
nA
V
FLOAT
100
1.326
100
V
BG
1.274
1.3
BG_REF_OUT maximum loading
I
mA
W
BG
BV_OK Logic Low Impedance (Note 5)
BV_REF Voltage Range
R
300
BV_OK
BV_REF
100
7.5
800
mV
%
BV_OK Comparator Hysteresis
10
12.5
BV_OK Comparator VBUS divide ratio
VCC range for BV_OK low impedance
VCC Threshold Reference for BV_OK Input (POR) (Note 6)
POR Hysteresis
1/32
V/V
V
V
1
3.8
2.8
LI
V
2.6
V
BV_TH
150
mV
mV
mV/°C
dB
V/V
%
Shunt Monitor Offset Voltage, room temp (Note 7)
Shunt Monitor Offset Voltage Drift (Note 7)
V
−150
150
2
SM_OV
SM_VD
Shunt Monitor CMRR (V
in valid range, see above)
SM_CMRR
80
2
IN_Px
Shunt Current Gain Range (See Table 6)
24
0.6
2
Shunt Current Gain Tolerance (Note 11)
Differential Amp Input Offset Voltage, 25°C (Note 8)
Differential Amp Input Offset Voltage, −40°C to 105°C (Note 8)
V
−2
−6
mV
mV
dB
mV
V/V
D_OVRT
V
6
D_OVT
Differential Amp PSRR (V = 2.8 V to 3.8 V)
DA_PSRR
54
CC
Differential Amp Common−Mode Voltage
Differential Amp Closed Loop Gain (Note 11)
Differential Full Scale Output
V
CMR
575
0.994
875
1.006
800
G
1
DA
V
FSO
mV
pp
I_VCC (Fully Functional, EN_B = 0, MUX_SEL clocked at 2 MHz, VCC
must be 2.8 V − 3.8 V)
I
2.0
mA
VCC_F
I_VCC (Limited Function, EN_B=Tristate, VCC must be 2.8 V = 3.8 V)
I
400
mA
VCC_L
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. T
begins when EN_B goes low. After the power up time, MUX_SEL may begin clocking out data. This time also applies following
PWR_UP
any register programming.
4. Differential Output C
(i.e.: DIFF_OUT_x to GND) appears as a series RC with lumped equivalent R (0.86−8.6 W)
LOAD
5. BV_OK should be connected to a pull up resistor of value 10 KW or greater.
6. Vcc detection for BV_OK must trip in this range. Device can be either Full Function or Limited Function mode in this range
7. Shunt Monitor Offset Voltage and Offset Voltage Drift are referred to the IN_Px and IN_Nx pins.
8. Differential Amplifier Input Offset Voltage is referred to the multiplexer input pins
9. V = V ; Total V standby current is I for every IN_Px channel that is not floating
EN
CC
CC
BUS
VCC_S
10.Specifications for V
current draw are only applicable when V = 2.8 V to 3.8 V.
CC
11. 3−sigma variation specification
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NCP45495
Table 5. ELECTRICAL CHARACTERISTICS V
= 15 V, V
= 0 V, Vcc = 3.3 V, unless indicated otherwise. Min and Max
IN_PX
EN_B
values are valid for temperature range −40°C < T < +105°C unless noted otherwise and are guaranteed by test, design, characterization,
J
or statistical correlation. Typical values are referenced to T = 25°C
J
Parameter
Symbol
Min
Typ
Max
Unit
DC CHARACTERISTICS
I_VCC (STANDBY) (Note 9)
I
200
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
V/V
%
VCC_S
I_BV_IN (BV_IN current in STANDBY mode)
I_BV_IN (BV_IN current in LIMITED mode)
I_BV_IN (BV_IN current in Full Function)
I
BV_IN_S
I
120
600
2
BV_IN_L
BV_IN_F
I
I_BV_IN (BV_IN current when VCC = FLOATING)
I_IN_N (IN_N current in STANDBY/LIMITED mode) (Note 10)
I_IN_P (IN_P current in STANDBY/LIMITED mode) (Note 10)
I_IN_N (IN_N current in Full Function mode) (Note 10)
I_IN_P (IN_P current in Full Function mode mode) (Note 10)
I
BV_IN
I
1
IN_N
I
1
IN_P
60
60
1/4
0.6
V
BUS
V
BUS
Gain Range
1/64
Gain Tolerance
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. T
begins when EN_B goes low. After the power up time, MUX_SEL may begin clocking out data. This time also applies following
PWR_UP
any register programming.
4. Differential Output C
(i.e.: DIFF_OUT_x to GND) appears as a series RC with lumped equivalent R (0.86−8.6 W)
LOAD
5. BV_OK should be connected to a pull up resistor of value 10 KW or greater.
6. Vcc detection for BV_OK must trip in this range. Device can be either Full Function or Limited Function mode in this range
7. Shunt Monitor Offset Voltage and Offset Voltage Drift are referred to the IN_Px and IN_Nx pins.
8. Differential Amplifier Input Offset Voltage is referred to the multiplexer input pins
9. V = V ; Total V standby current is I for every IN_Px channel that is not floating
EN
CC
CC
BUS
VCC_S
10.Specifications for V
current draw are only applicable when V = 2.8 V to 3.8 V.
CC
11. 3−sigma variation specification
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NCP45495
DETAILED DESCRIPTION
Differential Output Amplifier: An integrated differential
The table below shows the available shunt gain settings.
output amplifier provides a scaled representation of multiple
bus voltages and currents to an external ADC on the
DIFF_OUT_P and DIFF_OUT_N pins. These voltages and
currents are presented sequentially (under control of the
Sequence Logic block) via the Multiplexer. The gain of the
differential amplifier is 1 V/V. The common−mode voltage
of the differential output amplifier is established by an
internal reference divider. The common mode voltage is
programmable from 575 mV to 875 mV in 25 mV
increments to offer flexibility for the ADC reading the
differential outputs. The contents of the DIFF_AMP_CM
register set the differential amplifier common mode voltage.
The offset of the differential amplifier is also programmable
by setting the DIFF_AMP_OFFSET register. The
differential offset can be set to 0 mV or from −325 to
−375 mV in 25 mV increments. See the DIFF_AMP register
Table 6. SHUNT CURRENT PROGRAMMABLE GAIN
SETTINGS
SHUNT_GAIN
(Bits 5−1)
Register Contents
(includes bit 0)
Shunt Current
Channel Gains
0b’11111
0b’11110
0b’11101
0b’11100
0b’11011
0b’11010
0b’11001
0b’11000
0b’10111
0b’10110
0b’10101
0b’10100
0b’10011
0b’10010
0b’10001
0b’10000
0b’01111
0b’01110
0b’01101
0b’01100
0b’01011
0b’01010
0b’01001
0b’01000
0b’00111
0b’00110
0b’00101
0b’00100
0b’00011
0b’00010
0b’00001
0b’00000
0x3E
0x3C
0x3A
0x38
0x36
0x34
0x32
0x30
0x2E
0x2C
0x2A
0x28
0x26
0x24
0x22
0x20
0x1E
0x1C
0x1A
0x18
0x16
0x14
0x12
0x10
0x0E
0x0C
0x0A
0x08
0x06
0x04
0x02
0x00
24.000
22.151
20.445
18.870
17.417
16.075
14.837
13.694
12.639
11.665
10.767
9.937
9.172
8.465
7.813
7.212
6.656
6.143
5.670
5.233
4.830
4.458
4.115
2
description in the I C interface definition section for more
details.
Shunt Current Monitor (one of four identical instances):
The differential voltage across an external sense resistor
(R ) is converted to a current by a transconductor stage
SENSE
implemented by an op−amp and an internal shunt resistor
. The current is forced through a programmable
R
SC1
internal resistor R
to create the internal shunt voltage.
SC2
The resulting voltage is fed into the multiplexer for readout.
The conversion gain can be programmed to gains from 2x to
24x. The SHUNT_GAINx registers are used to set the shunt
current gains for each channel. The voltage represented on
the differential output for the shunt current is the voltage
drop across the external sense resistor multiplied by the
shunt gain.
Diff Output = Iload * Rsense * shunt gain
3.798
3.505
3.235
2.986
2.756
2.544
2.348
2.167
2.000
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NCP45495
High Impedance Voltage Monitor (one of two identical
instances):
The voltage on the IMON_INx pin is fed directly to the
multiplexer for readout. The differential output voltage
represents the voltage on the IMON_INx pin.
Bus Voltage Monitor (one of four identical instances): An
internal voltage divider (R and R ) is used to scale the
BV1
BV2
voltage on the BV_INx pin to an appropriate full−scale
range for the differential output amplifier. The voltage
divider is programmable from 1/4(V/V) to 1/64(V/V) as
shown in the table below. BUS_GAINx registers are used to
set the voltage gains for each channel. The differential
output voltage representing the bus voltage is the bus voltage
divided by the VBUS attenuation.
Multiplexer Select: The multiplexer selection is controlled
by a single digital input (MUX_SEL pin). The device will
monitor this pin and cycle through the different measured
parameters in a fixed sequence. The sequence will repeat the
cycle until either a timeout condition is detected or the
device is disabled. If the timeout is disabled, then
MUX_SEL must be clocked through the whole sequence
before the cycle will repeat.
VBUS
AV
Diff Output +
Table 7. VBUS PROGRAMMABLE ATTENUATION
SETTINGS
MUX_SEL Timeout
BUS_GAIN
(Bits 5−1)
Register Contents
(includes bit 0)
VBUS Attenuation
The MUX_SEL timeout can be enabled or disabled over
Setting (A )
V
2
the I C interface. If enabled, after 45 ms of idle time on the
0b’00000
0b’00001
0b’00010
0b’00011
0b’00100
0b’00101
0b’00110
0b’00111
0b’01000
0b’01001
0b’01010
0b’01011
0b’01100
0b’01101
0b’01110
0b’01111
0b’10000
0b’10001
0b’10010
0b’10011
0b’10100
0b’10101
0b’10110
0b’10111
0b’11000
0b’11001
0b’11010
0b’11011
0b’11100
0b’11101
0b’11110
0b’11111
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
64.00
58.524
53.517
48.939
44.752
40.923
37.422
34.220
31.292
28.615
26.167
23.928
21.881
20.009
18.297
16.732
15.300
13.991
12.794
11.700
10.699
9.783
MUX_SEL pin the MUX_SEL sequence is reset back to the
beginning. All new register settings will become effective at
the timeout. Writing 0b1 to the TIMEOUT register will
disable the timeout. If the timeout is disabled, MUX_SEL
must be clocked to complete the full sequence before the
cycle will repeat.
Paired Devices: In paired operation, programmed bits in the
MUX_SEL_SKIP register designate which device is
“Device A” and “Device B” of a pair. Device A always goes
first in the sequence. When paired, the differential output
amplifiers of the two devices are expected to be
“wire−or’ed” together, and the table logic insures that only
one device will actively drive the output pins DIFF_OUT_P
and DIFF_OUT_N at any given time. See description in the
Auxiliary Functions section for details. When in paired
mode, the configuration register settings for registers
TIMEOUT, DIFF_AMP_OFFSET and DIFF_AMP_CM
must match between the 2 devices.
Power−up Sequence
Correct functionality of the power monitor is not
dependent on a specific power up sequence. All used bus
voltages and VCC must be powered before the output will
be correct. The ACTIVE_CHAN register must be set over
2
the I C interface after VCC is up to set the active channel
count. MUX_SEL may begin clocking out data 40us after
EN_B goes low. Before the part is configured, BV_OK will
function with all VBUS channels considered active.
Because all VBUS channels are active by default until
otherwise configured, if BV_OK functionality is used
before the part is configured, un−used VBUS inputs should
be tied to used VBUS inputs.
8.946
8.181
7.481
6.841
6.256
5.720
Calibration Cycle
5.231
Setting bit 7 in the ACTIVE_CHAN register adds an
additional cycle at the end of the standard MUX_SEL
cycles. During this cycle, the device ground (connected to
the RGND pin) is muxed through the signal chain. The
4.783
4.374
4.000
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NCP45495
resulting differential output represents the differential
configuration settings. Data packets for the power monitor
I C interface are sent with a 7 bit slave address, an 8 bit
2
amplifier offset error. The RGND pin should be treated as a
reference ground. The controller can use the RGND readout
to cancel out remaining offset error if desired. The
calibration cycle is disabled by default. If in paired mode
with 2 devices, then a calibration cycle will be added to the
end of the sequence from each individual contributing
device respectively. See Figure 2 and Figure 10 for CAL
cycle example.
register address, a read / write bit, and 8 bits of data.
Acknowledge bits are used after the addresses and data as a
handshake verification. The address for the device can be set
to one of 4 available addresses using the ADRS[1:0] pins. If
in paired mode, Device A’s address must be different than
Device B’s address. Continuous read and continuous write
2
I C modes, or combined formats are not supported by the
NCP45495. Bits are always sent out MSB first.
Polarity Mode
The ADRS[1:0] address mapping is as follows:
Setting bit 7 in the ALTERNATING_MODE register puts
the differential output in alternating polarity mode. In
alternating polarity mode, the voltage and current readouts
will be repeated with alternating differential amplifier input
polarity. This allows the user to compute and cancel out any
differential amplifier offset. An example of an output using
polarity mode is shown in the application section. Polarity
mode is disabled by default. If in paired mode, the
alternating polarity cycles will be added for each individual
device output.
ADRS[1]
ADRS[0]
Set Device Address
0
0
1
1
0
1
0
1
0x34
0x35
0x36
0x37
It is recommended that all necessary registers are
programmed while EN_B is held high. On the falling edge
of EN_B, the programmed registers will be committed. On
the first rising edge of the first MUX_SEL, the register
setting will be effective. If register settings are programmed
after EN_B has been asserted low, then the new settings will
be effective at the beginning of the next MUX_SEL cycle.
If register settings are programed while MUX_SEL is
running, then the new settings will be effective on the rising
edge of the first MUX_SEL of the next cycle.
Ground Reference Bit set
for calibration cycle to be added
VB1 SC1 VB2 SC2 VB3 SC3 VB4 SC4 CAL VB1 SC1 VB2 SC2 VB3 SC3 VB4 SC4 CAL
Standard Polarity
Reverse Polarity(Differential Terminals Swapped)
Set POL bit for alternating polarity cycles
to be added to differential output
Figure 2. Sequence Showing Differential Output
Format Options
2
The I C bus can also be locked by setting the appropriate
2
bits in the LOCK register. Setting bit 1 will lock the I C
SYNC Signal
interface to any write commands. In this configuration, the
device will respond to read commands, but not to write
The SYNC output pin pulses high for the first MUX_SEL
period in a MUX_SEL sequence beginning with the second
MUX_SEL sequence and continuing for all subsequent
cycles. This is useful for the user to ensure synchronization,
to guarantee the right channels are sampled at the right time.
The SYNC pin is particularly useful for applications where
MUX_SEL is clocked continuously. When devices are used
in paired mode, the SYNC signal for each device will be
relative to its own position in the sequence.
2
commands. Setting bit 0 will lock the I C interface
completely. In this configuration the device will not respond
2
to any I C activity. The device must be power cycled to get
out of either of these locked states.
CONFIGURATION EXAMPLES
Figure 3 below shows an example of a register write. In
this example, the address pins of the NCP45495 are tied low,
selecting address 0x34 as the slave address. The
ACITVE_CHAN register is written with 0x89, which will
set channel 1 and channel 4 active, the ground reference is
also enabled.
2
I C INTERFACE DETAILS
2
The NCP45495 uses a 400 kHz, slave mode FM I C
interface for communication with an I C master. The
purpose of the I C interface is to provide access to
2
2
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8
NCP45495
SDA
SCL
0x34
0x04
0x89
Slave Address
ACTIVE_CHAN Register
Data Written to Register
Figure 3. I2C Register Write Example
Figure 4 below shows an example of a register read. In this example, the master reads 0x89 from the ACTIVE_CHAN register.
SDA
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
SCL
0x34 (7 bits)
Slave Address
0x04 (8 bits)
ACTIVE_CHAN Register
0x89 (8 bits)
Data Written to Register
Figure 4. I2C Register Read Example
Table 8. TIMING REQURIEMENTS: I2C INTERFACE
Rating
Symbol
Min
Max
0.4
−
Unit
MHz
ms
SCL Clock Frequency
F
I2C
Repeated hold time START condition (after this period, the
first clock pulse is generated)
t
0.26
HD,STA
Data hold time
t
0
−
−
ms
ms
ms
ms
ns
ns
ns
ms
ms
pF
V
HD,DAT
LOW period of the SCL clock
t
0.5
0.26
0.26
50
LOW
HIGH period of the SCL clock
t
−
HIGH
Setup time for repeated start condition
Data setup time
t
−
SU,STA
SU;DAT
t
−
Rise time for both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
t
r
−
120
120
−
t
f
18.1
0.26
0.5
−
t
SU,STO
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the LOW level for each connected device
Noise margin at the HIGH level for each connected device
Max ACK delay
t
−
BUF
C
550
−
B
V
0.1*V
nL
nH
CC
CC
V
0.2*V
−
V
ACK
1
ms
MAX
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9
NCP45495
MSB
SDA
SCL
tr
tSU,DAT
tr
tHD,STA
tf
tBUF
tLOW
tof
tSU,STA
tSU,STO
tHIGH
tHD,STA
tHD,DAT
Figure 5. I2C Bus Timing
Write Data Example
1 bit
7 bits
Slave
1 bit 1 bit
8 bits
1 bit
8 bits
DATA
1 bit 1 bit
Register
Address
S
W=0
A
A
A/A
P
Address
Read Data Example
1 bit
S
7 bits
1 bit
R=1
1 bit
8 bits
1 bit
8 bits
DATA
1 bit 1 bit
A/A
Slave
Register
Address
A
A
P
Address
•
•
•
•
A = acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
From master to slave
From slave to master
P = STOP condition
Figure 6. I2C Read / Write Protocol Format
Repeated Start format is also supported as shown below.
Read Data Example with Repeated Start
1 bit
1 bit
S
7 bits
1 bit 1 bit
8 bits
1 bit
7 bits
1 bit 1 bit
8 bits
DATA
1 bit 1 bit
A/A
Slave
Address
Register
Address
Slave
Address
R=0
A
A
Sr
R=1
A
P
Repeated Start
•
•
•
•
A = acknowledge (SDA low)
From master to slave
From slave to master
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
Figure 7. I2C Read with Repeated Start Format
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10
NCP45495
The purposes and utilities of all accessible registers in the NCP45495 are detailed below. Addresses and bit assignments are
explained.
Table 9. REGISTER MAP
Register
Address
Default
Setting
New Value
Takes Effect
Register Name
VendorID
Bits
7:0
7:0
7
R/W
R
Description
onsemi Specific ID
0x00
0x01
0x04
0x4F
0x2D
0
N/A
N/A
DeviceID
R
NCP45495 Specific Device ID
Enable Ground Reference
ACTIVE_CHAN
R/W
At next
MUX_SEL cycle
5
4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable iMon Channel 2
Enable iMon Channel 1
Enable Channel 4
0
0
At next
MUX_SEL cycle
At next
MUX_SEL cycle
3
1
At next
MUX_SEL cycle
2
Enable Channel 3
1
At next
MUX_SEL cycle
1
Enable Channel 2
1
At next
MUX_SEL cycle
0
Enable Channel 1
1
At next
MUX_SEL cycle
0x05
MUX_SEL_SKIP
7:4
Pulses to skip at the start of the MUX_SEL
cycle (skipping pulses at the beginning de-
fines device as device B in paired mode)
0x0
At next
MUX_SEL cycle
(set as 0x00 if operating
in single device mode)
3:0
R/W
Pulses to skip at the end of the MUX_SEL
cycle (skipping pulses at the end defines
device as device A in paired mode)
0x0
At next
MUX_SEL cycle
0x06
0x07
ALTERNATING_MODE
DIFF_AMP_OFFSET
7:7
1:0
R/W
R/W
0b1: Use Alternating Polarity Mode
0b0: Alternating Polarity Mode Disabled
0
At next
MUX_SEL cycle
0b11: −375 mV
0b10: −350 mV
0b01: −325 mV
0b00: 0 mV
0x0
Immediately
0x08
DIFF_AMP_CM
Note: Differential output
accuracy not guaranteed
3:0
R/W
0b1111: 875 mV
0b1110: 850 mV
0b0111: 675 mV
0b0100: 600 mV
0b0011: 575 mV
0x7
(675mV)
Immediately
with V
below 575 mV.
CMR
(Codes 0x0, 0x1, 0x2)
0x0F
TIMEOUT
7:7
R/W
0b1: Disable Timeout
0b0: Timeout Active
0
Immediately
Immediately
0x10
0x11
0x12
0x13
0x20
0x21
0x22
0x23
0x24
BUS_GAIN1
BUS_GAIN2
BUS_GAIN3
BUS_GAIN4
SHUNT_GAIN1
SHUNT_GAIN2
SHUNT_GAIN3
SHUNT_GAIN4
LOCK
5:1
5:1
5:1
5:1
5:1
5:1
5:1
5:1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(Register contents: See Table 7)
0x3E: 1/4
0x00: 1/64
0x00
(1/64)
(Register contents: See Table 6)
0x3E: 24x
0x00: 2x
0x00
(2x)
Immediately
2
Lock I C interface writes
0
0
Immediately
Immediately
2
0
Lock I C interface reads / writes
www.onsemi.com
11
NCP45495
APPLICATIONS DIAGRAMS
+3.3V
VBUS
IN_Px
Must be
Kelvin
BV_OK
VB_INx
IN_Nx
To controller
Connections
DIFF_OUT_P
IMON_IN1
IMON_IN2
Differential
to ADC
To Load
DIFF_OUT_N
SYNC
NCP45495
BG_REF_OUT
BV_REF
SCL
To controller
SDA
Pull to 3.3V or 0V
to set SKIP logic
SKIP
GND
RGND
Reference
Ground
Figure 8. Stand Alone Device Typical Application Diagram
Power-Up Time
MUX_SEL
Diff. Out
SYNC
Ch 1 BV Ch 1 SC Ch 2 BV Ch 2 SC Ch 3 BV Ch 3 SC Ch 4 BV Ch 4 SC Ch 1 BV Ch 1 SC
EN_B
VCC
Figure 9. Stand Alone Signal Characteristics with all 4 Channels Activated
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12
NCP45495
MUX_SEL
Diff. Out
Ch 1 BV Ch 1 SC Ch 2 BV Ch 2 SC Ch 3 BV Ch 3 SC Ch 4 BV Ch 4 SC IMON 1 IMON 2
CAL
Ch 1 BV Ch 1 SC Ch 2 BV
SYNC
EN_B
VCC
Figure 10. Stand Alone Signal Characteristics with IMON 1, IMON2, and Ground Reference Bits Set and all
Channels Activated
MUX_SEL
Diff. Out
Ch 1 BV
Ch 1 SC
Ch 2 BV
Ch 2 SC
Ch 3 BV
Ch 3 SC
Ch 4 BV
Ch 4 SC
Ch 1 BV
Ch 1 SC
Ch 2 BV
Ch 2 SC
Ch 3 BV
Ch 3 SC
Ch 4 BV
Ch 4 SC
Standard Polarity
Reverse Polarity
SYNC
EN_B
VCC
Figure 11. Stand Alone Signal Characteristics with ALTERNATING_MODE Bit Set and all Channels Activated
+3.3V
+3.3V
0V
+3.3V
Differential
to ADC
To Controller
VBUSx
VBUSx
VCC
Must be
Kelvin
Connections
IN_Px
IN_Px
VB_INx
IN_Nx
Must be
Kelvin
Connections
VB_INx
IN_Nx
BV_OK
DIFF_OUT_P
DIFF_OUT_N
BV_OK
To Loads
To Loads
IMON_IN1
IMON_IN2
SYNC
IMON_IN1
IMON_IN2
SYNC
NCP45495
Device A
NCP45495
Device B
DIFF_OUT_P
Pull to 3.3V or 0V
to set SKIP logic
Pull to 3.3V or 0V
to set SKIP logic
SKIP
SKIP
DIFF_OUT_N
BG_REF_OUT
BG_REF_OUT
GND
GND
BV_REF
BV_REF
Figure 12. Six−Channel Paired Devices Connection Diagram
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13
NCP45495
MUX_SEL
Ch 1 BV
Ch 1 SC
Ch 2 BV
Ch 2 SC
Ch 3 BV
Ch 3 SC
Ch 1 BV
Ch 1 SC
Hi-Z
Diff. Out (Device A)
Diff. Out (Device B)
ADC Input
Ch 4 BV
Ch 4 BV
Ch 4 SC
Ch 4 SC
Ch 5 BV
Ch 5 BV
Ch 5 SC
Ch 6 BV
Ch 6 BV
Ch 6 SC
Ch 6 SC
Hi-Z
Hi-Z
Ch 1 BV
Ch 1 SC
Ch 2 BV
Ch 2 SC
Ch 3 BV
Ch 3 SC
Ch 5 SC
Ch 1 BV
Ch 1 SC
EN_B
VCC
Figure 13. Six−Channel Paired Device Signal Characteristics with 6 Channels Activated
The following example shows the output sequence when all channels are active with a ground reference and alternating mode
enabled in paired mode. The register settings for each device are shown below.
2
2
DEVICE A (I C address: 0x34)
DEVICE B (I C Address: 0x35)
Register Address
Register Setting
0xBF
Register Address
Register Setting
0xBF
0x04
0x05
0x06
0x04
0x05
0x06
0x0B
0xB0
0x80
0x80
www.onsemi.com
14
NCP45495
Clock Cycle
Diff Output (Device A)
Diff Output (Device B)
High Z
0
High Z
Ch 1 Bus Voltage
Ch 1 Shunt Current
Ch 2 Bus Voltage
Ch 2 Shunt Current
Ch 3 Bus Voltage
Ch 3 Shunt Current
Ch 4 Bus Voltage
Ch 4 Shunt Current
iMon1
1
High Z
2
High Z
3
High Z
4
High Z
5
High Z
6
High Z
7
High Z
8
High Z
9
High Z
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
iMon2
High Z
Ref GND
High Z
High Z
Ch 1 Bus Voltage
Ch 1 Shunt Current
Ch 2 Bus Voltage
Ch 2 Shunt Current
Ch 3 Bus Voltage
Ch 3 Shunt Current
Ch 4 Bus Voltage
Ch 4 Shunt Current
iMon1
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
iMon2
High Z
Ref GND
Ch 1 Bus Voltage Reversed
Ch 1 Shunt Current Reversed
Ch 2 Bus Voltage Reversed
Ch 2 Shunt Current Reversed
Ch 3 Bus Voltage Reversed
Ch 3 Shunt Current Reversed
Ch 4 Bus Voltage Reversed
Ch 4 Shunt Current Reversed
iMon1 Reversed
iMon2 Reversed
Ref GND Reversed
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
Ch 1 Bus Voltage Reversed
Ch 1 Shunt Current Reversed
Ch 2 Bus Voltage Reversed
Ch 2 Shunt Current Reversed
Ch 3 Bus Voltage Reversed
Ch 3 Shunt Current Reversed
Ch 4 Bus Voltage Reversed
Ch 4 Shunt Current Reversed
iMon1 Reversed
iMon2 Reversed
Ref GND Reversed
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
Ch 1 Bus Voltage
www.onsemi.com
15
NCP45495
AUXILIARY FUNCTIONS
Bus Comparator (BV_OK): The BV_OK pin provides a
real−time indication that V and all bus voltages (as
Enable Function: The EN_B pin controls device operation
according to the corresponding table.
CC
measured on the BV_INx pins) are valid. BV_OK remains
low until all used BV_INx pins are above a user−defined
threshold voltage. The BV_OK threshold is set by an
external resistor divider on the BV_REF pin. The internal
BV_OK comparator has built in hysteresis of 10% to
prevent chatter as voltage busses come up. All channels
specified in the ACTIVE_CHAN register will be
represented. If desired, the user can use the SKIP pin to
modify the logic as shown in the corresponding table (H =
high, L = low, Z = tristate, X = don’t care). The SKIP pin can
EN_B LOGIC
Level
Device Operation
LOW
Fully Functional
Tri−state
(floating)
Limited Function: BG_REF_OUT is valid, BV_OK
comparators and output are functional. All other
functions to be disabled. DIFF_OUT to be Hi−Z
and multiplexer select logic is held in reset.
HIGH
Standby: Power down state. Nothing is active.
Input Filtering:
If additional filtering is needed on the input bus lines,
external filtering can be added as shown below.
also be used to hold BV_OK = L in the absence of V
.
CC
VCC EN_B VB_INx SKIP BV_OK Notes
open
drain
No Power
V
BUS1
L
L
L
L
X
X
L
Provided to Part
SKIP Pin Provides
H
L
Power Needed to
Hold BV_OK Low
BV_IN1
IN_P1
open
drain
R
R
F
H
H
H
H
X
X
L
L
Standby Mode
H
H
H
L
L
Standby Mode
C
F
Functional or
Limited Mode
Functional or
Limited Mode
Functional or
Limited Mode
Z/L
F
open
drain
open
drain
IN_N1
H
H
Z/L
Z/L
H
X
H
L
Mismatch between the 2 R values will contribute to the
F
overall measurement offset error. To avoid this, the
tolerance of external R resistors should be < 1%. External
R values should not exceed 20 kW.
F
F
Reset/Timeout: If the timeout is enabled, holding the
MUX_SEL pin HIGH or LOW linger then 45 ms will reset
to the beginning of the MUX_SEL sequence. If the timeout
has been disabled, then the MUX_SEL must cycle through
all set channels to return to the beginning of the sequence.
Toggling the EN_B pin will also reset the sequence back to
the beginning.
Layout Considerations
Sensitive signals that require special attention in board
layout include the channel inputs (IN_N, IN_P, and BV_IN
signals), the differential output signals, and the MUX_SEL
signal. The IN_N and IN_P signals require a direct kelvin
connection to the leads of the sense resistor to avoid parasitic
trace resistance affecting the shunt current measurement.
This direct connection is shown below. The sense resistors
and connections from source to load for each channel need
to be large enough to accommodate the expected high load
currents.
Bandgap Reference: The BG_REF_OUT pin provides a
high−accuracy voltage that can be used to generate the
BV_REF voltage for the BV_OK comparators.
www.onsemi.com
16
NCP45495
Keep MUX_SEL
isolated from other
dynamic signals
GND
Channel 1 (Repeat circuit for each channel)
Optional Input Filter Not Shown For Clarity
C1
To LOAD
Width based
on expected
load current
>= 6mil
I2C Data Signal
SDA
SCL
IN_N1
Matched length
and width
R5
I2C Clock Input
IN_P1
BV_IN1
IN_N2
>= 6mil
>= 6mil
Tie to GND or VCC to set Address 1 Bit
Top down view of PCB
ADRS[1]
ADRS[0]
DIFF_OUTP
Width based
on expected
load current
Tie to GND or VCC to set Address 0 Bit
Anti-Aliasing Filter
VBUS
IN_P2
To ADC
C1
BV_IN2
DIFF_OUTN
BV_REF
BG_OUT
Connect back
paddle to GND
Keep Differential
Pair close
Imon1 input voltage
Imon1 input voltage
IMON_IN1
IMON_IN2
together and
matched
R3
R4
To GND
To GND
Care should be taken to keep DIFF_OUT_P and
DIFF_OUT_N matched. As a differential pair, any noise
introduced to the pair will be common and will be rejected
if the signals are close together and matched in length. Care
should be taken to keep the MUX_SEL line isolated from
other dynamically changing signals.
Unused Pins
Connection
BV_INx
Connect to BV_IN pin of a previous channel
or GND
IN_Px
IN_Nx
IMONx
SYNC
Connect to the same potential as BV_INx or
Float
Float or GND
Float
Unused Channels
Unused channels should be disabled by setting Register
2
0x04 over I C. The IN_P and IN_N pins for an unused
channel should have the same connection. The following
table details the recommended connections for unused pins.
www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN32 4x4, 0.4P
CASE 485CD
ISSUE A
1
DATE 09 OCT 2012
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
B
E
A
D
L
L
PIN ONE
REFERENCE
L1
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
DETAIL A
MILLIMETERS
ALTERNATE TERMINAL
CONSTRUCTIONS
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
0.15
0.25
D
D2
E
E2
e
K
K2
L
L1
4.00 BSC
0.10
0.10
C
EXPOSED Cu
MOLD CMPD
2.60
2.80
4.00 BSC
C
2.60
2.80
TOP VIEW
0.40 BSC
0.30 REF
0.45 REF
A
DETAIL B
0.05
C
ALTERNATE
A3
0.25
−−−
0.45
0.15
CONSTRUCTION
GENERIC
MARKING DIAGRAM*
0.05
C
DETAIL B
NOTE 4
A1
SEATING
PLANE
C
SIDE VIEW
XXXXXX
XXXXXX
ALYWG
G
C
A
B
0.10
DETAIL A
D2
K
9
4X
K2
XXXXX = Specific Device Code
A
L
Y
W
G
17
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
32X L
DETAIL C
CORNER LEAD
CONSTRUCTION
E2
(Note: Microdot may be in either location)
1
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
C
B
A
B
0.10
25
32X
DETAIL C
b
0.07
e
M
M
C
A
RECOMMENDED
MOUNTING FOOTPRINT
C
0.05
NOTE 3
BOTTOM VIEW
4.30
2.80
32X
0.58
PACKAGE
OUTLINE
1
2.80
4.30
8X
C0.08
32X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON66248E
QFN32 4X4, 0.4P
PAGE 1 OF 1
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