NCP5106AMNTWG [ONSEMI]
MOSFET / IGBT 驱动器，高电压，高压和低压侧;
| 型号： | NCP5106AMNTWG |
| 厂家： | 
ONSEMI |
| 描述： | MOSFET / IGBT 驱动器，高电压，高压和低压侧 驱动 双极性晶体管 高压 光电二极管 接口集成电路 驱动器 |
| 文件： | 总18页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP5106A, NCP5106B
High Voltage, High and Low
Side Driver
The NCP5106 is a high voltage gate driver IC providing two
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration version B or any other
high−side + low−side configuration version A.
It uses the bootstrap technique to ensure a proper drive of the
high−side power switch. The driver works with 2 independent inputs.
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MARKING
DIAGRAMS
Features
1
8
• High Voltage Range: Up to 600 V
• dV/dt Immunity 50 V/nsec
• Negative Current Injection Characterized Over the Temperature Range
• Gate Drive Supply Range from 10 V to 20 V
• High and Low Drive Outputs
SOIC−8
D SUFFIX
CASE 751
5106x
ALYW
G
1
• Output Source / Sink Current Capability 250 mA / 500 mA
• 3.3 V and 5 V Input Logic Compatible
NCP5106x
AWLG
1
PDIP−8
P SUFFIX
CASE 626
YYWW
• Up to V Swing on Input Pins
CC
• Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
for Signal Propagation
• Matched Propagation Delays Between Both Channels
• Outputs in Phase with the Inputs
• Independent Logic Inputs to Accommodate All Topologies (Version A)
• Cross Conduction Protection with 100 ns Internal Fixed Dead Time
(Version B)
NCP5106 = Specific Device Code
x
A
= A or B version
= Assembly Location
= Wafer Lot
L or WL
Y or YY
W or WW = Work Week
G or G
= Year
= Pb−Free Package
• Under V LockOut (UVLO) for Both Channels
CC
• Pin−to−Pin Compatible with Industry Standards
• These are Pb−Free Devices
PINOUT INFORMATION
VBOOT
VCC
IN_HI
IN_LO
GND
1
2
3
4
8
7
6
5
DRV_HI
BRIDGE
DRV_LO
Typical Applications
• Half−Bridge Power Converters
• Any Complementary Drive Converters (Asymmetrical Half−Bridge,
Active Clamp) (A Version Only).
8 Pin Package
• Full−Bridge Converters
ORDERING INFORMATION
†
Device
Package
Shipping
NCP5106APG
PDIP−8
50 Units / Rail
(Pb−Free)
NCP5106ADR2G
NCP5106BPG
SOIC−8 2500 / Tape & Reel
(Pb−Free)
PDIP−8
50 Units / Rail
(Pb−Free)
NCP5106BDR2G
SOIC−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
March, 2010 − Rev. 5
NCP5106/D
NCP5106A, NCP5106B
+
Vbulk
Vcc
C1
D4
U1
GND
Q1
L1
D1
Out+
T1
C3
+
C4
8
1
2
3
4
C3
GND
VBOOT
Vcc
IN_HI DRV_HI
Bridge
7
6
5
Lf
NCP1395
GND
Out−
IN_LO
D2
R1
GND DRV_LO
NCP5106
C6
Q2
GND
GND
D3
GND
U2
Figure 1. Typical Application Resonant Converter (LLC type)
+
Vbulk
Vcc
C1
C5
D4
GND
Q1
L1
D1
C3
Out+
T1
U1
VBOOT
C4
+
GND
1
2
3
4
8
7
6
5
Vcc
C3
Out−
IN_HI DRV_HI
IN_LO Bridge
GND DRV_LO
NCP5106
MC34025
GND
D2
R1
C6
Q2
GND
GND
D3
GND
U2
Figure 2. Typical Application Half Bridge Converter
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2
NCP5106A, NCP5106B
VCC
VCC
VBOOT
UV
DETECT
IN_HI
S Q
DRV_HI
BRIDGE
PULSE
TRIGGER
LEVEL
SHIFTER
R
Q
UV
DETECT
GND
GND
VCC
IN_LO
GND
DRV_LO
GND
DELAY
GND
GND
GND
Figure 3. Detailed Block Diagram: Version A
VCC
VCC
VBOOT
UV
DETECT
IN_HI
S Q
DRV_HI
BRIDGE
PULSE
TRIGGER
LEVEL
SHIFTER
R
Q
UV
DETECT
CROSS
CONDUCTION
PREVENTION
GND
GND
VCC
DRV_LO
GND
IN_LO
DELAY
GND
GND
Figure 4. Detailed Block Diagram: Version B
PIN DESCRIPTION
Pin Name
IN_HI
Description
Logic Input for High Side Driver Output in Phase
Logic Input for Low Side Driver Output in Phase
Ground
IN_LO
GND
DRV_LO
Low Side Gate Drive Output
V
V
Low Side and Main Power Supply
Bootstrap Power Supply
CC
BOOT
DRV_HI
BRIDGE
High Side Gate Drive Output
Bootstrap Return or High Side Floating Supply Return
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3
NCP5106A, NCP5106B
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 20
23
Unit
V
V
Main power supply voltage
CC
CC_transient
V
Main transient power supply voltage:
IV = 5 mA during 10 ms
V
CC_max
V
V
VHV: High Voltage BRIDGE pin
−1 to 600
−10
V
V
BRIDGE
Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO
(see characterization curves for detailed results)
BRIDGE
V
V
VHV: Floating supply voltage
VHV: High side output voltage
−0.3 to 20
V
V
BOOT− BRIDGE
V
V
− 0.3 to
DRV_HI
BRIDGE
V
+ 0.3
BOOT
V
Low side output voltage
Allowable output slew rate
Inputs IN_HI, IN_LO
−0.3 to V + 0.3
V
V/ns
V
DRV_LO
CC
dV
BRIDGE
/dt
50
V
−1.0 to V + 0.3
IN_XX
CC
ESD Capability:
− HBM model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
− Machine model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
2
kV
V
200
Latch up capability per JEDEC JESD78
R
q
JA
Power dissipation and Thermal characteristics
PDIP−8: Thermal Resistance, Junction−to−Air
SO−8: Thermal Resistance, Junction−to−Air
°C/W
100
178
T
Storage Temperature Range
−55 to +150
°C
°C
ST
T
Maximum Operating Junction Temperature
+150
J_max
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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4
NCP5106A, NCP5106B
ELECTRICAL CHARACTERISTIC (V = V
= 15 V, V
= V , −40°C < T < 125°C, Outputs loaded with 1 nF)
bridge J
CC
boot
GND
T −40°C to 125°C
J
Min
Typ
Max
Rating
Symbol
Units
OUTPUT SECTION
Output high short circuit pulsed current V
= 0 V, PW v 10 ms (Note 1)
I
−
−
−
−
−
−
250
500
30
−
−
mA
mA
W
DRV
DRVsource
Output low short circuit pulsed current V
= V , PW v 10 ms (Note 1)
I
DRV
CC
DRVsink
Output resistor (Typical value @ 25°C) Source
Output resistor (Typical value @ 25°C) Sink
R
OH
60
20
1.6
0.6
R
OL
10
W
High level output voltage, V
−V
@ I
= 20 mA
V
0.7
0.2
V
BIAS DRV_XX
DRV_XX
DRV_H
Low level output voltage V
@ I
= 20 mA
V
DRV_L
V
DRV_XX
DRV_XX
DYNAMIC OUTPUT SECTION
Turn−on propagation delay (Vbridge = 0 V)
Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 2)
Output voltage rise time (from 10% to 90% @ V = 15 V) with 1 nF load
t
−
−
−
−
−
100
100
85
170
170
160
75
ns
ns
ns
ns
ns
ON
t
OFF
tr
CC
Output voltage fall time (from 90% to 10% @V = 15 V) with 1 nF load
tf
35
CC
Propagation delay matching between the High side and the Low side
@ 25°C (Note 3)
Dt
20
35
Internal fixed dead time (only valid for B version) (Note 4)
Minimum input width that changes the output
Maximum input width that does not change the output
INPUT SECTION
DT
65
−
100
−
190
50
−
ns
ns
ns
t
PW1
PW2
t
20
−
Low level input voltage threshold
V
−
−
−
200
−
0.8
−
V
kW
V
IN
Input pull−down resistor (V < 0.5 V)
R
V
IN
IN
High level input voltage threshold
2.3
−
−
IN
Logic “1” input bias current @ V
Logic “0” input bias current @ V
SUPPLY SECTION
= 5 V @ 25°C
= 0 V @ 25°C
I
I
5
25
2.0
mA
mA
IN_XX
IN_XX
IN+
IN−
−
−
V
V
UV Start−up voltage threshold
V
_stup
8.0
7.3
0.3
8.0
8.9
8.2
0.7
8.9
9.9
9.1
−
V
V
V
V
CC
CC
CC
UV Shut−down voltage threshold
V
CC
_shtdwn
Hysteresis on V
V
CC
_hyst
CC
Vboot Start−up voltage threshold reference to bridge pin
(Vboot_stup = Vboot − Vbridge)
Vboot_stup
9.9
Vboot UV Shut−down voltage threshold
Hysteresis on Vboot
Vboot_shtdwn
Vboot_shtdwn
7.3
0.3
−
8.2
0.7
5
9.1
−
V
V
Leakage current on high voltage pins to GND
I
40
mA
HV_LEAK
(V
BOOT
= V
= DRV_HI = 600 V)
BRIDGE
Consumption in active mode (V = Vboot, fsw = 100 kHz and 1 nF load on
ICC1
−
4
5
mA
CC
both driver outputs)
Consumption in inhibition mode (V = Vboot)
ICC2
ICC3
ICC4
−
−
−
250
200
50
400
−
mA
mA
mA
CC
V
CC
current consumption in inhibition mode
Vboot current consumption in inhibition mode
−
1. Parameter guaranteed by design.
2. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design.
3. See characterization curve for Dt parameters variation on the full range temperature.
4. Version B integrates a dead time in order to prevent any cross conduction between DRV_HI and DRV_LO. See timing diagram of Figure 10.
5. Timing diagram definition see: Figure 7, Figure 8 and Figure 9.
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5
NCP5106A, NCP5106B
IN_HI
IN_LO
DRV_HI
DRV_LO
Figure 5. Input/Output Timing Diagram (A Version)
IN_HI
IN_LO
DRV_HI
DRV_LO
Figure 6. Input/Output Timing Diagram (B Version)
50%
50%
IN_HI
(IN_LO)
t
r
t
f
t
on
t
off
90%
90%
DRV_HI
(DRV_LO)
10%
10%
Figure 7. Propagation Delay and Rise / Fall Time Definition
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6
NCP5106A, NCP5106B
IN_LO
&
IN_HI
50%
50%
ton_HI
toff_HI
90%
Delta_t
DRV_HI
10%
ton_LO
Delta_t
90%
toff_LO
DRV_LO
Matching Delay 1 = ton_HI − ton_LO
Matching Delay 2 = toff_LO − toff_HI
10%
Figure 8. Matching Propagation Delay (A Version)
50%
50%
IN_HI
toff_HI
ton_HI
90%
DRV_HI
IN_LO
10%
Matching Delay1=ton_HI−ton_LO
Matching Delay2=toff_HI−toff_LO
50%
50%
toff_LO
ton_LO
10%
90%
DRV_LO
Figure 9. Matching Propagation Delay (B Version)
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7
NCP5106A, NCP5106B
IN_HI
IN_LO
DRV_HI
DRV_LO
Internal Deadtime
Internal Deadtime
Figure 10. Input/Output Cross Conduction Output Protection Timing Diagram (B Version)
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8
NCP5106A, NCP5106B
CHARACTERIZATION CURVES
140
120
100
80
140
T
ON
Low Side
120
100
80
T
ON
High Side
60
60
T
ON
High Side
T
ON
Low Side
40
40
20
0
20
0
10
12
14
16
18
20
−40
−20
0
20
40
60
80
100
120
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 11. Turn ON Propagation Delay vs.
Figure 12. Turn ON Propagation Delay vs.
Temperature
Supply Voltage (VCC = VBOOT
)
140
120
100
80
140
120
100
T
Low Side
OFF
T
OFF
Low Side
80
60
40
20
0
T
OFF
High Side
60
T
High Side
OFF
40
20
0
10
12
14
16
18
20
−40
−20
0
20
40
60
80
100
120
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 13. Turn OFF Propagation Delay vs.
Supply Voltage (VCC = VBOOT
Figure 14. Turn OFF Propagation Delay vs.
Temperature
)
160
140
120
100
80
140
120
100
80
60
60
40
40
20
20
0
0
0
10
20
30
40
50
0
10
20
30
40
50
BRIDGE PIN VOLTAGE (V)
BRIDGE PIN VOLTAGE (V)
Figure 15. High Side Turn ON Propagation
Delay vs. VBRIDGE Voltage
Figure 16. High Side Turn OFF Propagation
Delay vs. VBRIDGE Voltage
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9
NCP5106A, NCP5106B
CHARACTERIZATION CURVES
160
140
120
100
80
140
120
100
t Low Side
r
t High Side
r
80
60
40
20
0
t High Side
r
60
40
t Low Side
r
20
0
10
−40 −20
0
20
40
60
80
100 120
12
14
16
18
20
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 17. Turn ON Risetime vs. Supply
Voltage (VCC = VBOOT
Figure 18. Turn ON Risetime vs. Temperature
)
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
t Low Side
f
t High Side
f
t High Side
f
t Low Side
f
10
12
14
16
18
20
−40 −20
0
20
40
60
80
100
120
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 19. Turn OFF Falltime vs. Supply
Voltage (VCC = VBOOT
Figure 20. Turn OFF Falltime vs. Temperature
)
20
200
180
160
140
120
100
80
15
10
60
5
0
40
20
0
−40
−40
−20
0
20
40
60
80
100
120
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Propagation Delay Matching
Between High Side and Low Side Driver vs.
Temperature
Figure 22. Dead Time vs. Temperature
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10
NCP5106A, NCP5106B
CHARACTERIZATION CURVES
1.4
1.2
1
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.8
0.6
0.4
0.2
0
10
12
14
16
18
20
−40 −20
0
20
40
60
80
100
120
TEMPERATURE (°C)
V , VOLTAGE (V)
CC
Figure 23. Low Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT
Figure 24. Low Level Input Voltage Threshold
vs. Temperature
)
2.5
2
2.5
2.0
1.5
1.0
0.5
0.0
1.5
1
0.5
0
10
12
14
16
18
20
−40 −20
0
20
40
60
80
100
120
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 25. High Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT
Figure 26. High Level Input Voltage Threshold
vs. Temperature
)
4
6
5.5
5
3.5
3
2.5
2
4.5
4
3.5
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
−40
−20
0
20
40
60
80
100 120
10
12
14
16
18
20
TEMPERATURE (°C)
V , VOLTAGE (V)
CC
Figure 27. Logic “0” Input Current vs. Supply
Voltage (VCC = VBOOT
Figure 28. Logic “0” Input Current vs.
Temperature
)
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11
NCP5106A, NCP5106B
CHARACTERIZATION CURVES
8
7
6
5
4
3
2
1
0
10
8
6
4
2
0
−40
10
12
14
16
18
20
−20
0
20
40
60
80
100
120
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 30. Logic “1” Input Current vs.
Temperature
Figure 29. Logic “1” Input Current vs. Supply
Voltage (VCC = VBOOT
)
1.0
1
0.8
0.6
0.4
0.2
0.0
0.8
0.6
0.4
0.2
0
10
12
14
16
18
20
−40 −20
0
20
40
60
80
100
120
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 31. Low Level Output Voltage vs.
Supply Voltage (VCC = VBOOT
Figure 32. Low Level Output Voltage vs.
Temperature
)
1.6
1.2
0.8
0.4
0.0
1.6
1.2
0.8
0.4
0
−40 −20
0
20
40
60
80
100 120
10
12
14
16
18
20
TEMPERATURE (°C)
V , VOLTAGE (V)
CC
Figure 33. High Level Output Voltage vs.
Supply Voltage (VCC = VBOOT
Figure 34. High Level Output Voltage vs.
Temperature
)
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12
NCP5106A, NCP5106B
CHARACTERIZATION CURVES
400
350
300
250
200
150
100
50
400
I
src
High Side
350
300
250
200
150
100
50
I
src
High Side
I
src
Low Side
I
src
Low Side
0
10
0
−40
−20
0
20
40
60
80
100 120
12
14
16
18
20
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 35. Output Source Current vs. Supply
Voltage (VCC = VBOOT
Figure 36. Output Source Current vs.
Temperature
)
600
500
400
300
200
100
0
600
500
400
300
200
100
0
I
High Side
I
High Side
sink
sink
I
Low Side
sink
I
Low Side
sink
10
12
14
16
18
20
−40
−20
0
20
40
60
80
100 120
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 37. Output Sink Current vs. Supply
Voltage (VCC = VBOOT
Figure 38. Output Sink Current vs.
Temperature
)
20
15
10
5
0.2
0.16
0.12
0.08
0.04
0
0
−40
0
100
200
300
400
500
600
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
HV PINS VOLTAGE (V)
Figure 39. Leakage Current on High Voltage
Pins (600 V) to Ground vs. VBRIDGE Voltage
Figure 40. Leakage Current on High Voltage
Pins (600 V) to Ground vs. Temperature
(VBRIDGE = VBOOT = VDRv_HI = 600 V)
(VBRIGDE = VBOOT = VDRV_HI
)
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13
NCP5106A, NCP5106B
CHARACTERIZATION CURVES
100
80
60
40
20
0
100
80
60
40
20
0
0
4
8
12
, VOLTAGE (V)
16
20
−40
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
V
BOOT
Figure 41. VBOOT Supply Current vs. Bootstrap
Supply Voltage
Figure 42. VBOOT Supply Current vs.
Temperature
240
200
160
120
80
400
300
200
100
0
40
0
0
4
8
12
16
20
−40
−20
0
20
40
60
80
100
120
V , VOLTAGE (V)
CC
TEMPERATURE (°C)
Figure 43. VCC Supply Current vs. VCC Supply
Voltage
Figure 44. VCC Supply Current vs. Temperature
10.0
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
V
UVLO Shutdown
CC
V
UVLO Startup
CC
V
UVLO Shutdown
BOOT
V
UVLO Startup
BOOT
−40
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 45. UVLO Startup Voltage vs.
Temperature
Figure 46. UVLO Shutdown Voltage vs.
Temperature
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14
NCP5106A, NCP5106B
CHARACTERIZATION CURVES
40
25
20
15
10
5
C
LOAD
= 2.2 nF/Q = 33 nC
C
LOAD
= 1 nF/Q = 15 nC
R
GATE
= 0 R
35
30
25
20
15
10
5
R
GATE
= 10 R
R
GATE
= 22 R
R
GATE
= 0 R to 22 R
0
0
0
100
200
300
400
500
600
0
100
200
300
400
500
600
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
Figure 47. ICC1 Consumption vs. Switching
Frequency with 15 nC Load on Each Driver @
VCC = 15 V
Figure 48. ICC1 Consumption vs. Switching
Frequency with 33 nC Load on Each Driver @
VCC = 15 V
70
60
120
100
80
60
40
20
0
C
LOAD
= 6.6 nF/Q = 100 nC
C
LOAD
= 3.3 nF/Q = 50 nC
R
= 0 R
GATE
R
= 0 R
GATE
50
40
30
20
10
0
R
= 10 R
R
GATE
= 10 R
GATE
R
GATE
= 22 R
R
GATE
= 22 R
0
100
200
300
400
500
600
0
100
200
300
400
500
600
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
Figure 49. ICC1 Consumption vs. Switching
Figure 50. ICC1 Consumption vs. Switching
Frequency with 50 nC Load on Each Driver @
VCC = 15 V
Frequency with 100 nC Load on Each Driver @
VCC = 15 V
0
−5
0
−5
−40°C
−40°C
25°C
−10
−15
−20
−25
−30
−35
−10
−15
−20
−25
−30
−35
25°C
125°C
125°C
0
100
200
300
400
500
600
0
100
200
300
400
500
600
NEGATIVE PULSE DURATION (ns)
NEGATIVE PULSE DURATION (ns)
Figure 51. NCP5106A, Negative Voltage Safe
Operating Area on the Bridge Pin
Figure 52. NCP5106B, Negative Voltage Safe
Operating Area on the Bridge Pin
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15
NCP5106A, NCP5106B
APPLICATION INFORMATION
Negative Voltage Safe Operating Area
Summary:
When the driver is used in a half bridge configuration, it
is possible to see negative voltage appearing on the bridge
pin (pin 6) during the power MOSFETs transitions. When
the high−side MOSFET is switched off, the body diode of
the low−side MOSFET starts to conduct. The negative
voltage applied to the bridge pin thus corresponds to the
forward voltage of the body diode. However, as pcb copper
tracks and wire bonding introduce stray elements
(inductance and capacitor), the maximum negative voltage
of the bridge pin will combine the forward voltage and the
oscillations created by the parasitic elements. As any
CMOS device, the deep negative voltage of a selected pin
can inject carriers into the substrate, leading to an erratic
behavior of the concerned component. ON Semiconductor
provides characterization data of its half−bridge driver to
show the maximum negative voltage the driver can safely
operate with. To prevent the negative injection, it is the
designer duty to verify that the amount of negative voltage
pertinent to his/her application does not exceed the
characterization curve we provide, including some safety
margin.
In order to estimate the maximum negative voltage
accepted by the driver, this parameter has been
characterized over full the temperature range of the
component. A test fixture has been developed in which we
purposely negatively bias the bridge pin during the
freewheel period of a buck converter. When the upper gate
voltage shows signs of an erratic behavior, we consider the
limit has been reached.
Figure 51 (or 52), illustrates the negative voltage safe
operating area. Its interpretation is as follows: assume a
negative 10 V pulse featuring a 100 ns width is applied on
the bridge pin, the driver will work correctly over the whole
die temperature range. Should the pulse swing to −20 V,
keeping the same width of 100 ns, the driver will not work
properly or will be damaged for temperatures below
125°C.
• If the negative pulse characteristic (negative voltage
level & pulse width) is above the curves the driver
runs in safe operating area.
• If the negative pulse characteristic (negative voltage
level & pulse width) is below one or all curves the
driver will NOT run in safe operating area.
Note, each curve of the Figure 51 (or 52) represents the
negative voltage and width level where the driver starts to
fail at the corresponding die temperature.
If in the application the bridge pin is too close of the safe
operating limit, it is possible to limit the negative voltage
to the bridge pin by inserting one resistor and one diode as
follows:
Vcc
D2
Vbulk
MUR160
U1
C1
100n
NCP5106A
M1
1
2
3
4
8
7
6
5
VCC VBOOT
IN_Hi
IN_HI
IN_LO BRIDGE
GND DRV_LO
DRV_HI
R1
10R
IN_LO
M2
0
D1
MUR160
0
Figure 53. R1 and D1 Improves the Robustness of the
Driver
R1 and D1 should be placed as close as possible of the
driver. D1 should be connected directly between the bridge
pin (pin 6) and the ground pin (pin 4). By this way the
negative voltage applied to the bridge pin will be limited
by D1 and R1 and will prevent any wrong behavior.
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16
NCP5106A, NCP5106B
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
C
N X 45
_
SEATING
PLANE
1.27 BSC
−Z−
0.10
0.19
0.40
0
0.10 (0.004)
M
J
H
D
8
0
8
_
_
_
_
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
ǒinches
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
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17
NCP5106A, NCP5106B
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8
5
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−B−
MILLIMETERS
INCHES
MIN
1
4
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
K
L
C
7.62 BSC
0.300 BSC
M
N
---
0.76
10
_
1.01
---
0.030
10
0.040
_
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
B
0.13 (0.005)
T A
The product described herein is covered by U.S. patents: 6,097,075; 7,176,723; 6,362,067. There may be some other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5106/D
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