NCP5215MNR2G [ONSEMI]
Dual Synchronous Buck Controller for Notebook;
| 型号： | NCP5215MNR2G |
| 厂家： | 
ONSEMI |
| 描述： | Dual Synchronous Buck Controller for Notebook 开关 |
| 文件： | 总22页 (文件大小：2969K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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NCP5215
Dual Synchronous Buck
Controller for Notebook
Power System
The NCP5215, a high−efficiency and fast−transient−response
dual−channel buck controller, provides a multifunctional power
solution for notebook power system. 180 interleaved operation
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MARKING
o
function between the two channels has capabilities of reducing the
common input capacitor requirement and improving noise immunity.
Adaptive−Voltage−Positioning (AVP) control reduces the
requirement of output filter capacitors. Programmable power−saving
operation ensures high efficiency over entire load range. Input
feedforward voltage−mode control is employed to deal with wide
input voltage range. Transient−Response−Enhancement (TRE)
control for the both channels enables fast transient response.
DIAGRAM
QFN40
MN SUFFIX
CASE 488AR
NCP5215
AWLYYWWG
1
40
A
= Assembly Location
Features
WL = Wafer Lot
YY = Year
WW = Work Week
• Wide Input Voltage Range: 4.5 V to 24 V
• Adjustable Output Voltage Range: 0.8 V to 3.0 V
• Selectable Nominal Fixed Switching Frequency:
200 kHz, 300 kHz, and 400 kHz
G
= Pb−Free Package
PIN CONNECTIONS
• 180° Interleaved Operation Function between the Two Channels
• Programmable Adaptive−Voltage−Positioning (AVP) Operation
• Programmable Transient−Response−Enhancement (TRE) Control
• Power Saving Operation under Light Load Condition
• Input Feedforward Voltage Mode Control
• Resistive or Inductor’s DCR Current Sensing
• 1% Internal 0.8 V Reference
FSET
VCC
BST1
30
29
28
27
26
25
1
2
VCCP1
BG1
AGND
VREF
PGOOD1
PGOOD2
EN1
3
PGND1
VIN
4
• External Soft−Start Operation
5
• Output Discharge and Soft−Stop
NCP5215
FPWM#
6
• Built−in Gate Drivers
7
24 PGND2
23 BG2
EN2
8
• Input Supplies Undervoltage Lockout
• Output Overvoltage and Undervoltage Protections
• Accurate Overcurrent Protection
SS1
VCCP2
BST2
22
21
9
SS2
10
• Thermal Shutdown Protection
• QFN40 Package
• This is a Pb−Free Device
(Top View)
Typical Applications
• Notebook Computers
• CPU Chipset Power Supplies
ORDERING INFORMATION
Device
NCP5215MNR2G
Package
Shipping
QFN40
2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
October, 2008 − Rev. 5
NCP5215/D
NCP5215
TRESET1
CS1+
40
33
TRE1
5VCC
Vin
BST1
TG1
30
31
32
CS1−/Vo1
34
CS1+
CS1−
PWM1
RAMP GENERATOR
DSCH1
CDIFF1
12
Ohm
GATE
DRIVER
1
SWN1
&
Vo1
FB1
FB1
37
PWM LOGIC
1
5VCC
CCM1
LSEN1
SWN1
VCCP1
BG1
Vo1
29
28
27
INV1
VDRP1
COMP1
38
36
39
COMP1
VREF
PGND1
VREF
OVP1
EN_DRV1
CLK CLK1
VIN
FPWM
SS1
EN1
9
Soft Start 1
VREF
VCC
Vin
VREF
7
CDIFF1
Over Current
Detector 1
OC1
ILIM1
35
25
TSD
THERMAL
SHUTDOWN
FPWM
FB1
5VCC
EN1
VCC
FSET
5VCC
Vin
2
1
OC1
PROTECTION
and
DSCH1
Digital Counter &
180o Phase Shift
OSC
NCP5215
PGOOD1
AGND
VREF
CONTROL LOGIC
3
FB2
0.8V
4
Vin
EN2
VIN
OC2
26
5
DSCH2
PGOOD2
PGOOD1
PGOOD2
6
CLK CLK2
VIN
FPWM
OVP2
EN_DRV2
TRESET2
CS2+
11
18
TRE2
5VCC
Vin
BST2
TG2
21
20
19
CS2−/Vo2
17
CS2+
CS2−
PWM2
RAMP GENERATOR
DSCH2
12
Ohm
GATE
DRIVER
2
SWN2
&
Vo2
FB2
FB2
14
PWM LOGIC
2
5VCC
VCCP2
BG2
CDIFF2
CCM2
LSEN2
SWN2
Vo2
22
23
24
INV2
VDRP2
COMP2
13
15
12
COMP2
PGND2
VREF
VREF
SS2
EN2
10
8
Soft Start 2
VREF
CDIFF2
Over Current
Detector 2
OC2
ILIM2
16
Figure 1. Internal Block Diagram and Typical Application
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2
NCP5215
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
FSET
Description
1
2
Frequency SET Programmable pin of switching frequency for two channels.
VCC This pin powers the control section of IC.
VCC
3
AGND
VREF
PGOOD1
PGOOD2
EN1
Analog Ground Low noise ground for control section of IC.
Reference Voltage Output Internal 0.8 V reference output.
Power GOOD 1 Power good indicator of the output voltage of Channel 1. (Open drained)
Power GOOD 2 Power good indicator of the output voltage of Channel 2. (Open drained)
Enable 1 Enable logic input of Channel 1.
4
5
6
7
8
EN2
Enable 2 Enable logic input of Channel 2.
9
SS1
Soft−Start 1 Soft−starting programmable pin of Channel 1.
Soft Start 2 Soft−starting programmable pin of Channel 2.
10
11
SS2
TRESET2
Transient Response Enhancement SET 2 Channel 2 Transient−Response−Enhancement (TRE)
programmable pin.
12
13
14
15
COMP2
INV2
COMP2 Output of the error amplifier of Channel 2.
Inverting Input 2 Error amplifier’s inverting input pin of Channel 2.
Feedback 2 Output voltage feedback of Channel 2.
FB2
VDRP2
Voltage Droop 2 Channel 2 voltage droop output to the compensation. This pin is used to program the
adaptive−voltage−position (AVP) function for Channel 2.
16
17
18
19
20
21
ILMT2
CS2− / Vo2
CS2+
Current Limit 2 Current limit programmable pin of Channel 2.
Current Sense 2− Channel 2 inductor current differential sense inverting input.
Current Sense 2+ Channel 2 inductor current differential sense non−inverting input.
Switch Node 2 Switch node between the top MOSFET and bottom MOSFET of Channel 2.
Top Gate 2 Gate driver output of the top N−Channel MOSFET for Channel 2.
SWN2
TG2
BST2
BOOTSTRAP Connection 2 Channel 2 top gate driver input supply, a bootstrap capacitor connection
between SWN2 and this pin.
22
23
24
25
VCCP2
BG2
VCC Power 2 This pin powers the bottom gate driver of Channel 2.
Bottom Gate 2 Gate driver output of the bottom N−Channel MOSFET for Channel 2.
Power Ground 2 Ground reference and high−current return path for the bottom gate driver of Channel 2.
PGND2
FPWM#
Forced PWM Forced PWM enable logic input. Low to enable forced PWM mode and disable power−saving
mode for both channels.
26
27
28
29
30
Vin
Vin Input voltage monitor input.
PGND1
BG1
Power Ground 1 Ground reference and high−current return path for the bottom gate driver of Channel 1.
Bottom Gate 1 Gate driver output of the bottom N−Channel MOSFET for Channel 1.
VCC Power 1 This pin powers the bottom gate driver of Channel 1.
VCCP1
BST1
BOOTSTRAP Connection 1 Channel 1 top gate driver input supply, a bootstrap capacitor connection
between SWN1 and this pin.
31
32
33
34
35
36
TG1
SWN1
Top Gate 1 Gate driver output of the top N−Channel MOSFET for Channel 1.
Switch Node 1 Switch node between the top MOSFET and bottom MOSFET of Channel 1.
Current Sense 1+ Channel 1 inductor current differential sense non−inverting input.
Current Sense 1− Channel 1 inductor current differential sense inverting input.
Current Limit 1 Current limit programmable pin of Channel 1.
CS1+
CS1− / Vo1
ILMT1
VDRP1
Voltage Droop 1 Channel 1 voltage droop output to the compensation. This pin is used to program the
Adaptive−Voltage−Position (AVP) function for Channel 1.
37
38
39
40
FB1
INV1
Feedback 1 Output voltage feedback of Channel 1.
Inverting Input 1 Error amplifier’s inverting input pin of Channel 1.
COMP1 Output of the error amplifier of Channel 1.
COMP1
TRESET1
Transient Response Enhancement SET 1 Channel 1 Transient−Response−Enhancement (TRE)
program pin.
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3
NCP5215
MAXIMUM RATINGS
Rating
Symbol
, V
Value
Unit
Power Supply Voltages to AGND
V
,
−0.3, 6.0
V
CC CCP1
V
CCP2
High−Side Gate Driver Supplies: BST1 to SWN1, BST2 to SWN2
High−Side FET Gate Driver Voltages: TG1 to SWN1, TG2 to SWN2
V
V
V
− V
− V
,
,
,
−0.3, 6.0
−0.3, 27
V
BST1
SWN1
BST2
SWN2
− V
TG1
TG2
SWN1
V
− V
,
SWN2
Input Voltage Sense Inputs to AGND
Switch Nodes
V
in
V
V
V
, V
−4.0 (<100 ns),
−0.3 (dc), 32
SWN1 SWN2
PGND1, PGND2 to AGND
V
GND
−0.3, 0.3
V
Thermal Characteristics
Thermal Resistance, Junction−to−Air (Pad soldered to PCB)
R
q
JA
36
°C/W
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
T
−40 to +150
−40 to +85
−55 to +150
1
°C
°C
°C
−
J
T
A
T
stg
Moisture Sensitivity Level
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains ESD protection and exceeds the following tests:
Human Body Model (HBM) ≤2.0kV per JEDEC standard: JESD22−A114.
Machine Model (MM) =≤200V per JEDEC standard: JESD22−A115, except Pin 17 and Pin 34, which are ≤150V.
2. Latchup Current Maximum Rating: ≤150mA per JEDEC standard: JESD78.
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4
NCP5215
ELECTRICAL CHARACTERISTICS (V = 5.0 V, V = 12 V, F
= 5.0 V, Fsw = 300 kHz, T = −40°C to 85°C, unless otherwise
A
CC
IN
SET
noted.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGE
Input Voltage
Vin
−
−
−
−
4.5
4.5
4.5
4.5
−
24
5.5
5.5
5.5
V
V
V
V
V
V
V
Operating Voltage
V
CC
5.0
5.0
5.0
CC
Operating Voltage
Operating Voltage
V
CCP1
CCP2
CCP1
CCP2
V
SUPPLY CURRENT
Quiescent Supply Current in Normal
V
I
VEN1 = VEN2 = 5.0 V,
VFPWM# = 0 V TG1, BG1, TG2,
and BG2 are open
−
−
3.0
3.0
6.0
6.0
mA
mA
CC
VCC_N
Operation
V
CC
Quiescent Supply Current in
I
VEN1 = VEN2 = 5.0 V,
VFPWM# = 5.0 V TG1, BG1,
TG2, and BG2 are open
VCC_PS
Power−Saving Operation
V
V
Shutdown Current
I
VEN1 = VEN2 = 0 V
−
−
−
10
mA
CC
VCC_SD
Quiescent Supply Current in Normal
I
,
VEN1 = VEN2 = 5.0 V,
VFPWM# = 0 V TG1, BG1, TG2,
and BG2 are open
1.2
2.0
mA
CCP
VCCP1_N
Operation
I
VCCP2_N
V
Shutdown Current
I
,
VEN1 = VEN2 = 0 V
−
−
−
10
mA
CCP
VCCP1_SD
I
VCCP2_SD
BST Quiescent Supply Current in Normal
Operation
I
, I
VEN1 = VEN2 = 5.0 V,
VFPWM# = 0 V TG1, BG1, TG2,
and BG2 are open
1.0
2.0
mA
BST1_N BST2_N
BST Shutdown Current
I
,
VEN1 = VEN2 = 0 V
−
−
5.0
mA
BST1_SD
I
BST2_SD
VOLTAGE−MONITOR
V
CC
Start Threshold
VCC
V
and V are connected to
CCP
4.05
4.25
4.48
V
UV+
CC
the same voltage source
V
UVLO Hysteresis
VCC
−
200
275
112
400
mV
%
CC
hys
Power Good Higher Threshold
Power Good Lower Threshold
Output Overvoltage Trip Threshold
VPGH
With Respect to Error Comparator
Threshold of 0.8 V
−
−
VPGL
With Respect to Error Comparator
Threshold of 0.8 V
−
88
−
%
%
FBOVPth
With respect to Error Comparator
Threshold of 0.8 V
113
117
121
Overvoltage Fault Propagation Delay
Output Undervoltage Trip Threshold
−
FB forced 2% above trip threshold
−
1.5
68
−
ms
FBUVPth
With respect to Error Comparator
Threshold of 0.8 V
63
73
%
Output Undervoltage Protection Blanking
Time
UVPT
(Note 3)
−
16/fsw
−
s
blk
VREF OUTPUT
Reference Voltage
V
ref
T = 25°C
T = −40 to 85°C
A
0.796
0.792
0.8
−
0.804
0.808
V
A
Reference Load Regulation
Sinking Current
DV
Ivref = 0 to 100 mA
−
−
−
4.0
mV
ref
Isink_VREF
Vref rises 10%
20
−
mA
CURRENT LIMIT
Current Limit Threshold
V
V
= 0.4 V
72
80
88
mV
V
((CS+)−(CS−))
ILIM
ILIM Setting Range
Range
(Note 3)
−
−
0.8
ILIM
3. Guaranteed by design, not tested in production.
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NCP5215
ELECTRICAL CHARACTERISTICS (continued) (V = 5.0 V, V = 12 V, F
= 5.0 V, Fsw = 300 kHz, T = −40°C to 85°C, unless
A
CC
IN
SET
otherwise noted)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
THERMAL SHUTDOWN
Thermal Shutdown
Tsd
(Note 4)
(Note 4)
−
−
150
30
−
−
°C
°C
Thermal Shutdown Hysteresis
Tsdhys
OSCILLATOR
Operation Frequency
Fsw
FSET pin open loop (T = 25°C)
160
200
240
kHz
kHz
A
Pull high FSET pin (T = 25°C)
262.5
255
300
−
337.5
345
A
(T = −40°C to 85°C)
A
Pull low FSET pin (T = 25°C)
340
400
460
kHz
A
SOFT−START
Soft−Start Source Current
I
−
3.0
4.0
0.9
5.0
mA
SS
Soft−Start Complete Threshold
V
SSTh
(Note 4)
−
−
V
SWITCHING REGULATORS
Main Ramp Amplitude Voltage
Vramp
Dmax
V
IN
V
IN
V
IN
V
IN
= 5.0 V (Note 4)
= 5.0 V
−
−
−
−
1.25
92
−
−
−
−
V
%
%
%
Maximum Duty Cycle
= 12 V
48
= 24 V
27
GATE DRIVERS
TG Gate Pull−HIGH Resistance
R
, R
, R
V
V
−V
−V
TG SWN
= 5.0 V,
= 4.0 V
−
−
1.5
1.5
4.0
4.0
W
W
H_TG1
H_TG2
BST SWN
TG Gate Pull−LOW Resistance
R
V
−V
−V
TG SWN
= 5.0 V,
= 1.0 V
L_TG1
L_TG2
BST SWN
V
BG Gate Pull−HIGH Resistance
BG Gate Pull−LOW Resistance
Dead Time
R
, R
, R
V
V
= 5.0 V, V = 4.0 V
−
−
−
−
1.5
0.5
42
4.0
1.5
−
W
W
H_BG1
H_BG2
CCP
CCP
BG
R
= 5.0 V, V = 1.0 V
BG
L_BG1
L_BG2
T
LH
HL
BG Falling to TG Rising
TG Falling to BG Rising
ns
T
34
−
DIFFERENTIAL CURRENT ERROR AMPLIFIER
Input Bias Current
CS−IIB
−
Refer to AGND
(Note 4)
−200
−
−
−
−
−
200
3.0
1.0
1.0
nA
V
CS+ to CS− Input Signal Range
Output Voltage Swing
VCS_MAX
VOS_DRP
Ioffset_DRP
0.6
V
Offset Current at VDRP
(CS+)−(CS−) = 0 V, no connection
−1.0
mA
from VDRP pin to VREF
[(CS+)−(CS−)] to VDRP Gain
Gain_CS
((V_VDRP−Vref)/
((CS+)−(CS−)))
(CS+)−(CS−) = 20 mV
2.35
2.4
2.6
2.85
2.9
V/V
Internal Droop Resistance
R
DRP
From V
to V
REF
2.65
kW
DRP
4. Guaranteed by design, not tested in production.
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NCP5215
ELECTRICAL CHARACTERISTICS (continued) (V = 5.0 V, V = 12 V, F
= 5.0 V, Fsw = 300 kHz, T = −40°C to 85°C, unless
A
CC
IN
SET
otherwise noted)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
VOLTAGE ERROR AMPLIFIER
DC Gain
GAIN_VEA
Ft_VEA
(Note 5)
(Note 5)
(Note 5)
−
−
−
80
13
−
−
−
dB
Unity Gain Bandwidth
Slew Rate
MHz
V/ms
SR_VEA
1.0
(COMP PIN TO GND = 100 pF)
Inverting Input Current
Output Voltage Swing
Source Current
I
, I
V
= 0.8 V
−
−
−
0.5
3.0
−
mA
V
INV1 INV2
INV
VOS_EA
−
1.0
2.0
1.5
Isource_EA
Isink_EA
COMP = 3.0 V
COMP = 1.0 V
4.0
2.0
mA
mA
Sink Current
−
CONTROL SECTION
VEN1, VEN2 Threshold High
V
, V
−
−
−
1.4
−
−
−
−
−
V
V
EN1_H EN2_H
VEN1, VEN2 Threshold Low
VEN1, VEN2 Source Current
V
I
, V
0.5
0.5
EN1_L EN2_L
,
−
mA
EN1_SOURCE
I
EN2_SOURCE
VEN1, VEN2 Sink Current
I
,
−
−
−
0.5
mA
EN1_SINK
I
EN2_SINK
VFPWM# Threshold High
VFPWM# Threshold Low
VFPWM# Source Current
VFPWM# Sink Current
V
−
−
−
−
1.4
−
−
−
−
V
V
FPWM_H
V
0.5
0.5
0.5
−
FPWM_L
FPWM_SOURCE
I
−
−
mA
mA
W
I
−
−
FPWM_SINK
PGOOD Pin ON Resistance
PGOOD Pin OFF Current
PGOOD_R
I_PGOOD = 5.0 mA
−
25
−
PGOOD_LK
−
−
1.0
mA
OUTPUT DISCHARGE MODE
Output Discharge On−Resistance
R
−
−
−
12
−
W
discharge
System Restart Threshold of the Output
Voltage
Vth_SRST
0.2
0.3
0.4
V
TRE OFFSET
TRESET Offset Current
I
−
3.0
4.0
5.0
mA
TRE
5. Guaranteed by design, not tested in production.
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7
NCP5215
TYPICAL OPERATING CHARACTERISTICS
0.803
0.802
0.801
0.8
306
304
302
300
298
296
294
0.799
0.798
0.797
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 2. Reference Voltage vs. Ambient
Temperature
Figure 3. Switching Frequency vs. Ambient
Temperature
2.9
4.3
4.2
4.1
4
2.8
2.7
2.6
2.5
2.4
2.3
3.9
3.8
3.7
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 4. Soft−Start Current vs. Ambient
Figure 5. VDRP Gain vs. Ambient Temperature
Temperature
2.9
2.8
2.7
2.6
2.5
2.4
2.3
4.3
4.2
4.1
4
3.9
3.8
3.7
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 6. Internal Droop Resistance vs.
Ambient Temperature
Figure 7. TRESET Offset Current vs. Ambient
Temperature
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NCP5215
TYPICAL OPERATING CHARACTERISTICS
1.1
1.09
1.08
1.07
1.06
1.05
1.54
1.52
1.5
1.48
1.46
1.44
1.42
1.4
V
= 20 V, PS
V
= 20 V, PS
IN
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 12 V, PS
V
IN
V
IN
V
IN
V
IN
V
IN
= 12 V, PS
1.04
1.03
1.02
= 9 V, PS
= 9 V, PS
= 20 V, FPWM
= 12 V, FPWM
= 9 V, FPWM
= 20 V, FPWM
= 12 V, FPWM
= 9 V, FPWM
1.38
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
I , OUTPUT CURRENT (A)
O
I , OUTPUT CURRENT (A)
O
Figure 8. Output Voltage vs. Output Current
(VO = 1.5 V, without AVP Function)
Figure 9. Output Voltage vs. Output Current (Vo
= 1.05 V, Without AVP Function)
1.54
1.52
1.5
1.1
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
V
= 20 V, PS
V
= 20 V, PS
IN
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 12 V, PS
V
IN
V
IN
V
IN
V
IN
V
IN
= 12 V, PS
= 9 V, PS
= 9 V, PS
= 20 V, FPWM
= 12 V, FPWM
= 9 V, FPWM
= 20 V, FPWM
= 12 V, FPWM
= 9 V, FPWM
1.48
1.46
1.44
1.42
1.4
1.38
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
I , OUTPUT CURRENT (A)
O
I , OUTPUT CURRENT (A)
O
Figure 10. Output Voltage vs. Output Current
(VO = 1.5 V, with AVP Function)
Figure 11. Output Voltage vs. Output Current
(VO = 1.05 V, with AVP Function)
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
V
= 20 V, PS
V
= 20 V, PS
IN
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 12 V, PS
V
IN
V
IN
V
IN
V
IN
V
IN
= 12 V, PS
= 9 V, PS
= 9 V, PS
= 20 V, FPWM
= 12 V, FPWM
= 9 V, FPWM
= 20 V, FPWM
= 12 V, FPWM
= 9 V, FPWM
0
0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
I , OUTPUT CURRENT (A)
O
I , OUTPUT CURRENT (A)
O
Figure 12. Switching Frequency vs. Output
Current (VO = 1.5 V)
Figure 13. Switching Frequency vs. Output
Current (VO = 1.05 V)
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NCP5215
TYPICAL OPERATING CHARACTERISTICS
100
100
80
60
40
20
0
12 V, PS
12 V, PS
9 V, PS
V
= 20 V, PS
V
IN
= 20 V, PS
IN
9 V, PS
80
20 V, FPWM
12 V, FPWM
20 V, FPWM
60
12 V, FPWM
40
20
0
9 V, FPWM
9 V, FPWM
0.01
0.1
1
10
0.01
0.1
1
10
I , OUTPUT CURRENT (A)
O
I , OUTPUT CURRENT (A)
O
Figure 14. Efficiency vs. Output Current
(VO = 1.5 V)
Figure 15. Efficiency vs. Output Current
(VO = 1.05 V)
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NCP5215
TYPICAL OPERATING CHARACTERISTICS
Top: Vin, Input Voltage Ripple, (100mV/div)
Top: SWN1, CH1 Switching Node Voltage, (10V/div)
Middle 1: Vo1, CH1 Output Voltage Ripple, (50mV/div)
Middle 2: SWN2, CH2 Switching Node Voltage, (10V/div)
Bottom: Vo2, CH2 Output Voltage Ripple, (50mV/div)
Time: 2ms/div
Middle: SWN1, CH1 Switching Node Voltage, (10V/div)
Bottom: SWN2, CH2 Switching Node Voltage, (10V/div)
Time: 2ms/div
Figure 16. Input Voltage Ripple with
Interleaved Operation (VO1 = 1.5 V, IO1 = 4 A,
VO2 = 1.05 V, IO2 = 6 A)
Figure 17. Output Voltage Ripple with
Interleaved Operation (VO1 = 1.5 V, IO1 = 4 A,
VO2 = 1.05 V, IO2 = 6 A)
Top: EN1, CH1 Enable Signal, (5V/div)
Top: EN2, CH2 Enable Signal, (5V/div)
Middle 1: PGOOD1, CH1 Power Good Signal, (5V/div)
Middle 2: SWN1, CH1 Switching Node Voltage, (10V/div)
Middle 1: PGOOD2, CH2 Power Good Signal, (5V/div)
Middle 2: SWN2, CH2 Switching Node Voltage, (10V/div)
Bottom: V 1, CH1 Output Voltage, (1V/div)
Bottom: V 2, CH2 Output Voltage, (1V/div)
O
O
Time: 200ms/div
Time: 200ms/div
Figure 19. Powerup Operation (VO2 = 1.05 V,
Figure 18. Powerup Operation (VO1 = 1.5 V,
IO1 = 4 A)
IO2 = 6 A)
Top: EN1, CH1 Enable Signal, (5V/div)
Middle 1: PGOOD1, CH1 Power Good Signal, (5V/div)
Middle 2: SWN1, CH1 Switching Node Voltage, (10V/div)
Top: EN2, CH2 Enable Signal, (5V/div)
Middle 1: PGOOD2, CH2 Power Good Signal, (5V/div)
Middle 2: SWN2, CH2 Switching Node Voltage, (10V/div)
Bottom: Vo2, CH2 Output Voltage, (1V/div)
Time: 5ms/div
Bottom: V 1, CH1 Output Voltage, (1V/div)
O
Time: 5ms/div
Figure 20. Powerdown Operation (VO1 = 1.5 V,
Figure 21. Powerdown Operation
IO1 = 0 A, FPWM)
(VO2 = 1.05 V, IO2 = 0 A, FPWM)
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NCP5215
TYPICAL OPERATING CHARACTERISTICS
Top: Vo1, CH1 Output Voltage Ripple, (50mV/div)
Top: Vo2, CH2 Output Voltage Ripple, (50mV/div)
Middle: Io2, CH2 Output Current, (5A/div)
Bottom: SWN2, CH2 Switching Node Voltage, (10V/div)
Time: 20ms/div
Middle: Io1, CH1 Output Current, (5A/div)
Bottom: SWN1, CH1 Switching Node Voltage, (10V/div)
Time: 20ms/div
Figure 22. Load Transient Response with
Figure 23. Load Transient Response with
FPWM Operation (VO1 = 1.5 V,
FPWM Operation (VO2 = 1.05 V, IO2 =
IO1 = 0 A−4 A−0 A)
0 A−6 A−0 A)
Top: Vo1, CH1 Output Voltage Ripple, (50mV/div)
Middle: Io1, CH1 Output Current, (5A/div)
Bottom: SWN1, CH1 Switching Node Voltage, (10V/div)
Time: 50ms/div
Top: Vo2, CH2 Output Voltage Ripple, (50mV/div)
Middle: Io2, CH2 Output Current, (5A/div)
Bottom: SWN2, CH2 Switching Node Voltage, (10V/div)
Time: 50ms/div
Figure 24. Load Transient Response with
Figure 25. Load Transient Response with
Skip−Mode Operation (VO1 = 1.5 V, IO1 =
0.1 A−4 A−0.1 A)
Skip−Mode Operation (VO2 = 1.05 V, IO2 =
0.1 A−6 A−0.1 A)
Top: FPWM#, FPWM# Signal, (5V/div)
Top: FPWM#, FPWM# Signal, (5V/div)
Middle 1: Vo1, CH1 Output Voltage Ripple, (50mV/div)
Middle 2: iL1, CH1 Inductor Current, (5A/div)
Bottom: SWN1, CH1 Switching Node Voltage, (10V/div)
Time: 50ms/div
Middle 1: Vo2, CH2 Output Voltage Ripple, (50mV/div)
Middle 2: iL2, CH2 Inductor Current, (5A/div)
Bottom: SWN2, CH2 Switching Node Voltage, (10V/div)
Time: 50ms/div
Figure 26. On−Line Mode−Changing Operation
Figure 27. On−Line Mode−Changing Operation
(VO1 = 1.5 V, IO1 = 0.2 A, FPWM−Skip
Mode−FPWM)
(VO2 = 1.05 V, IO2 = 0.2 A, FPWM−Skip
Mode−FPWM)
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NCP5215
OPERATION DESCRIPTION
1.2MHz
General
The
NCP5215,
a
high−efficiency
and
PWM1
Fast
fast−transient−response dual−channel buck controller,
provides a multifunctional power solution for notebook
power system. 180° interleaved operation function
between the two channels has capabilities of reducing the
common input capacitor requirement and improving noise
immunity. Adaptive−Voltage−Positioning (AVP) control
reduces the requirement of output filter capacitors.
Programmable power−saving operation ensures high
efficiency over entire load range. Input feedforward
voltage−mode control is employed to deal with wide input
voltage range. Transient−Response−Enhancement (TRE)
control for the both channels enables fast transient
response.
Response
CLK1
300kHz
Digital Counter & 180°
OSC
1.2MHz
Interleaved in CCM
Phase Shift
(4*F
)
SW
300kHz
CLK2
High Sampling
Rate
PWM2
1.2MHz
Figure 28. Internal Clocks in the NCP5215 as FSW
300 kHz
=
PWM Operation
The NCP5215 operates at a pin−selectable normal
operation switching frequency, allowing 200 kHz,
300 kHz, or 400 kHz. As shown in Table 1, the connection
of the pin FSET determines normal operation frequency in
continuous−conduction−mode (CCM).
Light−Load Pulse−Skipping Operation (Skip Mode)
If the skip mode is enabled by pulling high FPWM# pin,
the NCP5215 works in pulse−skipping enabled operation
(PS).
In medium and high load range, the converter still runs
in CCM, and the switching frequency is fixed as the
selected frequency. If both channels run in CCM, they
operate interleaved.
Table 1. SWITCHING FREQUENCY SELECTION
FSET Pin
Fsw (kHz)
Float
200
VCC
300
GND
400
In light load range, the converter will enter skip mode if
negative inductor current appears continuously. In the skip
mode, the bottom MOSFET will be turned off when the
inductor current is going negative. The top MOSFET’s
on−time is fixed to around 1.5 times as the on−time in
CCM. The NCP5215 continuously monitors the voltage at
FB pin and comparing to the voltage at VDRP Pin. When
the FB voltage drops below the VDRP voltage, a fixed
on−time will be initiated at the time of the next coming
high−frequency clock edge, which can be either rising edge
or falling edge. The minimum off−time is half
high−frequency cycle.
To speed up transient response and increase sampling
rate, an internal high−frequency clock is employed, which
frequency is four times of the selected normal operating
frequency. As an instance, if the FSET pin is connected to
V , the normal switching frequency is set to 300 kHz. The
CC
internal high−frequency clock is 1.2 MHz. Figure 28
shows internal clocks of the NCP5215 in this case. The
1.2MHz high−frequency clock with 50% duty−ratio
introduced to the two PWM channels. A digital circuitry
generates two interleaved 300 kHz clocks using the
1.2 MHz clock and output them to the two PWM channels
as normal operation clocks in CCM, respectively.
When the load increases and the inductor current
becomes continuous, the controller will automatically
return to fixed−frequency operation and be synchronized to
the normal operation clock.
Forced−PWM Operation (FPWM Mode)
If the FPWM# pin is pulled low, the NCP5215 works
under forced−PWM operation and thus always in CCM.
The two channels always run in selected fixed frequency
and 180° interleaved operation. In this mode, the low−side
gate−drive signal is forced to be the complement of the
high−side gate−drive signal. This mode allows reverse
inductor current, in such a way that it provides more
accurate voltage regulation and fast transient response.
During soft−start operation, the NCP5215 automatically
runs in FPWM mode regardless of the FPWM# pin’s setting
to guarantee smooth powerup.
Transient Response Enhancement (TRE)
In the skip mode, the operation of the NCP5215 is similar
to constant on−time scheme. The response time of the
controller is between half to one cycle of the
high−frequency clock. However, for a conventional
trailing−edge PWM controller in CCM, the fastest
response time is one switching cycle in the worst case. To
further improve transient response in CCM, a transient
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NCP5215
response enhancement circuitry is introduced to the
where I
is a sourcing current out the TRESET pin. A
TRE
NCP5215.
recommended value for V
is around 1.5 times of
th_TRE
In CCM operation, the controller continuously monitors
the output voltage (COMP) of the error amplifier to detect
load transient events. As shown in Figure 1, there is a
threshold voltage in each channel made in a way that a
filtered COMP signal pluses an adjustable offset voltage,
which is set by an external resistor. Once large load
transient occurs, the COMP signal is possible to exceed the
threshold and then TRE signal will be high in a short period,
which is typically around one normal switching cycle. In
this short period, the controller will be running at high
frequency and therefore has faster response. After that the
controller comes back to normal switching frequency
operation. Figure 29 shows TRE effect on a load transient
response.
peak−to−peak value of the COMP signal in CCM
operation. The higher V , the lower sensitivity to load
transient. The TRE function can be disabled by pulling
th_TRE
high the TRESET pin to V or just leaving it float.
CC
Adaptive Voltage Positioning (AVP)
For applications with fast transient currents, adaptive
voltage positioning can reduce peak−to−peak output
voltage deviations due to load transients and allow use of
a smaller output filter. Adaptive voltage positioning sets
output voltage higher than nominal at light loads, and
output voltage is allowed limited sag when the load current
is applied. Upon removal of the load, output voltage returns
no higher than the original level, allowing one output
transient peak to be canceled over a load stepup and release
cycle.
+5% x V
O
V
V
with AVP
O
without AVP
O
Figure 30. Adaptive Voltage Positioning
Figure 30 shows how AVP works. The waveform labeled
“Vo without AVP” shows output voltage waveform in a
converter without AVP. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With AVP, the
peak−to−peak excursions are cut around in half. The
controller can be configured to adjust the output voltage
based on the output current of the converter as shown in
Figure 31. In order to realize the AVP function, a resistor
Top: Vo (50mV/div), Middle: Transient signal (20V/div),
Bottom: SWN (10V/div), Time: (10us/div)
(a) TRE disabled
is connected between V
and V . During no−load
REF
DRP
conditions, the VDRP Pin voltage stays at the same voltage
level as the V . As the output current increases, the
REF
VDRP Pin voltage decreases. This causes V
according to a loadline set by the resistor.
to droop
OUT
In the NCP5215, the output current of each channel is
sensed differentially. A high gain and low offset−voltage
differential amplifier in each channel allows
low−resistance current−sensing resistor or low−DCR
inductor to be used to minimize power dissipation. For
lossless inductor current sensing as shown in Figure 31, the
sensing RC network should satisfy
Top: Vo (50mV/div), Middle: Transient signal (20V/div),
Bottom: SWN (10V/div), Time: (10us/div)
(b) TRE enabled
Figure 29. Transient Response Comparison on TRE
The internal offset voltage of the TRE threshold is set by
L
(eq. 2)
RCS CCS
+
an external resistor R
connected from the TRESET Pin
TRE
DCR
to AGND.
where DCR is a DC resistance of a inductor, and normally
is selected to be around 0.1 mF. In high accuracy
I
TRE @ RTRE
(eq. 1)
C
Vth_TRE
+
cs
4
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NCP5215
applications, to compensate measurement error caused by
temperature, an additional resistance network including a
negative−temperature−coefficient (NTC) thermistor can
If an additional current sensing resistor (R ) is employed
CS
to improve accuracy, as shown in Figure 32, the load line
resistance can be calculated by
be connected with C in parallel.
(eq. 6)
CS
RDRP_ext
VO0
R
LL + RCS Gain_CS @
@
R
DRP_int ) RDRP_ext VREF
The AVP function can be easily disabled by shorting
VDRP pin and VREF pin together.
Control Logic
The internal control logic is powered by V . Figure 33
CC
shows a power−up and powerdown timing diagram for
each channel. Figure 34 shows a state diagram for each
channel.
The NCP5215 continuously monitors V and V level
CC
IN
with an undervoltage lockout (UVLO) function. If both
and V are in operation range, and output voltage is
below 0.3 V, the converter has a soft−start after ENBL
signal goes high. The soft−start time is programmed by an
V
CC
IN
Figure 31. Programmable AVP with Lossless Inductor
Current Sensing
external capacitor C connected from the SS Pin to
SS
AGND, which can be calculated by
0.8 CSS
(eq. 7)
tSS
+
ISS
where I is a sourcing current output from the SS pin.
SS
When the ENBL goes low, or the internal fault latch is set
by over current or output undervoltage, the device operates
in soft stop and output discharge mode. The output is
discharged to GND through an internal 12 W switch
connected from the CS−/Vo pin to the PGND Pin, until the
output voltage decreases to 0.3 V. Also if restart the system
when the output voltage is still above 0.3 V, the device will
discharge the output voltage to 0.3 V first and then start
soft−start.
Figure 32. Figure 32. Programmable AVP with
Resistive Current Sensing
Overcurrent Protection (OCP)
The output voltage with AVP is
The NCP5215 protects power system if overcurrent
occurs. The current through each channel is continuously
monitored with the differential current sense. Current limit
VO + VO0 * IO @ RLL
(eq. 3)
where I is load current, no−load output voltage V is set
o
O0
threshold is related to an external voltage at the I
pin,
LIM
by the external resistor divider, that is
which is normally produced by an external resistor divider
(R and R ) connected from the V pin to AGND. The
RFO
il1
il2
REF
(eq. 4)
+ ǒ1 ) Ǔ
VO0
@ VREF
RFG
current−limit threshold for peak current is set by
R
il2 @ VREF
R
is a resistor connected between the output and the FB
FO
ILIM(Peak) + 0.2 @
(eq. 8)
pin, and R is a resistor connected between the FB Pin to
ǒ
R
Ǔ
FG
il1 ) Ril2 @ DCR
AGND. The load−line impedance R by the AVP function
is given by
LL
or
R
il2 @ VREF
(eq. 5)
RDRP_ext
ILIM(Peak) + 0.2 @
VO0
(eq. 9)
ǒ
R
Ǔ
R
LL + DCR Gain_CS @
@
il1 ) Ril2 @ RCS
R
DRP_int ) RDRP_ext VREF
If inductor current exceeds the current threshold
continuously, the top gate drive will be turned off
cycle−by−cycle. In the meanwhile, an internal fault timer
will be triggered to count normal operation clock. After 16
continuous clock pulses, if the fault still exists the part
latches off, both the top gate drive and the bottom gate drive
where DCR is DC resistance of the inductor, Gain_CS is a
gain from [(CS+)−(CS−)] to (VDRP−VREF), R is a
DRP_int
internal resistance connected between the output reference
and the VDRP Pin, R is a external resistance
DRP_ext
connected between the output reference and the VDRP pin.
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NCP5215
are turned off and their outputs are float. The fault remains
voltage level. If the output voltage is below this threshold,
a UV fault is set. If an OV protection is set before, the
bottom gate drive is forced high. If no OV protection set,
an internal fault timer will be triggered to count normal
operation clock. After 16 continuous clock pulses, if the
fault still exists the part latches off, both the top gate drive
and the bottom gate drive are turned off and their outputs
are float. The fault remains set until the system has
shutdown and re−applied power or the enable input signal
to the regulator controller has toggled states.
set until the system has shutdown and re−applied power or
the enable input signal to the regulator controller has
toggled states.
Overvoltage Protection (OVP)
An OVP circuit monitors the output voltages to prevent
from over voltage. OVP limit is typically 117% of the
nominal output voltage level. If the output voltage is above
this threshold, an OV fault is set, the top gate drive is turned
OFF, and then the bottom gate drive is latched ON to
discharge the output. The fault remains set until the system
has shutdown and re−applied power or the enable input
signal to the regulator controller has toggled states.
Thermal Protection
The NCP5215 has a thermal shutdown protection to
protect the device from overheating when the die
temperature exceeds 150°C. Once the thermal protection is
Undervoltage Protection (UVP)
A UVP circuit monitors the output voltages to detect
undervoltage. UVP limit is 68% of the nominal output
triggered, the fault state can be ended by re−applying V
,
CC
V , or ENBL when the temperature drops down below
IN
120°C.
VCCA
t
SFT_START
VIN
ENBL
Vo
PGOOD
32 Cycles
VCCA goes
above 4.4V to
enable the IC
PGOOD Goes High
ENBL goes high. Vo is enabled but not
actived until VIN goes above 3.5V.
Soft−Start
Completed
PGOOD Goes Low
Figure 33. Powerup and Powerdown Timing Diagram per Channel
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NCP5215
Power Up
Re−apply
VCC or VIN or ENBL
VCC > 4.25V ?
& VIN > 4.0V ?
& ENBL= HIGH ?
yes
no
& no OV
Vo Discharge
Mode
TG Latch Off
BG Latch On
Vo < 0.3V
yes
OV
VCC < 4.0V
or VIN < 3.5V
OVP
or ENBL = LOW
OV
Soft Start and
Normal Operation
OC
UV
TG & BG
Latch Off
OCP
UVP
Vo Discharge
Mode
Figure 34. State Diagram per Channel
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NCP5215
Vin
M1
M3
M2
M4
L1
2.2uH
L2
1.5uH
Vo1
Cin1 Cin2
10uF 10uF
Vo2
1.5V / 5A
1.05V/6A
Co2 Co21
10uF
Co11 Co1
220uF
Cs1
Cs2
10uF
220uF*2
0.1uF
0.1uF
PGND
PGND
PGND
5VCC
Db1
5VCC
Db2
Cpf1
1uF
Cpf2
1uF
BAT54WT1
BAT54WT1
Cb1
Cb2
30 29 28 27 26 25 24 23 22 21
0.1uF
0.1uF
TG1
TG2
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
SWN1
SWN2
CS2+
CS1+
VREF
VREF
CS1−/Vo1
ILIM1
CS2−/Vo2
ILIM2
Ril11
Ril12
Ril22
Ril21
100k
Rdp2
100k
Rdp1
82k
Cdp1
36k
Cdp2
NCP5215MNR2G
VDRP1
FB1
VDRP2
FB2
47pF
2k
47pF
3k
R11
R21
13k
INV1
INV2
10k
COMP1
TRESET1
COMP2
TRESET2
1
2
3
4
5
6
7
8
9
10
5VCC
Rcf
Cref
1uF
Css2
Ccf
20
4.7nF
1uF
PGND
Figure 35. Typical Application Schematic Diagram
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NCP5215
Table 2. BILL OF MATERIALS FOR THE TYPICAL APPLICATION
Part
Reference
Item
PCS
Description
Value
Package
QFN40
SO8
Part Number
NCP5215MNR2G
NTMS4705N
Manufacturer
ON Semiconductor
ON Semiconductor
1
2
1
4
IC1
NCP5215
M1, M2,
M3, M4
Power MOSFET 30 V, 12 A,
Single N−Channel SO−8
3
4
2
2
Db1, Db2
Schottky Diode, 30V
SC70
0603
BAT54WT1G
ON Semiconductor
Panasonic
TDK
Cdp1,
Cdp2
MLCC Cap 50V, $5%, Char:
COG
47pF
68pF
ECJ1VB1H470J
C1608C0G1H470J
ECJ1VB1H680J
C1608C0G1H680J
ECJ1VC1H221J
C1608C0G1H221J
ECJ1VC1H821J
C1608C0G1H821J
ECJ1VC1H102J
C1608C0G1H102J
ECJ1VB1H472K
C1608X7R1H472K
ECJ1VB1H153K
C1608X7R1H153K
ECJ1VB1C104K
C1608X7R1H104K
ECJ2FB1E105K
C3216X5R1H105K
ECJ3YB1C106M
C3216X7R1C106M
C4532X7R1E106M
5
6
2
2
1
1
2
1
4
4
2
C11, C22
C12, C22
C23
MLCC Cap 50V, $5%, Char:
COG
0603
0603
0603
0603
0603
0603
0603
0805
0805
Panasonic
TDK
MLCC Cap 50V, $5%, Char:
COG
220pF
820pF
1000pF
4700pF
15nF
Panasonic
TDK
7
MLCC Cap 50V, $5%, Char:
COG
Panasonic
TDK
8
C13
MLCC Cap 50V, $5%, Char:
COG
Panasonic
TDK
9
CSS1,
CSS2
MLCC Cap 50V, $10%, Char:
X7R
Panasonic
TDK
10
11
12
13
CIF
MLCC Cap 50V, $10%, Char:
X7R
Panasonic
TDK
Cb1, Cb2,
Cs1, Cs2
MLCC Cap 16V, $10%, Char:
X7R
0.1mF
1mF
Panasonic
TDK
Ccf, Cpf1,
Cpf2, Cref
MLCC Cap 25V, $10%, Char:
X5R
Panasonic
TDK
Co11,
Co21
MLCC Cap 10V, $20%, Char:
X7R
10mF
Panasonic
TDK
14
15
2
3
CIN1,
CIN2
MLCC Cap 25V, $20%, Char:
X7R
10mF
1812
7343
TDK
Co1, Co2
(x2)
SP−Cap/Polymer Aluminum Ca-
pacitors, 22 mF, 2 V, ESR =
12 mW
220mF
EEFUD0D221XR
Panasonic
16
17
18
19
20
21
22
23
2
1
1
1
1
1
1
1
Rcf, Rif
R13
Thick Film Chip Resistors,
20W
750W
910W
2kW
0603
0603
0603
0603
0603
0603
0603
0603
ERJ3EKF20R0V
ERJ3EKF7500V
ERJ3EKF9100V
ERJ3EKF2001V
ERJ3EKF3001V
ERJ3EKF3601V
ERJ3EKF4301V
ERJ3EKF1002V
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Power Rating 0.1W, Tol: $1%
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
R23
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
Rdp1
Rdp2
RS1
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
3kW
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
3.6kW
4.3kW
10kW
RS2
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
R11
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
http://onsemi.com
19
NCP5215
Part
Reference
Item
PCS
Description
Value
Package
Part Number
Manufacturer
24
1
R14
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
11kW
0603
ERJ3EKF1102V
Panasonic
25
26
27
28
29
30
31
32
33
1
2
1
1
2
2
1
1
1
R21
Thick Film Chip Resistors,
13kW
36kW
0603
0603
0603
0603
0603
0603
0603
ERJ3EKF1302V
ERJ3EKF3602V
ERJ3EKF7502V
ERJ3EKF8202V
ERJ3EKF1003V
ERJ3EKF2003V
ERJ3EKF3903V
PCMC104T−2R2MN
PCMC104T−1R5MN
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Cyntec
Power Rating 0.1W, Tol: $1%
R24, Ril22
R12
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
75kW
Ril12
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
82kW
Ril11,
Ril21
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
100kW
200kW
390kW
2.2mH
1.5mH
R22, Rt2
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
Rt1
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
L1
Power Choke Coil, DCR =
7.0mW, IDC = 12A, ISAT = 27A
L2
Power Choke Coil, DCR =
4.2mW, IDC = 16A, ISAT = 33A
Cyntec
http://onsemi.com
20
NCP5215
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
MN SUFFIX
CASE 488AR−01
ISSUE A
NOTES:
D
A B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
LOCATION
E
MILLIMETERS
DIM MIN
MAX
1.00
0.05
2X
0.15
C
A
A1
A3
b
0.80
0.00
0.20 REF
0.18
6.00 BSC
TOP VIEW
0.30
2X
0.15
C
D
D2
E
E2
e
L
K
4.00
6.00 BSC
4.00
0.50 BSC
0.30
0.20
4.20
(A3)
0.10
C
C
4.20
A
0.50
−−−
40X
0.08
SIDE VIEW
D2
A1
SEATING
PLANE
SOLDERING FOOTPRINT*
C
6.30
4.20
L
K
40X
11
20
40X
21
40X
10
0.65
EXPOSED PAD
1
E2
40X b
4.20 6.30
1
30
0.10
0.05
C
A B
40
31
C
36X
e
BOTTOM VIEW
40X
0.30
36X
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5215/D
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