NCP5369NMNTXG [ONSEMI]

带有高压侧和低压侧 MOSFET 的集成驱动器;


型号：	NCP5369NMNTXG
厂家：	ONSEMI
描述：	带有高压侧和低压侧 MOSFET 的集成驱动器驱动高压驱动器
文件：	总8页 (文件大小：181K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP5369N

Integrated Driver and

MOSFET

The NCP5369N integrates a MOSFET driver, high−side MOSFET

and low−side MOSFET into a 6 mm x 6 mm 40−pin QFN package.

The driver and MOSFETs have been optimized for high−current

DC−DC buck power conversion applications. The NCP5369N

integrated solution greatly reduces package parasitics and board space

compared to a discrete component solution.

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MARKING

DIAGRAM

Features

• Capable of Switching Frequencies Up to 1 MHz

• Capable of Output Currents Up to 35 A

• Internal Bootstrap Diode

NCP5369N

AWLYYWWG

QFN40

MN SUFFIX

CASE 485AZ

• Zero Current Detection

• Undervoltage Lockout

• Internal Thermal Warning / Thermal Shutdown

• These are Pb−Free Devices

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

5 V

12−20 V

Thermal

Warning

ORDERING INFORMATION

THWN

VIN

BOOT

†

Device

Package

Shipping

VCIN

NCP5369NMNTXG QFN40

2500/Tape & Reel

SMOD

DISB#

GL Control

(Pb−Free)

PHASE

VSWH

Output

Disable

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Vout

PWM

CGND

PGND

Figure 1. Application Schematic

Publication Order Number:

August, 2014 − Rev. 6

NCP5369N/D

NCP5369N

BOOT

VIN

VCIN

PWM

PHASE

VSWH

Logic

SMOD

Anti−Cross

Conduction

VCIN

PGND

DISB#

UVLO

THWN/THDN

THWN

Figure 2. Simplified Block Diagram

VIN 11

PWM

VIN

FLAG42

CGND

FLAG41

39 DISB#

38 THWN

VIN 14

CGND

VSWH

PGND

36 GL

35 VSWH

PGND 17

PGND

33 VSWH

VSWH

FLAG43

PGND 19

PGND 20

VSWH

Figure 3. Pin Connections (Top View)

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NCP5369N

Table 1. PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

SMOD

VCIN

Description

GL Control

Control Input Voltage

No Connect

3, 8

BOOT

CGND

Bootstrap Voltage

5, 37, FLAG 41

Control Signal Ground

High Side FET Gate Access

PHASE

Provides a return path for the high side driver of the internal IC. Place a high frequency

ceramic capacitor of 0.1 mF to 1.0 mF from this pin to BOOT pin.

9−14, FLAG 42

VIN

Input Voltage

15, 29−35,

FLAG 43

VSWH

Switch Node Output

16−28

PGND

Power Ground

Low Side FET Gate Access

Thermal Warning

THWN

DISB#

PWM

Output Disable Pin

PWM Drive Logic

Table 2. ABSOLUTE MAXIMUM RATINGS

Symbol

VCIN

VIN

Pin Name / Rating

Control Input Voltage

Min

Max

Unit

−0.3

Power Input Voltage

Bootstrap Voltage

BOOT

−0.3 V wrt/VSWH (pin 35)

35 V wrt/PGND

40 V < 50 ns wrt/PGND

7 V wrt/GH

7.7 V < 50 ns wrt/GH

VSWH

Switch Node Output

−5 V

35 V

−10 V < 200 ns

40 V < 50 ns

High Side Gate Access

−0.3 V wrt/VSWH (pin 35)

7 V wrt/VSWH (pin 35)

7.7 V < 50 ns wrt/VSWH (pin 35)

SMOD

PWM

GL Control

−0.3

6.5

PWM Drive Logic

DISB#

THWN

Output Disable

Thermal Warning

Junction Temperature

Storage Temperature

Thermal Resistance, High−Side FET

Thermal Resistance, Low−Side FET

Moisture Sensitivity Level

−55 to 150

°C

−55 to 150

°C

°C/W

JPCB

MSL

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

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NCP5369N

Table 3. OPERATING RANGES

Rating

Symbol

VCIN

VIN

Min

4.5

Typ

Max

5.5

Unit

Control Input Voltage

Input Voltage

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

ELECTRICAL CHARACTERISTICS (Note 1) (VCIN = 5 V, VIN = 12 V, T = −10°C to +100°C, unless otherwise noted)

Parameter

SUPPLY CURRENT

Symbol

Condition

Min

Typ

Max

Unit

VCIN Current (normal mode)

−

DISB# = 5 V, PWM = OSC,

FSW = 400 kHz

VCIN Current (shutdown mode)

UNDERVOLTAGE LOCKOUT

UVLO Startup

DISB# = GND

−

3.8

4.35

200

4.5

UVLO Hysteresis

150

250

BOOTSTRAP DIODE

Forward Voltage

−

VCIN = 5 V, forward bias current = 2 mA

0.1

0.4

0.6

PWM INPUT

PWM Input Voltage High

PWM Input Voltage Mid−State

PWM Input Voltage Low

PWM Input Leakage

3.7

1.3

−

PWM_HI

3.0

0.7

PWM_MID

−

PWM_LO

−6

250

Zero Cross Detect Threshold

ZCD Blanking Timer

OUTPUT DISABLE

Output Disable Input Voltage High

Output Disable Input Voltage Low

Output Disable Hysteresis

Output Disable Propagation Delay

SMOD PIN INPUT

2.0

−

0.8

−

DISB#_HI

DISB#_LO

−

500

−

SMOD

2.0

−

SMOD_HI

SMOD

−

0.8

SMOD_LO

THERMAL WARNING/SHUTDOWN

Thermal Warning Temperature

Thermal Warning Hysteresis

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

150

°C

180

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low

duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

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NCP5369N

APPLICATIONS INFORMATION

Theory of Operation

PWM

SMOD

OFF

The NCP5369N is an integrated driver and MOSFET

module designed for use in a synchronous buck converter

topology. A single PWM input signal is all that is required

to properly drive the high−side and low−side MOSFETs.

Do not care

OFF

OFF, after blanking time

and ZCD is triggered

Low−Side Driver

The low−side driver is designed to drive

ground−referenced low R N−Channel MOSFET. The

OFF

OFF, immediately

DS(on)

voltage rail for the low−side driver is internally connected to

VCIN and PGND.

With the above logic table, the NCP5369N supports two

types of PWM controllers. The first type has tri−state PWM

output, including NCP81102, NCP81119, NCP6153,

NCP6133, NCP6151 and NCP6131. The other type has

2−state PWM output and SMOD output with its own zero

current detection, including NCP81105, NCP81001,

NCP81111 and NCP4200 family.

High−Side Driver

The high−side driver is designed to drive a floating low

RDS(on) N−channel MOSFET. The gate voltage for the

high side driver is developed by a bootstrap circuit

referenced to Switch Node (VSWH) pin.

The bootstrap circuit is comprised of the internal diode

and an external bootstrap capacitor. When the NCP5369N is

starting up, the VSWH pin is at ground, so the bootstrap

capacitor will charge up to VCIN through the bootstrap

diode See Figure 1. When the PWM input goes high, the

high−side driver will begin to turn on the high−side

MOSFET using the stored charge of the bootstrap capacitor.

As the high−side MOSFET turns on, the VSWH pin will

rise. When the high−side MOSFET is fully on, the switch

node will be at 12 V, and the BST pin will be at 5 V plus the

charge of the bootstrap capacitor (approaching 17 V).

The bootstrap capacitor is recharged when the switch

node goes low during the next cycle.

Safety Timer and Overlap Protection Circuit

It is very important that MOSFETs in a synchronous buck

regulator do not both conduct at the same time. Excessive

shoot−through or cross conduction can damage the

MOSFETs, and even a small amount of cross conduction

will cause a decrease in the power conversion efficiency.

The NCP5369N prevents cross conduction by monitoring

the status of the MOSFETs and applying the appropriate

amount of “dead−time” or the time between the turn off of

one MOSFET and the turn on of the other MOSFET.

When the PWM input pin goes high, the gate of the

low−side MOSFET (GL pin) will go low after a propagation

delay (tpdlGL). The time it takes for the low−side MOSFET

to turn off (tfGL) is dependent on the total charge on the

low−side MOSFET gate. The NCP5369N monitors the gate

voltage of both MOSFETs and the switchnode voltage to

determine the conduction status of the MOSFETs. Once the

low−side MOSFET is turned off an internal timer will delay

(tpdhGH) the turn on of the high−side MOSFET.

Zero Current Detect

When PWM is set high, DRVH will be set high after the

adaptive non−overlap delay. When PWM is set low, DRVL

will be set high after the adaptive non−overlap delay.

When PWM is set to the mid state, DRVH will be set low,

and after the adaptive non−overlap delay, DRVL will be set

high. DRVL remains high during the ZCD blanking time.

When the timer has expired, the VSWH pin will be

monitored for zero cross detection. After the detection,

DRVL will be set low. The zero current detection timing is

illustrated in Figure 4.

The threshold on VSWH to determine zero current

undergoes an auto−calibration cycle every time DISB# is

brought from low to high. This auto−calibration cycle

typically takes 55 ms to complete.

Likewise, when the PWM input pin goes low, the gate of

the high−side MOSFET (GH pin) will go low after the

propagation delay (tpdlGH). The time to turn off the

high−side MOSFET (tfGH) is dependent on the total gate

charge of the high−side MOSFET. A timer will be triggered

once the high−side MOSFET has stopped conducting, to

delay (tpdhGL) the turn on of the low−side MOSFET.

Thermal Warning / Thermal Shutdown

When the temperature of the driver reaches 150°C, the

THWN pin will be pulled low indicating a thermal warning.

At this point, the part continues to function normally. When

the temperature drops below 135°C, the THWN will go high.

If the driver temperature exceeds 180°C, the part will

enter thermal shutdown and turn off both MOSFETs. Once

the temperature falls below 155°C, the part will resume

normal operation. The THWN pin has a maximum current

capability of 30 mA.

Low−side MOSFET Control

Besides the tri-state PWM input, the SMOD can controls

the low-side MOSFET on/off without any delay. This allows

controller implements advanced features of immediate OVP

protection and body−diode braking. The SMOD timing is

illustrated in Figure 5. The combination of tri−state PWM

and SMOD control is listed in the table below.

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NCP5369N

Power Supply Decoupling

Bootstrap Circuit

The NCP5369N can source and sink relatively large

current to the gate pins of the MOSFETs. In order to

maintain a constant and stable supply voltage (VCIN) a low

ESR capacitor should be placed near the power and ground

pins. A 1 mF to 4.7 mF multi layer ceramic capacitor

(MLCC) is usually sufficient.

The bootstrap circuit uses a charge storage capacitor

(C ) and the internal diode. The bootstrap capacitor must

BST

have a voltage rating that is able to withstand twice the

maximum supply voltage. A minimum 50 V rating is

recommended. A bootstrap capacitance greater than 100 nF

and a minimum 50 V rating is recommended. A good quality

ceramic capacitor should be used.

PWM

ZCD

Blanking

timer

Blanking

timer

Blanking

timer

Figure 4. Zero Current Detection

PWM

SMOD

Figure 5. SMOD Control

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFN40 6x6, 0.5P

CASE 485AZ−01

ISSUE O

DATE 09 JAN 2009

SCALE 2:1

A B

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

PIN ONE

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30mm FROM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. POSITIONAL TOLERANCE APPLIES TO ALL

THREE EXPOSED PADS.

LOCATION

DETAIL A

ALTERNATE

CONSTRUCTIONS

MILLIMETERS

0.15

DIM MIN

MAX

1.00

0.05

EXPOSED Cu

MOLD CMPD

0.80

−−−

0.20 REF

0.18

TOP VIEW

0.15

0.30

DETAIL B

(A3)

6.00 BSC

0.10

DETAIL B

2.30

1.40

2.50

1.60

ALTERNATE

43X

CONSTRUCTION

6.00 BSC

4.30

1.90

4.50

2.10

0.08

SIDE VIEW

SEATING

PLANE

NOTE 4

0.50 BSC

2.20 BSC

0.20

0.30

−−−

0.50

0.15

0.10

C A B

NOTE 5

40X L

DETAIL A

GENERIC

MARKING DIAGRAM*

XXXXXXXX

AWLYYWWG

40X b

e/2

XXXXX = Specific Device Code

0.10

= Assembly Location

= Wafer Lot

NOTE 3

0.05

BOTTOM VIEW

= Year

SOLDERING FOOTPRINT

= Work Week

= Pb−Free Package

6.30

4.56

2.56

40X

0.63

*This information is generic. Please refer

to device data sheet for actual part

marking.

1.66

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

2.16

4.56

6.30

2.16

40X

0.30

PKG

OUTLINE

0.50

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON38217E

QFN40 6x6, 0.5P

PAGE 1 OF 1

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

NCP5369NMNTXG [ONSEMI]

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