NCP5424A [ONSEMI]
Dual Synchronous Buck Controller;
| 型号： | NCP5424A |
| 厂家： | 
ONSEMI |
| 描述： | Dual Synchronous Buck Controller |
| 文件： | 总20页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP5424A
Dual Synchronous
Buck Controller with Input
Current Sharing
The NCP5424A is a flexible dual N−channel synchronous buck
2
controller utilizing V
control for fast transient response and
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excellent line and load regulation. This highly versatile controller can
be configured as a single two phase output converter that draws
programmable amounts of current from two different input voltages or
all current from one supply. The NCP5424A can also be configured as
two independent out−of−phase controllers.
SO−16
D SUFFIX
CASE 751B
16
1
Using the NCP5424A in a current sharing input configuration is
ideal for applications where more power is required than is available
from one supply, such as video cards or other plug−in boards. When
configured as a dual output controller, the output of one controller can
be divided down and used as the reference for the second controller.
This tracking capability is useful in applications such as Double Data
Rate (DDR) Memory power where the termination voltage must track
VDD.
PIN CONNECTIONS AND
MARKING DIAGRAM
1
16
GATE(H)1
GATE(L)1
GND
GATE(H)2
GATE(L)2
V
CC
BST
R
OSC
The NCP5424A provides a cycle−to−cycle current limit allowing
the system to handle transient overcurrent events. In addition, the
NCP5424A provides Soft Start, undervoltage lockout, and built−in
adaptive FET nonoverlap time to prevent shoot through.
IS+1
IS+2
V
V
FB−2
IS−
FB+2
V
FB1
COMP1
COMP2
Features
A
= Assembly Location
= Year
• Cycle−to−Cycle Current Limit
• Programmable Soft Start
• 100% Duty Cycle for Enhanced Transient Response
• 150 kHz to 600 kHz Programmable Frequency Operation
WL = Wafer Lot
Y
WW = Work Week
• Switching Frequency Set by Single Resistor
• Out−Of−Phase Synchronization Between the Channels Reduces the
Input Filter Requirement
ORDERING INFORMATION
Device
Package
SO−16
SO−16
Shipping
• Undervoltage Lockout
Applications
48 Units/Rail
NCP5424AD
2500 Tape & Reel
NCP5424ADR2
• Video Graphics Card
• DDR Memory
• High Current (Two−Phase) Power Supplies
• Dual Output DC−DC Converters
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
August, 2003 − Rev. 0
NCP5424A/D
NCP5424A
12 V
3.3 V
+
+
C17
220 µF
C18
220 µF
5.0 V
+
+
C2
220 µF
C1
220 µF
C6
C11
0.1 µF
1.0 µF
R1
x k
R2
x k
U1
Q1 MTD60N03
L1
V
CC
BST
Q3
MTD60N03
Q4
L2
GATE(H)1 GATE(H)2
1.3 µH/15 A
1.3 µH/15 A
C19/20/21
680 µF/
4 V
C3/4/5
680 µF/
4 V
+
+
Q2
MTD90N02
R17
4 k
GATE(L)1 GATE(L)2
MTD90N02
IS+1
IS−
IS+2
NCP5424A
C14
R3
V
FB+2
0.1 µF
x k ± 1%
COMP1
COMP2
C8
.22 µF
C13
0.01 µF
R5
V
FB1
V
FB−2
5 k ± 1%
R
GND
OSC
R4
x k ± 1%
R6
10 k ± 1%
R12
30.9 k
1.5 V @ 20 A
Figure 1. Two−Phase Buck Regulator Application, with Input Current Sharing
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2
NCP5424A
MAXIMUM RATINGS*
Rating
Value
150
Unit
°C
Operating Junction Temperature, T
J
Storage Temperature Range, T
−65 to +150
2.0
°C
S
ESD Susceptibility (Human Body Model)
Package Thermal Resistance, SO−16:
kV
Junction−to−Case, R
Junction−to−Ambient, R
28
115
°C/W
°C/W
θ
JC
θ
JA
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
230 peak
°C
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Symbol
Pin Name
V
MAX
V
MIN
I
I
SOURCE
SINK
V
IC Power Input
16 V
4.0 V
5.0 V
20 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
N/A
1.5 A peak
200 mA DC
CC
COMP1, COMP2
Compensation Capacitor for
Channel 1 or 2
1.0 mA
1.0 mA
N/A
3.5 mA
V
FB1
, V
FB+2
, V
FB−2
Voltage Feedback Input for
Channel 1 or 2
1.0 mA
BST
Power Input for GATE(H)1, 2
1.5 A peak
200 mA DC
R
Oscillator Resistor
4.0 V
20 V
−0.3 V
−0.3 V
1.0 mA
1.0 mA
OSC
GATE(H)1 GATE(H)2
High−Side FET Driver
for Channel 1 or 2
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
,
GATE(L)1 GATE(L)2
Low−Side FET Driver for
Channel 1 or 2
16 V
0 V
−0.3 V
0 V
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
,
GND
IS+1, IS+2
IS−
Ground
1.5 A peak
200 mA DC
N/A
Positive Current Sense for
Channel 1 or 2
6.0 V
6.0 V
−0.3 V
−0.3 V
1.0 mA
1.0 mA
1.0 mA
Negative Current Sense for
Channels 1 and 2
1.0 mA
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NCP5424A
ELECTRICAL CHARACTERISTICS (0°C < T < 70°C; 0°C < T < 125°C; R
= 30.9 k, C
= 0.1 µF,
COMP1,2
A
J
OSC
10.8 V < V < 13.2 V; 10.8 V < BST < 20 V, C
= C
= 1.0 nF, V
= 1.0 V; unless otherwise specified.)
CC
GATE(H)1,2
GATE(L)1,2
FB+2
Characteristic
Error Amplifier
Test Conditions
Min
Typ
Max
Unit
V
Bias Current
V
= 0 V
−
0
0.5
−
1.6
1.1
60
60
1.020
−
µA
V
FB
FBX
V
FB1(2)
Input Range
Note 2
COMP1,2 = 1.2 V to 2.5 V; V
COMP1,2 Source Current
COMP1,2 Sink Current
Reference Voltage 1(2)
COMP1,2 Max Voltage
COMP1,2 Min Voltage
Open Loop Gain
= 0.8 V
15
15
0.980
3.0
−
30
µA
µA
V
FB1(−2)
COMP1,2 = 1.2 V; V
= 1.2 V
30
FB1(−2)
COMP1 = V ; COMP2 = V
1.000
3.3
0.25
95
FB1
FB−2
V
= 0.8 V
= 1.2 V
V
FB1(−2)
FB1(−2)
V
0.35
−
V
−
−
−
−
−
−
−
dB
kHz
dB
mmho
MΩ
mV
V
Unity Gain Band Width
PSRR @ 1.0 kHz
−
40
−
−
70
−
Transconductance
−
32
−
Output Impedance
−
2.5
0
−
Input Offset, Error Amp. 2
Error Amp. 2 Common Mode Range
GATE(H) and GATE(L)
High Voltage (AC)
−3.0
1.75
3.0
−
Note 2
2.0
Measure: V − GATE(L)1,2;
−
0
0.5
V
CC
BST − GATE(H)1,2; Note 2
Low Voltage (AC)
Rise Time
Measure:GATE(L)1,2 or GATE(H)1,2; Note 2
−
−
0
0.5
50
V
1.0 V < GATE(L)1,2 < V − 1.0 V
20
ns
CC
1.0 V < GATE(H)1,2 < BST − 1.0 V,
BST ≤ 14 V
Fall Time
V
CC
− 1.0 > GATE(L)1,2 > 1.0 V
−
15
50
ns
BST − 1.0 > GATE(H)1,2 > 1.0 V,
BST ≤ 14 V
GATE(H) to GATE(L) Delay
GATE(H)1,2 < 2.0 V, GATE(L)1,2 > 2.0 V
BST ≤ 14 V
20
20
50
40
40
70
70
ns
ns
GATE(L) to GATE(H) Delay
GATE(L)1,2 < 2.0 V, GATE(H)1,2 > 2.0 V;
BST ≤ 14 V
GATE(H)1(2) and GATE(L)1(2) pull−down.
Resistance to GND
Note 2
125
280
kΩ
PWM Comparator
PWM Comparator Offset
V
= 0 V; Increase COMP1,2 until
0.30
0.40
0.50
V
FB1(−2)
GATE(H)1,2 starts switching
Artificial Ramp
Duty cycle = 50%, Note 2
Note 2
60
−
105
−
150
300
mV
ns
Minimum Pulse Width
2. Guaranteed by design, not 100% tested in production.
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NCP5424A
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; R
= 30.9 k, C
= 0.1 µF,
COMP1,2
A
J
OSC
10.8 V < V < 13.2 V; 10.8 V < BST < 20 V, C
= C
= 1.0 nF, V
= 1.0 V; unless otherwise specified.)
CC
GATE(H)1,2
GATE(L)1,2
FB+2
Characteristic
Oscillator
Test Conditions
Min
Typ
Max
Unit
Switching Frequency
Switching Frequency
Switching Frequency
R
R
R
R
= 61.9 k; Measure GATE(H)1; Note 3
= 30.9 k; Measure GATE(H)1
= 15.1 k; Measure GATE(H)1; Note 3
= 30.9 k, Note 3
112
250
450
0.970
−
150
300
188
350
750
1.030
−
kHz
kHz
kHz
V
OSC
OSC
OSC
OSC
600
R
Voltage
1.000
180
OSC
Phase Difference
−
°
Supply Currents
V
Current
COMP1,2 = 0 V (No Switching)
COMP1,2 = 0 V (No Switching)
−
−
13
17
mA
mA
CC
BST Current
3.5
6.0
Undervoltage Lockout
Start Threshold
GATE(H) Switching; COMP1,2 charging
GATE(H) not switching; COMP1,2 discharging
Start−Stop
7.8
7.0
0.5
8.6
7.8
0.8
9.4
8.6
1.5
V
V
V
Stop Threshold
Hysteresis
Cycle−to−Cycle Current Limit
OVC Comparator Offset Voltage
IS+ 1, 2 Bias Current
0 V < IS+ 1, 2 < 5.5 V, 0 V < IS− < 5.5 V
55
−1.0
0
70
0.1
−
85
1.0
5.5
3.5
0.30
2.0
8.0
mV
µA
V
0 V < IS+ 1, 2 < 5.5 V
OVC Common Mode Range
OVC Latch COMP2 Discharge Current
Discharge Threshold
−
COMP = 1.0 V
−
0.3
1.2
0.25
0.2
5.0
mA
V
0.20
−2.0
2.0
IS− Bias Current
0 V < IS− < 5.5 V
COMP1 = 1.0 V
µA
µA
OVC Latch COMP1 Discharge Current
3. Guaranteed by design, not 100% tested in production.
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NCP5424A
PACKAGE PIN DESCRIPTION
PIN #
SYMBOL
GATE(H)1
GATE(L)1
GND
FUNCTION
1
2
3
4
5
6
7
8
High Side Switch FET driver pin for channel 1.
Low Side Synchronous FET driver pin for channel 1.
Ground pin for all circuitry contained in the IC. This pin is internally bonded to the substrate of the IC.
Power input for GATE(H)1 and GATE(H)2 pins.
BST
IS+1
Positive input for channel 1 overcurrent comparator.
IS−
Negative input for channels 1 and 2 overcurrent comparator.
Error amplifier inverting input for channel 1.
V
FB1
COMP1
Channel 1 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation. The same capacitor provides Soft Start timing for channel 1. This pin also dis-
ables the channel 1 output when pulled below 0.3 V.
9
COMP2
Channel 2 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation and Soft Start timing for channel 2. Channel 2 output is disabled when this pin is
pulled below 0.3 V.
10
11
12
13
14
15
16
V
V
Error amplifier inverting input for channel 2.
FB−2
Error amplifier noninverting input for channel 2.
Positive input for channel 2 overcurrent comparator.
Oscillator frequency pin. A resistor from this pin to ground sets the oscillator frequency.
Input Power supply pin.
FB+2
IS+2
R
OSC
V
CC
GATE(L)2
Low Side Synchronous FET driver pin for channel 2.
High Side Switch FET driver pin for channel 2.
GATE(H)2
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NCP5424A
V
CC
R
OSC
BIAS
CURRENT
SOURCE
GEN
+
−
RAMP2
BST
RAMP1
+
V
CC
8.6 V
7.8 V
−
BST
CLK1
IS+1
IS−
+
OSC
+
CLK2
S
−
GATE(H)1
GATE(L)1
−
Reset
Dominant
70 mV
V
CC
PWM
Comparator 1
+
−
IS+2
−
+
R
+
−
FAULT
70 mV
S
Q
Set
Dominant
R
RAMP1
BST
−
0.40 V
−
+
+
S
GATE(H)2
GATE(L)2
+
Reset
Dominant
0.25 V
−
V
CC
PWM
Comparator 2
R
RAMP2
E/A OFF
E/A OFF
+
0.40 V
FAULT
−
1.2 mA
5 mA
−
+
−
E/A1
1.0 V
+
E/A2
GND
V
FB1
COMP1
V
FB−2
V
FB+2
COMP2
Figure 2. Block Diagram
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NCP5424A
APPLICATIONS INFORMATION
THEORY OF OPERATION
time to the output load step is not related to the crossover
frequency of the error signal loop.
The NCP5424A is a dual output or single two−phase
2
power supply controller that utilizes the V control method.
The error signal loop can have a low crossover frequency,
since the transient response is handled by the ramp signal
loop. The main purpose of this ‘slow’ feedback loop is to
provide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be rolled
off at a low frequency. Enhanced noise immunity improves
remote sensing of the output voltage, since the noise
associated with long feedback traces can be effectively
filtered.
2
Two synchronous V buck regulators can be built using a
single controller or a single output converter that draws
programmable amounts of current from two input voltages.
The fixed−frequency architecture, driven from a common
oscillator, ensures a 180° phase differential between
channels.
V2 Control Method
The V method of control uses a ramp signal that is
2
Line and load regulation is drastically improved because
there are two independent control loops. A voltage mode
controller relies on the change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains a fixed error signal during
line transients, since the slope of the ramp signal changes in
this case. However, regulation of load transients still requires
generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the DC output voltage. This control scheme
inherently compensates for variation in either line or load
conditions, since the ramp signal is generated from the
2
output voltage itself. The V method differs from traditional
techniques such as voltage mode control, which generates an
artificial ramp, and current mode control, which generates
a ramp using the inductor current.
2
a change in the error signal. The V method of control
maintains a fixed error signal for both line and load variation,
since the ramp signal is affected by both line and load.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope in the output ripple can
lead to pulse width jitter and variation caused by both random
and synchronous noise. A ramp waveform generated in the
oscillator is added to the ramp signal from the output voltage
to provide the proper voltage ramp at the beginning of each
switching cycle. This slope compensation increases the noise
immunity particularly at higher duty cycle (above 50%).
−
GATE(H)
GATE(L)
PWM
+
RAMP
Output
Voltage
Slope
Error
Amplifier
V
FB
Compensation
−
COMP
Reference
Voltage
Error
Signal
+
Start Up
The NCP5424A features a programmable Soft Start
function, which is implemented through the Error Amplifier
and the external Compensation Capacitor. This feature
prevents stress to the power components and overshoot of
the output voltage during start−up. As power is applied to the
regulator, the NCP5424A Undervoltage Lockout circuit
Figure 3. V2 Control with Slope Compensation
2
The V control method is illustrated in Figure 3. The
output voltage generates both the error signal and the ramp
signal. Since the ramp signal is simply the output voltage, it
is affected by any change in the output, regardless of the
origin of that change. The ramp signal also contains the DC
portion of the output voltage, allowing the control circuit to
drive the main switch to 0% or 100% duty cycle as required.
A variation in line voltage changes the current ramp in the
(UVL) monitors the IC’s supply voltage (V ). The UVL
CC
circuit resets an internal fault latch when the input voltage
exceeds 8.6 volts. This fault latch disables the error
amplifiers until it is reset. Once the amplifiers are enabled,
they start charging the compensation capacitors with a 30 uA
constant current that causes a linear voltage ramp. The
output of the error amplifier is connected internally to the
negative input of the PWM comparator. The comparator’s
positive input is connected back to the feedback voltage pin
through a 0.45−volt offset. With the feedback voltage
starting at zero, the offset voltage forces the comparator
high, which prevents resetting the RS latches that control the
output drivers. Once the compensation capacitor voltage
reaches 0.45 volts, the PWM comparator will switch and
2
inductor, which causes the V control scheme to compensate
the duty cycle. Since any variation in inductor current modifies
2
the ramp signal, as in current mode control, the V control
scheme offers the same advantages in line transient response.
A variation in load current will affect the output voltage,
modifying the ramp signal. A load step immediately changes
the state of the comparator output, which controls the main
switch. The comparator response time and the transition
speed of the main switch determine the load transient
response. Unlike traditional control methods, the reaction
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8
NCP5424A
allow a short PWM pulse. This pulse will gradually increase
buildup of negative currents that arise during a long start
interval where the bottom FET of controller 2 is on. For
applications where there are two outputs, this problem can
not occur.
in width as the voltage ramp on the Compensation Capacitor
continues to rise. This process will continue until the output
voltage reaches the designed value set by the feed back
resistors and the parts 1.0−volt reference voltage. Thus the
user can determine both soft start and power sequence
functions by selecting the compensation capacitors and
simply knowing that the amplifiers charge these capacitors
with 30 uA and that the threshold for starting PWM pulses
is 0.45 volts.
V
IN
(V − 1.15)
IN
kW
0.958
COMP2
Comp
Cap
V
IN
1.2 kW
8.6 V
V
COMP
0.45 V
Figure 5. Preventing Reverse Current
Gate Charge Effect on Switching Times
V
FB
When using the onboard gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading,
according to the following graphs.
GATE(H)1
GATE(H)2
UVLO
STARTUP
NORMAL OPERATION
t
S
Figure 4. Idealized Waveforms
Average Fall Time
Average Rise Time
Normal Operation
90
80
70
60
50
40
During normal operation, the duty cycle of the gate drivers
remains approximately constant as the V control loop
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load
conditions will result in changes in duty cycle to maintain
regulation.
2
30
20
10
0
Zero Current Start Up in Single Output Shared Input
Current Applications
One problem that occurs with dual controllers when
connected as a single output is that reverse currents can
occur during zero load conditions. As the two controllers
start up and start delivering current, if there is no load a
reverse current will develop in the inductor of controller 2
that is equal and opposite the current in the controller 1
inductor. When the controller 2 starts to deliver power this
reverse current will flow backwards through the top FET
back into the supply. In the extreme this can cause the supply
to over voltage and/or shut down. Fortunately, there are
several ways to deal with this problem. One is to simply
insure the part has a minimum load. Another is illustrated in
Figure 5, where a diode and voltage divider biases the
controller 2 Compensation Capacitor above the 0.45 V soft
start threshold, such that the controller starts switching
without a soft start delay. The effect of this is to eliminate the
8
0
1
2
3
4
5
6
7
Load (nF)
Figure 6. Average Rise and Fall Times
Transient Response
The 150 ns reaction time of the control loop provides fast
transient response to any variations in input voltage and
output current. Pulse−by−pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
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NCP5424A
Out−of−Phase Synchronization
Current limiting
In out−of−phase synchronization, the turn−on of the
second channel is delayed by half the switching cycle. This
delay is supervised by the oscillator, which supplies a clock
signal to the second channel which is 180° out of phase with
the clock signal of the first channel.
The advantages of out−of−phase synchronization are
many. Since the input current pulses are interleaved with one
another, the overlap time is reduced. The effect of this
overlap reduction is to reduce the input filter requirement,
allowing the use of smaller components. In addition, since
peak current occurs during a shorter time period, emitted
EMI is also reduced, thereby reducing shielding
requirements.
The NCP5424A has two current limit amplifiers with
internal 70 mV offsets. These differential amplifiers have a
common mode range from zero to 5.5 volts, and low input
bias currents. Both amplifiers share a common negative
input, which restricts dual current limiting to single output
mode applications. In dual output mode applications,
independent current limits are not supported. The preferred
method of current sensing is inductor sensing (see following
section). However, alternate means of current sensing, such
as Rds(on), or sense resistors, are also supported. Once a
voltage greater that 70 mV is applied to the current limiting
amplifier; it will produce an output that resets the output RS
flip flop. This event terminates the PWM pulse for that
cycle, limiting the energy delivered to the load on a
cycle−by−cyclebasis. An advantage of this current limiting
scheme is that the chip will resume normal operation within
one cycle after the overcurrent condition clears.
Overvoltage Protection
Overvoltage Protection (OVP) is provided as a result of
2
the normal operation of the V control method and requires
no additional external components. The control loop
responds to an overvoltage condition within 150 ns, turning
off the upper MOSFET and disconnecting the regulator
from its input voltage. This results in a crowbar action to
clamp the output voltage preventing damage to the load. The
regulator remains in this state until the overvoltage
condition ceases.
A second benefit of PWM pulse width limiting occurs in
input power sharing applications, where one channel of the
controller can be current limited while the other channel
supplies the remaining current in excess of that level. It is
important to realize that in current limit the feedback path to
the error amplifier is effectively opened. The error amplifier
output will start to drift high in response to the condition of
output voltage low with respect to its reference. When the
part comes out of current limit, the error amplifier output
voltage will be at the wrong quiescent voltage, and will
immediately start to recover. If the response of the output
filter is faster than the response of the error amplifier, an
undesirable positive overshoot can occur in the output. This
phenomenon is not unique to the NCP5424A, but is more
pronounced because the response of the error amplifier with
a large compensation capacitor is intentionally slow. This
effect can be mitigated by the addition of a voltage divider
and diode clamp connected to limit Comp pin voltage
excursions.
The nominal voltage at the Comp pin is the sum of the
reference voltage, the 0.45 Volt offset, and the ramp voltage.
Clamping the Comp voltage 0.2 volts above the sum of these
voltages keeps the recovery of the Error amplifier response
fast enough to eliminate output overshoot. An additional 8K
resistor connected between the channel 1 and channel 2
Comp pins will prevent overshoot of the Channel one output
during recovery from a Channel 1 overload.
Input Current Sharing
In contemporary high−end applications, part of a system
may require more power than is available from one supply.
The NCP5424A dual controller can address this
requirement in two ways.
In many cases, it is sufficient to be able to set the input
power sharing as a ratio so that one source always supplies
a certain percentage of the total. This is achieved by having
the Error Amplifier inputs from Slave side, Controller Two,
brought to external pins so its’ reference is available.
Current information from the Master, Controller One,
provides a reference for the Slave. Current information from
the Slave is fed back to the error amplifier’s inverting input.
The Slave will try to adjust its current to match the current
information fed to its reference input from the Master. If this
information is 1/2 the voltage developed across the Master’s
output inductor, the Slave will run at half current and supply
a percentage, nominally 33% in this case, of the total current.
In other applications however, the user may not only wish
to draw a percentage of power from one source, but also may
need to limit the power drawn from that source. The Slave
has a Cycle−By−Cycle current limit. In this case, the Slave
can be programmed to budget the maximum input power.
For example, a designer may wish to draw equal amounts of
power from two 5−volt sources, but only 2 amps are
available from one of the supplies. In this case, the dual
controller will draw equally from the two sources up to a
total of 4 amps. At this point, the Slave controller goes into
current limit and draws no more than its preset budget. The
Master continues to supply the remaining output current up
to the maximum that the application requires.
Output Enable
On/Off control of the regulator outputs can be
implemented by pulling the COMP pins low. The COMP
pins must be driven below the 0.40 V PWM comparator
offset voltage in order to disable the switching of the GATE
drivers.
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NCP5424A
DESIGN GUIDELINES
V = output inductor voltage drop due to inductor wire
L
DC resistance;
= buck regulator input voltage;
Definition of the design specifications
The output voltage tolerance can be affected by any or all
of the following:
V
V
IN
= low side FET voltage drop due to R
.
DS(ON)
LFET
Selecting the Switching Frequency
1. buck regulator output voltage setpoint accuracy;
2. output voltage change due to discharging or charging
of the bulk decoupling capacitors during a load
current transient;
3. output voltage change due to the ESR and ESL of the
bulk and high frequency decoupling capacitors,
circuit traces, and vias;
Selecting the switching frequency is a trade−off between
component size and power losses. Operation at higher
switching frequencies allows the use of smaller inductor and
capacitor values. Nevertheless, it is common to select lower
frequency operation because a higher frequency results in
lower efficiency due to MOSFET gate charge losses.
Additionally, the use of smaller inductors at higher
frequencies results in higher ripple current, higher output
voltage ripple, and lower efficiency at light load currents.
The value of the oscillator resistor is designed to be
linearly related to the switching period. If the designer
prefers not to use Figure 8 to select the necessary resistor, the
following equation quite accurately predicts the proper
resistance for room temperature conditions.
4. output voltage ripple and noise.
Budgeting the tolerance is left to the designer who must
consider all of the above effects and provide an output
voltage that will meet the specified tolerance at the load.
The designer must also ensure that the regulator
component temperatures are kept within the manufacturer’s
specified ratings at full load and maximum ambient
temperature.
21700 * f
SW
R
+
OSC
Selecting Feedback Divider Resistors
2.31f
SW
where:
V
OUT
R
OSC
= oscillator resistor in kΩ;
f
= switching frequency in kHz.
SW
R1
800
700
V
FB
R2
600
500
Figure 7. Selecting Feedback Divider Resistors
400
300
The feedback pins (V
) are connected to external
FB1(2)
resistor dividers to set the output voltages. The error
amplifier is referenced to 1.0 V and the output voltage is
determined by selecting resistor divider values. Resistor R1
is selected based on a design trade−off between efficiency
and output voltage accuracy. The output voltage error can be
estimated due to the bias current of the error amplifier
neglecting resistor tolerance:
200
100
10
20
30
40
50
60
R
W
)
OSC (k
Figure 8. Switching Frequency
*6
1 10
R1
Selection of the Output Inductor
Error% +
100%
1
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the
inductor value will decrease output voltage ripple, but
degrade transient response. There are many factors to
consider in selecting the inductor including cost, efficiency,
EMI and ease of manufacture. The inductor must be able to
handle the peak current at the switching frequency without
saturating, and the copper resistance in the winding should
be kept as low as possible to minimize resistive power loss.
There are a variety of materials and types of magnetic
cores that could be used for this application. Among them
are ferrites, molypermalloy cores (MPP), amorphous and
powdered iron cores. Powdered iron cores are very
R2 can be sized after R1 has been determined:
V
OUT
1
R2 + R1ǒ
* 1Ǔ
Calculating Duty Cycle
The duty cycle of a buck converter (including parasitic
losses) is given by the formula:
V
) (V
LFET
) V )
L
HFET
OUT
) V
HFET
* V
Duty Cycle + D +
V
* V
IN
L
where:
V
V
= buck regulator output voltage;
OUT
= high side FET voltage drop due to R
;
HFET
DS(ON)
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NCP5424A
DI
2
commonly used. Powdered iron cores are very suitable due
L
I
+ I *
OUT
L(VALLEY)
to its high saturation flux density and have low loss at high
frequencies, a distributed gap and exhibit very low EMI.
The minimum value of inductance which prevents
inductor saturation or exceeding the rated FET current can
be calculated as follows:
where:
I
= inductor valley current.
L(VALLEY)
Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
(V
* V
)V
OUT OUT
I
SW(MAX)
IN(MIN)
V
L
+
MIN
f
SW
IN(MIN)
where:
L
V
V
= minimum inductance value;
= minimum design input voltage;
= output voltage;
MIN
IN(MIN)
OUT
f
I
= switching frequency;
− maximum design switch current.
The inductor ripple current can then be determined:
SW
SW(MAX)
V
(1 * D)
OUT
DI
+
L
L f
SW
where:
∆I = inductor ripple current;
L
V
= output voltage;
L = inductor value;
D = duty cycle.
OUT
t
ESL
Dt
TR
ǒ
Ǔ
DV
+ DI
OUT
) ESR )
OUT
C
OUT
where:
f
= switching frequency
SW
∆I
∆I
/ ∆t = load current slew rate;
= load transient;
The designer can now verify if the number of output
capacitors will provide an acceptable output voltage ripple
(1.0% of output voltage is common). The formula below is
used:
OUT
OUT
∆t = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
DV
OUT
ESR
DI
+
L
MAX
Rearranging we have:
t
= output voltage transient response time.
TR
DV
OUT
DI
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
ESR
+
MAX
L
where:
ESR
∆V
= maximum allowable ESR;
= 1.0% × V
voltage ripple ( budgeted by the designer );
∆I = inductor ripple current;
MAX
= maximum allowable output
OUT
OUT
The maximum allowable ESR can then be determined
according to the formula:
L
V
= output voltage.
OUT
The number of output capacitors is determined by:
DV
DI
ESR
OUT
ESR
+
MAX
ESR
CAP
Number of capacitors +
ESR
MAX
where:
∆V
= change in output voltage due to ESR (assigned
by the designer)
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula:
where:
ESR
ESR
= maximum ESR per capacitor (specified in
manufacturer’s data sheet).
CAP
The designer must also verify that the inductor value
yields reasonable inductor peak and valley currents (the
inductor current is a triangular waveform):
ESR
ESR
CAP
MAX
Number of capacitors +
DI
2
L
I
+ I )
OUT
L(PEAK)
where:
ESR
where:
= maximum ESR per capacitor (specified in
manufacturer’s data sheet).
= maximum allowable ESR.
CAP
I
I
= inductor peak current;
= load current;
L(PEAK)
OUT
ESR
MAX
∆I = inductor ripple current.
L
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NCP5424A
The actual output voltage deviation due to ESR can then
SELECTION OF THE POWER FET
be verified and compared to the value assigned by the
designer:
FET Basics
The use of a MOSFET as a power switch is compelled by
two reasons: 1) high input impedance; and 2) fast switching
times. The electrical characteristics of a MOSFET are
considered to be nearly those of a perfect switch. Control
and drive circuitry power is therefore reduced. Because the
input impedance is so high, it is voltage driven. The input of
the MOSFET acts as if it were a small capacitor, which the
driving circuit must charge at turn on. The lower the drive
DV
+ DI ESR
OUT MAX
ESR
Similarly, the maximum allowable ESL is calculated from
the following formula:
DV
Dt
ESL
DI
ESL
MAX
+
Selection of the Input Inductor
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors upon power up.
The inductor’s limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
bypass capacitor bank, which has to initially support the
sudden load change.
impedance, the higher the rate of rise of V , and the faster
GS
the turn−on time. Power dissipation in the switching
MOSFET consists of 1) conduction losses, 2) leakage
losses, 3) turn−on switching losses, 4) turn−off switching
losses, and 5) gate−transitions losses. The latter three losses
are proportional to frequency.
The most important aspect of FET performance is the
Static Drain−To−Source On−Resistance (R ), which
DS(ON)
affects regulator efficiency and FET thermal management
requirements. The On−Resistance determines the amount of
current a FET can handle without excessive power
dissipation that may cause overheating and potentially
catastrophic failure. As the drain current rises, especially
above the continuous rating, the On−Resistance also
increases. Its positive temperature coefficient is between
+0.6%/°C and +0.85%/°C. The higher the On−Resistance
the larger the conduction loss is. Additionally, the FET gate
charge should be low in order to minimize switching losses
and reduce power dissipation.
The minimum inductance value for the input inductor is
therefore:
DV
L
IN
+
(dIńdt)
MAX
Both logic level and standard FETs can be used.
where:
= input inductor value;
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven rail−to−rail due to overshoot caused by the
capacitive load they present to the controller IC.
L
IN
∆V = voltage seen by the input inductor during a full load
swing;
(dI/dt)
= maximum allowable input current slew rate.
MAX
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double−pole network
with a slope of −2.0, a roll−off rate of −40 dB/dec, and a
corner frequency:
Selection of the Switching (Upper) FET
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component’s
junction temperature to exceed 150°C.
The maximum RMS current through the switch can be
determined by the following formula:
1
f
C
+
Ǹ
2p LC
where:
L = input inductor;
C = input capacitor(s).
2
I
) (I
I )
L(VALLEY)
L(PEAK)
L(PEAK)
D
ƪ) I
ƫ
2
L(VALLEY)
Ǹ
I
RMS(H) +
3
where:
I
I
I
= maximum switching MOSFET RMS current;
= inductor peak current;
RMS(H)
L(PEAK)
= inductor valley current;
L(VALLEY)
D = duty cycle.
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NCP5424A
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non−overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
2
P
+ I
RMS(H)
R
RMS(H)
DS(ON)
where:
P
+ V
I non−overlap time f
LOAD SW
SWL
SD
P
I
R
= switching MOSFET conduction losses;
= maximum switching MOSFET RMS current;
= FET drain−to−source on−resistance
RMS(H)
RMS(H)
where:
P
SWL
= lower FET switching losses;
DS(ON)
V
SD
= lower FET source−to−drain voltage;
The upper MOSFET switching losses are caused during
MOSFET switch−on and switch−off and can be determined
by using the following formula:
I
= load current;
LOAD
Non−overlap time
=
GATE(L)−to−GATE(H) or
GATE(H)−to−GATE(L) delay (from NCP5424A data sheet
Electrical Characteristics section);
P
+ P
) P
SWH(ON)
SWH
SWH(OFF)
V
I
(t ) t
)
FALL
f
= switching frequency.
IN
OUT
RISE
6T
SW
+
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
where:
P
P
V
= upper MOSFET switch−on losses;
= upper MOSFET switch−off losses;
= input voltage;
SWH(ON)
SWH(OFF)
P
+ P
) P
RMS(L) SWL
LFET(TOTAL)
where:
IN
P
P
P
= Synchronous (lower) FET total losses;
LFET(TOTAL)
I
t
= load current;
OUT
RISE
= Switch Conduction Losses;
RMS(L)
= MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
= MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
= Switching losses.
SWL
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
t
FALL
T = 1/f = period.
SW
The total power dissipation in the switching MOSFET can
then be calculated as:
T + T ) [P
R
]
QJA
J
A
LFET(TOTAL)
where:
T = MOSFET junction temperature;
P
+ P
) P
) P
SWH(ON) SWH(OFF)
HFET(TOTAL)
RMS(H)
J
T = ambient temperature;
A
where:
P
= total synchronous (lower) FET losses;
LFET(TOTAL)
P
P
P
P
= total switching (upper) MOSFET losses;
= upper MOSFET switch conduction Losses;
= upper MOSFET switch−on losses;
= upper MOSFET switch−off losses;
HFET(TOTAL)
R
Θ
JA
= lower FET junction−to−ambient thermal resistance.
RMS(H)
SWH(ON)
Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
SWH(OFF)
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
used, V , and the NCP5424A operating frequency. The
CC
average MOSFET gate charge current typically dominates
the control IC power dissipation.
The IC power dissipation is determined by the formula:
T + T ) [P
R
]
QJA
J
A
HFET(TOTAL)
where:
T = FET junction temperature;
T = ambient temperature;
A
P
+ I
V
) I
V
P
CONTROL(IC)
CC1 CC1
BST BST ) GATE(H)1
J
) P
GATE(L)1
) P
) P
GATE(H)2 GATE(L)2
where:
P
P
R
= total switching (upper) FET losses;
= upper FET junction−to−ambient thermal resistance.
HFET(TOTAL)
= control IC power dissipation;
= IC quiescent supply current;
CONTROL(IC)
ΘJA
I
CC1
Selection of the Synchronous (Lower) FET
The switch conduction losses for the lower FET can be
calculated as follows:
V
= IC supply voltage;
CC1
P
P
= upper MOSFET gate driver (IC) losses;
= lower MOSFET gate driver (IC) losses.
GATE(H)
GATE(L)
2
The upper (switching) MOSFET gate driver (IC) losses
are:
P
+ I
RMS
R
RMS(L)
+ [I
DS(ON)
2
Ǹ
(1 * D)] R
OUT
DS(ON)
P
+ Q
f V
SW BST
GATE(H)
GATE(H)
where:
where:
P
= lower MOSFET conduction losses;
= load current;
RMS(L)
P
= upper MOSFET gate driver (IC) losses;
GATE(H)
I
OUT
Q
= total upper MOSFET gate charge at V
;
GATE(H)
CC
D = Duty Cycle;
= lower FET drain−to−source on−resistance.
f
= switching frequency;
SW
R
DS(ON)
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
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NCP5424A
The lower (synchronous) MOSFET gate driver (IC)
losses are:
To ensure greater accuracy, the equivalent parallel
resistance of R1 and R2 should be greater or equal to the value
R17, the resistance value calculated for the inverting signal.
P
+ Q
f V
SW CC
GATE(L)
GATE(L)
R1 · R2
R1 ) R2
R17 v
where:
P
= lower MOSFET gate driver (IC) losses;
GATE(L)
R17 = The inverting signal filter resistance.
Q
= total lower MOSFET gate charge at V
;
GATE(L)
CC
f
= switching frequency;
SW
Current Sharing Errors
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
The three main errors in current sharing arise from board
layout imbalances, inductor mismatch, and input offsets in
the error amplifiers. The first two sources of error can be
controlled through careful component selection and good
layout practice. With a 4.0 mW inductor, for example, one
mV of input offset error will represent .25 A of error. One
way to diminish this effect is to use higher resistance
inductors but the penalty is higher power losses in the
inductors. Fortunately, the input offset of the NCP5424A is
low so that this error term is reduced.
Selection of the Current Sharing Ratio
When the two controllers are connected together as a
single output two−phase Buck Converter, the two
controllers are in a Master−Slave configuration. The Slave
controller on the right side of Figure 1 tries to follow
information provided by the Master controller, on the left.
The circuit uses inductor current sensing, in which the
parasitic resistance (LSR) of the controller’s output chokes
are used as a current sensing element. On the Slave side
(Controller Two), both Error Amplifier inputs are brought to
external pins so the reference is available. The RC network
in parallel with the output inductor on the Master side
(Controller One) generates the reference for the Slave.
Current information from the Slave is fed back to the error
amplifier’s inverting input. In this configuration, the Slave
tries to adjust its current to match the current information fed
to its reference input from the Master Controller. In Figure 1,
R1, R2 and C6 are used to generate the Slave’s reference.
R17 and C14 generate the Slave’s inverting input signal. If
50−50 current sharing is needed, then only R2 and C6 are
required to generate the reference signal. The values for both
sides should be calculated with the following equation.
Current Sharing Compensation Capacitor Selection
The NCP5424A is designed for single and dual output
applications. Therefore the IC needs two separate
compensation capacitors for the dual output designs, which
is not desirable for a single output design. With two
compensation capacitors, a race condition between the
master and slave controllers is created. During start−up the
Master’s Error Amplifier starts charging Comp1. When
Comp1 reaches 0.40 V, both controllers begin to regulate the
output. The Slave Controller voltage reference is generated
externally by the Master’s output, while the Master has an
internal 1.0 V reference. Since Comp2 does not start
charging until Comp1 reaches 0.40 V, the Slave’s PWM
inverting input is lower than its Vfb−2 input causing a reset
of the Slave Controller output driver. Gate(L)2 turns on,
sinking current from the output, while the Master’s output
driver is set turning Gate(H)1 on and sourcing current to the
output (since its PWM inverting input is higher than its Vfb1
input). This condition will continue until Comp2’s
amplitude is equal to Comp1’s. During this condition, the
output voltage is being shorted to ground through the bottom
FET, on the slave side. In hiccup mode, if this shoot−through
current is large enough to develop 70 mV across L1, the
Controllers will remain in hiccup mode even after the
external load or short is removed. To avoid this condition,
the Comp2 ramp’s rise time is increased to minimize the
shoot−through current. The value of the Comp2 capacitor is
calculated by the following equations.
L
R +
C6 · RL
where:
L = Inductor value, both Controllers should use the
same inductor.
RL = Internal resistance of L, from inductor data sheet.
C6 = Select a value such that R < 15 kW.
With the RC time constant selected to equal the L/R time
L
constant, the voltage across the capacitor will be equal to the
voltage drop across the internal resistance of the inductor. For
proper sharing, the inductors on both sides should be the same.
If a ratio other than 50−50 is needed, the R and C values
of the inverting signal filter are calculated using the previous
equation. Since the reference signal has to be divided down
to the proper ratio, R1 is required. Using the same
capacitance value, the following equation is used to
calculate the proper values for the reference filter.
R
+ R ) R
fet
X
L2
C8
0.45 · R
L2
(0.07 · 25%) · R
C13 +
) 1
X
R1(1 * Ratio)
R2 +
where:
C8 = Comp1 capacitor value, 0.22 mF is suggested.
Ratio
where:
R
L2
=Inductor parasitic resistance (LSR), see inductor’s
data sheet.
R1 = Chosen Value, 10 kW is recommended.
%slave
%master
Ratio +
, input power ratio
R
fet
=R
of the Slave’s lower FET, see data sheet.
DS(on)
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NCP5424A
A good rule of thumb is a 20 to 1 ratio between Comp1 and
where:
Comp2. If soft start rise time is not an issue, a 0.22 mF
capacitor on the Comp1 pin and a 0.01 mF capacitor on the
Comp2 pin in suggested.
V
= Output regulated voltage.
out
V = Offset voltage, example above was 20 mV.
os
R4 = Chosen value, 10 KW is a good choice.
If V is larger than 70 mV, then the current signal from the
os
Selecting Current Sharing Current Limit
output chokes must be divided down. For example, if the
inductor’s LSR is equal to 8.0 mW and the current limit is
15 A, then the current signal is 120 mV, which is almost
twice the comparator’s offset (70 mV). This signal can be
divided down by adding a resistor (R1) in parallel with the
capacitor (C6) in the inductor sensing network, see Figure 1.
The divider R1 and R2 can be set to equal value to divide the
current signal in half and equation (3) should be used to
select the proper voltage divider. Notice that the divider R1
and R2, divides down the voltage applied to the capacitor
In a two−phase single output application, the Slave
current limit lower than that of the Master, which limits the
Slave’s input power when its limit is reached, while the
output voltage remains in regulation. During
Cycle−By−Cycle current limit, the Slave’s operating
frequency will decrease in half, due to pulse skipping,
resulting in phase overlap. This overlap will increase the
output voltage ripple.
Exceeding 70 mV between the IS+ and IS− pins trips the
current limits. A divided down V signal is used to generate
out
C
by a factor of 2. This divides the voltage across the
RC
the IS− reference, and inductor sensing of the controllers
output chokes provide the output current information to
IS+X pin. The inductor sensing is achieved by placing a
series RC in parallel with the output choke. With the RC time
output inductor’s LSR by a factor of two and results in twice
the current limit. This scaling technique is another way the
current limit may be set so that virtually any current limit
may be obtained.
constant selected to equal the L/R time constant, the
L
To ensure accuracy, the equivalent parallel resistance of
voltage across the capacitor will be equal to the voltage drop
across the internal resistance of the inductor.
The resistance of the output choke (LSR) must be known
to calculate the overcurrent trip point. The voltage drop
across the inductor at overcurrent is calculated as follows:
R1 and R2 should be greater or equal to the value R , the
RC
resistance value calculated from equation (2).
Current Sensing
The current supplied to the load can be sensed easily using
the IS+ and IS− pins for the output. These pins sense a
voltage, proportional to the output current, and compare it to
a fixed internal voltage threshold. When the differential
voltage exceeds 70 mV, the internal overcurrent protection
system goes into hiccup mode. Two methods for sensing the
current are available.
Sense Resistor. A sense resistor can be added in series
with the inductor. When the voltage drop across the sense
resistor exceeds the internal voltage threshold of 70 mV, a
fault condition is set.
(eq. 1)
V
+ R · I
out
L
L
where:
V = Voltage drop across the inductor,
L
R = LSR of the inductor,
L
I
= Output current trip point for one phase.
out
If the inductor selected has a 5.0 mW LSR and the current
limit is 10 A through one of the phases, then the analog
signal will be 50 mV. Since this value is less than 70 mV,
then the IS− divider, R3 and R4 in Figure 1, must scale down
the V by 20 mV, thus placing a 20 mV offset across the IS−
out
The sense resistor is selected according to:
and IS+x pin at no load and allowing the Controllers to trip
into current limit with only 50 mV across the inductor. In
this case, the RC values are calculated using the following
equation:
0.070 V
R
+
SENSE
I
LIMIT
In a high current supply, the sense resistor will be a very
low value, typically less than 10 mΩ. Such a resistor can be
either a discrete component or a PCB trace. The resistance
value of a discrete component can be more precise than a
PCB trace, but the cost is also greater.
Setting the current limit using an external sense resistor is
very precise because all the values can be designed to
specific tolerances. However, the disadvantage of using a
sense resistor is its additional constant power loss and heat
generation.
L
RC
(eq. 2)
R
+
RC
C
· R
L
L = Inductor value, both Controllers should have the
same value.
R = Internal resistance of L, see data sheet.
L
C
RC
=Chosen value, 0.1 mF will make R a reasonable
value.
And the IS− divider value can be selected with this equation.
V
out
* V
(eq. 3)
R3 + ǒ
* 1Ǔ· R4
V
out
os
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16
NCP5424A
Inductor ESR. Another means of sensing current is to use
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that very little
the intrinsic resistance of the inductor. A model of an
inductor reveals that the windings of an inductor have an
effective series resistance (ESR).
voltage ramp exists at the control IC feedback pin (V ),
FB
The voltage drop across the inductor ESR can be
measured with a simple parallel circuit: an RC integrator. If
resulting in increased regulator sensitivity to noise and the
potential for loop instability. In applications where the
internal slope compensation is insufficient, the performance
of the NCP5424A−based regulator can be improved through
the addition of a fixed amount of external slope
compensation at the output of the PWM Error Amplifier (the
COMP pin) during the regulator off−time. Referring to
Figure 8, the amount of voltage ramp at the COMP pin is
dependent on the gate voltage of the lower (synchronous)
FET and the value of resistor divider formed by R1and R2.
the value of R and C are chosen such that:
S1
L
ESR
+ R
C
S1
then the voltage measured across the capacitor C will be:
V
+ ESR I
LIM
C
Selecting Components. Select the capacitor C first. A
value of 0.1 µF is recommended. The value of R can be
S1
selected according to:
−t
)
R2
1
t
ǒ
Ǔ
V
+ V
GATE(L)
(1 * e
SLOPECOMP
R
+
S1
R1 ) R2
ESR C
where:
Typical values for inductor ESR range in the low m;
consult manufacturer’s datasheet for specific details.
Selection of components at these values will result in a
current limit of:
V
V
= amount of slope added;
= lower MOSFET gate voltage;
SLOPECOMP
GATE(L)
R1, R2 = voltage divider resistors;
t = t or t (switch off−time);
ON
OFF
0.070 V
ESR
I
+
LIM
τ = RC constant determined by C1 and the parallel
combination of R1, R2 neglecting the low driver
output impedance.
L
ESR
V
CC
Co
C
RS1
GATE(H)
COMP
C
COMP
GATE(L)
IS+
NCP5424A
R2
C1
R1
IS−
Figure 9. Inductor ESR Current Sensing
GATE(L)
To Synchronous
FET
Given an ESR value of 3.5 mΩ, the current limit becomes
20 A. If an increased current limit is required, a resistor
divider can be added.
The advantages of setting the current limit by using the
winding resistance of the inductor are that efficiency is
maximized and heat generation is minimized. The tolerance
of the inductor ESR must be factored into the design of the
current limit. Finally, one or two more components are
required for this approach than with resistor sensing.
Figure 10. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
Each On−Time Cycle
The artificial voltage ramp created by the slope
compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
than the off−time cycle duration (time during which the
lower MOSFET is conducting). It is important that the series
combination of R1 and R2 is high enough in resistance to
avoid loading the GATE(L) pin. Also, C1 should be very
small (less than a few nF) to avoid heating the part.
Adding External Slope Compensation
Today’s voltage regulators are expected to meet very
stringent load transient requirements. One of the key factors
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17
NCP5424A
EMI MANAGEMENT
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections and
component vias, and the bottom layers for the noise
sensitive traces.
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
6. Keep the inductor switching node small by placing
the output inductor, switching and synchronous FETs
close together.
7. The MOSFET gate traces to the IC must be short,
straight, and wide as possible.
8. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
9. Place the switching MOSFET as close to the input
capacitors as possible.
LAYOUT GUIDELINES
When laying out the CPU buck regulator on a printed
circuit board, the following checklist should be used to
ensure proper operation of the NCP5424A.
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
10. Place the output capacitors as close to the load as
possible.
11. Place the COMP capacitor as close as possible to the
COMP pin.
12. Connect the filter components of the following pins:
R
V
, V
, and COMP to the GND pin with a
OSC, FB OUT
single trace, and connect this local GND trace to the
output capacitor GND.
2. Keep high currents out of sensitive ground
connections.
13. Place the V bypass capacitors as close as possible
CC
3. Avoid ground loops as they pick up noise. Use star or
single point grounding.
to the IC.
14. Place the R
resistor as close as possible to the
OSC
4. For high power buck regulators on double−sided
PCB’s a single ground plane (usually the bottom) is
recommended.
5. Even though double sided PCB’s are usually
sufficient for a good layout, four−layer PCB’s are the
optimum approach to reducing susceptibility to
R
pin.
OSC
15. Include provisions for 100−100pF capacitor across
each resistor of the feedback network to improve
noise immunity and add COMP.
16. Assign the output with lower duty cycle to channel 2,
which has better noise immunity.
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NCP5424A
PACKAGE DIMENSIONS
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
M
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
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19
NCP5424A
2
V is a trademark of Switch Power, Inc.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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NCP5424A/D
相关型号：
NCP5424DG
1.5A DUAL SWITCHING CONTROLLER, 750kHz SWITCHING FREQ-MAX, PDSO16, LEAD FREE, SOIC-16
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