NCP5810 [ONSEMI]
Dual 1 W Output AMOLED Driver Supply; 双1 W输出AMOLED驱动器电源
| 型号： | NCP5810 |
| 厂家： | 
ONSEMI |
| 描述： | Dual 1 W Output AMOLED Driver Supply |
| 文件： | 总13页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP5810
Dual 1 W Output AMOLED
Driver Supply
The NCP5810 is a dual−output DC/DC converter which can
generate both a positive and a negative voltage. Both PWM
converters achieve high efficiency for portable application. Thanks
to the high output voltage accuracy and signal integrity the NCP5810
is particularly suitable for powering applications such as AMOLED
display drivers. The output voltage of the inverter is fully
configurable using external feedback resistors, where the output
voltage of the boost is internally fixed. The switching regulator
operates at 1.75 MHz which allows the use of small inductors and
ceramic capacitors. In addition both converters are internally
compensated which simplifies the design and reduces the PCB
component count. Cycle−by−cycle peak current limit and thermal
shut down provide value added features to protect the device. The
NCP5810 is housed in a low profile space efficient 3 x 3 x 0.55 mm
LLGA package.
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1
12 PIN LLGA
MU SUFFIX
CASE 513AD
MARKING DIAGRAM
Features
5810
AYWG
G
• High Overall Efficiency: 83% (Refer to Figure 4)
• Low Noise 1.75 MHz PWM DC/DC Converter
• Positive Output Fixed + 4.6 V
5810
A
Y
W
G
= Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
• Negative Output from − 2.0 to − 15.0 V
• High Output Voltage Accuracy
• Excellent Line Transient Rejection
• Soft Start to Limit Inrush Current
(Note: Microdot may be in either location)
• Enable Control Facility with True−Shut Down
• Small LLGA 3 x 3 x 0.55 mm Package
1
2
3
4
5
6
12
11
10
9
VOUTP
SWP
LXP
PVIN
SWN
EN
Typical Applications
• AMOLED Driver Supply
♦ Cellular Phones
PGND
AGND
VREF
VS
♦ MP3 Player
♦ Digital Cameras
♦ Personal Digital Assistant and Portable Media Player
♦ GPS
NCP5810
(Top View)
8
AVIN
FBN
7
12−pin 3 x 3 x 0.55 mm LLGA
Exposed pad must be soldered to PCB Ground plane
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
April, 2007 − Rev. 0
NCP5810/D
NCP5810
L1 4.7 mH
VBAT
U1
12
11
3
2
VOUTP
PVIN
SWP
1
C1
4.7 mF
VOUTP
C3
4.7 mF
PGND
EN
ENABLE
VBAT
9
6
NCP5810
VS
8
AVIN
D1
VOUTN
C2
10
1 mF
SWN
C4
4.7 mF
4
5
7
L2
4.7 mH
R2
56 k
C5
0.1 mF
R1
536 k
D1: ON NSR0320MW2
L1, L2: TDK VLF3010AT−4R7
C1: 4.7 mF 6.3 V X5R
C2: 1 mF 6.3 V X5R 0603
C1,C3,C4: 4.7 mF 6.3 V X5R 0805
C6 10 pF
Figure 1. Typical Application Circuit
Option of powering
CINP
Vbat
4.7 mF
L1
4.7 mH
CINA
1 mF
D2
AVIN
PVIN
MP0
LXP
SWP
VOUTP
Thermal
VOUTP
Shut down
COUTP
4.7 mF
BOOST
MN1
ENABLE
EN
PWM CONTROLLER
Osc
Bangap
1.26 V
VS
1.75 Mhz
D1
MP1
SWN
VOUTN
COUTN
NEGATIVE BUCK
PWM CONTROLLER
4.7 mH
L2
Verf
4.7 mF
1.26 V
R1
10 pF
R2
FBN
AGND
PGND
VREF
0.1 mF
Figure 2. Simplified Block Diagram
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NCP5810
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Type
Description
1
VOUTP
OUTPUT
Positive Power Output: A filter capacitor is necessary on this pin for the stability of the loop, to
smooth the current flowing into the load, and limit the noise created by the fast transients present in
this circuitry. A 4.7 mF ceramic bypass capacitor to GND is recommended. Cares must be observed
to avoid EMI through the PCB copper tracks connected to this pin.
2
3
SWP
POWER
POWER
Switch LXP: Positive power switch pin where one end of the L1 inductor is connected. Typical ap-
plication uses a 4.7 mH inductor.
PGND
Power Ground: This pin is the power ground and carries the high switching current. A high quality
ground must be provided to avoid any noise spikes/uncontrolled operation. Cares must be observed
to avoid high−density current flow in a limited PCB copper track.
4
5
AGND
VREF
POWER
OUTPUT
Analog Ground: This pin is the analog ground of the device notably used by VREF.
Voltage Reference: This output provides a 1.265 V voltage reference used notably for the negative
feedback resistive network.
6
7
VS
INPUT
INPUT
Positive Output Voltage Sense: This pin is the output voltage sense input for the positive boost
converter and must be connected to COUTP bypass capacitor.
FBN
Feedback Negative: This pin is the feedback voltage input for the negative Buck−Boost inverter. The
middle point of a resistive bridge divider must be connected here. The resistive network must be con-
nected between VREF and the anode of external Schottky.
8
9
AVIN
EN
POWER
INPUT
Analog Power Supply: The external voltage supply is connected to this pin. A 4.7 mF ceramic ca-
pacitor must be connected across this pin and the power ground to achieve the specified output pow-
er parameters.
Enable: An active high logic level on this pin enables the circuit. A built−in pull−down resistor disables
the device if the pin is left open. Also in disable condition the device provide a true cut−off from PVIN
to VOUTP and SWN.
10
11
12
SWN
PVIN
LXP
INPUT
POWER
POWER
Switch Negative: Negative power switch pin where one end of the L2 inductor is connected. Typical
application uses a 4.7 mH inductor.
Power Supply: This pin is the power supply of the device. A 4.7 mF ceramic capacitor or larger must
bypass this input to the ground. This capacitor should be placed as close a possible to this input.
Switch LXP: The inductor should be connected between this node and SWP. This output supplies
power from PVIN and give a true−cut off function in disable condition.
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NCP5810
MAXIMUM RATINGS (Note 1)
Rating
Symbol
Value
Unit
V
Power Supply Voltage (Note 2)
V
bat
7.0
2000
Human Body Model (HBM) ESD Rating are (Note 3)
Machine Model (MM) ESD Rating are (Note 3)
ESD HBM
ESD MM
V
200
V
Digital Input Voltage
Digital Input Current
ENP, ENN
−0.3 ≤ V ≤ V +0.3
V
mA
in
1
bat
LLGA 3x3 mm package (Notes 6 and 7)
Thermal Resistance Junction−to−Case
R
q
JC
12
°C/W
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
T
−40 to +85
−40 to +125
+150
°C
°C
°C
°C
A
T
J
T
JMAX
T
STG
−65 to +150
Level 1
Moisture Sensitivity (Note 5)
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTES:
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T = 25°C
A
2. According to JEDEC standard JESD22−A108B.
3. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) 200 V per JEDEC standard: JESD22−A115 for all pins.
4. Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78., class II
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
6. The thermal shutdown set to 165°C (typical) avoids irreversible damage on the device due to power dissipation.
7. The R
is dependent on the PCB heat dissipation. The maximum power dissipation (P ) is dependent on the min input voltage, the max output
q
CA
D
current and external components selected.
125 * T
A
RqCA
+
* RqJC
PD
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NCP5810
ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −40°C to +85°C and V between 2.7 V to 4.6 V (Unless
A
IN
otherwise noted). Typical values are referenced to T = +25°C and V = 3.7 V (Unless otherwise noted)
A
IN
Characteristic
Symbol
Min
Typ
Max
Unit
POSITIVE BOOST DC/DC CONVERTER
Positive Operational Output Voltage Range
Maximum Inductor Peak Current
Switches P0 ON Resistance
V
4.55
530
−
4.6
700
320
4.65
800
640
V
OUTP
I
mA
mW
PEAKP_MAX
P0
MOS
R
DSON
Switches N1 ON Resistance
Switches N1 Leakage Current
N
R
−
−
−
300
0.05
85
600
0.5
−
mW
mA
1MOS
DSON
N
1MOS
L
At V = 4.2 V
IN
Efficiency (Notes 8, 9)
E
%
FF
Positive Output Current Available (Notes 9, 10)
I
mA
OUTP
VIN ≥ 3.1 V
VIN ≥ 2.9 V, T between 0 to +85°C
0
0
270
−
−
145
A
Output Voltage Line Regulation I
= 0 mA
L
−
−
10
−
mV
OUTP
INE_RP
2.7 < V < 4.6
IN
Output Voltage Line Transient Overshoot (Note 12)
L
−
4
mV
dB
INE_TP
Power Supply Ripple Rejection (Notes 9, 13)
1.0 Hz to 1.0 kHz
1.0 kHz to 10 kHz
P
SRRP
−
−
60
40
−
−
Output Voltage Load Regulation (Note 14)
L
−
−
−
−
0.5
%/100mA
mV
OAD_RP
Output Voltage Load Transient Response: Overshoot and
Undershoot Vs. Steady State Voltage (Notes 9, 15)
L
TRP
100
NEGATIVE BUCK DC/DC CONVERTER
Typical Negative Operational Output Voltage Range
Peak Inductor Current (Note 9)
V
−15
620
−
−
−2.0
920
V
OUTN
I
800
700
mA
mW
PEAKN_MAX
Switches P2 ON Resistance
P
2MOS
R
DSON
1400
Switches P2 Leakage Current
P
L
−
−
0.05
80
0.5
−
mA
2MOS
At V = 4.2 V
IN
Efficiency (Notes 8, 9)
E
FF
%
Negative Output Power Available (Notes 9, 10) @ V
= −5.4 V
P
OUTN
mA
OUTN
VIN ≥ 3.1 V
VIN ≥ 2.9, T between 0 to +85°C
−
0
175
−
−
100
A
Output Voltage Reference 0 mA < I
< 100 mA
O
−1 %
−2 %
1.265
0.632
+1 %
+2 %
V
REF
VR
Feedback Voltage Threshold in Steady State:
F
BVN
mV
2.7 < V < 4.6
IN
Feedback Input Current
F
−50
−
−
−
50
20
nA
BICN
Output Voltage Line Regulation at I
= 0 mA (Note 11)
L
mV
OUTN
INE_RN
2.7 < V < 4.6
IN
Output Voltage Line Transient Overshoot (Note 12)
L
−
4
−
mV
dB
INE_TN
Power Supply Ripple Rejection (Notes 9, 13)
1.0 Hz to 1.0 kHz
1.0 kHz to 10 kHz
P
SRRN
−
−
60
40
−
−
Load Regulation (Notes 11, 14)
L
−
−
−
−
0.5
%/100mA
mV
OAD RN
Load Transient Response: Overshoot and Undershoot Vs.
Steady State Voltage (Notes 9, 15)
L
TRN
100
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NCP5810
ELECTRICAL CHARACTERISTICS (Min & Max Limits apply for T between −40°C to +85°C and V between 2.7 V to 4.6 V.
A
IN
Typical values are referenced to T = +25°C and V = 3.7 V, unless otherwise noted)
A
IN
Rating
Symbol
Min
Typ
Max
Unit
Operational Power Supply
V
IN
2.7
−
4.6
V
Internal Oscillator Frequency, T = 25°C, V = 3.7 V
F
OSC
1.6
87
−
1.75
90
−
1.9
−
MHz
%
A
IN
Maximum Duty Cycle
M
DCY
STB
Stand by Current at I
= I
OUTN
= 0 mA, EN = Low
I
2.0
mA
OUTP
V
IN
= 4.2 V, T between 0 to +85°C
A
Quiescent Current @ V
Switching (Note 9)
No Switching
= −5.4 V @ T = +25°C
I
Q
mA
OUTN
A
−
−
1.5
1.0
3.0
−
Soft Start Time to limit the Inrush Current
Thermal Shut Down Protection
Thermal Shut Down Protection Hysteresis
Voltage Input Logic Low
S
−
−
1.0
165
15
−
−
−
ms
°C
°C
V
ST
T
SD
T
SDH
−
−
V
−
0.4
−
IL
Voltage Input Logics High
V
1.2
280
−
V
IH
EN pin Pull Down Resistance
NOTES:
R
ENP
400
670
kW
8. Efficiency is defined by 100 * (Pout / Pin), Vin = 3.1 to 4.2 V, L = VLF3010AT−4R7MR70 (DCR = 280 mW max, Isat = 700 mA), Load = 15
to 30 mA, Voutn = −5.4 V.
9. Guaranteed by design and characterized.
10.Typical application circuit and components depicted Figure 1.
11. Tested at 25°C and guaranteed from −40°C to +85°C by characterization.
12.Line drop and rise between 3.4 to 2.9 V in 50 ms at I
= 25 mA, V
= −5.4 V.
OUT
OUTN
13.Ripple = 0.2 V p−p at 25°C, Cout = 4.7 mF, I
= 0 to 100 mA, V = 3.7 V.
OUT
IN
14.I
from 0 to 100 mA.
OUT
15.Load step 10 to 90 mA and 90 to 10 mA, rising and falling edge in 10 ms, Cout = 4.7 mF, V = 3.7 V.
IN
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NCP5810
TYPICAL OPERATING CHARACTERISTICS
80
70
80
V
IN
= 3.7 V
V
IN
= 4.5 V
70
V
IN
= 2.9 V
V
IN
= 3.7 V
V
IN
= 2.9 V
60
50
60
50
V
OUTN
= −5.4 V
V
OUTN
= −5.4 V
0
50
100
150
(mA)
200
250
0
50
100
150
(mA)
200
250
I
I
OUT
OUT
Figure 3. Efficiency vs. IOUT
Figure 4. Efficiency vs. IOUT, L = MURAWA
L = MURAWA CXFU0208−4R7
CXFU0208−4R7 plus Optional D2 NSR0320MW2
Figure 5. Line Transient Response V
at 100 mA
Figure 6. Line Transient Response V
= −5.4 V,
OUTP
OUTN
1 VBAT, 500 mV/div DC, from 3.5 to 3.0 V in 50 ms
100 mA 1 VBAT, 500 mV/div DC, from 3.5 to 3.0 V in 50 ms
2 VOUTP, 10 mV/div AC, T = 400 ms/div
2 VOUTN, 10 mV/div AC, T = 400 ms/div
Figure 7. Continuous Conduction Mode (CCM)
Figure 8. Discontinuous Current Mode (DCM)
1 SWP, 5 V/div DC, 4 I , 100 mA/div, DC, I
= 100 mA
1 SWP, 5 V/div, DC 4 I , 50 mA/div, DC, I
= 20 mA
LP
OUTP
LP
OUTP
Figures 7 and 8 have been done at VBAT = 3.7 V, V
= −5.4 V
OUTN
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NCP5810
TYPICAL OPERATING CHARACTERISTICS
Figure 9. Continuous Conduction Mode (CCM)
Figure 10. Discontinuous Current Mode (DCM)
1 SWN, 5 V/div DC, 4 I , 100 mA/div, DC, I
= 100 mA
1 SWN, 5 V/div, DC 4 I , 50 mA/div, DC, I
= 20 mA
LN
OUTN
LN
OUTN
Figure 11. Positive Output Voltage Ripple in CCM
Figure 12. Negative Output Voltage Ripple in CCM
1 V
, 10 mV/div AC, 4 I , 100 mA/div DC, I
= 100 mA
1 V
, 10 mV/div AC, 4 I , 100 mA/div DC, I
= 100 mA
OUTP
LP
OUTP
OUTN
LN
OUTN
V
OUTP
V
OUTN
Figure 13. Start−Up After Enable
1 VOUTP, 2 V/div, 2 VOUTN, 2 V/div, 3 EN pin, 2 V/div
Figures 9 through 12 have been done at VBAT = 3.7 V and schematic depict Figure 1
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NCP5810
DETAILED OPERATING DESCRIPTION
Option of powering
V Bat
2.7 to 5.5 V
L1
4.7 mH
CINA
CINP
1 mF
4.7 mF
AVIN
PVIN
AVIN
LXP
SWP
SCHOTTKY
MPO
VOUTP
VOUTP
BAND GAP
1.245 V
THERMAL
TSD
COUTP
4.7 mF
PROTECTION
ENABLE
X5R 10V
True Cut−Off
FBP
FBP
ERROR
AMP
−
MAX DP
1
2
3
4
5
6
7
1.260 V
+
TSD
−
RST
8
OPAMP
MN1
PWM
COMPP
+
Driver
RAMP
COMP
SENSE
CURRENT
SET
ONE
SHOT
+
IPEAK MAX P
IPEAK
COMP
−
Ipeak Max Threshold P
OSC
1.75 Mhz
ENABLE
EN
ENABLE
Ipeak Max Threshold N
PIVIN
−
IPEAK MAX N
400 k
IPEAK
COMP
+
SENSE
NSR0320
D1
CURRENT
SWN
VOUTN
COUTN
MP1
1
2
3
4
5
6
7
FBN
+
ERROR
AMP
FBN
PWM
COMPN
−
RST
8
−
TSD
LX2
4.7 mH
4.7 mF
+
623 mV
X5R 10V
MAX DN
R3
OPAMP
R4
VREF
1.260 V
ONE S
SET
PGND
AGND
AGND
PGND
Figure 14. Functional Block Diagram
Boost Operation
Detailed Descriptions
The internal oscillator provides a 1.75 MHz clock signal
to trigger the PWM controller on each rising edge (SET
signal) which starts a cycle. During this phase the low side
MN1 switch is turned on thus increasing the current
through the inductor L1. The switch current is measured by
the SENSE CURRENT and added to the RAMP COMP
signal. Then PWM COMPP compares the output of the
adder and the signal from ERROR AMP. When the
comparator threshold is exceeded, the MN1 power switch
is turned off until the rising edge of the next clock cycle. In
The NCP5810 is a dual−output DC/DC converter which
can generate both a positive and a negative voltage. The
output voltage of the inverter is fully configurable using
external feedback resistors. The switching regulator
operates at 1.75 MHz which allows the use of small
inductors and ceramic capacitors. The both converters are
internally compensated which simplifies the design and
reduces the PCB component count. Cycle−by−cycle peak
current limit and thermal provide value added features to
protect the device.
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NCP5810
High Output Voltage Accuracy
addition, there are five functions which can reset the
flip−flop logic to switch off the MN1. The MAX DP
monitors the pulse width and if it exceeds 88% (nom) of the
cycle time the switch will be turned off. This limits the
switch from being on for more than one cycle. IPEAK
COMP compares the sensed inductor current with the
IPEAK_MAX threshold set at 700 mA (nom). If the current
exceeds this value, the controller turns off the NMOS
switch for the remainder of the cycle. This is a safety
function to prevent any excessive current that could
overload the inductor and the power stage. The boost
regulator is internally compensated and provides a
minimum of 45° phase margin.
NCP5810 integrates a very accurate internal voltage
reference (1% nom). Combined with the use of precision
feedback resistors, the NCP5810 will achieve highly
precise output voltages.
Excellent Line Transient Rejection and High Power
Supply Rejection Ratio
High output voltage accuracy and signal integrity makes
the NCP5810 the perfect solution for biasing Active Matrix
OLED displays. In order to have a steady, clean display,
OLEDs have to be biased by a very accurate voltage with
high immunity to line and load transients. Both regulators
have been specifically designed with high loop gain and
high phase margin to satisfy the great constraints of
AMOLED driving.
Buck−Boost Inverter Operation
Figure 9 depicts the two intervals of the buck−boost
operation in Continuous Conduction Mode (CCM) in a
simplified way. During the first interval, the internal PMOS
power switch is turned on and the external Schottky diode
is reverse biased. The inductor stores energy through the
battery while the load is supplied by the output capacitor to
maintain regulation. During the second interval, the switch
is turned off and the diode is forward biased, this allows the
energy stored in the inductor to be supplied to both the load
and the capacitor.
The boost converter features a high power supply
rejection ratio of 60 dB (nom).
PSRR is defined by
OutputRipple
VinRipple
* 20LOGǒ
Ǔ
Enable
This input logic allows enabling and disabling the
converter. An active high logic level on this pin enables the
device. A built−in pull−down resistor disables the device if
the pin is left open.
In CCM, the voltage ratio of a buck−boost inverter
converter can be expressed as:
VOUT_N
TON
TSW
D
1 * D
+
where D +
True Shut Down
VIN
When in disable condition, the switch MP0 is turned off
and truly isolates the battery from the output. The True shut
down eliminates the leakage current from the battery to the
load and significantly reduces battery consumption during
disable condition, thus increasing battery life.
The internal oscillator provides a 1.75 MHz clock signal
to trigger the PWM controller on each rising edge (SET
signal) which starts a cycle. During this phase the high side
PMOS switch is turned on thus increasing the current
through the inductor. The switch current is measured by the
SENSE CURRENT and added to the RAMP COMP signal.
Then PWM COMPN compares the output of the adder and
the signal from ERROR AMP. When the comparator
threshold is exceeded, the PMOS power switch is turned off
until the rising edge of the next clock cycle. In addition,
there are five functions which can reset the flip−flop logic
to switch off the NMOS. The MAX DUTY CYCLE COMP
monitors the pulse width and if it exceeds 88% (nom) of the
cycle time the switch will be turned off. This limits the
switch from being on for more than one cycle. IPEAK
COMP compares the sensed inductor current with the
IPEAK_MAX threshold set at 800 mA (nom). If the current
exceeds this value, the controller turns off the PMOS
switch for the remainder of the cycle. This is a safety
function to prevent any excessive current that could
overload the inductor and the power stage. The buck−boost
inverter is internally compensated and provides a
minimum of 45° phase margin.
Inrush Current Limiting Circuitry
Before the NCP5810 boost converter is turned on, it is
unknown whether the output capacitor COUTP is charged
or discharged. If the output capacitor is discharged, a
common boost converter shows high inductor inrush
current at start−up. The internal circuitry of the NCP5810
has been carefully designed to limit the amplitude of the
inrush current at start−up.
Thermal Shutdown
When the IC junction temperature exceeds 165°C (nom),
the power section of the device is disabled. Normal
operation will resume when the junction temperature drops
below 150°C (nom).
Design Procedure
Buck−Boost Inverter Output Voltage Setting
The output voltage of the buck−boost inverter is also
adjusted using external feedback resistors, and can be set
from −2 V down to −15 V. Unlike for the boost converter,
the lower feedback resistor R2 does not use the ground as
a reference but uses the reference voltage (nom 1.265 V).
Sequencing
The sequencing is designed internally. The positive
output first comes up, and then the negative output does.
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NCP5810
R2 is placed between the feedback pin FBN (nom 632 mV)
typically for each DC/DC converter, it is recommended to
use a 4.7 mH low profile inductor. Some recommended
inductors include but are not limited to:
and the reference pin REF. As for the boost converter, the
current flowing out of the feedback resistors must be as low
as possible to ensure high efficiency in low load conditions.
Nevertheless the feedback resistor impedance must not be
too high to keep good voltage accuracy. Therefore it is
recommended to use values in the 10 kW to 100 kW range
for the lower resistor R2. The upper feedback resistor R1
can calculated using the following equation:
TDK: VLF3010AT−4R7MR70 (1.0 mm)
TDK: MLP3216S2R7T (0.6 mm)
SUMIDA: CDH2D09BNP (1.0 mm)
MURAWA CXFU0208−4R7 (0.8 mm)
Schottky Diode Selection
VOUTN * VFBN
An external diode is required for the rectification of the
negative output. The reverse voltage rating of the selected
diode must be equal to or greater than the difference
between the output voltage of the inverter and the input
voltage. The average current rating of the diode must be
greater than the maximum output load current. The peak
current rating must be larger than the maximum peak
inductor current. It is recommended to use a Schottky diode
with lower forward voltage to minimize the power
dissipation and therefore to maximize the efficiency of the
converter.
ǒ
Ǔ
R1 + R2
VFBN * VREF
VREF
2
But : VFBN
+
2 ŤVOUTNŤ
So: R1 + R2
ǒ
1 )
Ǔ
VREF
For example, should one need –5.4 V for V
, if a
OUTN
56 kW 1% is selected of R2, R1 should be selected
according to the following equation:
Also a particular care must be observed for parasitic
capacitance versus reverse voltage and leakage current
versus junction diode temperature. Both parameters are
impacting the efficiency in low load condition and
switching quiescent current.
2 5.4
ǒ
1.265 Ǔ + 536 kW "1%
R1 + 56 1 )
Inductor Selection
Three different electrical parameters need to be
considered when selecting an inductor, the absolute value
of the inductor, the saturation current and the DCR. During
normal operation, the NCP5810 is intended to operate in
Continuous Conduction Mode (CCM). The two equations
below can be used to calculate the peak current for each
converters:
Some recommended Schottky diodes include but are not
limited to:
ON SEMICONDUCTOR: NSR0320MW2
ON SEMICONDUCTOR: RB521S30
ROHM: RSX051VA−30
PHILIPS: PMEG2005AEL
IOUT_P
hP (1 * DP) 2 LP F
VIN DP
IPEAK_P
+
)
Input and Output Capacitors
C
and C
store energy during the T
phase
For the boost converter
OUTP
OUTN
OFF
and sustain the load during the T
phase. In order to
ON
IOUT_N DN
VIN DN
minimize the output ripple, a 4.7 mF low ESR multi−layer
ceramic capacitor type X5R is recommended. To achieve
high performances (signal integrity) two 4.7 mF 6.3 V X5R
IPEAK_N
+
)
hN (1 * DN) 2 LN F
For the buck−boost inverter
should be used to bypass the input supply, C
and C
.
INA
Where V is the battery voltage, I
is the load
INP
IN
OUT_X
Also a particular care must be observed for DC−bias
effects in ceramic capacitor. Actually smaller the case−size
and higher the DC bias voltage, the bigger drop in
capacitance. For a stability viewpoint the percentage drop
in capacitance for the chosen input or output operating
voltage must be limit to 20%.
current, L the inductor value, F the switching frequency,
and D the duty cycle.
X
The global converter efficiency h varies with load
current. A good approximation is to use h = 0.8 from the
boost and h = 0.75 for the buck−boost inverter. It is
important to ensure that the inductor current rating is high
enough such that it not saturate. As the inductor size is
reduced, the peak current for a given set of conditions
increases along with higher current ripple so it is not
possible to deliver maximum output power at lower
inductor values. Finally an acceptable DCR must be
selected regarding losses in the coil and must be lower than
300 mW to limit excessive voltage drop. In addition, as
DCR is reduced, overall efficiency will improve. The
inductor value should range between 2.7 mH and 6.8 mH,
Some recommended capacitors include but are not
limited to:
4.7 mF 6.3 V 0603
TDK: C1608X5R0J475MT
TDK: CGB4B1X5R0J475M (0.5 mm)
4.7 mF 10 V 0805
TDK: C2012X5R1A475MT
MURATA: GRM219R61A475KE
http://onsemi.com
11
NCP5810
ORDERING INFORMATION
Device
†
Package
Shipping
NCP5810MUTXG
LLGA−123x3 mm
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Demo Board Available:
• The NCP5810GEVB/D evaluation board that configures the device in typical application to supply constant voltage.
http://onsemi.com
12
NCP5810
PACKAGE DIMENSIONS
12 PIN LLGA
MU SUFFIX
CASE 513AD
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
D
B
E
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
0.60
0.05
0.30
2X
A
A1
b
0.50
0.00
0.20
0.15
C
2X
D
3.00 BSC
D2
E
E2
e
2.75
3.00 BSC
1.65
0.50 BSC
2.85
0.15
C
TOP VIEW
1.75
K
L
0.20
0.35
−−−
0.45
0.10
0.08
C
C
A
12X
SIDE VIEW
D2
A1
SEATING
PLANE
C
SOLDERING FOOTPRINT*
3.30
12X
0.56
1
e
6
1
0.25
PITCH
0.40
12X K
12X L
E2
2.78
11X
0.28
12
7
12X
0.10 C A
B
1.73
b
0.05
C
NOTE 3
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
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