NCP6922CCMTTXG [ONSEMI]
LDO Regulator, Dual, 4-Channel PMIC, Dual DC-DC Converters;
| 型号： | NCP6922CCMTTXG |
| 厂家： | 
ONSEMI |
| 描述： | LDO Regulator, Dual, 4-Channel PMIC, Dual DC-DC Converters 集成电源管理电路 |
| 文件： | 总42页 (文件大小：2237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP6922C
4 Channels PMIC,
2 x DC-to-DC Converters,
2 x LDOs
The NCP6922C integrated circuit is part of the ON Semiconductor
mini power management IC family (PMIC). It is optimized to supply
battery powered portable application sub−systems such as camera
function, microprocessors. This device integrates 2 high efficiency
800 mA Step−down DC−to−DC converters with DVS (Dynamic
Voltage Scale) and 2 low dropout (LDO) voltage regulators in a
4x4 mm WQFN package.
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MARKING
DIAGRAM
xxxxxx
ALYW
G
Features
WQFN20
CASE 510AV
• 2 DC−to−DC Converters (3 MHz, 1 mH / 10 mF, 800 mA)
♦ Peak Efficiency 95%
♦ Programmable Output Voltage from 0.6 V to 3.3 V by 12.5 mV
Steps
• 2 Low Noise − Low Drop Out Regulators (2.2 mF, 150 mA)
♦ Programmable Output Voltage from 1.0 V to 3.3 V by 50 mV Steps
♦ 50 mVrms Typical Low Output Noise
xxxxxx = 22CB2: NCP6922CB prototype
= 22CC2: NCP6922CC prototype
= 6922CB: NCP6922CB
= 6922CC: NCP6922CC
= 6922CD: NCP6922CD
A
L
= Assembly Location
= Wafer Lot
• Control
Y
W
G
= Year
= Work Week
= Pb−Free Package
2
♦ 400 kHz / 3.4 MHz I C Compatible
2
♦ Independent Enable Pins, I C Enable Control Bits
♦ Power Good Output Pin
♦ Customizable Power Up Sequence
(Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.)
• Extended Input Voltage Range from 2.3 V to 5.5 V
• 82 mA Low Quiescent Current at No Load
• Less than 7 mA Sleep Mode Current
PIN OUT
• Footprint: 4.0 x 4.0 mm WQFN 0.5 mm Pitch
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
20
1
Compliant
Typical Applications
VIN3
PGND2
• Cellular Phones, Tablets
• Digital Cameras
VIN4
PVIN2
ENDCDC2
PVIN1
21
AGND
VOUT4
ENLDO3
ENLDO4
(Thermal Pad)
PGND1
System Supply
NCP6922C
5.0 V
4.7 mF
System Supply
5.0 V
AVIN
1.0 mF
AGND
10
21
PVIN1
4
6
Core
SW1
DCDC1 Out
1.2 V
DCDC1
800 mA
1 mH
FB1
8
5
10 mF
PGND1
Thermal
4.7 mF
System Supply
5.0 V
Protection
PVIN2
2
(Top View)
SW2
20
19
DCDC2 Out
1.2 V
ENDCDC1
ENDCDC2
ENLDO3
9
DCDC2
800 mA
1 mH
FB2
3
12
10 mF
Processor
or System
Supply
PGND2
1
Enabling
PG
ENLDO4 11
PG
15 VIN3
System Supply
5.0 V
ORDERING INFORMATION
LDO3
7
150 mA
16 VOUT3
LDO3 Out
2.5 V
See detailed ordering and shipping information page 40 of this
data sheet.
System
Supply
5.0 V
SDA 17
14 VIN4
2.2 mF
LDO4
2
Processor
I C
SCL
150 mA
18
13
VOUT4
2
LDO4 Out
2.5 V
I C
2.2 mF
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
September, 2019 − Rev. 2
NCP6922C/D
NCP6922C
AVIN
THERMAL
SHUTDOWN
PVIN1
SERIAL
SCL
SDA
DC to DC 1
SW1
INTERFACE
800 mA
STEP−DOWN
CONVERTER
FB1
PGND1
ENDCDC1
ENDCDC2
ENLDO3
PVIN2
DC to DC 2
SW2
CONTROL
800 mA
STEP−DOWN
CONVERTER
FB2
ENLDO4
PG
PGND2
VIN3
LDO3
VOUT3
VIN4
150 mA LDO
UVLO
VREF
OSC
LDO4
VOUT4
AGND
150 mA LDO
Figure 2. Functional Block Diagram
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2
NCP6922C
20
1
VIN3
PGND2
PVIN2
VIN4
21
AGND
(Thermal Pad)
VOUT4
ENLDO3
ENLDO4
ENDCDC2
PVIN1
PGND1
Figure 3. Pin Out (Top View)
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
SUPPLY
10
AVIN
Analog Input
Analog Supply. This pin is the device analog and digital supply. A 1.0 mF ceramic capacitor or larger
must bypass this input to ground. This capacitor should be placed as close as possible to this pin.
21
I/O
9
AGND
Analog Ground
Analog Ground. Analog and digital modules ground. Must be connected to the system ground.
ENDCDC1
ENDCDC2
ENLDO3
ENLDO4
SCL
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital Output
DCDC1 Enable, high level will enable DCDC1; there is internal pull down resistor on this pin.
DCDC2 Enable, high level will enable DCDC2; there is internal pull down resistor on this pin.
LDO3 Enable, high level will enable LDO 3; there is internal pull down resistor on this pin.
LDO4 Enable, high level will enable LDO 4; there is internal pull down resistor on this pin.
3
12
11
18
17
7
2
I C interface Clock
2
SDA
I C interface Data
PG
Power Good open drain output.
DC−DC CONVERTERS
4
6
8
5
PVIN1
Power Input
Power Output
Analog Input
Power Ground
DCDC1 Power Supply. This pin must be decoupled to ground by a 4.7 mF ceramic capacitor.
This capacitor should be placed as close a possible to this pin.
SW1
DCDC1 Switch Power. This pin connects the power transistors to one end of the inductor. Typic-
al application uses 1.0 mH inductor; refer to application section for more information.
FB1
DCDC1 Feedback Voltage. This pin is the input to the error amplifier and must be connected to
the output capacitor.
PGND1
DCDC1 Power Ground. This pin is the power ground and carries the high switching current. A
high quality ground must be provided to prevent noise spikes. A local ground plane is recom-
mended to avoid high−density current flow in a limited PCB track.
2
20
19
1
PVIN2
SW2
Power Input
Power Output
Analog Input
Power Ground
DCDC2 Power Supply. This pin must be decoupled to ground by a 4.7 mF ceramic capacitor.
This capacitor should be placed as close a possible to this pin.
DCDC2 Switch Power. This pin connects the power transistors to one end of the inductor. Typic-
al application uses 1.0 mH inductor; refer to application section for more information.
FB2
DCDC2 Feedback Voltage. This pin is the input to the error amplifier and must be connected to
the output capacitor.
PGND2
DCDC2 Power Ground. This pin is the power ground and carries the high switching current. A
high quality ground must be provided to prevent noise spikes. A local ground plane is recom-
mended to avoid high−density current flow in a limited PCB track.
LDO REGULATORS
15 VIN3
Power Input
LDO3 Power Supply
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NCP6922C
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
LDO REGULATORS
16
14
13
VOUT3
VIN4
Power Output
Power Input
Power Output
LDO3 Output Power. This pin requires a 2.2 mF decoupling capacitor.
LDO4 Power Supply
VOUT4
LDO4 Output Power. This pin requires a 2.2 mF decoupling capacitor.
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Analog and power pins: AVIN, PVIN1, SW1, PVIN2, SW2, VIN3,
VIN4, VOUT3, VOUT4, PG, FB1, FB2
V
A
−0.3 to + 6.0
V
Digital pins: SCL, SDA, ENDCDC1,ENDCDC2, ENLDO3, ENLDO4:
Input Voltage
Input Current
VDG
IDG
−0.3 to VA +0.3 ≤ 6.0
V
mA
10
Human Body Model (HBM) ESD Rating are (Note 1)
Charged Device Model (CDM) ESD Rating are (Note 1)
ESD HBM
ESD CDM
ILU
2000
750
V
V
Latch up Current: (Note 2)
Digital pins
10
mA
All other pins
100
Storage Temperature Range
TSTG
TJMAX
MSL
−65 to + 150
−40 to +150
Level 1
°C
°C
Maximum Junction Temperature
Moisture Sensitivity (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
AV PV
Parameter
Analog and Power Supply
Conditions
Min
2.3
1.7
−40
−40
−
Typ
−
Max
5.5
Unit
V
(Note 12)
IN
IN
LDO
LDO Input Voltage range
−
5.5
V
VIN
T
A
Ambient Temperature Range
25
25
40
+85
+125
−
°C
T
J
Junction Temperature Range (Note 5)
Thermal Resistance Junction to Ambient (Note 6)
°C
R
WQFN−20 on
Demo−board
°C/W
q
JA
P
P
Power Dissipation Rating (Note 7)
T
≤ 85°C
−
−
1000
2125
1
−
−
mW
mW
mH
mF
D
A
Power Dissipation Rating (Note 7)
T = 40°C
A
D
L
Inductor for DC−to−DC converters (Note 4)
Output Capacitor for DC−to−DC Converters (Note 4)
Output Capacitors for LDO (Note 4)
0.47
−
2.2
−
Co
10
1.2
−
2.2
4.7
−
mF
Cin
Input Capacitor for DC−to−DC Converters (Note 4)
−
mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22−A114,
Charged Device Model (CDM) 750 V per JEDEC standard: JESD22−C101.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
4. Refer to the Application Information section of this data sheet for more details.
5. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
6. The R
is dependent of the PCB heat dissipation. Board used to drive this data was a 2″ x 2″ NCP6922CEVB board. It is a multilayer board
q
JA
with 1−once internal power and ground planes and 2−once copper traces on top and bottom of the board.
7. The maximum power dissipation (P ) is dependent by input voltage, maximum output current and external components selected.
D
125 * TA
RqJA
+
PD
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NCP6922C
Table 4. ELECTRICAL CHARACTERISTICS (Min and Max limits apply for T = −40°C to +85°C, AV = PV
= PV
= V
IN3
=
A
IN
IN1
IN
IN2
IN1
V
V
= 5.0 V and default configuration, unless otherwise specified. Typical values are referenced to T = + 25°C, AV = PV
= PV
=
IN4
A
IN2
= V
= 5.0 V and default configuration) (Note 9).
IN3
IN4
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY CURRENT: PINS AVIN – PVIN1 – PVIN2
Operating Quiescent Current
I
Q
mA
DCDCs & LDO4 Off
−
−
−
−
17
36
82
7
30
70
LDO3 on – no load
DCDC1 on – no load – PFM
DCDC2 & LDOs off
DCDCs on – no load – PFM
LDOs on – no load
150
15
I
Sleep Mode Current
All DCDC and LDOs off
mA
SLEEP
DCDC1&2 STEP DOWN CONVERTERS
PV
Input Voltage Range
V
V
V
≤ 2.1 V (Note 11)
2.3
5.0
5.0
−
5.5
5.5
−
IN1,2
OUT
> 2.1 V
V
+0.2V
OUT
OUT
I
Maximum Output Current
Output Voltage DC Error
0.8
A
OUTMAX
D
Forced PWM mode, V range,
−1
−
1
%
VOUT
IN
I
from 0 mA and 100 mA
OUT
Forced PWM mode, VIN range,
IOUT up to I (Note 10)
−1
−1
−
−
1
2
OUTMAX
Auto mode, V range,
IN
(Note 10)
OUTMAX
I
up to I
OUT
F
SW
Switching Frequency
Forced PWM
2.7
3
3.3
MHz
R
P−Channel MOSFET
On Resistance
From PVIN1 / PVIN2 pins to SW1 /
SW2 pins
−
270
400
mW
ONHS
R
N−Channel MOSFET
On Resistance
From SW1 / SW2 pins to PGND1 /
PGND2 pins
−
190
300
mW
ONLS
I
Peak Inductor Current
Load Regulation
Open loop
1.0
−
1.3
5
1.6
−
A
PK
DC
I
from 100 mA to I
OUTMAX
mV/A
%
LOAD
OUT
DC
Line Regulation
PV = PV
to 5.0 V, I = 100 mA
OUT
−
0.5
100
−
−
LINE
IN
INMIN
D
Maximum Duty Cycle
Soft−Start Time
−
−
%
2
t
Time from I C command ACK to 90% of
Output Voltage
−
0.6
ms
START
R
DCDC Active Output
Discharge
−
7
−
W
DISDCDC
LDO3 and LDO4
V
V
LDO3 and LDO4 Input Voltage
V
V
<= 1.5 V, I
= 150 mA
1.7
−
−
5.5
5.5
−
V
IN3, IN4
OUT
OUT
> 1.5 V, I
= 150 mA
Vout+V
V
OUT
OUT
DROP
I
Maximum Output Current
150
−
mA
mA
OUT
I
Short Circuit Protection
(foldback)
V
IN
= 3.6 V
−
70
−
SC
I
Current Limit
V
I
= 3.6 V
= 75 mA
200
−1
−
500
+1
LIMIT
IN
ΔV
Output Voltage Accuracy
%
V
OUT
OUT
NOM
NOM
V
IN
range, I
= 0 mA and 150 mA
−2
V
+2
OUT
(Note 10)
DC
Load Regulation
Line Regulation
I
= 0 mA to 150 mA
−
−
0.5
0.5
−
−
%
%
LOAD
OUT
DC
V
= V
to 5.5 V, I
= 150 mA
LINE
IN
INMIN
OUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
8. Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels to
the V voltage to which the pull−up resistors R are connected.
DD
P
9. Refer to the Application Information section of this data sheet for more details.
10.Guaranteed by design and characterized.
11. Operation above 5.5 V input voltage for extended periods may affect device reliability.
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NCP6922C
Table 4. ELECTRICAL CHARACTERISTICS (Min and Max limits apply for T = −40°C to +85°C, AV = PV
= PV
= V
IN3
=
A
IN
IN1
IN
IN2
IN1
V
V
= 5.0 V and default configuration, unless otherwise specified. Typical values are referenced to T = + 25°C, AV = PV
= PV
=
IN4
A
IN2
= V
= 5.0 V and default configuration) (Note 9).
IN3
IN4
Symbol
LDO3 and LDO4
Dropout Voltage
Parameter
Conditions
Min
Typ
Max
Unit
V
V
V
= V
− 2%, I
= 150 mA
−
95
180
mV
mV
DROP
OUT
NOM
OUT
= 1.15 V, I
= 150 mA
550
−
OUT
OUT
(Driven by V
)
INMIN
PSRR
Ripple Rejection
dB
F = 1 kHz,
OUT
−
−
−65
−55
−
−
I
75% max load, V
=1.8 V
=1.8 V
OUT
F = 10 kHz
75% max load, V
I
OUT
OUT
Noise
10 Hz ³ 100 kHz, V
= 1.8 V
−
−
55
20
−
−
mV
OUT3,4
R
LDO Active Output Discharge
W
DISLDO3,4
ENx
V
High input voltage
Low input voltage
Enable Filter
1.1
−
−
−
−
V
V
IH
V
0.4
18
1.0
IL
EN
PD
t
I
Enable pins rising / falling (Note 10)
4
−
ms
uA
Enable Pins Pull−Down (input
bias current)
−
0.1
POWER GOOD
V
Power Good Low Threshold
Falling edge as a percentage of nominal
output voltage
86
90 of
NOM
95
5
%
PGL
V
V
Power Good detection level
Power Good Reaction Time
0.2
3
%
PGHYS
t
Falling (Note 10)
Rising (Note 10)
−
3
3
−
−
14
ms
RT
V
Power Good low output voltage
Power Good leakage current
I
= 5 mA
−
−
−
−
−
−
0.2
100
5.5
V
nA
V
PGL
PG
PG
3.6V at PG pin when power good valid
Open drain
LK
V
PGH
Power Good high output volt-
age
2
I C
V
High level at SCL/SDA line
SCL, SDA low input voltage
SCL, SDA high input voltage
SCL, SDA low output voltage
−
−
−
−
−
−
−
5.5
0.5
−
V
V
I2CINT
V
SCL, SDA pin (Note 9 and 10)
SCL, SDA pin (Note 9 and 10)
I2CIL
I2CIH
I2COL
V
0.8xV
V
I2CINT
V
I
= 3 mA (Note10)
−
−
0.4
3.4
V
SINK
2
F
I C clock frequency
(Note 10)
MHz
SCL
TOTAL DEVICE
V
Under Voltage Lockout
V
V
falling
rising
−
−
−
2.3
V
UVLO
IN
V
Under Voltage Lockout
Hysteresis
60
200
mV
UVLOH
IN
T
Thermal Shut Down Protection
Warning Rising Edge
150
135
35
°C
°C
°C
SD
T
WARNING
T
Thermal Shut Down Hysteresis
SDHYS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
8. Devices that use non−standard supply voltages which do not conform to the intent I C bus system levels must relate their input levels to
the V voltage to which the pull−up resistors R are connected.
DD
P
9. Refer to the Application Information section of this data sheet for more details.
10.Guaranteed by design and characterized.
11. Operation above 5.5 V input voltage for extended periods may affect device reliability.
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NCP6922C
TYPICAL CHARACTERISTICS
(AV = PV
= PV
= V
= V
= 5.0 V (Unless otherwise noted). T = +25_C, DCDC1 = 1.20 V, DCDC2 = 3.30 V, LDO3 = 1.15 V
IN
IN1
IN2
IN3
IN4
A
LDO4 = 2.5 V, C
= 2.2 mF 0603, L
= 1.0 mF (SPM3012−1R0M) * C
= 10 mF 0603)
LDO
DCDC
DCDC
Figure 4. Efficiency vs ILOAD and VIN VOUT
3.30 V, SPM6530 Inductor
=
=
=
Figure 5. Efficiency vs ILOAD and Temperature
OUT = 3.30 V, SPM6530 Inductor
V
Figure 6. Efficiency vs ILOAD and VIN VOUT
1.20 V, SPM6530 Inductor
Figure 7. Efficiency vs ILOAD and Temperature
OUT = 1.20 V, SPM6530 Inductor
V
Figure 8. Efficiency vs ILOAD and VIN VOUT
0.60 V, SPM6530 Inductor
Figure 9. Efficiency vs ILOAD and Temperature
OUT = 0.60 V, SPM6530 Inductor
V
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NCP6922C
TYPICAL CHARACTERISTICS
(AV = PV
= PV
= V
= V
= 5.0 V (Unless otherwise noted). T = +25_C, DCDC1 = 1.20 V, DCDC2 = 3.30 V, LDO3 = 1.15 V
IN
IN1
IN2
IN3
IN4
A
LDO4 = 2.5 V, C
= 2.2 mF 0603, L
= 1.0 mF (SPM3012−1R0M) * C
= 10 mF 0603)
LDO
DCDC
DCDC
Figure 10. Efficiency vs ILOAD and VIN DCDC1,
OUT = 1.20 V, SPM3012 Inductor
Figure 11. Efficiency vs ILOAD and Temperature
DCDC1, VOUT = 1.20 V, SPM3012 Inductor
V
Figure 12. Efficiency vs ILOAD and VIN DCDC2
Figure 13. Efficiency vs ILOAD and Temperature
DCDC2, VOUT = 1.20 V, SPM3012 Inductor
− VOUT = 1.20 V, SPM3012 Inductor
Figure 14. Efficiency vs ILOAD and VIN DCDC2
Figure 15. Efficiency vs ILOAD and Temperature
DCDC2, VOUT = 3.30 V, SPM3012 Inductor
− VOUT = 3.30 V, SPM3012 Inductor
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NCP6922C
TYPICAL CHARACTERISTICS
(AV = PV
= PV
= V
= V
= 5.0 V (Unless otherwise noted). T = +25_C, DCDC1 = 1.20 V, DCDC2 = 3.30 V, LDO3 = 1.15 V
IN
IN1
IN2
IN3
IN4
A
LDO4 = 2.5 V, C
= 2.2 mF 0603, L
= 1.0 mF (SPM3012−1R0M) * C
= 10 mF 0603)
LDO
DCDC
DCDC
Figure 16. VOUT accuracy (mV) vs ILOAD and
IN DCDC1, VOUT = 1.20 V
Figure 17. VOUT accuracy (%) vs ILOAD and
Temperature DCDC1, VOUT = 1.20 V
V
Figure 18. VOUT accuracy (mV) vs ILOAD and
IN DCDC2, VOUT = 1.20 V
Figure 19. VOUT accuracy (%) vs ILOAD and
Temperature DCDC1, VOUT = 1.20 V
V
Figure 20. VOUT accuracy (mV) vs ILOAD and
IN DCDC2, VOUT = 3.30 V
Figure 21. VOUT accuracy (%) vs ILOAD and
Temperature DCDC2, VOUT = 3.30 V
V
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NCP6922C
TYPICAL CHARACTERISTICS
(AV = PV
= PV
= V
= V
= 5.0 V (Unless otherwise noted). T = +25_C, DCDC1 = 1.20 V, DCDC2 = 3.30 V, LDO3 = 1.15 V
IN
IN1
IN2
IN3
IN4
A
LDO4 = 2.5 V, C
= 2.2 mF 0603, L
= 1.0 mF (SPM3012−1R0M) * C
= 10 mF 0603)
LDO
DCDC
DCDC
Figure 22. DCDC1 HSS RON vs VIN and
Temperature
Figure 23. DCDC1 LSS RON vs VIN and
Temperature
Figure 24. DCDC2 HSS RON vs VIN and
Temperature
Figure 25. DCDC2 LSS RON vs VIN and
Temperature
Figure 26. DCDC1 Switchover Point VOUT
1.20V
=
Figure 27. DCDC2 Switchover Point VOUT
3.30V
=
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NCP6922C
TYPICAL CHARACTERISTICS
(AV = PV
= PV
= V
= V
= 5.0 V (Unless otherwise noted). T = +25_C, DCDC1 = 1.20 V, DCDC2 = 3.30 V, LDO3 = 1.15 V
IN
IN1
IN2
IN3
IN4
A
LDO4 = 2.5 V, C
= 2.2 mF 0603, L
= 1.0 mF (SPM3012−1R0M) * C
= 10 mF 0603)
LDO
DCDC
DCDC
Figure 28. ISLEEP vs VIN and Temperature
Figure 29. IQ LDO3 vs VIN and Temperature
Figure 30. IQ PFM vs VIN and Temperature
Figure 31. IQ PWM vs VIN and Temperature
Figure 32. IQ vs VIN and Temperature
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NCP6922C
TYPICAL CHARACTERISTICS
(AV = PV
= PV
= V
= V
= 5.0 V (Unless otherwise noted). T = +25_C, DCDC1 = 1.20 V, DCDC2 = 3.30 V, LDO3 = 1.15 V
IN
IN1
IN2
IN3
IN4
A
LDO4 = 2.5 V, C
= 2.2 mF 0603, L
= 1.0 mF (SPM3012−1R0M) * C
= 10 mF 0603)
LDO
DCDC
DCDC
Figure 33. VOUT accuracy (mV) vs ILOAD and
IN LDO3, VOUT = 1.15 V
Figure 34. VOUT accuracy (%) vs ILOAD and VIN
LDO3, VOUT = 1.15 V
V
Figure 35. VOUT accuracy (mV) vs ILOAD and
IN LDO3, VOUT = 2.50 V
Figure 36. VOUT accuracy (%) vs ILOAD and VIN
LDO3, VOUT = 2.50 V
V
Figure 37. VOUT accuracy (mV) vs ILOAD and
IN LDO4, VOUT = 2.50 V
Figure 38. VOUT accuracy (%) vs ILOAD and VIN
LDO4, VOUT = 2.50 V
V
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NCP6922C
TYPICAL CHARACTERISTICS
(AV = PV
= PV
= V
= V
= 5.0 V (Unless otherwise noted). T = +25_C, DCDC1 = 1.20 V, DCDC2 = 3.30 V, LDO3 = 1.15 V
IN
IN1
IN2
IN3
IN4
A
LDO4 = 2.5 V, C
= 2.2 mF 0603, L
= 1.0 mF (SPM3012−1R0M) * C
= 10 mF 0603)
LDO
DCDC
DCDC
Figure 39. Load transient response DCDC1
FPWM, VOUT = 1.20 V
Figure 40. Load transient response DCDC2
FPWM, VOUT = 1.20 V
Figure 41. Load transient response DCDC2
FPWM, VOUT = 3.30 V
Figure 42. Load transient response LDO3,
VOUT = 1.35 V
Figure 43. Load transient response LDO3,
Figure 44. Load transient response LDO4,
VOUT = 2.50 V
V
OUT = 2.50 V
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NCP6922C
TYPICAL CHARACTERISTICS
(AV = PV
= PV
= V
= V
= 5.0 V (Unless otherwise noted). T = +25_C, DCDC1 = 1.20 V, DCDC2 = 3.30 V, LDO3 = 1.15 V
IN
IN1
IN2
IN3
IN4
A
LDO4 = 2.5 V, C
= 2.2 mF 0603, L
= 1.0 mF (SPM3012−1R0M) * C
= 10 mF 0603)
LDO
DCDC
DCDC
Figure 45. Ripple voltage in PWM mode
DCDC1, VOUT = 1.35 V, IOUT=200mA
Figure 46. Ripple voltage in PWM mode
DCDC2, VOUT = 1.20 V, IOUT=200mA
Figure 47. Ripple voltage in PWM mode
DCDC2, VOUT = 3.30 V, IOUT=200mA
Figure 48. NCP6922CB Power−up Sequence
All Enable pins high
Figure 49. NCP6922CB power−up sequence
Figure 50. NCP6922CB power−up sequence
ENLDO4 high first then others enable
All ENx after the power up sequence
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NCP6922C
TYPICAL CHARACTERISTICS
(AV = PV
= PV
= V
= V
= 5.0 V (Unless otherwise noted). T = +25_C, DCDC1 = 1.20 V, DCDC2 = 3.30 V, LDO3 = 1.15 V
IN
IN1
IN2
IN3
IN4
A
LDO4 = 2.5 V, C
= 2.2 mF 0603, L
= 1.0 mF (SPM3012−1R0M) * C
= 10 mF 0603)
LDO
DCDC
DCDC
Figure 51. LDO3 PSRR IOUT = 100 mA
Figure 52. LDO3 Noise VIN = 3.8 V, IOUT = 10 mA
Figure 53. LDO4 PSRR IOUT = 100 mA
Figure 54. LDO3 vs LDO4 Noise VIN = 3.8 V,
OUT = 1.8 V, IOUT = 10 mA
V
Figure 55. DCDC PSRR VIN = 3.8V, VOUT
1.2 V, IOUT = 200 mA
=
Figure 56. LDO4 noise with or without DCDC2
LDO4 VOUT = 2.50 V, DCDC2 VOUT = 1.80 V
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NCP6922C
GENERAL DESCRIPTION
circuit is therefore implemented to prevent the part from
being damaged. This protection circuit is only activated
when the core is in active mode (at least one output channel
is enabled). During thermal shutdown, all outputs of the
NCP6922C are off. When the NCP6922C returns from
thermal shutdown mode, it cans re−start in three different
configurations depending on REARM[1:0] bits:
1. If REARM[1:0] = 00 then NCP6922C re−starts
with default register values,
The NCP6922C mini power management integrated
circuit is optimized to supply different sub systems of
battery powered portable applications. The IC can be
supplied directly from the latest technology single cell
batteries such as Lithium−Polymer as well as from triple
alkaline cells. Alternatively, the IC can be supplied from a
pre−regulated supply rail in case of multi−cell or mains
powered applications.
It integrates two switched mode DC−to−DC converters
and two low dropout linear regulators. The IC is widely
programmable through an I C interface and includes low
level IO signaling. An analog core provides the necessary
references for the IC while a digital core ensures proper
control.
The output voltage range, current capabilities and
performance of the switched mode DC−to−DC converters
are well suited to supply the different peripherals in the
system as well as to supply processor cores. To reduce
overall power consumption of the application, Dynamic
Voltage Scaling (DVS) is supported on the DC−to−DC
converters. For PWM operation, the converters run on a
local 3 MHz clock. A low power PFM mode ensures that,
even at low loads, high efficiency can be achieved. All the
switching components are integrated including the
compensation networks and synchronous rectifier. Only a
small size 1 mH inductor and 10 mF bypass capacitor are
required for typical applications.
2. If REARM[1:0] = 01 it re−starts with register
values set prior to thermal shutdown,
3. Finally if REARM[1:0] = 10, NCP6922C does not
re−start automatically, a toggle of HWEN or ENx
pins is needed.
2
In addition, a thermal warning is implemented which can
inform the processor through an interrupt (if not masked)
that NCP6922C is close to its thermal shutdown so that
preventive measurement can be taken by software.
ACTIVE OUTPUT DISCHARGE
Active output discharge can be independently enabled /
disabled by the appropriate settings in the DIS register (refer
to the register definition section). However to prevent any
disturbances on the power−up sequence, a quick active
output discharge is done during the start−up sequence for all
output channels. When the IC is turned off through HWEN
pin (or ENx pins) or AVIN drops down below UVLO
threshold, no shut down sequence is expected, all supplies
are disabled and outputs discharged simultaneously if
discharge enabled.
The general purpose low dropout regulators can be used
to supply the lower power rails in the application. To
improve the overall application standby current, regulators
bias current is very low. The regulators have their own input
supply pin to be able to connect them independently to either
the system supply rail or to the DC−to−DC converter output,
in the application. The regulators are bypassed with a small
size 2.2 mF capacitor.
ENABLING
By default when applying a valid AVIN with all Enable
pins (ENx) low, all supply rails will remain off. Each power
rail can be independently enabled by making the ENx pins
high or by setting the related enable bit in the ENABLE
register, see Table 2. The voltage of the supply rails can be
2
All IC feature can be controlled by I C interface. In
2
programmed through I C before enabling. A built−in
addition to this bus, digital control pins including individual
enable (ENx) and power good (PG) are provided.
pull−down resistor disables supply rail if the corresponding
EN pin is left unconnected.
UNDER VOLTAGE LOCKOUT
Power Up Sequence and ENx
The core does not operate for voltages below the Under
Voltage lock Out (UVLO) level. Below UVLO threshold, all
internal circuitry (both analog and digital) is held in reset.
NCP6922C operation is guaranteed down to VUVLO
when battery voltage is dropping down. To avoid erratic on
/ off behaviour, a maximum 200 mV hysteresis is
implemented. Restart is guaranteed at 2.5 V when VBAT
voltage is recovering or rising up.
When applying a valid AVIN with all ENx pins high, the
part will start up in the default configuration that is factory
programmed. This default configuration determines the
order of enabling and the output voltage.
During the power−up sequence, the state of
a
LDO/DC−to−DC is defined by its corresponding EN pin, its
2
I C EN bit and its TAP position in the sequence. The
LDO/DC−to−DC will be enabled as soon as the sequencer
2
passes its TAP, AND the corresponding EN pin OR I C EN
THERMAL SHUTDOWN
bit is high.
The thermal capabilities of the device can be exceeded
due to the output power capabilities of the on chip step down
converters and low drop out regulators. A thermal protection
Any order and output voltage setting can be factory
programmed upon request.
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NCP6922C
Two different power−up sequences are pre−defined:
Table 5. NCP6922CB POWER UP SEQUENCE
Table 6. NCP6922CC POWER UP SEQUENCE
Default
Vprog
Default Mode −
Default
Vprog
Default Mode −
ON/OFF
ON/OFF
Rail
Sequencer
Rail
Sequencer
DCDC1
DCDC2
LDO3
T2
T1
T2
T1
1.20 V
1.20 V
2.50 V
2.50 V
Forced PWM − OFF
Forced PWM − OFF
OFF
DCDC1
DCDC2
LDO3
T3
T0
T0
T0
1.35 V
3.30 V
1.15 V
2.50 V
Forced PWM − OFF
Auto mode − OFF
OFF
LDO4
OFF
LDO4
OFF
Table 7. NCP6922CD POWER UP SEQUENCE
Default
Vprog
Default Mode −
ON/OFF
Rail
Sequencer
DCDC1
DCDC2
LDO3
T2
T4
T1
T3
1.50 V
1.10 V
1.80 V
3.30 V
Auto Mode − ON
Auto Mode − ON
ON
ON
LDO4
NCP6922CB power−up diagrams are depicted in Figures 57, 58, 59:
AVIN
ENx
Sequencer
T0 T1 T2 T3 T4 T5 T6 T7
DVS ramp
time
600 ms
T17
Tstart
(2 ms)
Bias
time
DCDC1
1.20 V
Init time
160 ms
DVS ramp time
DCDC2
1.20 V
Init time
160 ms
t
VOUT3
2.5 V
Init time
50 ms
VOUT4
2.5 V
Init time
50 ms
Reset
36 ms (18 x Tsequencer)
Figure 57. NCP6922CB Power Up Sequence with All ENx Pins High
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NCP6922C
AVIN
ENLDO4
Other
ENx
Sequencer
(2 ms)
T0 T1 T2 T3 T4 T5 T6 T7
T17
Tstart
Bias
time
DCDC1
1.20 V
600 ms
Init time
160 ms
DCDC2
1.20 V
Init time
160 ms
VOUT3
2.5 V
Init time
50 ms
VOUT4
2.5 V
Init time
50 ms
Reset
36 ms (18 x Tsequencer)
Figure 58. NCP6922CB Power−up Sequence with Only ENLDO4 High First then Others Enable
AVIN
ENx
Sequencer
T0 T1
T17
Tstart
(2 ms)
Bias time
DCDC1
1.20 V
600 ms
Init time
160 ms
DCDC2
1.20 V
Init time
160 ms
VOUT3
2.5 V
Init time
50 ms
VOUT4
2.5 V
Init time
50 ms
Reset
36 ms (18 x Tsequencer)
Figure 59. NCP6922CB Power−up Sequence with All ENx After the Power Up Sequence
2
I C registers can be read and written while ENx pins are
low. By programming the appropriate registers (see registers
description section), the power up sequence can be
modified.
Note that each enable pin has a corresponding sense bit
reflecting the state of the pin: sense bit is 1 when pin is high
(filtered) and 0 when the pin is low (filtered).
Shutdown
Reset to the factory default configuration can be achieved
either by hardware reset (all power supplies removed) or by
writing through the I C in the RESET register.
When shutting down the device (AVIN falls below the
Under Voltage threshold VUVLO), no shut down sequence
is applied. All supplies are disabled and outputs are
discharged simultaneously, and PG open drain output is low.
2
Enable Control
DYNAMIC VOLTAGE SCALING (DVS)
Table 8. TRUTH TABLE OF ENABLE/DISABLE CONTROL
The step down converters support dynamic voltage
scaling (DVS). This means output voltage can be
individually reprogrammed by I C commands to provide
the different voltages required by the processor. Change
between two different voltages is managed in a smooth
manner without disturbing the operation of the processor.
Enable Pin
Enable bit
Output
Disabled
Enabled
Enabled
Enabled
L
L
0
1
0
1
2
H
H
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NCP6922C
When programming a higher voltage, the reference of the
to change DCDCx Output Voltage from 1.2 V to 0.9 V, and
be programmed to 0 to move back from 0.9 V to 1.2 V.
switcher and therefore the output is raised in equidistant
steps per defined time period such that the dV/dt is
controlled (by default 12.5 mV / 1.33 ms). When
programming a lower voltage the output voltage will
decrease accordingly. The DVS step is fixed and the speed
is programmable.
Table 11. VPROGDCDCX / VDVSDCDCX SETTINGS
FOR VDCDCX SWITCHING BETWEEN 1.2 V AND 0.9 V
Register Name
VPROGDCDCx
VDVSDCDCx
Values
0$30
Target VDCDC (V)
1.2
0.9
V2
0$18
Output
Voltage
Internal
Reference
DV
DC−to−DC CONVERTERS AND LDOS POWER GOOD
To indicate the output of a converter is established, a
power good signal is available for each output channel
(routed in the INT_SEN1 register). The power good signal
is high when the channel is off and goes low when enabling
the channel. Once the output voltage reaches the expected
output level, the power good signal becomes high again.
When during operation the output gets below 90% of the
expected level, the power good signal goes low which
indicates a power failure. When the voltage rises again
above 95% the power good signal goes high again.
Dt
V1
Figure 60. Default Dynamic Voltage Scaling Effect
Timing Diagram
Programmability
DC−to−DC converter output voltage can be controlled by
GOx bit (TIME register) with VPROGDCDCx[7:0] and
VDVSDCDCx[7:0] registers. Available output levels are
listed in table VPROGDCDCx[7:0] and VDVSDCDCx[7:0]
in register description.
GOx bit determines whether DC−to−DC output voltage
value is set in VPROGDCDCx[7:0] register or in
VDVSDCDCx[7:0] register.
Note that these PG Sense bits are independent of
PGASSIGN_x and PGGATE_x bits.
ENDCDCx
95%
90%
160 ms
Table 9. GO BIT DESCRIPTION
DCDCx
GOx
Bit Description
3−14 ms 3 ms
3−14 ms
0
1
Output voltage is set to VPROGDCDCx
Output voltage is set to VDVSDCDCx
SEN_PG_DCDCx
The two DVS bits in the TIME register determine the
ramp up time per each voltage step.
Figure 61. DCDCx Channel Internal Power Good
Signal
Table 10. DVS BITS DESCRIPTION
ENLDOx
DVS [1:0]
Bit Description
1.33 ms per step (default)
95%
90%
50 ms
00
01
10
11
LDOx
2.67 ms per step
5.33 ms per step
10.67 ms per step
250 ms 3 ms
250 ms
SEN_PG_LDOx
2
There are two ways of I C registers programming to
switch the DC−to−DC converters output voltages between
different levels:
Figure 62. DCDCx Channel Internal Power Good
Signal
Power Good Assignment and Gating
1. Preset VPROGDCDCx[7:0] and
Each power good sense signal can be individually
assigned to the PG pin through PGASSIGN_x bits of
PGOOD1 register. In addition, 3 other signals can be
assigned to the PG pin: the internal reset signal and the
DCDC DVS signals through the PGOOD1 register. By
assigning the internal reset signal, the PG pin is held low
throughout the power up sequence and the reset period (by
default). By assigning the DVS signal of a converter, the PG
pin is made low during the period the output voltage is being
VDVSDCDCx[7:0] registers, and start DVS
sequence by changing GOx bit state.
2. GOx bit remains unchanged, change output
voltage value in either VPROGDCDCx[7:0] or
VDVSDCDCx[7:0] register.
For example, the device needs to supply either 1.2 V or
0.9 V depending on working conditions. If using method 1,
VPROGDCDCx[7:0] and VDVSDCDCx[7:0] should be set
as shown in Table 11. GOx bit should be programmed to 1
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NCP6922C
raised to the new setting as shown in Figure 63. The PG pin
state is an AND combination of assigned signals.
Moreover PGGATE_x bits of the PGOOD2 register force
the PG pin low when the channel is off.
2
POWER GOOD PIN
I C
The PG pin is an open drain output. By default, the power
good signal of DCDC2 converter and reset signal are
assigned to the PG pin and DCDC2 gates PG pin.
DVS START
DCDCx
95%
FINAL VALUE
of FINAL
VALUE
INITIAL
VALUE
PG
Figure 63. PG Operation in DVS Sequence
ENDCDC1
PGGATE_DCDC1
OR
OR
OR
OR
SEN_PG_DCDC1
PGASSIGN_DCDC1
AND
AND
OR
OR
OR
ENDCDC2
PGGATE_DCDC2
SEN_PG_DCDC2
PGASSIGN_DCDC2
ENLDO3
PGGATE_LDO3
SEN_PG_LDO3
PGASSIGN_LDO3
AND
ENLDO4
PGGATE_LDO4
PG pin
SEN_PG_LDO4
PGASSIGN_LDO4
AND
AND
OR
OR
OR
DCDC1_DVS
PGASSIGN_DVS1
DCDC2_DVS
PGASSIGN_DVS2
RESET
PGASSIGN_RST
OR
Figure 64. PG Pin Description Behavior
in the TIME register. The default delay is 0 ms could be
change upon request
ENDCDC1
DCDC1
ENDCDC2
DCDC2
PG
INTERNAL SIGNAL (RESULT
OF THE ASSIGNED INTERNAL PG)
PG
No Delay
Figure 65. Power Good Behavior in Case of
DCDC2 Monitoring and DCDC2 Gating
Delay Programmed in TOR[2:0]
Power Good Delay
Figure 66. PG Delay
A delay can be programmed between the moment the
AND result of the assigned internal power good signals
becomes high and the moment the PG pin is released. The
delay is set from 0 ms to 512 ms through the TOR[2:0] bits
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NCP6922C
Interrupt
Individual bits generating interrupts will be set to 1 in the
INT_ACK1/INT_ACK2 registers (I C read only registers),
2
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when a
system status change is detected (dual/rising edge
monitoring). The interrupt sources include:
indicating the interrupt source. INT_ACK1/INT_ACK2
2
registers are reset by an I C read. INT_SEN1/INT_SEN2
registers (read only registers) are real time indicators of
interrupt sources.
When the host reads the INT_ACK1/INT_ACK2
registers the interrupt registers INT_ACK1/INT_ACK2 are
cleared.
Table 12. INTERRUPT SOURCES
Interrupt
PG_DCDC1
PG_DCDC2
PG_LDO3
PG_LDO4
UVLO
Description
DCDC1 Converter Power Good (dual edge)
DCDC2 Converter Power Good (dual edge)
LDO3 Power Good (dual edge)
LDO4 Power Good (dual edge)
UVLO state (dual edge)
Figure 67 shows how DCDC1 converter power good
2
produces interrupt with INT_SEN1/INT_ACK1 and I C
read access (assuming no other interrupt happens during this
read period).
IDCDC1
DCDC1 Converter Output Over Current (ris-
ing edge)
IDCDC2
DCDC2 Converter Output Over Current (ris-
ing edge)
ILDO3
ILDO4
WNRG
TSD
LDO3 Output Over Current (dual edge)
LDO4 Output Over Current (dual edge)
Thermal Warning (dual edge)
Thermal Shutdown (dual edge)
PG_DCDC1
INT_SEN1[0]
INT_ACK1[0]
2
read read
read
I C access on INT_ACK1
read
Figure 67. Interrupt Timing Chart Example of PG_DCDC1
Note that each enable pin has a corresponding sense bit
reflecting the state of the pin, without interrupt associated.
Foldback also reduces power dissipation in the load in
fault conditions, which can reduce the risks of fire and heat
damage.
LOW DROP OUT REGULATOR
The LDOs (low drop out regulator) are based on an
embedded PMOS and requires no external stability
components or feedback networks.
The low drop out regulators can be supplied from the
systems supply rail such as a battery or from a step down
convertor as available on the IC itself. The latter case
provides a power efficient line up when the voltage drop
allows such. When the output of the LDO gets out of
regulation, due to for instance a short at the output, an
interrupt is generated and optionally the LDO is
automatically disabled.
Current Limitation
Figure 68. 1.0 V LDO Foldback Current Limit Principe
Both LDOs have foldback current limiter: the goal of the
foldback current limit is to reduce the output voltage and the
current in order to limit the power dissipation (see
Figure 68). Under a short circuit, where the output voltage
has reduced below ~30% nominal value, the current (I ) is
typically limited to a small fraction of the maximum current
DC−to−DC STEP DOWN CONVERTERS
The DC−to−DC converters are synchronous rectifier type
with both high side and low side integrated switches. Neither
external transistor nor diodes are required for proper
operation. Feedback and compensation network are also
fully integrated.
SC
(I
).
LIMIT
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NCP6922C
The DC−to−DC converters can operate in two different
P−MOSFET on−pulse with very small negative current
limit. When load increases and current in inductor becomes
continuous again, the controller automatically turns back to
PWM fixed frequency mode.
modes: PWM and PFM. The transition between PWM/PFM
modes can occur automatically or the switcher can be placed
2
in forced PWM mode by I C programming. (MODEDCDC1
& MODEDCDC2 bits of ENABLE register)
Forced PWM
The DC−to−DC converters can be programmed to only
use PWM and disable the transition to PFM.
PWM (Pulse Width Modulation) Operating Mode
In medium and high load conditions, DC−to−DCs operate
in PWM mode from a fixed clock and adapts its duty cycle
to regulate the desired output voltage. In this mode, the
inductor current is in CCM and the voltage is regulated by
PWM. The internal N−MOSFET switch operates as
synchronous rectifier and is driven complementary to the
P−MOSFET switch. In CCM, the lower switch
(N−MOSFET) in a synchronous converter provides a lower
voltage drop than the diode in an asynchronous converter,
which provides less loss and higher efficiency.
Table 13. MODEDCDC1&2 BIT DESCRIPTION
MODEDCDC1&2
Bit Description
Auto switching PFM / PWM
Forced PWM
0
1
Inductor Peak Current Limitation
During normal operation, peak current limitation will
monitor and limit the current through the inductor. This
current limitation is particularly useful when size and/or
height constrains inductor power
PFM (Pulse Frequency Modulation) Operating Mode
In order to save power and improve efficiency at low loads
the DC−to−DC converters operate in PFM mode as the
inductor drops into DCM (Discontinuous Current Mode).
The upper FET on time is kept constant and the switching
frequency is variable. Output voltage is regulated by varying
the switching frequency which becomes proportional to
loading current. As it does in PWM mode, the internal
N−MOSFET operates as synchronous rectifier after each
Soft Start
A soft start is provided to limit inrush currents when
enabling the converter. After enabling and internal delays
elapsed, the DC to DC converter output will gradually ramp
up to the programmed voltage.
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NCP6922C
2
I C COMPATIBLE INTERFACE
NCP6922C can support a subset of I C protocol, below are detailed introduction for I C programming.
2
2
I2C Communication Description
ON Semiconductor communication protocol is a subset of I C protocol.
2
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
READ OUT
1
0
ACK
ACK
/ACK
START
IC ADRESS
ACK
ACK
DATA n
DATA n
STOP
STOP
DATA 1
DATA 1
FROM PART
1à READ
IC ADRESS
/ACK
ACK
WRITE
INSIDE PART
START
If PART does not Acknolege, the /NACK will be followed by a STOP or Sr.
If PART Acknoleges, the ACK can be followed by another data or Stop or Sr
0à WRITE
Figure 69. General Protocol Description
The first byte transmitted is the Chip address (with LSB
bit sets to 1 for a read operation, or sets to 0 for a Write
operation). Then the following data will be:
• In case of a Write operation, the register address
(@REG) we want to write in followed by the data we
will write in the chip. The writing process is incremental.
So the first data will be written in @REG, the second
one in @REG + 1... The data are optional.
• In case of read operation, the NCP6922C will output
the data out from the last register that has been accessed
by the last write operation. Like writing process,
reading process is an incremental process.
Read Out from Part
The Master will first make a “Pseudo Write” transaction
with no data to set the internal address register. Then, a stop
then start or a Repeated Start will initiate the read transaction
from the register address the initial write transaction has set:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
STETS INTERNAL
REGISTER POINTER
0
REGISTER ADRESS
ACK
ACK STOP
IC ADRESS
0àWRITE
START
START
ACK
/ACK STOP
IC ADRESS
DATA1
ACK
DATA n
1
REGISTER ADRESS
REGISTER ADRESS + (n − 1)
n REGISTERS READ
VALUE
VALUE
1
à
READ
Figure 70. Read Out from Part
The first WRITE sequence will set the internal pointer on the register we want access to. Then the read transaction will start
at the address the write transaction has initiated.
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NCP6922C
Transaction with Real Write then Read:
With Stop Then Start
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
WRITE VALUE IN
REGISTER REG0
WRITE VALUE IN
SETS INTERNAL
REGISTER REG0 + (n − 1)
REGISTER POINTER
REGISTER REG0 ADDRESS
REG + (n − 1) VALUE
ACK STOP
IC ADRESS 0 ACK
REG VALUE
ACK
START
ACK
n REGISTERS WRITE
0àWRITE
1
IC ADRESS
ACK
DATA1
ACK
DATA k
/ACK STOP
START
REGISTER REG + (n − 1)
REGISTER ADRESS + (n − 1) +
VALUE
(k − 1) VALUE
1à READ
k REGISTERS READ
Figure 71. Write Followed by Read Transaction
Write In Part
Write operation will be achieved by only one transaction. After chip address, the MCU first data will be the internal register
we want access to, then following data will be the data we want to write in Reg, Reg + 1, Reg + 2, ...., Reg +n.
Write n Registers:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
WRITE VALUE IN
REGISTER REG0 + (n − 1)
SETS INTERNAL
WRITE VALUE IN
REGISTER REG0
REGISTER POINTER
REGISTER REG0 ADDRESS
0
ACK
STOP
START
IC ADRESS
ACK
ACK
REG VALUE
ACK
REG + (n − 1) VALUE
n REGISTERS WRITE
0
WRITE
à
Figure 72. Write In n Registers
2
I C Address
2
NCP6922C has fixed I C (7 bit address, see below table A7~A1):
Table 14. NCP6922C I2C ADDRESS
2
I C Address
Hex
A7
A6
A5
A4
A3
A2
A1
A0
NCP6922CBMTTXG
W 0x28
R 0x29
0
0
1
0
1
0
0
R/W
Add
0x14
1
−
NCP6922CCMTTXG
NCP6922CDMTTXG
W 0x30
R 0x31
0
0
0
0
1
1
0
0
0
0
0
0
R/W
Add
0x18
1
−
W 0x30
R 0x31
R/W
Add
0x18
−
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NCP6922C
Register Map
2
Following register map describes I C registers.
Registers can be:
R
RC
Read only register
Read then Clear
RW
Read and Write register
RWM
Reserved
Spare
Read, Write and can be modified by the IC
Address is reserved and register is not physically designed
Address is reserved and register is physically designed
Table 15. I2C REGISTER MAP NCP6922CB CONFIGURATION
Address
0x00
Register Name
INT_ACK1
INT_ACK2
INT_SEN1
INT_SEN2
−
Type
RC
RC
R
Default
0x00
Function
Interrupt 1 Register, dual edge
0x01
0x00
Interrupt 2 Register, rising edge and dual edge
Sense 1 Register, real time status
Sense 2 Register, real time status
Reserved, do not access these registers
Reset Register
0x02
0x03
0x03
R
0x00
0x04 to 0x0F
0x10
−
0x00
RESET
RW
R
0x10
0x11
PID
0x0C
Product Identification
0x12
RID / FID
−
R
0x3B
Revision Identification / Features Identification
Reserved, do not access these registers
Enable Register
0x13
−
0x00
0x14
ENABLE
DIS
RWM
RW
RW
RW
RW
RW
−
fuse 0x05
fuse 0x33
fuse 0x42
fuse 0x02
0x00
0x15
Active Output Discharge Register
Power Good Pin Assignment
0x16
PGOOD1
PGOOD2
TIME
0x17
Power Good Pin Gating
0x18
Timing Definition
0x19
SEQUENCER1
−
fuse 0x0A
0x00
Sequencer register for DCDC1 and DCDC2
Reserved, do not access these registers
Sequencer register for LDO3 and LDO4
Reserved, do not access these registers
DCDC1 Output Voltage Setting
DCDC1 DVS Output Voltage Setting
DCDC2 Output Voltage Setting
DCDC2 DVS Output Voltage Setting
Reserved, do not access these registers
LDO3 Output Voltage Setting
0x1A
0x1B
SEQUENCER2
−
−
fuse 0x0A
0x00
0x1C to 0x1F
0x20
−
VPROGDCDC1
VPROGDVS1
VPROGDCDC2
VPROGDVS2
−
RW
RW
RW
RW
−
fuse 0x30
fuse 0x30
fuse 0x30
fuse 0x30
0x00
0x21
0x22
0x23
0x24 to 0x25
0x26
VPROGLDO3
VPROGLDO4
−
RW
RW
−
fuse 0x1E
fuse 0x1E
0x00
0x27
LDO4 Output Voltage Setting
0x28 to 0x3F
Reserved, do not access these registers
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NCP6922C
Table 16. I2C REGISTER MAP NCP6922CC CONFIGURATION
Address
0x00
Register Name
INT_ACK1
INT_ACK2
INT_SEN1
INT_SEN2
−
Type
RC
RC
R
Default
Function
Interrupt 1 Register, dual edge
0x00
0x00
0x01
Interrupt 2 Register, rising edge and dual edge
Sense 1 Register, real time status
Sense 2 Register, real time status
Reserved, do not access these registers
Reset Register
0x02
0x03
0x03
R
0x00
0x04 to 0x0F
0x10
−
0x00
RESET
RW
R
0x10
0x11
PID
0x0C
Product Identification
0x12
RID / FID
−
R
0x3C
Revision Identification / Features Identification
Reserved, do not access these registers
Enable Register
0x13
−
0x00
0x14
ENABLE
DIS
RWM
RW
RW
RW
RW
RW
−
fuse 0x01
fuse 0x33
fuse 0x42
fuse 0x02
0x00
0x15
Active Output Discharge Register
Power Good Pin Assignment
0x16
PGOOD1
PGOOD2
TIME
0x17
Power Good Pin Gating
0x18
Timing Definition
0x19
SEQUENCER1
−
fuse 0x03
0x00
Sequencer register for DCDC1 and DCDC2
Reserved, do not access these registers
Sequencer register for LDO3 and LDO4
Reserved, do not access these registers
DCDC1 Output Voltage Setting
DCDC1 DVS Output Voltage Setting
DCDC2 Output Voltage Setting
DCDC2 DVS Output Voltage Setting
Reserved, do not access these registers
LDO3 Output Voltage Setting
0x1A
0x1B
SEQUENCER2
−
−
fuse 0x00
0x00
0x1C to 0x1F
0x20
−
VPROGDCDC1
VPROGDVS1
VPROGDCDC2
VPROGDVS2
−
RW
RW
RW
RW
−
fuse 0x3C
fuse 0x3C
fuse 0xD8
fuse 0xD8
0x00
0x21
0x22
0x23
0x24 to 0x25
0x26
VPROGLDO3
VPROGLDO4
−
RW
RW
−
fuse 0x03
fuse 0x1E
0x00
0x27
LDO4 Output Voltage Setting
0x28 to 0x3F
Reserved, do not access these registers
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NCP6922C
Table 17. I2C REGISTER MAP NCP6922CD CONFIGURATION
Address
0x00
Register Name
INT_ACK1
INT_ACK2
INT_SEN1
INT_SEN2
−
Type
RC
RC
R
Default
0x00
Function
Interrupt 1 Register, dual edge
0x01
0x00
Interrupt 2 Register, rising edge and dual edge
Sense 1 Register, real time status
Sense 2 Register, real time status
Reserved, do not access these registers
Reset Register
0x02
0x03
0x03
R
0x00
0x04 to 0x0F
0x10
−
0x00
RESET
RW
R
0x10
0x11
PID
0x0C
Product Identification
0x12
RID / FID
−
R
0x2C
Revision Identification / Features Identification
Reserved, do not access these registers
Enable Register
0x13
−
0x00
0x14
ENABLE
DIS
RWM
RW
RW
RW
RW
RW
−
fuse 0xCA
fuse 0x33
fuse 0x73
fuse 0x00
0x00
0x15
Active Output Discharge Register
Power Good Pin Assignment
0x16
PGOOD1
PGOOD2
TIME
0x17
Power Good Pin Gating
0x18
Timing Definition
0x19
SEQUENCER1
−
fuse 0x22
0x00
Sequencer register for DCDC1 and DCDC2
Reserved, do not access these registers
Sequencer register for LDO3 and LDO4
Reserved, do not access these registers
DCDC1 Output Voltage Setting
DCDC1 DVS Output Voltage Setting
DCDC2 Output Voltage Setting
DCDC2 DVS Output Voltage Setting
Reserved, do not access these registers
LDO3 Output Voltage Setting
0x1A
0x1B
SEQUENCER2
−
−
fuse 0x19
0x00
0x1C to 0x1F
0x20
−
VPROGDCDC1
VPROGDVS1
VPROGDCDC2
VPROGDVS2
−
RW
RW
RW
RW
−
fuse 0x48
fuse 0x48
fuse 0x28
fuse 0x28
0x00
0x21
0x22
0x23
0x24 to 0x25
0x26
VPROGLDO3
VPROGLDO4
−
RW
RW
−
fuse 0x10
fuse 0x2E
0x00
0x27
LDO4 Output Voltage Setting
0x28 to 0x3F
Reserved, do not access these registers
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NCP6922C
Registers Description
Table 18. INT_ACK1 REGISTER
Name: INT_ACK1
Address: 0x00
Type: RC
Default: 0x00
D3
D7
D6
D5
D4
D2
D1
D0
spare=0
spare=0
ACK_PG_LDO4
ACK_PG_LDO3
spare=0
spare=0
ACK_PG_DCDC2
ACK_PG_DCDC1
Table 19. BIT DESCRIPTION OF INT_ACK1 REGISTER
Bit
Bit Description
ACK_PG_DCDC1
ACK_PG_DCDC2
ACK_PG_LDO3
ACK_PG_LDO4
ACK_UVLO
DCDC1 Power Good Sense Acknowledgement
0: Cleared
1: DCDC1 Power Good Event detected
DCDC2 Power Good Sense Acknowledgement
0: Cleared
1: DCDC2 Power Good Event detected
LDO3 Power Good Sense Acknowledgement
0: Cleared
1: LDO3 Power Good Event detected
LDO4 Power Good Sense Acknowledgement
0: Cleared
1: LDO4 Power Good Event detected
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected
Table 20. INT_ACK2 REGISTER
Name: INT_ACK2
Address: 0x01
Default: 0x00
Type: RC
D7
D6
D5
D4
D3
D2
D1
D0
ACK_TSD
ACK_WNRG
ACK_ILDO4
ACK_ILDO3
spare=0
ACK_UVLO
ACK_IDCDC2
ACK_IDCDC 1
Table 21. BIT DESCRIPTION OF INT_ACK2 REGISTER
Bit
Bit Description
ACK_IDCDC1
ACK_IDCDC2
ACK_UVLO
ACK_ILDO3
ACK_ILDO4
ACK_WNRG
ACK_TSD
DCDC1 Over Current Sense Acknowledgement
0: Cleared
1: DCDC1 Over Current Event detected
DCDC2 Over Current Sense Acknowledgement
0: Cleared
1: DCDC2 Over Current Event detected
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected
LDO3 Over Current Sense Acknowledgement
0: Cleared
1: LDO3 Over Current Event detected
LDO4 Over Current Sense Acknowledgement
0: Cleared
1: LDO4 Over Current Event detected
Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event detected
Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event detected
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NCP6922C
Table 22. INT_SEN1 REGISTER
Name: INT_SEN1
Address: 0x02
Type: R
Default: 0x00
D3
D7
D6
D5
D4
D2
D1
D0
SEN_ENLDO4
SEN_ENLDO3
SEN_PG_LDO4
SEN_PG_LDO3
SEN_ENDCDC2
SEN_ENDCDC1 SEN_PG_DCDC2 SEN_PG_DCDC1
Table 23. BIT DESCRIPTION OF INT_SEN1 REGISTER
Bit
Bit Description
SEN_PG_DCDC1
SEN_PG_DCDC2
SEN_ENDCDC1
SEN_ENDCDC2
SEN _PG_LDO3
SEN _PG_LDO4
SEN_ENLDO3
DCDC1 Power Good Sense
0: DCDC1 Output Voltage below target
1: DCDC1 Output Voltage within nominal range
DCDC2 Power Good Sense
0: DCDC2 Output Voltage below target
1: DCDC2 Output Voltage within nominal range
ENDCDC1 pin Sense
0: ENDCDC1 pin is low
1: ENDCDC1 pin is high
ENDCDC2 pin Sense
0: ENDCDC2 pin is low
1: ENDCDC2 pin is high
LDO3 Power Good Sense
0: LDO3 Output Voltage below target
1: LDO3 Output Voltage within nominal range
LDO4 Power Good Sense
0: LDO4 Output Voltage below target
1: LDO4 Output Voltage within nominal range
ENLDO3 pin Sense
0: ENLDO3 pin is low
1: ENLDO3 pin is high
SEN_ENLDO4
ENLDO4 pin Sense
0: ENLDO4 pin is low
1: ENLDO4 pin is high
Table 24. INT_SEN2 REGISTER
Name: INT_SEN2
Address: 0x03
Default: 0x00
Type: R
D7
D6
D5
D4
D3
D2
D1
D0
SEN_TSD
SEN_WNRG
SEN_ILDO4
SEN_ILDO3
spare=0
SEN_UVLO
SEN_IDCDC2
SEN_IDCDC1
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NCP6922C
Table 25. BIT DESCRIPTION OF INT_SEN2 REGISTER
Bit
SEN _IDCDC1
Bit Description
DCDC1 Over Current Sense
0: DCDC1 Output Current below limit
1: DCDC1 Output Current over limit
SEN _IDCDC2
SEN _UVLO
SEN _ILDO3
SEN _ILDO4
SEN _WNRG
SEN _TSD
DCDC2 Over Current Sense
0: DCDC2 Output Current below limit
1: DCDC2 Output Current over limit
Under Voltage Sense
0: Input Voltage higher than UVLO threshold
1: Input Voltage lower than UVLO threshold
LDO3 Over Current Sense
0: LDO3 Output Current below limit
1: LDO3 Output Current over limit
LDO4 Over Current Sense
0: LDO4 Output Current below limit
1: LDO4 Output Current over limit
Thermal Warning Sense
0: Junction temperature below thermal warning limit
1: Junction temperature over thermal warning limit
Thermal Shutdown Sense
0: Junction temperature below thermal shutdown limit
1: Junction temperature over thermal shutdown limit
Table 26. RESET REGISTER
Name: RESET
Address: 0x10
Default: 0x10
Type: RW
D7
D6
D5
D4
D3
D2
D1
D0
FORCERST
spare=0
spare=0
RSTSTATUS
spare=0
spare=0
REARM
Table 27. BIT DESCRIPTION OF RESET REGISTER
Bit
Bit Description
REARM[1:0]
Rearming of device after TSD
2
00: Re−arming active after TSD with reset of I C registers: new power−up sequence is initiated with de-
2
fault I C registers values (default)
2
01: Re−arming active after TSD with no reset of I C registers: new power−up sequence is initiated with
2
I C registers values
10: No re−arming after TSD
11: N / A
RSTSTATUS
FORCERST
Reset Indicator Bit
0: Must be written to 0 after register reset
1: Default (loaded after Registers reset)
Force Reset Bit
0: Default
1: Force reset of internal registers to default
Table 28. PID (Product Identification) REGISTER
Name: PID
Type: R
Address: 0x11
Default: 0x0C
D3
D7
D6
D5
D4
D2
D1
D0
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0
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NCP6922C
Table 29. RID/FID: (Revision Identification / Features Identification) REGISTER
Name: RID/FID
Type: R
D7
Address: 0x12
Default: see register map
D6
D5
D4
D3
D2
D1
D0
RID3
RID2
RID1
RID0
FID3
FID2
FID1
FID0
Table 30. BIT DESCRIPTION OF RID/FID REGISTER
Bit
Bit Description
RID[3:0]
Revision Identification
0001: Pass 1.0
0010: Pass 1.1
0011: Production
FID[3:0]
Feature identification
Pass 0.0 (first prototype : NCP6924C)
0000
Pass 1.x
1011: NCP6922CB
1100: NCP6922CC
1101: NCP6922CD
Table 31. ENABLE REGISTER
Name: ENABLE
Address: 0x14
Default: see register map
Type: RWM
D7
D6
D5
D4
D3
D2
D1
D0
ENLDO4
ENLDO3
spare = 0
spare=0
ENDCDC2
MODEDCDC2
ENDCDC1
MODEDCDC1
Table 32. BIT DESCRIPTION OF ENABLE REGISTER
Bit
Bit Description
MODEDCDC1
ENDCDC1
MODEDCDC2
ENDCDC2
ENLDO3
DCDC1 Operating Mode
0: Auto switching PFM / PWM
1: Forced PWM (default)
DCDC1 Enabling
0: Disabled
1: Enabled
DCDC2 Operating Mode
0: Auto switching PFM / PWM
1: Forced PWM (default)
DCDC2 Enabling
0: Disabled
1: Enabled
LDO3 Enabling
0: Disabled
1: Enabled
ENLDO4
LDO4 Enabling
0: Disabled
1: Enabled
Table 33. DIS REGISTER
Name: DIS
Address: 0x15
Default: 0x33
D3
Type: RW
D7
D6
D5
D4
D2
D1
D0
spare=0
spare=0
DISLDO4
DISLDO3
spare=0
spare=0
DISDCDC2
DISDCDC1
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NCP6922C
Table 34. BIT DESCRIPTION OF DIS REGISTER
Bit
Bit Description
DISDCDC1
DISDCDC2
DISLDO3
DISLDO4
DCDC1 Active Output Discharge
0: Disabled
1: Enabled
DCDC2 Active Output Discharge
0: Disabled
1: Enabled
LDO3 Active Output Discharge
0: Disabled
1: Enabled
LDO4 Active Output Discharge
0: Disabled
1: Enabled
Table 35. PGOOD1 REGISTER
Name: PGOOD1
Address: 0x16
Type: RW
Default: 0x42
D3
D7
D6
D5
D4
D2
D1
D0
Spare=0
PGASSIGN_
RST
PGASSIGN_
LDO4
PGASSIGN_
LDO3
PGASSIGN_
DVS2
PGASSIGN_
DVS1
PGASSIGN_
DCDC2
PGASSIGN_
DCDC1
Table 36. BIT DESCRIPTION OF PGOOD1 REGISTER
Bit
Bit Description
PGASSIGN_DCDC1
PGASSIGN_DCDC2
PGASSIGN_DVS1
PGASSIGN_DVS2
PGASSIGN_LDO3
PGASSIGN_LDO4
PGASSIGN_RST
DCDC1 Power Good Assignment
0: Not assigned
1: Assigned to PG pin
DCDC2 Power Good Assignment
0: Not assigned
1: Assigned to PG pin
DCDC1 DVS Assignment
0: Not assigned
1: Assigned to PG pin
DCDC2 DVS Assignment
0: Not assigned
1: Assigned to PG pin
LDO3 Power Good Assignment
0: Not assigned
1: Assigned to PG pin
LDO4 Power Good Assignment
0: Not assigned
1: Assigned to PG pin
Internal Reset Signal Assignment
0: Not assigned
1: Assigned to PG pin
Table 37. PGOOD2 REGISTER
Name: PGOOD2
Address: 0x17
Type: RW
Default: 0x02
D3
D7
D6
D5
D4
D2
Spare=0
D1
PGGATE_DCDC2
D0
Spare=0
Spare=0
PGGATE_LDO4
PGGATE_LDO3
Spare=0
PGGATE_DCDC1
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NCP6922C
Table 38. BIT DESCRIPTION OF PGOOD2 REGISTER
Bit
Bit Description
PGGATE_DCDC1
DCDC1 Power Good Gating
0: DCDC1 state does not gate PG pin
1: DCDC1 state gates PG pin
PGGATE_DCDC2
PGGATE_LDO3
PGGATE_LDO4
DCDC2 Power Good Gating
0: DCDC2 state does not gate PG pin
1: DCDC2 state gates PG pin
LDO3 Power Good Gating
0: LDO3 state does not gate PG pin
1: LDO3 state gates PG pin
LDO4 Power Good Gating
0: LDO4 state does not gate PG pin
1: LDO4 state gates PG pin
Table 39. TIME REGISTER
Name: TIME
Address: 0x18
Type: RW
Default: 0x00
D3
D7
D6
D5
D4
D2
D1
D0
GO2
GO1
spare=0
DVS[1:0]
TOR[2:0]
Table 40. BIT DESCRIPTION OF TIME REGISTER
Bit
Bit Description
TOR[2:0]
Power Good Out of Reset Delay Time (ms)
000: 0(default)
001: 8
010: 16
011: 32
100: 64
101: 128
110: 256
111: 512
DVS[1:0]
DVS Timing (ms)
00: 1.33 ms (default)
01: 2.67 ms
10: 5.33us
11: 10.67us
GO1
GO2
0: DCDC1 Output Voltage set to VPROGDCDC1[7:0]
1: DCDC1 Output Voltage set to VDVSDCDC1[7:0]
0: DCDC2 Output Voltage set to VPROGDCDC2[7:0]
1: DCDC2 Output Voltage set to VDVSDCDC2[7:0]
Table 41. SEQUENCER1 REGISTER
Name: SEQUENCER1
Type: RW
Address: 0x19
Default: see register map
D7
D6
D5
D4
D3
D2
D1
D0
D0
spare=0
spare=0
DCDC2_T[2:0]
DCDC1_T[2:0]
Table 42. SEQUENCER2 REGISTER
Name: SEQUENCER2
Type: RW
Address: 0x1B
Default: see register map
D3 D2
D7
D6
D5
D4
D1
spare=0
spare=0
LDO4_T[2:0]
LDO3_T[2:0]
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NCP6922C
Table 43. START−UP DELAY
LDOx_T[2:0] / DCDCx_T[2:0]
Start−up Delay
000
001
010
011
100
101
110
111
T0
T1
T2
T3
T4
T5
T6
T7
Table 44. VPROGDCDC1[7:0] REGISTER
Name: VPROGDCDC1
Address: 0x20
Default: see register map
Type: RW
D7
D6
D5
D4
D4
D4
D4
D3
D2
D1
D1
D1
D1
D0
D0
D0
D0
VPROGDCDC1[7:0]
Table 45. VDVSDCDC1[7:0] REGISTER
Name: VDVSDCDC1
Address: 0x21
Type: RW
Default: see register map
D7
D6
D5
D3
D2
VDVSDCDC1[7:0]
Table 46. VPROGDCDC2[7:0] REGISTER
Name: VPROGDCDC2
Address: 0x22
Type: RW
Default: see register map
D7
D6
D5
D3
D2
VPROGDCDC2[7:0]
Table 47. VDVSDCDC2[7:0] REGISTER
Name: VDVSDCDC2
Address: 0x23
Type: RW
Default: see register map
D3 D2
D7
D6
D5
VDVSDCDC2[7:0]
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Table 48. VPROGDCDCx[7:0] and VDVSDCDCx[7:0] BIT DESCRIPTION
Bit[7:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
V
(V)
Bit [7:0]
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
V
(V)
Bit [7:0]
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
V
(V)
Bit [7:0]
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
V
(V)
OUT
OUT
OUT
OUT
0.6000
0.6125
0.6250
0.6375
0.6500
0.6625
0.6750
0.6875
0.7000
0.7125
0.7250
0.7375
0.7500
0.7625
0.7750
0.7875
0.8000
0.8125
0.8250
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
1.6125
1.6250
1.6375
1.6500
1.6625
1.6750
1.6875
1.7000
1.7125
1.7250
1.7375
1.7500
1.7625
1.7750
1.7875
1.8000
1.8125
1.8250
1.8375
1.8500
1.8625
1.8750
1.8875
1.9000
1.9125
2.2000
2.2125
2.2250
2.2375
2.2500
2.2625
2.2750
2.2875
2.3000
2.3125
2.3250
2.3375
2.3500
2.3625
2.3750
2.3875
2.4000
2.4125
2.4250
2.4375
2.4500
2.4625
2.4750
2.4875
2.5000
2.5125
2.5250
2.5375
2.5500
2.5625
2.5750
2.5875
2.6000
2.6125
2.6250
2.6375
2.6500
2.6625
2.6750
2.6875
2.7000
2.7125
3.0000
3.0125
3.0250
3.0375
3.0500
3.0625
3.0750
3.0875
3.1000
3.1125
3.1250
3.1375
3.1500
3.1625
3.1750
3.1875
3.2000
3.2125
3.2250
3.2375
3.2500
3.2625
3.2750
3.2875
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
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NCP6922C
Table 48. VPROGDCDCx[7:0] and VDVSDCDCx[7:0] BIT DESCRIPTION
Bit[7:0]
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
V
(V)
Bit [7:0]
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
V
(V)
Bit [7:0]
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
V
(V)
Bit [7:0]
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6
0xF7
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
V
(V)
OUT
OUT
OUT
OUT
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.9250
1.9375
1.9500
1.9625
1.9750
1.9875
2.0000
2.0125
2.0250
2.0375
2.0500
2.0625
2.0750
2.0875
2.1000
2.1125
2.1250
2.1375
2.1500
2.1625
2.1750
2.1875
2.7250
2.7375
2.7500
2.7625
2.7750
2.7875
2.8000
2.8125
2.8250
2.8375
2.8500
2.8625
2.8750
2.8875
2.9000
2.9125
2.9250
2.9375
2.9500
2.9625
2.9750
2.9875
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
3.3000
Table 49. VPROGLDO3[5:0] REGISTER
Name: VPROGLDO3
Address: 0x26
Type: RW
Default: see register map
D3 D2
VPROGLDO3[5:0]
D7
D6
D5
D4
D4
D1
D1
D0
D0
spare=0
spare=0
Table 50. VPROGLDO4[5:0] REGISTER
Name: VPROGLDO4
Address: 0x27
Default: see register map
D3 D2
VPROGLDO4[5:0]
Type: RW
D7
D6
D5
spare=0
spare=0
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NCP6922C
Table 51. VPROGLDOx[5:0] BIT DESCRIPTION
VPROGLDOx
[5:0]
VPROGLDOx
[5:0]
VPROGLDOx
VPROGLDOx
[5:0]
[5:0]
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
V
OUT
(V)
V
OUT
(V)
V
OUT
(V)
V
OUT
(V)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.30
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
3.30
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NCP6922C
APPLICATION INFORMATION
System Supply
5.0 V
NCP6922C
4.7 mF
AVIN
PVIN1
10
21
4
6
System Supply
5.0 V
Core
1.0uF
AGND
SW1
DCDC 1 Out
1.2 V
DCDC 1
800 mA
1 mH
FB1
8
5
10 mF
PGND1
Thermal
Protection
4.7 mF
System Supply
5.0 V
PVIN2
2
SW2
DCDC 2 Out
1.2 V
20
DCDC 2
800 mA
ENDCDC1
ENDCDC2
ENLDO3
ENLDO4
PG
9
1 mH
FB2
3
19
1
10 mF
Processor
or
System
Supply
PGND2
Enabling
PG
12
11
7
15
16
14
13
VIN3
System Supply
5.0 V
LDO 3
150 mA
VOUT3
LDO 3 Out
2.5 V
System
Supply
5.0 V
SDA
17
VIN4
2.2 mF
LDO 4
150 mA
2
I C
Processor
SCL 18
VOUT4
LDO 4 Out
2.5 V
2
I C
2.2 mF
Figure 73. Typical Application Schematic
Inductor Selection
NCP6922C DC−to−DC converters typically use 1 mH
inductor. Use of different values can be considered to
optimize operation in specific conditions. The inductor
parameters directly related to device performances are
saturation current, DC resistance and inductance value. The
inductor ripple current (DIL) decreases with higher
inductance.
With:
• Fsw = Switching Frequency (Typical 3 MHz)
• L = Inductor value
• DI = Peak−To−Peak inductor ripple current
L
• I
= Maximum Inductor Current
LMAX
To achieve better efficiency, ultra low DC resistance
inductor should be selected.
VO
VIN
The saturation current of the inductor should be higher
than the ILMAX calculated with the Equations 1 and 2.
1 *
DIL + VO
(eq. 1)
(eq. 2)
L FSW
DIL
I
LMAX + IOMAX
)
2
Table 52. INDUCTOR L = 1.0 mH
Supplier
TDK
Part #
Size (mm) (L x l x T)
3.2 x 3.0 x 1.2
2.5 x 2.0 x 1.0
2.0 x 1.6 x 1.0
4.0 x 3.5 x 1.8
2.5 x 2.0 x 1.0
2.5 x 2.0 x 1.2
DC Rated Current (A)
DCR Max at 255C (mW)
SPM3012T−1R0M
TFM252010A−1R0M
TFM201610A−1R0M
LQH44PN−1R0NP0
LQM2HPN−1R0MG0
DFE252012C−1R0N
3.4
3.5
2.5
2.5
1.6
3.0
65
65
75
36
69
59
TDK
TDK
MURATA
MURATA
TOKO
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38
NCP6922C
Table 53. INDUCTOR L = 2.2 mH
Supplier
TDK
Part #
Size (mm) (L x l x T)
3.2 x 3.0 x 1.2
2.5 x 2.0 x 1.0
2.0 x 1.6 x 1.0
4.0 x 3.5 x 1.8
2.5 x 2.0 x 1.0
2.5 x 2.0 x 1.2
DC Rated Current (A)
DCR Max at 255C (mW)
SPM3012T−2R2M
TFM252010A−2R2M
TFM201610A−2R2M
LQH44PN−1R0NP0
LQM2HPN−2R2MG0
DFE252012C−2R2N
2.5
2.3
1.7
1.7
1.3
2.0
115
115
200
96
TDK
TDK
MURATA
MURATA
TOKO
100
108
Output Capacitor Selection for DC−to−DC Converters
Selecting the proper output capacitor is based on the
desired output ripple voltage. Ceramic capacitors with low
ESR values will have the lowest output ripple voltage and
are strongly recommended. The output capacitor requires
either an X7R or X5R dielectric.
The output ripple voltage in PWM mode can be estimated by:
V
O
1 * V
IN
1
ǒ
) ESRǓ
DV + V
O
O
L F
2 p C F
SW
O
SW
(eq. 3)
Table 54. RECOMMENDED OUTPUT CAPACITOR FOR DC−to−DC CONVERTERS
Manufacturer
MURATA
MURATA
MURATA
TDK
Part Number
Case Size
0603
HeightTyp. [mm]
C [mF]
10
GRM188R60J106ME47
GRM219R60J106KE19
GRM21BR60J226ME39
C1608X5R0C106K/M
C2012X5R0C106K/M
C2012X5R0C226K/M
0.8
1.25
1.25
0.8
0805
10
0805
22
0603
10
TDK
0805
1.25
1.25
10
TDK
0805
22
Input Capacitor Selection for DCDC Converters
In PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitor
can reduce the peak current transients drawn from the input
supply source, thereby reducing switching noise
significantly.
The maximum RMS current occurs at 50% duty cycle
with maximum output current, which is 1/2 of maximum
output current. A low profile ceramic capacitor of 4.7 mF
should be used for most of the cases. For effective bypass
results, the input capacitor should be placed as close as
possible to PVIN1 and PVIN2 pins.
Table 55. RECOMMENDED INPUT CAPACITOR FOR DC−to−DC CONVERTERS
Supplier
MURATA
MURATA
TDK
Part Number
CaseSize
0603
Height Typ. [mm]
C [mF]
4.7
GRM188R60J475KE
GRM188R60J106ME
C1608X5R0C475K/M
C1608X5R0C106K/M
0.8
0.8
0.8
0.8
0603
10
0603
4.7
TDK
0603
10
Output Capacitor for LDOs
the system is preferred. Input voltage of LDO, should
always be higher than VOUT + VLDODROP (VDROP,
LDO dropout voltage at maximum current).
For stability reason, a typical 2.2 mF ceramic output
capacitor is suitable for LDOs. The LDO output capacitor
should be placed as close as possible to the NCP6922C
output pin.
Capacitor DC Bias Characteristics
Real capacitance of ceramic capacitor changes versus DC
voltage. Special care should be taken to DC bias effect in
order to make sure that the real capacitor value is always
higher than the minimum allowable capacitor value
specified.
Input Capacitor for LDOs
NCP6922C LDOs do not require specific input capacitor.
However, a typical 1 mF ceramic capacitor placed close to
LDOs’ input is helpful for load transient.
Power input of LDO can be connected to main power
supply. However, for optimum efficiency and lower
NCP6922C thermal dissipation, lowest voltage available in
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NCP6922C
PCB layout Recommendation
The high speed operation of the NCP6922C demands
careful attention to board layout and component placement.
To prevent electromagnetic interference (EMI) problems
and reduce voltage ripple of the device, any high current
copper trace which see high frequency switching should be
optimized. Therefore, use short and wide traces for power
current paths and for power ground tracks, power plane and
ground plane are recommended if possible.
Both the inductor and input/output capacitor of
DC−to−DC converters are in the high frequency switching
path where current flow may be discontinuous. These
components should be placed as close to NCP6922C as
possible to reduce parasitic inductance connection. Also it
is important to minimize the area of the switching nodes and
use the ground plane under them to minimize cross−talk to
sensitive signals and ICs. It’s suggested to keep as complete
ground plane under NCP6922C as possible.
PGND and AGND pin connection must be connected to
the ground plane. Care should be taken to avoid noise
interference between PGND and AGND.
It is always good practice to keep the sensitive tracks such
as feedback connection (FB1 / FB2) away from switching
signal connections (SW1 / SW2) by laying the tracks on the
other side or inner layers of PCB.
Figure 74. Recommended PCB Layout
Thermal Considerations
Careful attention must be paid to the power dissipation of
the NCP6922C. The power dissipation is a function of
efficiency and output power. Hence, increasing the output
power requires better components selection. Care should be
taken of LDO VDROP, the larger it is, the higher dissipation
it will bring to NCP6922C. Keep large copper plane under
and close to NCP6922C is helpful for thermal dissipation.
ORDERING INFORMATION
†
Device
Marking
Comment
Package
Shipping
NCP6922CBMTTXG
6922CB
2 x 800 mA DCDC
2 x 150 mA LDO
I C address 0010 100x
(See detailed description)
WQFN – 4 x 4mm
(Pb – Free)
3000 / Tape & Reel
2
NCP6922CCMTTXG
NCP6922CDMTTXG
6922CC
6922CD
2 x 800 mA DCDC
2 x 150 mA LDO
I C address 0011 000x
(See detailed description)
WQFN – 4 x 4mm
(Pb – Free)
3000 / Tape & Reel
3000 / Tape & Reel
2
2 x 800 mA DCDC
2 x 150 mA LDO
I C address 0011 000x
(See detailed description)
WQFN – 4 x 4mm
(Pb – Free)
2
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Demo board available:
• The NCP6922CGEVB/D evaluation board configures the device in typical application to supply constant voltage.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WQFN20, 4x4, 0.5P
CASE 510AV−01
ISSUE O
DATE 22 JUN 2011
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.
A
B
A3
D
EXPOSED Cu
MOLD CMPD
PIN ONE
REFERENCE
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A1
E
DETAIL B
2X
MILLIMETERS
ALTERNATE
DIM MIN
MAX
0.80
0.05
CONSTRUCTIONS
0.15
C
A
A1
A3
b
0.70
0.00
2X
0.20 REF
0.15
C
0.20
0.30
L
L
TOP VIEW
D
4.00 BSC
D2
E
2.60
2.80
4.00 BSC
(A3)
DETAIL B
L1
A
E2
e
2.60
2.80
0.50 BSC
0.20 REF
0.10
0.08
C
K
DETAIL A
L
0.30
0.00
0.50
0.15
ALTERNATE
L1
C
CONSTRUCTIONS
SEATING
PLANE
NOTE 4
A1
GENERIC
C
SIDE VIEW
MARKING DIAGRAM*
0.10 C A B
20
D2
1
DETAIL A
20X L
XXXXXX
6
XXXXXX
ALYWG
G
0.10 C A B
11
E2
1
XXXXXX= Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
20
K
20X b
e
0.10 C A B
0.05
C
NOTE 3
BOTTOM VIEW
(Note: Microdot may be in either location)
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
4.30
20X
0.60
2.80
2.80
1
4.30
PKG
OUTLINE
20X
0.35
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON56888E
WQFN20, 4X4, 0.5P
PAGE 1 OF 1
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