NCP81161MNTBG [ONSEMI]

VR12.5 Compatible Synchronous Buck MOSFET Drivers;
NCP81161MNTBG
型号: NCP81161MNTBG
厂家: ONSEMI    ONSEMI
描述:

VR12.5 Compatible Synchronous Buck MOSFET Drivers

驱动 光电二极管 接口集成电路 驱动器
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NCP81161  
VR12.5 Compatible  
Synchronous Buck MOSFET  
Drivers  
The NCP81161 is a high performance dual MOSFET gate driver  
optimized to drive the gates of both highside and lowside power  
MOSFETs in a synchronous buck converter. It can drive up to 3 nF  
load with a 25 ns propagation delay and 20 ns transition time.  
Adaptive anticrossconduction and power saving operation  
circuit can provide a low switching loss and high efficiency solution  
for notebook and desktop systems. Bidirectional EN pin can provide  
a fault signal to controller when the gate driver fault detect under  
OVP, UVLO occur. Also, an undervoltage lockout function  
guarantees the outputs are low when supply voltage is low.  
http://onsemi.com  
1
DFN8  
MN SUFFIX  
CASE 506AA  
Features  
MARKING DIAGRAM  
Faster Rise and Fall Times  
Adaptive AntiCrossConduction Circuit  
Integrated Bootstrap Diode  
1
A4MG  
G
Pre OV function  
ZCD Detect  
A4 = Specific Device Code  
Floating Top Driver Accommodates Boost Voltages of up to 35 V  
Output Disable Control Turns Off Both MOSFETs  
Undervoltage Lockout  
M
G
= Date Code  
= PbFree Device  
Power Saving Operation Under Light Load Conditions  
ORDERING INFORMATION  
Direct Interface to NCP6151 and Other Compatible PWM  
Controllers  
Device  
Package  
Shipping  
Thermally Enhanced Package  
NCP81161MNTBG  
DFN8  
(PbFree)  
3000 / Tape & Reel  
These Devices are PbFree, Halogen Free/BFR Free and are RoHS  
Compliant  
NCP81161MNTWG  
DFN8  
3000 / Tape & Reel  
(PbFree)  
Typical Applications  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Power Solutions for Desktop Systems  
©
Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
August, 2013 Rev. 2  
NCP81161/D  
NCP81161  
BST  
PWM  
EN  
DRVH  
SW  
1
FLAG  
9
GND  
DRVL  
VCC  
(Top View)  
Figure 1. Pin Diagram  
BST  
VCC  
DRVH  
PWM  
Logic  
SW  
AntiCross  
Conduction  
VCC  
DRVL  
EN  
ZCD  
Detection  
UVLO  
PreOV  
Fault  
Figure 2. Block Diagram  
Table 1. Pin Descriptions  
Pin No.  
Symbol  
Description  
1
BST  
Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin  
and the SW pin.  
2
PWM  
Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode  
Emulation Enabled, High = High Side FET Enabled.  
3
4
5
6
7
8
9
EN  
VCC  
DRVL  
GND  
SW  
Logic input. A logic high to enable the part and a logic low to disable the part.  
Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground.  
Low side gate drive output. Connect to the gate of low side MOSFET.  
Bias and reference ground. All signals are referenced to this node (QFN Flag).  
Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET.  
High side gate drive output. Connect to the gate of high side MOSFET.  
DRVH  
FLAG  
Thermal flag. There is no electrical connection to the IC. Connect to ground plane.  
http://onsemi.com  
2
NCP81161  
12V_POWER  
TP1  
TP2  
+
C4  
R164  
0.0  
Q1  
NTMFS4821N  
0.027uF  
C1  
4.7uF  
C2  
4.7uF  
C3 CE9  
4.7uF 390uF  
R1  
1.02  
R142  
0.0  
NCP81161  
TP3  
R143  
0.0  
VREG_SW1_HG  
VREG_SW1_OUT  
BST HG  
PWM SW  
EN GND  
TP4  
PWM  
TP5  
VCCP  
L
235nH  
TP7  
DRON  
TP6  
R3  
2.2  
Q9 Q10  
NTMFS4851N NTMFS4851N  
VREG_SW1_LG  
VCC LG  
PAD  
CSN11  
CSP11  
JP13_ETCH  
JP14_ETCH  
TP8  
C5  
1uF  
C6  
2700pF  
Figure 3. Application Circuit  
Pin Name  
Table 2. ABSOLUTE MAXIMUM RATINGS  
Pin Symbol  
V
MAX  
V
MIN  
VCC  
BST  
Main Supply Voltage Input  
15 V  
0.3 V  
Bootstrap Supply Voltage  
35 V wrt/ GND  
0.3 V wrt/SW  
40 V 50 ns wrt/ GND  
15 V wrt/ SW  
SW  
Switching Node  
(Bootstrap Supply Return)  
35 V  
40 V 50 ns  
5 V  
10 V (200 ns)  
DRVH  
DRVL  
High Side Driver Output  
BST+0.3 V  
0.3 V wrt/SW  
2 V (<200 ns) wrt/SW  
Low Side Driver Output  
VCC+0.3 V  
0.3 V DC  
5 V (<200 ns)  
PWM  
EN  
DRVH and DRVL Control Input  
Enable Pin  
6.5 V  
6.5 V  
0 V  
0.3 V  
0.3 V  
0 V  
GND  
Ground  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
Table 3. THERMAL INFORMATION (All signals referenced to AGND unless noted otherwise)  
Symbol  
Parameter  
Thermal Characteristic (Note 1)  
Value  
74  
Unit  
°C/W  
°C  
R
q
JA  
T
J
Operating Junction Temperature Range (Note 2)  
Operating Ambient Temperature Range  
Maximum Storage Temperature Range  
Moisture Sensitivity Level  
0 to 150  
10 to +125  
55 to +150  
1
T
A
°C  
T
STG  
°C  
MSL  
* The maximum package power dissipation must be observed.  
2
1. I in Cu, 1 oz thickness.  
2. Operation at 40°C to 10°C guaranteed by design, not production tested.  
http://onsemi.com  
3
 
NCP81161  
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 10°C < T < +125°C; 4.5 V < V < 13.2 V,  
A
CC  
4.5 V < BSTSWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V)  
Parameter  
SUPPLY VOLTAGE  
Test Conditions  
Min.  
Typ.  
Max.  
Units  
VCC Operation Voltage  
Power ON Reset Threshold  
UNDERVOLTAGE LOCKOUT  
VCC Start Threshold  
4.5  
13.2  
3.2  
V
V
2.75  
3.8  
150  
2.1  
4.35  
200  
4.5  
250  
2.4  
V
mV  
V
VCC UVLO Hysteresis  
Output Overvoltage Trip Threshold at  
Startup  
Power Startup time, VCC > POR  
2.25  
SUPPLY CURRENT  
Normal Mode  
Icc + Ibst, EN = 5 V, PWM = OSC, Fsw = 100 KHz,  
Cload = 3 nF for DRVH, 3 nF for DRVL  
10  
mA  
Standby Current  
Standby Current  
Icc + Ibst, EN = GND  
0.5  
2.0  
1.4  
0.6  
mA  
mA  
I
+ I , EN = HIGH, PWM = LOW,  
BST  
CC  
No loading on DRVH & DRVL  
Standby Current  
I
+ I , EN = HIGH, PWM = HIGH,  
2.0  
0.4  
mA  
V
CC  
BST  
No loading on DRVH & DRVL  
BOOTSTRAP DIODE  
Forward Voltage  
V
CC  
= 12 V, forward bias current = 2 mA  
0.1  
PWM INPUT  
PWM Input High  
3.4  
1.3  
V
V
PWM MidState  
2.7  
0.7  
PWM Input Low  
V
ZCD Blanking Timer  
250  
ns  
HIGH SIDE DRIVER (VCC = 12 V)  
Output Impedance, Sourcing Current  
Output Impedance, Sinking Current  
DRVH Rise Time trDRVH  
DRVH Fall Time tfDRVH  
DRVH TurnOff Propagation Delay  
VBST VSW = 12 V  
VBST VSW = 12 V  
1.9  
1.0  
16  
3.0  
1.7  
30  
25  
30  
W
W
V
VCC  
V
VCC  
= 12 V, 3 nF load, VBSTVSW = 12 V  
= 12 V, 3 nF load, VBSTVSW = 12 V  
ns  
ns  
ns  
11  
C
LOAD  
= 3 nF  
8.0  
tpdl  
DRVH  
DRVH TurnOn Propagation Delay  
tpdh  
C
LOAD  
= 3 nF  
30  
ns  
DRVH  
SW Pull Down Resistance  
SW to PGND  
45  
45  
kW  
kW  
DRVH Pull Down Resistance  
DRVH to SW, BSTSW = 0 V  
HIGH SIDE DRIVER (VCC = 5 V)  
Output Impedance, Sourcing Current  
Output Impedance, Sinking Current  
VBST VSW = 5 V  
VBST VSW = 5 V  
2.5  
1.6  
30  
27  
20  
W
W
DRVH Rise Time tr  
V
VCC  
V
VCC  
= 5 V, 3 nF load, VBST VSW = 5 V  
= 5 V, 3 nF load, VBST VSW = 5 V  
ns  
ns  
ns  
DRVH  
DRVH  
DRVH Fall Time tf  
DRVH TurnOff Propagation Delay  
tpdl  
C
LOAD  
= 3 nF  
DRVH  
DRVH TurnOn Propagation Delay  
tpdh  
C
= 3 nF  
27  
45  
ns  
LOAD  
DRVH  
SW Pull Down Resistance  
SW to PGND  
kW  
http://onsemi.com  
4
 
NCP81161  
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 10°C < T < +125°C; 4.5 V < V < 13.2 V,  
A
CC  
4.5 V < BSTSWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V)  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Units  
HIGH SIDE DRIVER (VCC = 5 V)  
DRVH Pull Down Resistance  
DRVH to SW, BSTSW = 0 V  
45  
kW  
LOW SIDE DRIVER (VCC = 12 V)  
Output Impedance, Sourcing Current  
Output Impedance, Sinking Current  
2.0  
0.7  
16  
3.0  
1.5  
35  
20  
35  
W
W
DRVL Rise Time tr  
C
LOAD  
C
LOAD  
C
LOAD  
= 3 nF  
= 3 nF  
= 3 nF  
ns  
ns  
ns  
DRVL  
DRVL  
DRVL Fall Time tf  
11  
DRVL TurnOff Propagation Delay  
tpdl  
DRVL  
DRVL TurnOn Propagation Delay  
tpdh  
C
LOAD  
= 3 nF  
8.0  
30  
ns  
DRVL  
DRVL Pull Down Resistance  
DRVL to PGND, VCC = PGND  
45  
kW  
LOW SIDE DRIVER (VCC = 5 V)  
Output Impedance, Sourcing Current  
Output Impedance, Sinking Current  
2.5  
1.0  
30  
22  
27  
W
W
DRVL Rise Time tr  
C
LOAD  
C
LOAD  
C
LOAD  
= 3 nF  
= 3 nF  
= 3 nF  
ns  
ns  
ns  
DRVL  
DRVL  
DRVL Fall Time tf  
DRVL TurnOff Propagation Delay  
tpdl  
DRVL  
DRVL TurnOn Propagation Delay  
tpdh  
C
= 3 nF  
12  
45  
ns  
LOAD  
DRVL  
DRVL Pull Down Resistance  
EN INPUT  
DRVL to PGND, VCC = PGND  
kW  
Input Voltage High  
2.0  
V
V
Input Voltage Low  
1.0  
Hysteresis  
500  
20  
mV  
mA  
mA  
ns  
Normal Mode Bias Current  
Enable Pin Sink Current  
Propagation Delay Time  
SW Node  
1  
1
4
30  
40  
SW Node Leakage Current  
Zero Cross Detection Threshold Voltage  
20  
mA  
SW to 20 mV, ramp slowly until BG goes off  
(Start in DCM mode) (Note 3)  
6  
mV  
Table 5. DECODER TRUTH TABLE  
PWM INPUT  
ZCD  
ZCD Reset  
DRVL  
DRVH  
PWM High  
Low  
High  
Low  
High  
High  
Low  
Low  
Low  
PWM Mid  
Positive current through the inductor  
Zero current through the inductor  
ZCD Reset  
PWM Mid  
PWM Low  
3. Guaranteed by design; not production tested.  
http://onsemi.com  
5
 
NCP81161  
1V  
1V  
Figure 4.  
PWM  
DRVHSW  
DRVL  
IL  
Figure 5. Timing Diagram  
http://onsemi.com  
6
NCP81161  
APPLICATIONS INFORMATION  
The NCP81161 gate driver is a single phase MOSFET  
turn on of the high–side MOSFET. When the PWM pull  
low, gate DRVH will go low after the propagation delay  
(tpd DRVH).  
The time to turn off the high side MOSFET is depending  
on the total gate charge of the highside MOSFET. A timer  
will be triggered once the high side MOSFET is turn off to  
delay the turn on the lowside MOSFET.  
driver designed for driving Nchannel MOSFETs in a  
synchronous buck converter topology. The NCP81161 is  
designed to work with ON Semiconductor’s NCP6131  
multiphase controller. This gate driver is optimized for  
desktop applications.  
Undervoltage Lockout  
The DRVH and DRVL are held low until VCC reaches  
4.5 V during startup. The PWM signals will control the gate  
status when VCC threshold is exceeded. If VCC decreases to  
250 mV below the threshold, the output gate will be forced  
low until input voltage VCC rises above the startup threshold.  
LowSide Driver Timeout  
In normal operation, the DRVH signal tracks the PWM  
signal and turns off the Q1 highside switch with a few 10  
ns delay (t ) following the falling edge of the input  
pdlDRVH  
signal. When Q1is turned off, DRVL is allowed to go high,  
Q2 turns on, and the SW node voltage collapses to zero. But  
in a fault condition such as a highside Q1 switch  
drainsource short circuit, the SW node cannot fall to zero,  
even when DRVH goes low. This driver has a timer circuit  
to address this scenario. Every time the PWM goes low, a  
DRVL ontime delay timer is triggered.  
PowerOn Reset  
PowerOn Reset feature is used to protect a gate driver  
avoid abnormal status driving the startup condition. When  
the initial softstart voltage is higher than 2.75 V, the gate  
driver will monitor the switching node SW pin. If SW pin  
high than 2.25 V, bottom gate will be force to high for  
discharge the output capacitor. The fault mode will be latch  
and EN pin will force to be low, unless the driver is recycle.  
When input voltage is higher than 4.5 V, and EN goes high,  
the gate driver will normal operation, top gate driver  
DRVH and bottom gate driver will follow the PWM signal  
decode to a status.  
If the SW node voltage does not trigger a lowside  
turnon, the DRVL ontime delay circuit does it instead,  
when it times out with t  
delay. If Q1 is still turned on,  
SW(TO)  
that is, its drain is shorted to the source, Q2 turns on and  
creates a direct short circuit across the VDCIN voltage rail.  
The crowbar action causes the fuse in the VDCIN current  
path to open. The opening of the fuse saves the load (CPU)  
from potential damage that the highside switch short  
circuit could have caused.  
Bidirectional EN Signal  
Fault modes such as PowerOn Reset and Undervoltage  
Lockout will deassert the EN pin, which will pull down  
the DRON pin of controller as well. Thus the controller will  
be shut down consequently.  
Layout Guidelines  
Layout for DCDC converter is very important. The  
bootstrap and VCC bypass capacitors should be placed as  
close as to the driver IC.  
PWM Input and Zero Cross Detect (ZCD)  
Connect GND pin to local ground plane. The ground  
plane can provide a good return path for gate drives and  
reduce the ground noise. The thermal slug should be tied to  
the ground plane for good heat dissipation. To minimize the  
ground loop for low side MOSFET, the driver GND pin  
should be close to the lowside MOSFET source pin. The  
gate drive trace should be routed to minimize the length,  
the minimum width is 20 mils.  
The PWM input, along with EN and ZCD, control the  
state of DRVH and DRVL.  
When PWM is set high, DRVH will be set high after the  
adaptive nonoverlap delay. When PWM is set low, DRVL  
will be set high after the adaptive nonoverlap delay.  
When the PWM is set to the mid state, DRVH will be set  
low, and after the adaptive nonoverlap delay, DRVL will  
be set high. DRVL remains high during the ZCD blanking  
time. When the timer is expired, the SW pin will be  
monitored for zero cross detection. After the detection, the  
DRVL will be set low.  
Gate Driver Power Loss Calculation  
The gate driver power loss consists of the gate drive loss  
and quiescent power loss.  
The equation below can be used to calculate the power  
dissipation of the gate driver. Where QGMFis the total gate  
charge for each main MOSFET and QGSF is the total gate  
charge for each synchronous MOSFET.  
Adaptive Nonoverlap  
The nonoverlap dead time control is used to avoid the  
shoot through damage the power MOSFETs. When the  
PWM signal pull high, DRVL will go low after a  
propagation delay, the controller will monitors the  
switching node (SWN) pin voltage and the gate voltage of  
the MOSFET to know the status of the MOSFET. When the  
low side MOSFET status is off an internal timer will delay  
fSW  
2   n  
ǒ Ǔ  
  nMF   QGMF ) nSF   QGSF ) ICC]   VCC  
PDRV + [  
Also shown is the standby dissipation factor (ICC VCC)  
of the driver.  
http://onsemi.com  
7
NCP81161  
PACKAGE DIMENSIONS  
DFN8 2x2  
CASE 506AA  
ISSUE E  
NOTES:  
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER  
ASME Y14.5M, 1994 .  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. DIMENSION b APPLIES TO PLATED  
TERMINAL AND IS MEASURED BETWEEN  
0.15 AND 0.20 MM FROM TERMINAL TIP.  
4. COPLANARITY APPLIES TO THE EXPOSED  
PAD AS WELL AS THE TERMINALS.  
L1  
PIN ONE  
REFERENCE  
DETAIL A  
E
OPTIONAL  
CONSTRUCTIONS  
MILLIMETERS  
2X  
0.15  
C
DIM MIN  
MAX  
1.00  
0.05  
A
A1  
A3  
b
0.80  
0.00  
0.20 REF  
EXPOSED Cu  
MOLD CMPD  
2X  
0.15  
C
TOP VIEW  
0.20  
0.30  
D
D2  
E
2.00 BSC  
1.10  
1.30  
2.00 BSC  
A
C
DETAIL B  
0.10  
0.08  
C
C
DETAIL B  
E2  
0.70  
0.90  
OPTIONAL  
e
0.50 BSC  
0.30 REF  
CONSTRUCTION  
K
L
L1  
0.25  
−−−  
0.35  
0.10  
(A3)  
A1  
NOTE 4  
SEATING  
PLANE  
SIDE VIEW  
RECOMMENDED  
SOLDERING FOOTPRINT*  
DETAIL A  
8X  
0.50  
D2  
8X  
L
1.30  
4
1
PACKAGE  
OUTLINE  
E2  
0.90  
2.30  
5
8
K
8X b  
e/2  
1
0.10  
0.05  
C
C
A B  
e
8X  
0.30  
0.50  
PITCH  
NOTE 3  
BOTTOM VIEW  
DIMENSIONS: MILLIMETERS  
*For additional information on our PbFree strategy and soldering  
details, please download the ON Semiconductor Soldering and  
MountingTechniques Reference Manual, SOLDERRM/D.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any  
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental  
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over  
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under  
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,  
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death  
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,  
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of  
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
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USA/Canada  
Europe, Middle East and Africa Technical Support:  
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Phone: 81358171050  
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Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
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Fax: 3036752176 or 8003443867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your loca  
Sales Representative  
NCP81161/D  

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