NCP81258HMNTBG [ONSEMI]
MOSFET Driver, VR12 Compatible, Synchronous Buck;
| 型号： | NCP81258HMNTBG |
| 厂家： | 
ONSEMI |
| 描述： | MOSFET Driver, VR12 Compatible, Synchronous Buck |
| 文件： | 总10页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP81258H
Product Preview
Synchronous Buck MOSFET
Driver
The NCP81258H is a high−performance dual MOSFET gate driver
in a small 2 mm x 2 mm package, optimized to drive the gates of both
high−side and low−side power MOSFETs in a synchronous buck
converter. A zero−current detection feature allows for a
high−efficiency solution even at light load conditions. VCC UVLO
ensures the MOSFETs are off when supply voltages are low. A
bi−directional Enable pin provides a fault signal to the controller when
a UVLO fault is detected.
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1
DFN8
MN SUFFIX
CASE 506AA
Features
• Space−efficient 2 mm x 2 mm DFN8 Thermally−enhanced Package
• VCC Range of 4.5 V to 13.2 V
• Internal Bootstrap Diode
MARKING DIAGRAM
1
• 5 V 3−stage PWM Input
CRMG
• Zero Current Detect Function Provides Power Saving Operation
during Light Load Conditions
G
CR = Specific Device Code
• Bi−directional Enable Feature pulls Enable Pin Low during a UVLO
Fault
M
= Date Code
G
= Pb−Free Device
• Pre−OVP Function Protects Load during HS FET Short
(Note: Microdot may be in either location)
• Adaptive Anti−cross Conduction Circuit Protects against
Cross−conduction during FET Turn−on and Turn−off
• Output Disable Control Turns Off Both MOSFETs via Enable Pin
PIN CONNECTIONS
• VCC Undervoltage Lockout
• These Devices are Pb−free, Halogen−free/BFR−free and are RoHS
8
7
6
5
DRVH
SW
BST
PWM
EN
1
2
3
4
Compliant
FLAG
9
Typical Applications
GND
DRVL
• Power Solutions for Notebook and Desktop Systems
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
VCC
(Top View)
ORDERING INFORMATION
†
Device
NCP81258HMNTBG
Package
Shipping
DFN8
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
June, 2017 − Rev. P0
NCP81258H/D
NCP81258H
BST
VCC
DRVH
SW
Logic
PWM
Anti−Cross
Conduction
VCC
DRVL
VCC
EN
VCC UVLO
ZCD Detection
SW
Fault
Figure 1. Simplified Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
BST
Floating bootstrap supply pin for the high−side gate driver. Connect the external bootstrap ca-
pacitor between this pin and SW.
2
3
PWM
EN
Control input:
PWM = High ³ DRVH is high, DRVL is low.
PWM = Mid ³ Zero current detect enabled. Diode emulation mode.
PWM = Low ³ DRVH is low, DRVL is high.
Control input:
EN = High ³ Driver is enabled.
EN = Low ³ Driver is disabled.
4
5
6
7
VCC
DRVL
GND
SW
Power supply input. Connect a bypass capacitor (1 mF) from this pin to ground.
Low−side gate drive output. Connect to the gate of the low−side MOSFET.
Bias and reference ground. All signals are referenced to this node.
Switch node. Connect this pin to the source of the high−side MOSFET and drain of the low−
side MOSFET.
8
9
DRVH
FLAG
High−side gate drive output. Connect to the gate of the high−side MOSFET.
Thermal flag. There is no electrical connection to the IC. Connect to the ground plane.
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NCP81258H
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Min
Max
Main Supply Voltage (Note 1)
VCC
−0.3 V
15 V
16 V (< 50 ns)
Bootstrap Supply Voltage
BST
−0.3 V wrt/SW
35 V wrt/GND
40 V (v 50 ns) wrt/GND
15 V wrt/SW
Switch Node Voltage
SW
−5 V
−10 V (v 200 ns)
35 V
40 V (v 50 ns)
High−Side Driver Output
Low−Side Driver Output
DRVH
DRVL
−0.3 V wrt/SW
−2 V (v 200 ns) wrt/SW
BST + 0.3 V
SW + 15 V (< 80 ns)
−0.3 V
−5 V (v 200 ns)
VCC + 0.3 V
15 V (< 80 ns)
DRVH/DRVL Control Input, Enable Pin
Ground
PWM, EN
GND
−0.3 V
0 V
6.5 V
0 V
Storage Temperature Range
Operating Junction Temperature Range
Moisture Sensitivity Level
T
−55°C
−40°C
150°C
150°C
STG
T
J
MSL
1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, DFN8, 2x2 mm (Note 2)
Thermal Resistance, Junction−to−Air
R
74
°C/W
θJA
2
2
2. Values based on copper area of 645 mm (or 1 in ) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. OPERATING RANGES (Note 3)
Rating
Symbol
Min
4.5
Max
13.2
125
Unit
V
Input Voltage
VCC
Ambient Temperature
T
A
−10
°C
3. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
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NCP81258H
Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.5 V to 13.2 V, BST−SW = 4.5 V to 13.2 V, BST = 4.5 V to 30 V, SW = 0 V to
21 V; for typical values T = 25°C, for min/max values T = −10°C to 125°C; unless otherwise noted. (Notes 4, 5)
A
A
Parameter
SUPPLY VOLTAGE
Test Conditions
Symbol
Min
Typ
Max
Unit
VCC Operation Voltage
Pre−OVP VCC Threshold
UNDERVOLTAGE LOCKOUT
VCC Start Threshold
4.5
13.2
3.2
V
V
2.75
V
V
rising
V
3.8
150
2.1
4.35
200
4.5
250
2.4
V
mV
V
CC
UVLO
V
UVLO_HYS
VCC UVLO Hysteresis
Output Overvoltage Trip Threshold at
Startup
> Pre−OVP VCC Threshold
2.25
CC
SUPPLY CURRENT
Normal Mode
I
+ I , EN = 5 V, PWM = 100 kHz, C
I
normal
12.2
mA
CC
BST
LOAD
= 3 nF for DRVH, 3 nF for DRVL
Shutdown Mode
I
I
+ I , EN = GND
I
shutdown
0.5
2.1
1.9
mA
mA
CC
BST
Standby Current 1
+ I , EN = 5 V, PWM = 0 V, No loading
BST
I
CC
standby1
on DRVH & DRVL
Standby Current 2
I
+ I , EN = 5 V, PWM = 5 V, No loading
I
2.2
0.4
mA
V
CC
BST
standby2
on DRVH & DRVL
BOOTSTRAP DIODE
Forward Voltage
V
= 12 V, Forward bias current = 2 mA
0.1
0.6
CC
PWM INPUT
PWM Input High
PWM
3.4
1.3
V
V
HI
PWM Mid−State
PWM
2.7
0.7
MID
PWM Input Low
PWM
V
LO
ZCD Blanking Timer
250
ns
HIGH−SIDE DRIVER (VCC = 12 V)
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVH Rise Time
(V
(V
– V ) = 12 V
2.0
1.0
16
3.5
2.0
30
25
30
W
W
BST
SW
– V ) = 12 V
BST
SW
V
CC
V
CC
= 12 V, 3 nF load, (V
= 12 V, 3 nF load, (V
– V ) = 12 V
tr
tf
ns
ns
ns
BST
SW
DRVH
DRVH Fall Time
– V ) = 12 V
11
BST
SW
DRVH
DRVH Turn−Off Propagation Delay
C
= 3 nF, [PWM = PWM ] to [V
=
tpdl
DRVH
8
load
LO
DRVH
90%]
DRVH Turn−On Propagation Delay
C
= 3 nF, [V
= 1 V] to [V
−V
=
tpdh
DRVH
30
ns
load
DRVL
DRVH
SW
10%]
SW to PGND
DRVH to SW, (V
SW Pull−down Resistance
DRVH Pull−down Resistance
HIGH−SIDE DRIVER (VCC = 5 V)
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVH Rise Time
37.5
37.5
kW
kW
– V ) = 0 V
BST
SW
(V
(V
– V ) = 5 V
2.5
1.6
30
27
20
W
W
BST
SW
– V ) = 5 V
BST
SW
V
CC
V
CC
= 5 V, 3 nF load, (V
= 5 V, 3 nF load, (V
– V ) = 5 V
tr
tf
ns
ns
ns
BST
SW
DRVL
DRVH Fall Time
– V ) = 5 V
SW
BST
DRVL
DRVH Turn−Off Propagation Delay
C
= 3 nF, [PWM = PWM ] to [V
=
tpdl
DRVL
LOAD
LO
DRVH
90%]
DRVH Turn−On Propagation Delay
SW Pull−down Resistance
C
= 3 nF, [V
= 1 V] to [V
−V
SW
tpdh
DRVL
27
ns
LOAD
DRVL
DRVH
= 10%]
SW to PGND
37.5
kW
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4
NCP81258H
Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.5 V to 13.2 V, BST−SW = 4.5 V to 13.2 V, BST = 4.5 V to 30 V, SW = 0 V to
21 V; for typical values T = 25°C, for min/max values T = −10°C to 125°C; unless otherwise noted. (Notes 4, 5)
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
HIGH−SIDE DRIVER (VCC = 5 V)
DRVH Pull−down Resistance
LOW−SIDE DRIVER (VCC = 12 V)
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVL Rise Time
DRVH to SW, (V
– V ) = 0 V
37.5
kW
BST
SW
V
CC
V
CC
V
CC
V
CC
= 12 V
2.0
0.7
16
3.5
1.8
35
20
35
W
W
= 12 V
= 12 V, C
= 12 V, C
= 3 nF
= 3 nF
tr
tf
ns
ns
ns
LOAD
DRVL
DRVL Fall Time
11
LOAD
DRVL
DRVL Turn−Off Propagation Delay
C
= 3 nF, [PWM = PWM ] to [V
=
tpdl
DRVL
LOAD
HI
DRVL
90%]
DRVL Turn−On Propagation Delay
C
= 3 nF, [V
−V ] = 1 V to [V
tpdh
DRVL
8
30
ns
LOAD
DRVH
SW
DRVL
= 10%]
DRVL Pull−down Resistance
LOW−SIDE DRIVER (VCC = 5 V)
Output Impedance, Sourcing Current
Output Impedance, Sinking Current
DRVL Rise Time
DRVL to GND, VCC = GND
37.5
kW
V
CC
V
CC
V
CC
V
CC
= 5 V
2.5
1.0
30
22
27
W
W
= 5 V
= 5 V, C
= 5 V, C
= 3 nF
= 3 nF
tr
tf
ns
ns
ns
LOAD
DRVL
DRVL Fall Time
LOAD
DRVL
DRVL Turn−Off Propagation Delay
C
= 3 nF, [PWM = PWM ] to [V
=
tpdl
DRVL
LOAD
HI
DRVL
90%]
DRVL Turn−On Propagation Delay
C
= 3 nF, [V
−V
SW
= 1 V] to [V
tpdh
DRVL
12
ns
LOAD
DRVH
DRVL
= 10%]
DRVL Pull−down Resistance
EN INPUT
DRVL to GND, VCC = GND
37.5
kW
Enable Voltage High
Enable Voltage Low
Hysteresis
EN
2.0
V
V
HI
EN
1.0
LO
500
mV
mA
mA
ms
Normal Bias Current
Enable Pin Sink Current
EN High Propagation Delay Time
−1
4
1
30
60
PWM = 0 V, EN going from 0 V to EN to
tpd
EN_HI
HI
DRVL rising to 10%
SWITCH NODE
SW Node Leakage Current
20
mA
Zero Cross Detection Threshold Volt-
age
Ramp slowly until DRVL goes off (start in
DCM mode)
−3
mV
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
6. Values based on design and/or characterization.
Table 6. ZCD DECODER TRUTH TABLE
PWM Input
PWM High
ZCD
DRVL
Low
DRVH
High
Low
ZCD Reset
PWM Mid (positive current)
PWM Mid (negative current)
PWM Low
Positive current through the inductor
Zero current through the inductor (after ZCD blanking timer)
ZCD Reset
High
Low
Low
High
Low
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5
NCP81258H
12V_POWER
VIN
R2
0.0
C2
0.1 uF
Q1
C4
C5
C6
4.7 uF 4.7 uF 4.7 uF 390 uF
C7
R1
1.02
NCP81258
R3
0.0
DRVH
SW
BST
PWM
EN
L
VCCP
PWM
235 nH
Q2
Q3
R4
2.2
DRON
C3
2700 pF
DRVL
VCC
C1
1 uF
PAD
Figure 2. Application Circuit
PWM
DRVL
tpdlDRVL tfDRVL
90%
1 V
90%
10%
tpdhDRVH trDRVH
10%
tpdlDRVH
90%
trDRVL
tfDRVH
90%
10%
tpdhDRVL
10%
1 V
DRVH−
SW
Figure 3. Gate Timing Diagram
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NCP81258H
PWM
DRVH−SW
DRVL
IL
Figure 4. PWM/EN Logic Diagram
APPLICATIONS INFORMATION
The NCP81258H gate driver is a single−phase MOSFET
driver designed for driving N−channel MOSFETs in a
synchronous buck converter topology.
(MLCC) with a value greater than 100 nF should be used for
C
.
BST
Power Supply Decoupling
The NCP81258H can source and sink relatively large
currents to the gate pins of the MOSFETs. In order to
maintain a constant and stable supply voltage, a low−ESR
capacitor should be placed near the VCC and GND pins. A
MLCC between 1 mF and 4.7 mF is typically used.
Low−Side Driver
The low−side driver is designed to drive
ground−referenced low−R N−channel MOSFET. The
voltage supply for the low−side driver is internally
connected to the VCC and GND pins.
a
DS(on)
High−Side Driver
Undervoltage Lockout
The high−side driver is designed to drive a floating
DRVH and DRVL are low until VCC reaches the VCC
UVLO threshold, typically 4.35 V. Once VCC reaches this
threshold, the PWM signal will control DRVH and DRVL.
There is a 200 mV hysteresis on VCC UVLO. There are
pull−down resistors on DRVH, DRVL and SW to prevent the
gates of the MOSFETs from accumulating enough charge to
turn on when the driver is powered off.
low−R
N−channel MOSFET. The gate voltage for the
DS(on)
high−side driver is developed by a bootstrap circuit
referenced to the SW pin.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor. When the NCP81258H
is starting up, the SW pin is held at ground, allowing the
bootstrap capacitor to charge up to VCC through the
bootstrap diode. When the PWM input is driven high, the
high−side driver will turn on the high−side MOSFET using
the stored charge of the bootstrap capacitor. As the high−side
MOSFET turns on, the SW pin rises. When the high−side
MOSFET is fully turned on, SW will settle to VIN, and BST
will settle to VIN + VCC (excluding parasitic ringing).
Pre−Overvoltage Protection
The pre−Overvoltage Protection (pre−OVP) feature is
used to protect the load if there is a short across the high−side
FET. When VCC is greater than 2.75 V, the voltage on SW
is monitored. During startup, if SW is determined to be
greater than Output Overvoltage Trip Threshold, DRVL will
be latched high to turn on the synchronous FET and provide
a path from VIN to ground. This also pulls the EN pin low.
To exit this behavior, power to the driver must be turned off
Bootstrap Circuit
The bootstrap circuit relies on an external charge storage
capacitor (C ) and an integrated diode to provide current
(VCC less than V
minus V ) and then VCC
UVLO_HYS
BST
UVLO
to the high−side driver. A multi−layer ceramic capacitor
powered back on. When VCC rises above V
and EN is
UVLO
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NCP81258H
above EN , the gate driver enters normal PWM operation
tpdh
from the time DRVH – SW falls to 1 V, before
HI
DRVL
if SW is no longer above the Output Overvoltage Trip
Threshold.
DRVL is allowed to turn on.
When PWM enters the mid−state voltage range,
PWM
, DRVL goes high after the non−overlap delay, and
MID
Bi−Directional EN Signal
The Enable pin (EN) is used to disable the DRVH and
DRVL outputs to prevent power transfer. When EN is above
stays high for the duration of the ZCD blanking timer and an
80 ns de−bounce timer. Once these timers expire, SW is
monitored for zero current detection and pulls DRVL low
once zero current is detected.
the EN threshold, DRVH and DRVL change their states
HI
according to the PWM input. A UVLO fault turns on the
internal MOSFET that pulls the EN pin towards ground. By
connecting EN to the DRON pin of a controller, the
controller is alerted when the driver encounters a fault
condition.
Every time EN is brought from a low to a high state, the
NCP81258H conducts an auto−calibration cycle on the ZCD
SW threshold. During the auto−calibration cycle, the driver
outputs are prevented from responding to the PWM input,
and both outputs are in the low state. This auto−calibration
cycle is guaranteed to complete by 60 ms.
Thermal Considerations
As power in the NCP81258H increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCP81258H has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCP81258H can handle is given by:
Three−State PWM Input
ƪT
ƫ
J(MAX) * TA
Switching PWM between logic−high and logic−low states
will allow the driver to operate in continuous conduction
mode as long as VCC is greater than the UVLO threshold
and EN is high. The threshold limits are specified in the
electrical characteristics table in this datasheet. Refer to
Figure 21 for the gate timing diagrams and Table 1 for the
EN/PWM logic table.
PD(MAX)
+
(eq. 1)
RqJA
Since T is not recommended to exceed 150°C, the
NCP81258H, soldered on to a 645 mm copper area, using
1 oz. copper and FR4, can dissipate up to 2.3 W when the
ambient temperature (T ) is 25°C. The power dissipated by
the NCP81258H can be calculated from the following
equation:
J
2
A
When PWM is set above PWM , DRVL will first turn off
HI
after a propagation delay of tpdl . To ensure
DRVL
(eq. 2)
non−overlap between DRVL and DRVH, there is a delay of
tpdh from the time DRVL falls to 1 V, before DRVH is
ǒ
ƪ n
Ǔ
standbyƫ
P
[ VCC
D
Qg ) n Qg
f ) I
DRVH
HS
HS
LS
LS
allowed to turn on.
When PWM falls below PWM , DRVH will first turn
Where n and n are the number of high−side and
low−side FETs, respectively, Qg and Qg are the gate
charges of the high−side and low−side FETs, respectively
and f is the switching frequency of the converter.
HS
LS
LO
HS
LS
off after a propagation delay of tpdl
. To ensure
DRVH
non−overlap between DRVH and DRVL, there is a delay of
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE F
DATE 04 MAY 2016
1
SCALE 4:1
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
MILLIMETERS
2X
0.10
C
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
2.00 BSC
A3
2X
0.10
C
EXPOSED Cu
MOLD CMPD
TOP VIEW
0.30
D
D2
E
E2
e
K
L
L1
1.10
2.00 BSC
0.70
0.50 BSC
0.30 REF
0.25
−−−
1.30
A
C
DETAIL B
0.10
0.08
C
C
A1
0.90
DETAIL B
ALTERNATE
0.35
0.10
CONSTRUCTIONS
(A3)
A1
NOTE 4
SEATING
PLANE
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
8X
0.50
D2
1.30
8X
L
PACKAGE
OUTLINE
4
5
1
E2
0.90
2.30
8
K
8X b
1
e/2
e
0.10
0.05
C
C
A
B
8X
0.30
0.50
PITCH
NOTE 3
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
1
XXMG
G
XX = Specific Device Code
M
= Date Code
G
= Pb−Free Device
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON18658D
DFN8, 2.0X2.0, 0.5MM PITCH
PAGE 1 OF 1
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