NCP81599MNTXG [ONSEMI]
I2C Configurable, 4-Switch Buck Boost Controller for USB-PD Power Delivery and Type-C Applications;
| 型号： | NCP81599MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | I2C Configurable, 4-Switch Buck Boost Controller for USB-PD Power Delivery and Type-C Applications 光电二极管 |
| 文件： | 总33页 (文件大小：1499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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USB Power Delivery
4-Switch Buck Boost
Controller
32
1
32
1
QFN32 5x5, 0.5P
CASE 485CE
(NCP81599)
QFNW32 5x5, 0.5P
CASE 484AB
(NCV81599)
NCV81599, NCP81599
The NCV81599 USB Power Delivery (PD) Controller is a
synchronous buck boost that is optimized for converting battery
voltage or adaptor voltage into power supply rails required in
notebook, tablet, and desktop systems, as well as many other
consumer devices using USB PD standard and C−Type cables. The
NCV81599 is fully compliant to the USB Power Delivery
Specification when used in conjunction with a USB PD or C−Type
Interface Controller. NCV81599 is designed for applications requiring
dynamically controlled slew rate limited output voltage that require
either voltage higher or lower than the input voltage. The NCV81599
drives 4 NMOSFET switches, allowing it to buck or boost and support
the functions specified in the USB Power Delivery Specification
which is suitable for all USB PD applications. The USB PD Buck
Boost Controller operates with a supply and load range of 4.5 V to
32 V.
MARKING DIAGRAM
1
NCx81599
AWLYYWWG
G
NCx81599 = Specific Device Code
x
A
= V or P
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
(Note: Microdot may be in either location)
Features
Typical Application
• Wide Input Voltage Range:
from 4.5 V to 32 V for NCV81599
from 4.5 V to 28 V for NCP81599
• Automotive USB Charging Ports
• Wireless Charging
• Consumer Electronics
• Dynamically Programmed Frequency from 150 kHz to 1.2 MHz
2
• I C Interface
• Real Time Power Good Indication
• Controlled Slew Rate Voltage Transitioning
• Feedback Pin with Internally Programmed Reference
• Support USBPD/QC2.0/QC3.0 Profile
• 2 Independent Current Sensing Inputs
• Over Temperature Protection
• Adaptive Non−Overlap Gate Drivers
• Audible Range Switching Frequency Avoidance
• Over−Voltage and Over−Current Protection
• AEC−Q100 Qualified (NCV81599)
• 5 x 5 mm QFN32 Package
ORDERING INFORMATION
†
Device
Package
Shipping
NCV81599MWTXG
QFN32
(Pb−Free)
5000 / Tape & Reel
NCP81599MNTXG
QFN32
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation
and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
NCV81599/D
October, 2022 − Rev. 5
NCV81599, NCP81599
V1
V2
V1
VCCD
VDRV
CVCCD
CSP1
RS1
Q6
VBUS
CVDRV
CSN1
RVCCD
RDRV
RPU
FB
CO1
VCC
CSN2
RS2
CVCC
RPD
CSP2
V2
Current Sense 1
Current Sense 2
CS1
CS2
RCS1
BST2
BST1
RCS2
S1
CB1
CB2
S4
Curret Limit Indicator
Interrupt
CLIND
INT
HSG1
VSW1
HSG2
VSW2
Enable
EN
L1
SDA
SCL
ADDR
I2C
S2
LSG1
PGND1
COMP
S3
RADDR
LSG2
PGND2
RC
CP
AGND
THPAD
PDRV
CC
Figure 1. Typical Application Circuit
32 31 30 29 28 27 26 25
1
24
23
22
21
20
19
18
17
HSG1
LSG1
PGND1
CSN1
CSP1
V1
HSG2
2
3
4
5
6
7
8
LSG2
PGND2
CSP2
CSN2
FB
Exposed Thermal Pad
(THPAD)
CS1
CS2
CLIND
PDRV
9
10 11 12 13 14 15 16
Figure 2. Pinout
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2
NCV81599, NCP81599
_
+
OV1_th
v1_OVLO
ADDR
V1
V1
I2C ADDR
SETTING
BG
CSP1
CSP1
CS1
Thermal
CONFIG
+
_
Shutdown
TS
CSN1
BST1
CONFIG
+
Vcc_rdy
V1
4.0V
−
CS1_INT
VCC
CS2_INT
+
Startup
INPUT
UVLO
BG
OCP
logic
Boot1 _UVLO
VCC
Boot1V
HSG1
VSW1
LSG1
PGND1
PGND2
LSG2
VSW2
HSG2
BST2
VDRV
VDRV
CS1_INT
NOL
+
VDRV_rdy
Drive
Logic_1
4.0V
V2
−
VDRV
+
V2_OVLO
−
OV2_th
CS1
CS1
SW1
SW2
SW3
SW4
CLINDP1
+
Control
Logic
CLIMP1
CLIMP2
−
−
CLIND
CLINDP2
PG
TS
+
CS2
CS2
CLIND
EN
CLIND
NOL
Drive
VDRV
CLIND
Logic_2
−
PG_Low
VFB
EN_MASK
EN
OV_MSK
PG_MSK
EN_INT
+
−
FB
V1
CS1
CS2
−
EN
LOGIC
EN
Analog
Mux
+
0.8V
ADC
OV
PG
+
PG/
OV/
PG_High
+
VCCD
LOGIC
Boot2 _UVLO
CSP2
CSN2
Boot2 V
Value
Register
VFB
+
PDRV
Limit
Registers
+
_
CS2
−
OV_REF
CONFIG
CS2_INT
CSN2
SDA
SCL
INT
0_Ramp
Master OSC
Oscillator
Ramp_0
∑
∑
CS1_INT
CS2_INT
CS1_INT
I2C
Digital
Configuration
Interface
Ramp_180
BG
Reference
VDRV
PDRV
180_Ramp
INT
Status
Registers
CONFIG
Error OTA
500μS/100μS
Interface
−
COMP
PG
TS
SW1
SW4
Buck Logic
+
SW2
SW3
+
Boost Logic
Buck Boost
Logic
_
−
VFB
+
FB
VFB
0_Ramp
THPAD
AGND
Figure 3. Block Diagram
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3
NCV81599, NCP81599
Table 1. PIN FUNCTION DESCRIPTION
Pin
Pin Name
Description
1
HSG1
S1 gate drive. Drives the S1 N−channel MOSFET with a voltage equal to VDRV superimposed on the switch
node voltage VSW1.
2
LSG1
Drives the gate of the S2 N−channel MOSFET between ground and VDRV.
3, 22
PGND
Power ground for the low side MOSFET drivers. Connect these pins closely to the source of the bottom
N−channel MOSFETs.
4
5
6
7
CSN1
CSP1
V1
Negative terminal of the current sense amplifier.
Positive terminal of the current sense amplifier.
Input voltage of the converter
CS1
Current sense amplifier output. CS1 will source a current that is proportional to the voltage across RS1 to an
external resistor. CS1 voltage can be monitored with a high impedance input. Ground this pin if not used.
2
8
CLIND
Open drain output, high voltage on CLIND pin indicates that the CS1 or CS2 voltage has exceeded the I C
programmed limit.
2
9
SDA
SCL
INT
I C interface data line.
2
10
11
I C interface clock line.
Interrupt is an open drain output that indicates the state of the output power, the internal thermal trip, and oth-
er I C programmable functions.
2
2
2
12
13−14
15
ADDR
AGND
COMP
EN
I C address pin, placing a less than 200 kW resistor to the ground to set the I C address.
The ground pin for the analog circuitry.
Output of the transconductance amplifier used for stability in closed loop operation.
16
Logic high enables the switching and logic low shuts down and reset the device. Middle level makes the de-
vice to stop switching and keep the VCC alive.
17
18
PDRV
CS2
The open drain output used to control a PMOSFET.
Current sense amplifier output. CS2 will source a current that is proportional to the voltage across RS2 to an
external resistor. CS2 voltage can be monitored with a high impedance input. Ground this pin if not used.
19
20
21
23
24
FB
Feedback voltage of the output, negative terminal of the gm amplifier.
Negative terminal of the current sense amplifier.
CSN2
CSP2
LSG2
HSG2
Positive terminal of the current sense amplifier.
Drives the gate of the S3 N−channel MOSFET between ground and VDRV.
S4 gate drive. Drives the S4 N−channel MOSFET with a voltage equal to VDRV superimposed on the switch
node voltage VSW2.
25
BST2
Bootstrapped Driver Supply. The BST2 pin swings from a forward voltage drop below VDRV up to a forward
voltage drop below VOUT + VDRV. Place a 0.1 mF capacitor from this pin to VSW2.
26
27
28
VSW2
V2
Switch Node. VSW2 pin swings from a diode voltage drop below ground up to output voltage.
Output voltage of the converter. Connect to the output externally for OVLO sense.
VCCD
Internal digital power supply input. Always connect VCCD to VCC. A 1 mF capacitor should be placed close to
the part to decouple this line.
29
30
VDRV
VCC
Internal voltage supply to the driver circuits. A 1 mF capacitor should be placed close to the part to decouple
this line.
The VCC pin supplies power to the internal circuitry. The VCC is the output of a linear regulator which is pow-
ered from V1. Pin should be decoupled with a 1 mF capacitor for stable operation.
31
32
VSW1
BST1
Switch Node. VSW1 pin swings from a diode voltage drop below ground up to V1.
Bootstrapped Driver Supply. The BST1 pin swings from a forward voltage drop below VDRV up to a forward
voltage drop below V1 + VDRV. Place a 0.1 mF capacitor from this pin to VSW1.
33
THPAD
Center Thermal Pad. Connect to AGND externally.
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4
NCV81599, NCP81599
Table 2. MAXIMUM RATINGS
Over operating free−air temperature range unless otherwise noted
Rating
Symbol
VCCD
ADDR
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
Max
5.5
Unit
V
VCCD Input Voltage
Address Pin Output Voltage
Driver Input Voltage
5.5
V
VDRV
VCC
5.5
V
Internal Regulator Output
Output of Current Sense Amplifiers
Current Limit Indicator
Interrupt Indicator
5.5
V
CS1, CS2
CLIND
INT
5.5
V
VCC + 0.3
VCC + 0.3
5.5
V
V
Enable Input
EN
V
2
I C Communication Lines
SDA, SCL
COMP
V1
VCC + 0.3
VCC + 0.3
35 V, 40 V (20 ns)
35 V, 40 V (20 ns)
35 V, 40 V (20 ns)
35 V, 40 V (20 ns)
35 V, 40 V (20 ns)
5.5
V
Compensation Output
V
V1 Power Stage Input Voltage
Positive Current Sense
Negative Current Sense
Positive Current Sense
Negative Current Sense
Feedback Voltage
V
CSP1
CSN1
CSP2
CSN2
FB
V
V
V
V
V
Driver 1 and Driver 2 Positive Rails
BST1,
BST2
−0.3 V wrt/PGND
−0.3 V wrt/VSW
40 V
5.5 V wrt/VSW
V
High Side Driver 1 and Driver 2
HSG1,
HSG2
−0.3 V wrt/PGND
−0.3 V wrt/VSW
40 V
5.5 V wrt/VSW
V
V
Switching Nodes and Return Path of Driver 1 and Driver 2
VSW1, VSW2
−2.0 V,
−5 V (100 ns)
35 V, 40 V (20 ns)
Low Side Driver 1 and Driver 2
PMOSFET Driver
LSG1, LSG2
PDRV
−0.3 V
−0.3
−0.3
−0.5
0
5.5
V
V
35 V, 40 V (20 ns)
Voltage Differential
AGND to PGND
CS1DIF, CS2DIF
PDRVI
0.3
0.5
10
V
CSP1−CSN1, CSP2−CSN2 Differential Voltage
PDRV Maximum Current
V
mA
mA
PDRV Maximum Pulse Current
(100 ms on time, with > 1 s interval)
PDRVIPUL
0
200
Maximum VCC Current
VCCI
TJ
0
mA
°C
°C
°C
Operating Junction Temperature Range (Note 1)
Operating Ambient Temperature Range
Storage Temperature Range
−40
−40
−55
150
125
150
TA
TSTG
Thermal Characteristics (Note 2)
QFN 32 5mm x 5mm
Maximum Power Dissipation @ TA = 25°C
Maximum Power Dissipation @ TA = 85°C
Thermal Resistance Junction−to−Air with Solder
Thermal Resistance Junction−to−Case Top with Solder
Thermal Resistance Junction−to−Case Bottom with Solder
PD
PD
RQJA
RQJCT
RQJCB
4.1
2.1
30
1.7
2.0
W
W
°C/W
°C/W
°C/W
Lead Temperature Soldering (10 sec):
RF
260 Peak
°C
Reflow (SMD styles only) Pb−Free (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The maximum package power dissipation limit must not be exceeded.
2. The value of QJA is measured with the device mounted on a 3in x 3in, 4 layer, 0.062 inch FR−4 board with 1.5 oz. copper on the top and
bottom layers and 0.5 ounce copper on the inner layers, in a still air environment with TA = 25°C.
3. 60−180 seconds minimum above 237°C.
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NCV81599, NCP81599
Table 3. ELECTRICAL CHARACTERISTICS
(V1 = 12 V, V = 5 V , T = +25°C for typical value; −40°C < T = T < 125°C for min/max values unless noted otherwise)
out
A
A
J
Parameter
POWER SUPPLY
Symbol
Test Conditions
Min
Typ
Max
Units
V1 Operating Input Voltage
V1
V
NCV81599
NCP81599
4.5
4.5
32
28
VDRV Operating Input Voltage
VCCD Operating Input Voltage
VCC UVLO Rising Threshold
VCC UVLO Falling Threshold
UVLO Hysteresis for VCC
VDRV UVLO Rising Threshold
VDRV UVLO Falling Threshold
VDRV UVLO Hysteresis
VCC Output Voltage
VDRV
VCCD
4.5
5
5.5
V
V
4.5
5.5
VCC
VCC
4.21
3.90
4.27
3.96
300
4.31
4.01
300
5
4.35
4.06
V
RISE
FALL
V
VCCV
VDRV
VDRV
VDRV
VCC
Falling Hysteresis
mV
V
HYS
RISE
FALL
HYS
4.21
3.90
4.35
4.06
V
mV
V
With no external load
30 mA load
4.5
80
VCC Drop Out Voltage
VCCDROOP
IOUT
100
97
mV
mA
mA
mA
mA
VCC Output Current Limit
VCC Short Current Limit
V1 Shutdown Supply Current
V1 Normal Current
VCC Loaded to 4.3 V, EN > 0.8 V
VCC
IVCC_SHORT VCC short
14.6
8.0
IVCC_SD
IV1
EN < 0.4 V, V1 = 12 V
15
0.8 V < EN < 1.88 V, 4.5 V ≤ V1 ≤
32 V, (No Switching)
7.3
VCCD Standby Current
IVCCD
0.8 V < EN < 1.88 V
EN > 2.2 V
4
mA
mA
mA
VCCD Switching Current
VDRIVE Switching Current Buck
IVCCD_SW
IV1_SW
4.1
16
EN = 5 V, Cgate = 2.2 nF,
VSW = 0 V, FSW = 600 kHz
VDRIVE Switching Current Boost
IV1_SW
EN = 5 V, Cgate = 2.2 nF,
VSW = 0 V, FSW = 600 kHz
15
mA
VOLTAGE OUTPUT
Voltage Output Accuracy
FB
DAC_TARGET = 00110010
DAC_TARGET = 01111000
DAC_TARGET = 11001000
0.495
1.188
1.98
0.5
1.2
2.0
0.505
1.212
2.02
V
Voltage Accuracy Over Temperature
VOUTERT
VOUTER
VFB ≥ 0.5 V
−1.0
−5
1.0
5
%
VFB < 0.5 V
mV
T = 25°C
%
A
VFB ≥ 0.5 V
−0.45
0.45
TRANSCONDUCTANCE AMPLIFIER
Gain Bandwidth Product
Transconductance
GBW
(Note 4)
Default
5.2
500
80
MHz
mS
mA
mA
V
GM1
Max Output Source Current limit
Max Output Sink Current limit
Voltage Ramp
GMSOC
GMSIC
Vramp
60
60
80
1.2
INTERNAL BST SWITCH
Pass FET Rds(on)
RBST
DIL
I = 1 mA
60
W
F
Reverse Leakage Current from BST
pin to VDRV pin
BST = 32 V, T = 25°C
0.05
1
mA
A
BST−VSW UVLO
BST−VSW UVLO
BST
BST
Falling
Rising
3.2
3.4
3.5
3.7
3.8
4.1
V
V
_UVLO
_UVLO
4. Ensured by design. Not production tested.
5. Typical value only. Not production tested.
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NCV81599, NCP81599
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V1 = 12 V, V = 5 V , T = +25°C for typical value; −40°C < T = T < 125°C for min/max values unless noted otherwise)
out
A
A
J
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
mV
INTERNAL BST SWITCH
BST−VSW Hysteresis
BST
(Note 4)
200
_HYS
OSCILLATOR
Oscillator Frequency
FSW_0
kHz
FSW = 001 (Note 5)
FSW = 000, default
FSW = 010
150
600
300
450
740
880
1145
552
648
FSW = 011
FSW = 100
FSW = 101
FSW = 110
Oscillator Frequency Accuracy
Minimum On Time
FSWE
MOT
−12
12
60
%
ns
Measured at 10% to 90% of VCC (Note 4)
Measured at 90% to 10% of VCC (Note 4)
100
100
45
Minimum Off Time
MOFT
ns
Minimum Switching Frequency
F
MIN
30
kHz
INT THRESHOLDS
Interrupt Low Voltage
VINTI
INII
IINT(sink) = 2 mA
0.2
V
Interrupt High Leakage Current
Interrupt Startup Delay
Interrupt Propagation Delay
5 V
3
100
nA
ms
ms
ns
%
INTPG
PGI
Soft Start end to PG positive edge
Delay for power good in
Delay for power good out
2.1
3.3
100
PGO
PGTH
Power Good Threshold
Power Good in from falling
Power Good out from falling
104
93
PGTH
Power Good out from rising
Power Good in from rising
106
95
%
%
FB Overvoltage Threshold
FB_OV
V
FB
V
FB
= 0.5 V
= 1.3 V
112
112
115
115
117
118
Overvoltage Propagation Delay
VFB_OVDL
1 Cycle
EXTERNAL CURRENT SENSE (CS1,CS2)
Positive Current Measurement High
Transconductance Gain Factor
CS10
CSP1−CSN1 or CSP2−CSN2 = 25 mV
125
5
mA
CSGT
Current Sense Transconductance
Vsense = 10 mV to 100 mV
mS
Transconductance Deviation
CSGE
%
CSPx−CSNx = 10 mV
−30
−20
4.5
30
20
32
CSPx−CSNx = 25 mV to 100 mV
CSP1 is tied to V1
Input Current Sense Common Mode
Range
CSCMMR_I
CSCMMR_O
V
V
Output Current Sense Common Mode
Range
4
25.5
Input Sense Voltage Full Scale
CS Output Voltage Range
ISVFS
CSOR
(Note 4)
100
3
mV
V
VSENSE = 100 mV Rset = 6k (Note 4)
0
EXTERNAL CURRENT LIMIT (CLIND)
Current Limit Indicator Output Low
CLINDL
Input current = 500 mA
7.0
65
100
100
mV
nA
Current Limit Indicator Output High
Leakage Current
ICLINDH
Pull up to 5 V
4. Ensured by design. Not production tested.
5. Typical value only. Not production tested.
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NCV81599, NCP81599
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V1 = 12 V, V = 5 V , T = +25°C for typical value; −40°C < T = T < 125°C for min/max values unless noted otherwise)
out
A
A
J
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
INTERNAL CURRENT SENSE
Internal Current Sense Gain for PWM
Positive Peak Current Limit Trip
ICG
CSPx−CSNx = 25 mV
9.4
34
10
10.5
44
V/V
mV
PPCLT
OCP_L
NVCLT
CLIP = 00 (default)
CLIP = 01
CLIP = 10
CLIP = 11
39
23
11
70
Positive Peak Current Limit Latch−off
CLIP = 00 (default)
CLIP = 01
CLIP = 10
CLIP = 11
70
39
23
106
mV
mV
Negative Valley Current Limit Trip
CLIN = 00 (default)
CLIN = 01
CLIN = 10
CLIN = 11
34
40
25
15
0
45
SWITCHING MOSFET DRIVERS
HSG1 Pullup Resistance
HSG1_PU
HSG1_PD
LSG1_PU
LSG1_PD
HSG2_PU
HSG2_PD
LSG2_PU
LSG2_PD
HSLSD1
BST−VSW = 5 V
BST−VSW = 5 V
LSG −PGND = 5 V
LSG −PGND = 5 V
BST−VSW = 5 V
BST−VSW = 5 V
LSG −PGND = 5 V
LSG −PGND = 5 V
2
W
W
HSG1 Pulldown Resistance
LSG1 Pullup Resistance
0.8
2.4
0.7
2.7
0.9
2.0
0.7
16
W
LSG1 Pulldown Resistance
HSG2 Pullup Resistance
W
W
HSG2 Pulldown Resistance
LSG2 Pullup Resistance
W
W
LSG2 Pulldown Resistance
HSG1 Falling to LSG1 Rising Delay
LSG1 Falling to HSG1 Rising Delay
HSG2 Falling to LSG2 Rising Delay
LSG2 Falling to HSG2 Rising Delay
W
ns
ns
ns
ns
LSHSD1
36
HSLSD2
35
LSHSD2
56
SLEW RATE/SOFT START
Charge Slew Rate
SLEWP
SLEWN
Slew = 00, FB = 0.1 VOUT
Slew = 01, FB = 0.1 VOUT
Slew = 10, FB = 0.1 VOUT
Slew = 11, FB = 0.1 VOUT
0.6
1.2
2.4
4.8
mV/ms
mV/ms
(VOUT measured at V2 pin)
Discharge Slew Rate
(VOUT measured at V2 pin)
Slew = 00, FB = 0.1 VOUT
Slew = 01, FB = 0.1 VOUT
Slew = 10, FB = 0.1 VOUT
Slew = 11, FB = 0.1 VOUT
−0.6
−1.2
−2.4
−4.8
ENABLE
EN LDO High Threshold Voltage
EN LDO Low Threshold Voltage
EN Switching High Threshold Voltage
EN Switching Low Threshold Voltage
EN Pull Up Current (Default on)
ENLDOHT
ENLDOLT
ENHT
770
570
2.15
1.87
3.0
810
mV
mV
V
530
ENLT
1.65
V
IEN_UP
EN = 0.8 V
mA
ADDR
Internal Current Source
ADDR0
IADDR
9
10
11
mA
mV
mV
mV
ADDR = 74 H
ADDR = 75 H
ADDR = 76 H
110
300
500
ADDR1
220
380
260
440
ADDR2
4. Ensured by design. Not production tested.
5. Typical value only. Not production tested.
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8
NCV81599, NCP81599
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(V1 = 12 V, V = 5 V , T = +25°C for typical value; −40°C < T = T < 125°C for min/max values unless noted otherwise)
out
A
A
J
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
ADDR
ADDR3
ADDR = 77 H
600
715
830
mV
2
I C INTERFACE
Voltage Threshold Rising
Voltage Threshold Falling
Communication Speed
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
I2CVTH_R
I2CVTH_F
I2CSP
1.2
0.9
V
V
1
MHz
TSD
(Note 4)
(Note 4)
151
28
°C
°C
TSDHYS
PDRV
PDRV Operating Range
PDRV Leakage Current
PDRV Drain−Source Voltage
0
0
32
V
nA
V
PDRV_IDS
PDRV_VDS
FET OFF, VPDRV = 32 V
ISNK = 10 mA
180
0.20
INTERNAL ADC
Range
ADCRN
ADCLSB
ADCFE
(Note 4)
(Note 4)
(Note 4)
2.55
V
LSB Value
20
1
mV
LSB
Error
INPUT OVLO
Input OVLO Rising Threshold
Input OVLO Falling Threshold
Input OVLO Debounce Time
Input OVLO Recover Debounce Time
OUTPUT OVLO
V
34
28.5
2
V
V
OVLOIN_R
V
OVLOIN_F
(Note 4)
(Note 4)
ms
ms
1
Output OVLO Threshold
(Register 06h, bit [5:4])
sel_v2th = 00
sel_v2th = 01
sel_v2th = 10 (Default)
sel_v2th = 11
15
22.5
30
V
V
OVLO_O
36
Output OVLO Debounce Time
(Note 4)
1
ms
4. Ensured by design. Not production tested.
5. Typical value only. Not production tested.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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9
NCV81599, NCP81599
TYPICAL CHARACTERISTICS
Figure 1. Switching Frequency vs.
Figure 2. VCC vs. Temperature
Temperature
Figure 3. VCC Load Regulation
Figure 4. VCC Line Regulation (20 mA Load)
Figure 5. Shutdown Supply Current vs.
Temperature
Figure 6. V1 Normal Current vs. Temperature
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10
NCV81599, NCP81599
TYPICAL CHARACTERISTICS
6
5.5
5
4.5
4
3.5
3
2.5
2
−50
0
50
100
150
° C)
Ambient Temperature (
Figure 7. VCCD Current vs. Temperature,
VCCD = 5.0 V
Figure 8. ENABLE Rising Threshold vs.
Temperature
Figure 9. VDRIVE Switching Current Buck vs.
Temperature
Figure 10. VDRIVE Switching Current Boost
vs. Temperature
Figure 11. Voltage Accuracy vs. Temperature
(FB Setting > 500 mV)
Figure 12. Voltage Accuracy vs. Temperature
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11
NCV81599, NCP81599
TYPICAL CHARACTERISTICS
Figure 13. Voltage Ramp Up
(slew rate = 0.6 V/ms)
Figure 14. Voltage Ramp Down
(slew rate = 0.6 V/ms)
Figure 15. Voltage Ramp Up
(slew rate = 4.8 V/ms)
Figure 16. Voltage Ramp Down
(slew rate = 4.8 V/ms)
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12
NCV81599, NCP81599
TYPICAL CHARACTERISTICS
Vout
Vout
Load current (2A/div)
Load current (2A/div)
Vin=24V, Vout=5V, Load=0.3A to 3A
Vin=24V, Vout=5V, Load=0.5A to 5A
Figure 17. 5 V Load Step
Figure 18. 20 V Load Step
Figure 19. OCP Cycle−by−Cycle Waveform
Figure 20. OCP Hiccup Waveform
Figure 21. OVP Waveform
Figure 22. V2 Secondary OVP Waveform
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13
NCV81599, NCP81599
TYPICAL CHARACTERISTICS
EN
EN
Vsw2
Vsw2
Vout
Vsw1
Vsw1
Vout
Vin=12V, Vout=20V
Vin=12V, Vout=20V
Figure 23. Shutdown by EN
Vout gradually walks down, after EN pin goes
down from high (5V) to middle (1V)
Figure 24. Shutdown by EN
Vout is discharged by load current, after EN pin
does down from high (5V) to low (0V)
Figure 25. Efficiency vs. Load (MOSFET part number is NTMFS4C10N)
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14
NCV81599, NCP81599
APPLICATION INFORMATION
Dual Edge Current Mode Control
boost mode with S1 always on and S2 always off, but S3 and
S4 turning on alternatively in an active switching mode.
When COMP is below the midpoint, the system will
operation at buck mode, with S4 always on and S3 always
off, but S1 and S2 turning on alternatively in an active
switching mode. The controller can switch between buck
and boost mode smoothly based on the COMP signal from
peak current regulation.
When dual edge current mode control is used, two voltage
ramps are generated that are 180 degrees out of phase. The
inductor current signal is added to the ramps to incorporate
current mode control. In Figure 26, the COMP signal from
the compensation output interacts with two triangle ramps
to generate gate signals to the switches from S1 to S4. Two
ramp signals cross twice at midpoint within a cycle. When
COMP is above the midpoint, the system will operate at
Ramp1+i_sense
comp
Ramp2+i_sense
S1
S2
S3
S4
S4
S1
L1
V1
V2
S3
S2
Figure 26. Transitions for Dual Edge 4 Switch Buck Boost
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15
NCV81599, NCP81599
Feedback and Output Voltage Profile
in default. The reference voltage can be adjusted with
10 mV (default) or 5 mV steps from 0.1 V to 2.55 V through
the voltage profile register (01H), which makes the
continuous output voltage profile possible through an
external resistor divider. For example, by default, if the
external resistor divider has a 10:1 ratio, the output voltage
profile will be able to vary from 1 V to 25.5 V with 100 mV
steps.
The feedback of the converter output voltage is connected
to the FB pin of the device through a resistor divider.
Internally FB is connected to the inverting input of the
internal
transconductance
error
amplifier.
The
non−inverting input of the gm amplifier is connected to the
internal reference. The internal reference voltage is by
default 0.5 V. Therefore a 10:1 resistor divider from the
converter output to the FB will set the output voltage to 5 V
Table 4. VOLTAGE PROFILE REGISTER SETTINGS
dac_target Isb
(03h, bit 4)
dac_target (01h)
dac_target (01h)
Hex Value
Reference DAC
Voltage (mV)
bit_8
0
bit_7
0
bit_6
0
bit_5
0
bit_4
0
bit_3
0
bit_2
0
bit_1
0
bit_0
1
00
…
5
…
…
…
…
…
…
…
…
…
…
0
0
1
0
0
0
0
1
21
21
…
0
330
0
0
1
0
0
0
0
1
1
335
…
…
…
…
…
…
…
…
…
…
0
0
1
1
0
0
1
0
32
…
0
500 (Default)
…
…
1
…
1
…
0
…
0
…
1
…
0
…
0
…
0
…
0
C8
…
2000
…
…
…
…
…
…
…
…
…
…
1
1
1
1
1
1
1
1
FF
FF
0
2550
2555
1
1
1
1
1
1
1
1
1
Transconductance Voltage Error Amplifier
1000 mS allowing the DC gain of the system to be increased
more than a decade triggered by the adding and removal of
the bulk capacitance or in response to another user input.
The default transconductance is 500 mS.
To maintain loop stability under a large change in
capacitance, the NCV81599 can change the gm of the
internal transconductance error amplifier from 87 mS to
Table 5. AVAILABLE TRANSCONDUCTANCE SETTING
Address
AMP_2
AMP_1
AMP_0
Amplifier GM Value (mS)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
87
100
117
333
07h, bit [2:0]
400
500 (default)
667
1000
Programmable Slew Rate
output voltage is divided by a factor of the external resistor
divider and connected to FB pin. The 9 Bit DAC is used to
increase the reference voltage in 10 or 5 mV increments. The
slew rate is decreased by using a slower clock that results in
a longer time between voltage steps, and conversely
increases by using a faster clock. The step monotonicity
depends on the bandwidth of the converter where a low
2
The slew rate of the NCV81599 is controlled via the I C
registers with the default slew rate set to 0.6 mV/ms
(FB = 0.1 V2, assume the resistor divider ratio is 10:1)
which is the slowest allowable rate change. The slew rate is
used when the output voltage starts from 0 V to a user
selected profile level, changing from one profile to another,
or when the output voltage is dynamically changed. The
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16
NCV81599, NCP81599
bandwidth will result in a slower slew rate than the selected
value. The available slew rates are shown in Table 6. The
selected slew rate is maintained unless the current limit is
tripped; in which case the increased voltage will be governed
by the positive current limit until the output voltage falls or
the fault is cleared.
2.56 V
DAC_TARGET
VREF
9 bit DAC
DAC_TARGET_LSB
+
V2
−
RC
CI
CC
FB = 0.1*V2
Figure 27. Slew Rate Limiting Block Diagram and Waveforms
~2.0 V. The EN pin can NOT work with very slow dv/dt
signals. Please always keep the EN pin input signal faster
than 0.5 V/ms. The EN pin has a pull−up current of ~3 mA,
so that an open EN pin powers up the NCV81599. To keep
the EN pin signal faster enough, please keep total
capacitance on the EN pin below 4.7 nF.
Table 6. SLEW RATE SELECTION
Soft Start or
Voltage Transition
(FB = 0.1*V2)
0.6 mV/ms
1.2 mV/ms
2.4 mV/ms
4.8 mV/ms
Address
Slew Bits
Slew_0
Slew_1
Slew_2
Slew_3
When the EN pin goes from high (above ENHT) down to
middle (below ENLT, but still above ENLDOHT), the
NCV81599 walks down the Vout gradually to zero, in the
discharge slew rate selected by “voltage transition slew rate”
register value, as shown in waveforms in Figure 23. All the
02h, bit [1:0]
The discharge slew rate is accomplished in much the same
way as the charging except the reference voltage is
decreased rather than increased. The slew rate is maintained
unless the negative current limit is reached. If the negative
current limit is reached, the output voltage is decreased at the
maximum rate allowed by the current limit (see the negative
current limit section).
2
I C register value stays.
When the EN pin goes from high (above ENHT) down to
low (below ENLDOLT), the NCV81599 stops all switching
immediately, and Vout is discharged by load current, as
shown in waveforms in Figure24. Internal LDO shuts down,
2
and all I C register value resets.
Frequency Programming
The switching frequency of the NCV81599 can be
programmed from 150 kHz to 1.2 MHz via the I C interface.
The default switching frequency is set to 600 kHz. The
switching frequency can be changed on the fly. However, it
is a good practice to disable the part and then program to a
different frequency to avoid transition glitches at large load
current.
Soft−Start and EN Pin
During a 0 V soft−start, standard converters can start in
synchronous mode and have a monotonic rising of output
voltage. If a prebias exists on the output and the converter
starts in synchronous mode, the prebias voltage could be
discharged. The NCV81599 controller ensures that if a
prebias is detected, the soft−start is completed in a
non−synchronous mode to prevent the output from
discharging. During soft−start, the output rising slew rate
will follow the slew rate register with default value set to
0.6 mV/ms (FB = 0.1*V2).
2
The NVP81599 employs a minimum switching frequency
circuit (F
) to ensure the bootstrap caps remain charged
MIN
and operation in the audible hearing range band is avoided.
Typically, this circuit is only active when V is near V
at light loads.
IN
OUT
The EN Pin has 2 levels of threshold: the internal LDO and
I C function are powered up when EN pin reaches ~0.8 V;
2
while the buck−boost conversion starts when EN pin reaches
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17
NCV81599, NCP81599
Table 7. FREQUENCY PROGRAMMING TABLE
Name
Bit
Definition
Description
Freq1
03H [2:0]
Frequency Setting
3 Bits that Control the Switching Frequency from 150 kHz to 1.2 MHz.
000: 600 kHz (default)
001: 150 kHz
010: 300 kHz
011: 450 kHz
100: 750 kHz
101: 900 kHz
110: 1.2 MHz
111: Reserved
Current Sense Amplifiers
amplifier. In addition, R
must be small enough that
SENSE
Internal precision differential amplifiers measure the
potential between the terminal CSP1 and CSN1 or CSP2 and
CSN2. Current flows from the input V1 to the output in a
buck boost design. Current flowing from V1 through the
V
does not exceed the maximum input voltage
SENSE
100 mV, even under peak load conditions.
The potential difference between CSPx and CSNx is level
shifted from the high voltage domain to the low voltage
VCC domain where the signal is split into two paths.
The first path, or external path, allows the end user to
observe the analog or digital output of the high side current
sense. The external path gain is set by the end user allowing
the designer to control the observable voltage level. The
voltage at CS1 or CS2 can be converted to 7 bits by the ADC
and stored in the internal registers which are accessed
switches to the inductor passes through R . The
SENSE
external sense resistor, R , has a significant effect on
SENSE
the function of current sensing and limiting systems and
must be chosen with care. First, the power dissipation in the
resistor should be considered. The system load current will
cause both heat and voltage loss in R . The power loss
SENSE
and voltage drop drive the designer to make the sense
resistor as small as possible while still providing the input
dynamic range required by the measurement. Note that input
dynamic range is the difference between the maximum input
signal and the minimum accurately measured signal, and is
limited primarily by input DC offset of the internal
2
through the I C interface.
The second path, or internal path, has internally set gain
of 10 and allows cycle by cycle precise limiting of positive
and negative peak input current limits.
Internal Path
10x(CSP1-CSN1)
Positive Current
Limit
+
−
CLIP
10x(CSP2-CSN2)
10X
+
+
Negative Current
+
Limit
−
−
−
CSP1/CSP2
ILOAD
CLIN
RAMP 1
RAMP 2
VCM
+
+
Rsense
5 mW
+
CS1 or CS2
CS2 MUX
ADC
−
−
−
+
−
CSN1/CSN2
2
CS1 MUX
−
+
2
VCC
CLIND
CS2
CS1
CCS1
RCS1
CCS2
RCS2
Figure 28. Block Diagram and Typical Connection for Current Sense
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18
NCV81599, NCP81599
Positive Current Limit Internal Path
into a load in over current situations but are not up to the task
of limiting energy into a low impedance short. To address the
low impedance short, the NCV81599 does pulse by pulse
current limiting for 500 ms known as Ilim timeout, the
controller will enter into hiccup mode. The NCV81599
remains in fast stop state with all switches driven off for 10
ms. Once the 10 ms has expired, the part is allowed to soft
start to the previously programmed voltage and current level
if the short circuit condition is cleared.
The NCV81599 has a pulse by pulse current limiting
function activated when a positive current limit triggers.
CSP1/CSN1 will be the positive current limit sense channel.
When a positive current limit is triggered, the current
pulse is truncated. In both buck mode and in boost mode the
S1 switch is turned off to limit the energy during an over
current event. The current limit is reset every switching
cycle and waits for the next positive current limit trigger. In
this way, current is limited on a pulse by pulse basis. Pulse
by pulse current limiting is advantageous for limiting energy
2
The internal current limits can be controlled via the I C
interface as shown in Table 8.
Table 8. INTERNAL PEAK CURRENT LIMIT
CLIN_1
CLIN_0
Address
CSP2−CSN2 (mV)
Current at RSENSE = 5 mW (A)
0
0
−40 (Default)
−8
0
1
−25
−5
05h, bit[5:4]
1
0
−15
−3
1
1
0
0
CLIP_1
CLIP_0
Address
CSP1−CSN1 (mV)
Current at RSENSE = 5 mW (A)
0
0
1
1
0
1
0
1
38 (Default)
7.6
4.6
2.2
14
23
11
70
05h, bit[1:0]
Positive Current Limit Internal Latch−off
pins, has its threshold around twice that of the positive
current limit. As listed in the following table, OCP_L
threshold is set by the same I C register bits, CLIP_1 and
CLIP_0, which set the internal positive peak current limit at
the same time.
In addition to the positive current limit, there is a latch−off
over current protection, to provide quick protection against
output short and inductor saturation. The latch−off over
current protection, OCP_L, sensed across CSP2−CSN2
2
Table 9. THE LATCH−OFF CURRENT LIMIT OCP_L
CLIP_1
CLIP_0
Address
CSP2−CSN2 (mV)
Current at RSENSE = 5 mW (A)
0
0
1
1
0
1
0
1
05h, bit[1:0]
70 (Default)
14
7.6
38
23
4.6
106
21.2
Once the latch−off current limit protection is triggered, an
input OCP_L fault is set. All four switches are driven off
immediately. The OCP_L interrupt register bit set to 1. Only
toggling the EN or input power recycle can reset the part.
The latch−off current limit OCP_L can be disabled via I C
register as shown in the following table.
light load transition, output overvoltage, and high output
voltage to lower output voltage transitions. CSP2/CSN2 will
be the negative current limit sense channel.
During light load synchronous operation, or heavy load to
light load transitions the negative current limit can be
triggered during normal operation. When the sensed current
exceeds the negative current limit, the S4 switch is shut off
preventing the discharge of the output voltage both in buck
mode and in boost mode if the output is in the power good
range. Both in boost mode and in buck mode when a
negative current is sensed, the S4 switch is turned off for the
remainder of either the S4 or S2 switching cycle and is
turned on again at the appropriate time. In buck mode, S4 is
turned off at the negative current limit transition and turned
on again as soon as the S2 on switch cycle ends. In boost
mode, the S4 switch is the rectifying switch and upon
2
Table 10. OCP_L LATCH−OFF CURRENT LIMIT
ENABLING AND DISABLING
Address
04h, bit[1]
04h, bit[1]
Dis_OCP_L
Description
0
1
OCP_L Action Enabled
OCP_L Action Disabled
Negative Current Limit Internal Path
Negative current limit can be activated in a few instances,
including light load synchronous operation, heavy load to
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19
NCV81599, NCP81599
negative current limit the switch will shut off for the
The speed and accuracy of the dual amplifier stage allows
the reconstruction of the input and output current signal,
creating the ability to limit the peak current. If the user would
like to limit the mean DC current of the switch, a capacitor
remainder of its switching cycle. The internal negative
2
current limits can be controlled via the I C interface as
shown in Table 8.
can be placed in parallel with the R resistors. CS1, CS2
can be monitored with a high impedance input.
CS
External Path (CS1, CS2, CLIND)
The voltage drop across the sense resistors as a result of
the load can be observed on the CS1 and CS2 pins. Both
CS1, CS2 can be monitored with a high impedance input.
The voltage drop is converted into a current by a
transconductance amplifier with a typical GM of 5 mS. The
final gain of the output is determined by the end users
CS1, CS2 voltages are connected internally to 2 high
speed low offset comparators. When the external CLIND
flag is triggered, i.e, CLIND pin voltage is pulled high, it
indicates that one of the internal comparators has exceeded
the preset limit (CSx_LIM). The default comparator setting
is 250 mV which is a limit of 500 mA with a current sense
selection of the R resistors. The output voltage of the CS
CS
resistor of 5 mW and an R resistor of 20 kW. The external
CS
pin can be calculated from Equation 1. The user must be
careful to keep the dynamic range below 2.56 V when
considering the maximum short circuit current.
current limit settings are shown in Table 11.
V
CS + (IAVERAGE * RSENSE * Trans) * RCS t 2.56 V å
VCS
2.56 V
MAX * RSENSE * Trans
RCS
+
t
IAVERAGE * RSENSE * Trans
I
(eq. 1)
Table 11. REGISTER SETTING FOR THE CLIM COMPARATORS
Current at RSENSE = 5 mW Current at RSENSE = 5 mW
RSET = 20 kW (A)
RSET = 10 kW (A)
Address
CLIMx_1
CLIMx_0
CSx_LIM (V)
0
0
1
1
0
1
0
1
0.25
0.75
1.5
.5
1.5
3
1
3
06h, bit [3:0]
6
2.5
5
10
Overvoltage Protection (OVP)
OV_REF
When the divided output voltage is 15% (typical) above
the internal reference voltage for greater than one switching
cycle, an OV fault is set. During an overvoltage fault, S1 is
driven off, S2 is driven on, and S3 and S4 are modulated to
discharge the output while preventing the inductor current
−
+
OV
VFB
OV_MSK
2
from going beyond the I C programmed negative current
limit.
Figure 30. OV Block Diagram
S4
S1
L1
Input Overvoltage Lockout (OVLO) Protection
V1
V2
The goal of the input OVLO fault detection is to protect
our IC from overvoltage damage and obtain regulation again
once the OVLO fault is cleared. OVLO can be a latched
shutdown or hiccup mode by a user register.
S3
S2
In a latched shutdown mode, when the input voltage is
higher than V
for greater than the debounce time,
OVLOIN_R
an input OVLO fault is set. All switches are driven off
immediately. The PG and input OVLO interrupt registers
are set to 1. Only toggling the EN or input power recycle can
reset the part.
Figure 29. Diagram for OV Protection
During overvoltage fault detection the switching
2
frequency changes from its I C set value to 50 kHz to reduce
In a hiccup mode, when the input voltage is higher than
the power dissipation in the switches and prevent the
inductor from saturating. OVP is disabled during voltage
changes to ensure voltage changes and glitches during
slewing are not falsely reported as faults. The OVP faults are
reengaged 2 ms after completion of the soft start.
V
for greater than the debounce time, an input
OVLOIN_R
OVLO fault is set. The OVLO debounce time is to filter any
overvoltage spike that is shorter than the time. During an
input OV fault, all switches are driven off immediately. The
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20
NCV81599, NCP81599
DAC voltage is reset to 0. The PG and input OVLO interrupt
VTOP=2.56V
9 bit DAC
registers are set to 1. Once the input voltage falls under the
threshold, the debounce time starts counting. If input OVLO
keeps not detected during the OVLO recover debounce time,
a soft start will be reengaged.
VREF/SS
Code Gen
COMP
+
Profile
Margin
Input OVLO detection starts from the beginning of
soft−start and ends in shutdown.
−
1.5V, 2.25V,
3.0V, 3.6V
M
U
X
Output OVLO Protection and V2 Pin
The goal of the output OVLO fault detection is to protect
the MOSFET from overvoltage damage. The overvoltage
can be created by accidently write a wrong number in the
DAC_target register or installation problem on the external
feedback voltage divider. The default output OVLO
threshold is 30V. Customer can write to the 2−bit output
OVLO register 06h bit[5:4], sel_ov2th to configure the
threshold.
−
FB
V2
Output
OVLO
Threshold
To
Driver
+
Gate
Signals
2
9R
R
0.1*Vsw 2
The output OVLO threshold can be set as 15V, 22.5V, 30V
and 36V, therefore it can be used for customer user cases that
requires a max output voltage of 10V, 15V, 20V and 25.5V,
respectively. Since most of the time, OVP should be able to
protect the output over voltage, the output OVLO threshold
are set >40% higher than the max output in that range. When
the output has run away due to either external voltage divider
or DAC configure error, output OVLO will kick into action.
Output OVLO has a latched shutdown mode. When the
output voltage is higher than the output OVLO threshold for
greater than the debounce time, an OVLO fault is set. The
output OVLO interrupt register will be set to 1. All switches
are driven off immediately. The PG and output OVLO
interrupt registers are set to 1. Toggling the EN or input
power recycle can reset the part.
Figure 31. Output OVLO
Power Good Monitor (PG)
NCV81599 provides two window comparators to monitor
the internal feedback voltage. The target voltage window is
5% of the reference voltage (typical). Once the feedback
voltage is within the power good window, a power good
indication is asserted once a 3.3 ms timer has expired. If the
feedback voltage falls outside a 7.5% window for greater
than 1 switching cycle, the power good register is reset.
2
Power good is indicated on the INT pin if the I C register is
set to display the PG state. When DAC is set to below
400 mV, the PG high threshold is kept at a constant voltage,
and the PG low threshold is kept at 0 to avoid false
triggering.
Output OVLO detection starts from the beginning of
soft−start and ends in shutdown.
PG_MSK
PG_Low
The output OVLO is sensed on the V2 pin. In some
extreme conditions, the V2 pin voltage, i.e. the output
voltage, may be pulled to negative, such as when the output
is short by a long cable. When V2 pin voltage goes negative,
the NCV81599 may enter a VCC UVLO, which resets all
registers to default and initial a soft−start. To prevent
negative voltage on V2 pin, a resistor, such as 1 kW, can be
placed between V2 pin and output voltage.
−
PG
+
VFB
−
+
PG_High
Figure 32. PG Block Diagram
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21
NCV81599, NCP81599
VBUS
Power Not Good
Power Not Good
S4
L
107.5%
105%
10μF
S3
VFB
Power Good
100%Vref
95%
92.5%
NCV81599
PDRV
PG
PFET_DRV
Figure 33. Power Good Diagram
Figure 34. PFET Drive
Thermal Shutdown
The NCV81599 protects itself from overheating with an
internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown threshold
(typically 150°C), all MOSFETs will be driven to the off
state, and the part will wait until the temperature decreases
to an acceptable level. The fault will be reported to the fault
register and the INT flag will be set unless it is masked.
When the junction temperature drops below 125°C
(typical), the part will discharge the output voltage to Vsafe
0 V.
Analog to Digital Converter
The analog to digital converter is a 7−bit A/D which can
be used as an event recorder, an input voltage sampler,
output voltage sampler, input current sampler, or output
current sampler. The converter digitizes real time data
during the sample period. The internal precision reference is
used to provide the full range voltage; in the case of V1(input
voltage), or FB (with 10:1 external resistor divider) the full
range is 0 V to 25.5 V. The V1 is internally divided down by
10 before it is digitized by the ADC, thus the range of the
measurement is 0 V−2.55 V, same as FB. The resolution of
the V1 and FB voltage is 20 mV at the analog mux, but since
the voltage is divided by 10 output voltage resolution will be
200 mV. Therefore, the highest input voltage report is
200 mV x 127 = 25.4 V. When CS1 and CS2 are sampled, the
range is 0 V−2.55 V. The resolution will be 20 mV in the CS
monitoring case. The actual current can be calculated by
dividing the CS1 or CS2 values with the factor of Rsense ×
5 mS × RCSx, the total gain from the current input to the
external current monitoring outputs.
PFET Drive
The PMOS drive is an open drain output used to control
the turn on and turn off of PMOSFET switches at a floating
potential. The external PMOS can be used as a cutoff switch,
enable for an auxiliary power supply, or a bypass switch for
a power supply. The RDSon of the pulldown NMOSFET is
typically 20 W allowing the user to quickly turn on large
PMOSFET power channels.
Table 12. PFET ACTIVATION TABLE
Address PFET_DRV
Description
NFET OFF (Default)
NFET ON
04h, bit [0]
0
1
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22
NCV81599, NCP81599
0.1*V1
Figure 35. Analog to Digital Converter
Table 13. ADC RESULT BYTE
Address
MSB
5
4
3
2
1
LSB
10h, 11h, 12h, 13h
D6
D5
D4
D3
D2
D1
D0
Table 14. REGISTER SETTING FOR ENABLING DESIRED ADC BEHAVIOUR
Address
ADC_2
ADC_1
ADC_0
Description
08h, bit [4:2]
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Set Amux to VFB
Sets Amux to V1
Set Amux to CS2
Set Amux to CS1
Select all in rotating sequence (VFB, V1, CS2, CS1, VFB, …)
Table 15. REGISTER SETTING FOR ADC TRIGGER MANNER
Address
ADC Trigger
Description
Trigger a 1x read by a fault condition (Default)
08h, bit [1:0]
00
01
10
Trigger a 1x read
Trigger a continuous read
Interrupt Control
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when a
system status change is detected. Individual bits generating
09h and 0Ah. Masked sources will never generate an
interrupt request on the INT pin. The INT pin is an open
drain output. A non−masked interrupt request will result in
the INT pin being driven high. When the host reads the
INTACK registers, the INT pin will be driven low and the
interrupt register INTACK is cleared. Figure 36 illustrates
the interrupt process.
2
interrupts will be set to 1 in the INTACK register (I C read
only registers), indicating the interrupt source. INTACK
2
register is automatically reset by an I C read. All interrupt
sources can be masked by writing 1 in register INTMSK of
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23
NCV81599, NCP81599
OCP_L
OCP_L_MASK
V2OVP
V2OVP_MASK
V1OVP
V1OVP_MASK
TSD
INT
TSD_MASK
OCP_P
OCP_P_MASK
OV
OV_MASK
CLIND
CLIND_MASK
PG_BAR
PG_BAR_MASK
VCHN
VCHN_MASK
Figure 36. Interrupt Logic
Table 16. INTERPRETATION TABLE
Interrupt Name
OCP_L
V2OVP
V1OVP
TSD
Register name
Address
Description
ocp_l
v2ovp
v1ovp
tsd
14h, bit [6]
14h, bit [5]
14h, bit [4]
14h, bit [3]
14h, bit [2]
14h, bit [1]
14h, bit [0]
15h, bit [1]
15h, bit [0]
Internal positive over current latch−off
Output secondary over voltage
Input over voltage
Thermal shut down
OCP_P
OV
ocp_p
ov
Internal positive over current
Output over voltage
CLIND
ext_clind_ocp
vchn
External over current trip from CLIND
Output negative voltage change
Power good bar thresholds exceeded
VCHN
PG_BAR
pg_int
I2C Address and Registers
0 W, 26.1 kW, 44.2 kW, 71.5 kW from ADDR pin to GND to
set I2C address 74H, 75H, 76H, 77H respectively.
Unused bits in the register map below are marked with
“−”. Writing either “1” or “0” into these unused bits in
user−programmable registers does NOT change any
function/performance of the NCV81599.
2
NCV81599 can set up to 4 different I C addresses by
sensing the shunt resistor voltage at ADDR pin. The chip
will source a 10 mA current to the ADDR resistor and sense
the voltage corresponding to different I C addresses
everytime when it is powered on. Suggest to put resistors of
2
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24
NCV81599, NCP81599
Table 17. I2C REGISTER MAP BIT DETAIL
ADDR
(Hex)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
00h
32h
00h
00h
00h
00h
20h
05h
00h
00h
−
−
0
0
en_int
en_mask
−
−
dac_target
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
slew_rate
v1ovp_lat
cs2_dchrg
dac_target_isb
cs1_dchrg
pwm_frequency
dis_ocp_l
−
−
pfet
ocp_clim_neg
sel_ov2th
ocp_clim_pos
cs1_clim_pos
gm_amp_setting
amux_trigger
cs2_clim_pos
−
−
−
dis_adc
amux_sel
int_mask int_mask_v2ovp int_mask_v1ovp
_ocp_l
int_mask_tsd int_mask_ocp_p int_mask_ov
int_mask_clind
0Ah
0B .. 0Fh
10h
−
−
−
−
−
−
int_mask_vchn
int_mask_pg
00h
−
−
−
−
−
−
−
vfb
11h
vin
cs2
cs1
12h
13h
14h
ocp_l
v2ovp
v1ovp
tsd
ocp_p
ov
ext_clind_ocp
pg_int
15h
−
−
−
−
−
vchn
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25
NCV81599, NCP81599
I2C Interface
external processor by means of a serial link using a 400 kHz
up to 1.2 MHz I C two−wire interface protocol. The I C
2
2
2
The I C interface can support 5 V TTL, LVTTL, 2.5 V and
1.8 V interfaces with two precision SCL and SDA
comparators with 1 V thresholds shown in Figure 37. The
part cannot support 5 V CMOS levels as there can be some
ambiguity in voltage levels.
interface provided is fully compatible with the Standard,
2
Fast, and High−Speed I C modes. The NCV81599 is not
intended to operate as a master controller; it is under the
control of the main controller (master device), which
controls the clock (pin SCL) and the read or write operations
I2C Compatible Interface
The NCV81599 can support a subset of I C protocol as
detailed below. The NCV81599 communicates with the
2
through SDA. The I C bus is an addressable interface (7−bit
2
addressing only) featuring two Read/Write addresses.
TTL
5V CMOS
Vcc =4.5V−5.5V
Vcc =4.5V−5.5V
VOH= 4.44V
LVTTL
Vcc =2.7V−3.6V
EIS/JEDEC 8−5
V
IH = 0.7*vcc
2.5
Vcc =2.3V−2. 7V
EIS/JEDEC 8−5
1.8V
V
TH = 0.5*vcc
Vcc =1.65V−1.95V
EIS/JEDEC 8−7
V
OH= 2.4V
V
OH= 2.4V
VIH = 2.0V
VIH = 2.0V
VOH = 2.0V
VIH = 1.7V
VIL = 0.3*vcc
VOL = 0.5V
VOH = VCC−0.45V
VTH = 1.5V
VIH = 0.65*Vcc
1.0V Threshold
VIL = 0.8V
VOL = 0.4V
VIL = 0.35*Vcc
VOL = 0.45V
VIL = 0.8V
VOL = 0.4V
VIL = 0.7V
VOL = 0.4V
Figure 37. I2C Thresholds and Comparator Thresholds
I2C Communication Description
The first byte transmitted is the chip address (with the LSB
bit set to 1 for a Read operation, or set to 0 for a Write
operation). Following the 1 or 0, the data will be:
• In case of a Write operation, the register address
(@REG) pointing to the register for which it will be
written is followed by the data that will written in that
location. The writing process is auto−incremental, so
the first data will be written in @REG, the contents of
@REG are incremented, and the next data byte is
placed in the location pointed to @REG + 1..., etc.
• In case of a Read operation, the NCV81599 will output
the data from the last register that has been accessed by
the last write operation. Like the writing process, the
reading process is auto−incremental.
From MCU to NCV81599
From NCV81599 to MCU
READ OUT
FROM PART
Start IC ADDRESS
1
ACK
DATA 1
ACK
Data n
/ACK STOP
1
Read
/ACK
Start IC ADDRESS
0
ACK
DATA 1
ACK
Data n
STOP Write Inside Part
ACK
If part does not Acknowledge, the /NACK will be followed by a STOP or Sr. If part
Acknowledges, the ACK can be followed by another data or STOP or Sr.
0
Write
Figure 38. General Protocol Description
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26
NCV81599, NCP81599
Read Out from Part
The master will first make a “Pseudo Write” transaction
with no data to set the internal address register. Then, a stop
then start or a repeated start will initiate the Read transaction
from the register address the initial Write transaction was
pointed to:
From MCU to NCV81599
From NCV81599 to MCU
Sets Internal
Register Pointer
Start IC ADDRESS
0
ACK
Register Address
ACK STOP
0
Write
Start IC ADDRESS
1
ACK
DATA 1
ACK
Data n
/ACK STOP Write Inside Part
Register Address + (n+1)
Value
Register Address
Value
N Register Read
1
Read
Figure 39. Read Out From Part
From MCU to NCV81599
From NCV81599 to MCU
Write Value in
Register REG + (n−1)
Sets Internal
Register Pointer
Write Value in
Register REG
REG + (n−1) Value
ACK STOP
Start IC ADDRESS
0
ACK Register REG Address ACK
REG Value
ACK
N Register Read
0
Write
Start IC ADDRESS
1
ACK
DATA 1
ACK
Data n
/ACK STOP
Register Address + (n+1) +
Register Address + (n−1)
(k−1) Value
Value
k Register Read
1
Read
Figure 40. Write Followed by Read Transaction
Write In Part
Write operation will be achieved by only one transaction.
After the chip address, the MCU first data will be the internal
register desired to access, the following data will be the data
written in REG, REG + 1, REG + 2, ..., REG + (n−1).
From MCU to NCV81599
From NCV81599 to MCU
Sets Internal
Write Value in
Register REG + (n−1)
Write Value in
Register REG
Register pointer
REG + (n−1) Value ACK STOP
Start IC ADDRESS 0 ACK Register REG Address ACK
REG Value
ACK
N Register Read
0
Write
Figure 41. Write in n Registers
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27
NCV81599, NCP81599
I2C Communication Considerations
• It takes at least 3.3 ms for the digital core to reset all the
registers, so it is recommended not to change the
register value until at least 3.3 ms after the output
voltage finish ramping to a steady state.
• It is recommended to avoid setting reference voltage
profile below 0.1 V. When 0 V output is needed, it is
recommended to ramp down the output by pulling EN
pin low with external circuit or by I2C communication
in the firmware. Setting output voltage profile to 0 via
I2C is not recommended.
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28
NCV81599, NCP81599
DESIGN CONSIDERATIONS
dv/dt Induced False Turn On
4−switch buck−boost converter is not exempt from this
issue. To make things worse, errors are made when designers
simply copy the circuit parameters of a buck converter
directly to the boost phase of the 4−switch buck−boost
converter.
In synchronous buck converters, there is a well−known
phenomenon called “low side false turn−on,” or “dv/dt
induced turn on”, which can be potentially dangerous for the
switch itself and the reliability of the entire converter. The
Vin
Buck phase dv/dt induced false
turn on equivalent circuit
Vout
4−Switch
Buck−boost
Controller
Drain
S1
L
Rpu_ds(on)
Cgd
4−Switch
Buck−boost
Controller
Vsw1
Drain
Rg_int
Rg_ext
S4
dV/dt
HSG2
+
Gate
Cgd
Cgs
Rpu_ds(on)
Vgs’
Rg_int
Rg_ext
Rpd_ds(on)
S2
dV/dt
LSG1
Source
L
+
−
Gate
Cgs
Vsw2
Vsw2
S3
Vgs’
Rpd_ds(on)
Source
−
GND
Boost phase dv/dt induced
false turn on equivalent circuit
Figure 42. dv/dt Induced False Turn−on Equivalent Circuit of a 4−switch Buck−boost Converter
Figure 42 shows false turn on equivalent circuit of the
buck phase and the boost phase at the moment a positive
dv/dt transition appears across the drain−to−source junction.
The detailed analysis of this phenomenon can be found in
Gate Driver Design Considerations for 4−Switch
Buck−Boost Converters.
on dt/C , V and threshold voltage V . One way of
gs ds th
interpreting the dv/dt induced turn−on problem is when V
ds
reaches the input voltage, the Miller charge should be
smaller than the total charge on C at the V level, so that
gs
th
the rectifying switches will not be turned on. Then we will
have the following relation:
Cgd
Select the Switching Power MOSFET
Vgs
+
Vds t Vgs(th)
(eq. 3)
Cgd ) Cgs
The MOSFETs used in the power stage of the converter
should have a maximum drain−to−source voltage rating that
exceeds the sum of steady state maximum drain−to−source
voltage and the turn−off voltage spike with a considerable
margin (20%~50%).
Q
gd t QGS(th)
(eq. 4)
We can simply use Equation 4 to evaluate the rectifying
device’s immunity to dv/dt induced turn on. Ideally, the
charge Q should not be greater than 1.5*Q
leave enough margin.
in order to
When selecting the switching power MOSFET, the
MOSFET gate capacitance should be considered carefully
to avoid overloading the 5 V LDO. For one MOSFET, the
gd
gs(th)
Select Gate Drive Resistors
allowed maximum total gate charge Q can be estimated by
g
To increase the converter’s dv/dt immunity, the dv/dt
control is one approach which is usually related to the gate
driver circuit. A first intuitive method is to use higher pull
up resistance and gate resistance for the active switch. This
would slow down the turn on of the active switch, effectively
decreasing the dv/dt. Table 18 shows the recommended
value for MOSFETs’ gate resistors.
Equation 2:
Idriver
fsw
Qg +
(eq. 2)
where I
is the gate drive current and f is the switching
sw
driver
frequency.
It is recommended to select the MOSFETs with smaller
than 3 nF input capacitance (C ). The gate threshold
voltage should be higher than 1.0 V due to the internal
adaptive non−overlap gate driver circuit.
iss
Table 18. RECOMMENDED VALUE for Gate Resistors
Buck Phase
Boost Phase
HSG2
LSG2
In order to prevent dv/dt induced turn−on, the criteria for
HSG1
LSG1
(3.3~5.1)W
0W
0W
selecting a rectifying switch is based on the Q /Q
ratio.
gd gs(th)
(3.3~5.1)W
Q
gs(th)
is the gate−to−source charge before the gate voltage
An alternative approach is to add an RC snubber circuit to
the switching nodes V and V . This is the most direct
reaches the threshold voltage. Lowering C will reduce
dv/dt induced voltage magnitude. Moreover, it also depends
gd
sw1
sw2
www.onsemi.com
29
NCV81599, NCP81599
way to reduce the dv/dt. The side effect of the above two
methods are that losses would be increased because of slow
switching speed.
• VCC Decoupling: Place decoupling caps as close as
possible to the controller VCC pin. Place the RC filter
connecting with VDRV pin in general proximity of the
controller. The filter resistor should be not higher than
10 W to prevent large voltage drop.
LAYOUT GUIDELINES
• VDRV Decoupling: Place decoupling caps as close as
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction.
• Current Sensing: Run two dedicated trace with decent
width in parallel (close to each other to minimize the
loop area) from the two terminals of the input side or
output side current sensing resistor to the IC. Place the
common−mode RC filter components in general
proximity of the controller.
possible to the controller VDRV pin.
• Input Decoupling: The device should be well
decoupled by input capacitors and input loop area
should be as small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low−ESL MLCC is placed very close
to the input port. Place these capacitors on the same
PCB layer with the MOSFETs instead of on different
layers and using vias to make the connection.
Route the traces into the pads from the inside of the current
sensing resistor. The drawing below shows how to rout the
traces.
• Output Decoupling: The output capacitors should be
as close as possible to the load.
• Switching Node: The converter’s switching node
should be a copper pour to carry the current, but
compact because it is also a noise source of electrical
and magnetic field radiation. Place the inductor and the
switching MOSFETs on the same layer of the PCB.
Current Path
• Bootstrap: The bootstrap cap and an option resistor
need to be in general close to the controller and directly
connected between pin BST1/2 and pin SW1/2
respectively.
• Ground: It would be good to have separated ground
planes for PGND and AGND and connect the AGND
planes to PGND through a dedicated net tie or 0 W
resistor.
• Voltage Sense: Route a “quiet” path for the input and
output voltage sense. AGND could be used as a remote
ground sense when differential sense is preferred.
• Compensation Network: The compensation network
should be close to the controller. Keep FB trace short to
minimize it capacitance to ground.
Current Sense
Resistor
PCB Trace
CSP/CSN
• Gate Driver: Run the high side gate, low side gate and
switching node traces in a parallel fashion with decent
width. Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing
Vsw1/2 trace to high−side MOSFET source pin instead
of copper pour area. The controller should be placed
close to the switching MOSFETs gate terminals and
keep the gate drive signal traces short for a clean
MOSFET drive. It’s OK to place the controller on the
opposite side of the MOSFETs.
• I2C Communication: SDA and SCL pins are digital
pins. Run SDA and SCL traces in parallel and reduce
the loop area. Avoid any sensitive analog signal trace or
noise source from crossing over or getting close.
Thermal Layout Considerations
Good thermal layout helps power dissipation and junction
temperature reduction.
• The exposed pads must be well soldered on the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around IC and
underneath the exposed pads to connect the inner
ground layers to reduce thermal impedance.
• Use large area copper pour to help thermal conduction
and radiation.
• V1 Pin: Input for the internal LDO. Place a decoupling
capacitor in general proximity of the controller. Run a
dedicated trace from system input bus to the pin and do
not route near the switching traces.
• Do not put the inductor too close to the IC, thus the heat
sources are distributed.
www.onsemi.com
30
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFNW32 5x5, 0.5P
CASE 484AB
ISSUE D
DATE 07 SEP 2018
32
1
SCALE 2:1
L3
L4
L3
L4
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
L
L
REFERENCE
ALTERNATE
CONSTRUCTION
DETAIL A
E
MILLIMETERS
EXPOSED
COPPER
DIM MIN
NOM
0.90
−−−
0.20 REF
−−−
0.25
5.00
3.10
5.00
3.10
0.50 BSC
−−−
0.40
−−−
0.08 REF
MAX
1.00
0.05
A
A1
A3
A4
b
D
D2
E
0.80
−−−
A4
A1
0.10
0.20
4.90
3.00
4.90
3.00
−−−
0.30
5.10
3.20
5.10
3.20
TOP VIEW
PLATING
A1
A4
ALTERNATE
CONSTRUCTION
DETAIL B
A
DETAIL B
(A3)
0.10
0.08
C
C
E2
e
C
C
L3
K
L
L3
L4
0.35
0.30
−−−
−−−
0.50
0.10
A3
A4
SEATING
PLANE
C
NOTE 4
SIDE VIEW
DETAIL A
PLATED
GENERIC
MARKING DIAGRAM*
SURFACES
D2
9
SECTION C−C
17
8
1
32X
L
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
E2
1
32
25
K
32X
b
e
XXXXX = Specific Device Code
M
0.10
C A B
e/2
BOTTOM VIEW
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
M
NOTE 3
0.05
C
WL
YY
WW
G
RECOMMENDED
SOLDERING FOOTPRINT*
(Note: Microdot may be in either location)
5.30
32X
0.63
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
3.35
1
3.35
5.30
PACKAGE
OUTLINE
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14940G
QFNW32 5x5, 0.5P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 485CE
ISSUE O
DATE 07 FEB 2012
32
1
SCALE 2:1
A
B
D
NOTES:
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
ALTERNATE
E
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
1.00
0.05
0.15
C
A
A1
A3
b
0.80
−−−
0.20 REF
0.20
EXPOSED Cu
MOLD CMPD
0.15
C
0.30
3.60
3.60
TOP VIEW
D
5.00 BSC
D2 3.40
DETAIL B
(A3)
E
5.00 BSC
DETAIL B
0.10
0.08
C
C
E2 3.40
ALTERNATE
CONSTRUCTION
e
K
L
0.50 BSC
A
0.20
0.30
−−−
−−−
0.50
0.15
L1
SEATING
PLANE
A1
K
NOTE 4
C
SIDE VIEW
D2
GENERIC
MARKING DIAGRAM*
DETAIL A
1
8
XXXXXXXX
XXXXXXXX
AWLYYWWG
17
E2
32X
L
24
1
XXXXX = Specific Device Code
32
25
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
32X b
e
e/2
WL
YY
WW
G
M
M
0.10
C
C
A-B B
NOTE 3
0.05
BOTTOM VIEW
RECOMMENDED
*This information is generic. Please refer
to device data sheet for actual part
marking.
SOLDERING FOOTPRINT*
5.30
32X
0.62
Pb−Free indicator, “G” or microdot “ G”,
3.70
may or may not be present.
3.70
5.30
0.50
PITCH
32X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34336E
TDFN8, 2X3, 0.5P
PAGE 1 OF 1
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