NCS20232MUTAG [ONSEMI]
Operational Amplifier, 36 V, 3 MHz, 0.95 mV Input Offset Voltage, Rail-to-Rail;型号: | NCS20232MUTAG |
厂家: | ONSEMI |
描述: | Operational Amplifier, 36 V, 3 MHz, 0.95 mV Input Offset Voltage, Rail-to-Rail |
文件: | 总24页 (文件大小:777K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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Operational Amplifier, 36 V,
3 MHz, 0.95 mV Input Offset
Voltage, Rail-to-Rail
5
5
1
1
SC−88A / SC70−5
CASE 419A−02
TSOP−5
CASE 483
NCS20231, NCV20231,
NCS20232, NCV20232,
NCS20234, NCV20234
1
SOT−553, 5 LEAD
UDFN8
CASE 517AW
CASE 463B
The NCS2023x series of op amps feature a wide supply range of
2.7 V to 36 V with an input offset voltage as low as 0.95 mV max.
These op amps are available in single, dual, and quad channel
configurations. Automotive qualified options are available under the
NCV prefix with an optional extended operating temperature range
from −40°C to 150°C. All other versions are specified over the
operating temperature range from −40°C to 125°C.
8
14
1
1
SOIC−14 NB
CASE 751A−03
SOIC−8 NB
CASE 751−07
Features
• Supply Voltage Range: 2.7 V to 36 V
• Temperature Range: −40°C to 150°C
• Unity Gain Bandwidth: 3 MHz
14
1
TSSOP−14 WB
CASE 948G
• Input Offset Voltage: 1.2 mV max, T = −40 to 150°C
A
• Input Offset Voltage Drift: 2 mV/°C max
• Common−Mode Input Voltage Range
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 2 of this data sheet.
♦ Optimal: V – 0.1 to V − 2 V
SS
DD
♦ Functional: V – 0.1 to V + 0.1 V
SS
DD
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
PIN CONNECTIONS
See pin connections on page 3 of this data sheet.
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
• Telecom Equipment
• Power Supply Designs
• Diesel Injection Control
• Automotive
• Motor Control
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
April, 2022 − Rev. 2
NCS20231/D
NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
DEVICE MARKING INFORMATION
XXAYWG
XXMG
XXMG
G
G
G
TSOP−5
CASE 483
SC−88A / SC70−5
CASE 419A−02
SOT−553, 5 LEAD
CASE 463B
14
14
1
8
1
XX
AYWW
G
XXG
AWLYWW
XX
ALYWG
G
XX
YM
1
1
UDFN8, 2x2, 0.5P
CASE 517AW
SOIC−8 NB
CASE 751−07
SOIC−14 NB
CASE 751A−03
TSSOP−14 WB
CASE 948G
XX
A
Y
= Specific Device Code
= Assembly Location
= Year
W
M
= Work Week
= Date Code
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
†
Temperature
Industrial and Commercial
−40°C to 125°C
Channels
Package
Device Part Number
Marking
Shipping
Single
TSOP−5
SC−88
NCS20231SN2T1G
NCS20231SQ3T2G
NCS20231XV53T2G
NCS20232DR2G*
NCS20232MUTBG*
NCS20234DR2G*
NCS20234DTBR2G*
AAC
AAG
AC
3000 / Tape & Reel
3000 / Tape & Reel
4000 / Tape & Reel
2500 / Tape & Reel
3000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
SOT−553
SOIC−8
Dual
N232
DGA
234G
N234
UDFN−8
SOIC−14
TSSOP−14
Quad
Automotive Qualified, Grade 1
−40°C to 150°C
Single
TSOP−5
SC−88
NCV20231SN2T1G
NCV20231SQ3T2G
NCV20231XV53T2G
NCV20232DR2G*
NCV20234DR2G*
NCV20234DTBR2G*
AAC
AAG
AC
3000 / Tape & Reel
3000 / Tape & Reel
4000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
SOT−553
SOIC−8
Dual
N232
234G
N234
Quad
SOIC−14
TSSOP−14
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*In Development. Contact local sales office for more information.
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2
NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
PIN CONNECTIONS
Single Channel
1
2
3
5
OUT
VSS
IN+
IN+
VSS
IN−
VDD
OUT
1
2
3
VDD
5
4
4
IN−
SOT−553 / SC−88
SOT23−5 / TSOP−5
Dual Channel
Quad Channel
1
2
3
4
5
6
7
OUT 1
IN− 1
IN+ 1
VDD
14
13
12
11
10
9
OUT 4
IN− 4
IN+ 4
OUT 1
IN− 1
IN+ 1
VSS
1
2
3
4
8
7
6
5
VDD
−
−
−
OUT 2
IN− 2
IN+ 2
+
+
+
−
+
VSS
IN+ 3
IN− 3
OUT 3
IN+ 2
IN− 2
+
+
SOIC−8 / UDFN8
−
−
8
OUT 2
SOIC−14, TSSOP−14
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3
NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
ABSOLUTE MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Value
Unit
V
Supply Voltage Range (V − V
)
V
S
−0.3 to 40
DD
SS
Input Common−Mode Voltage
V
CM
V
SS
– 0.2 to V + 0.2
V
DD
Differential Input Voltage
Maximum Input Current
Maximum Output Current
V
V
V
ID
S
I
10
100
mA
mA
mW
°C
°C
V
I
I
O
Continuous Total Power Dissipation
Maximum Junction Temperature
P
200
D
T
150
J(max)
Storage Temperature Range
T
STG
−65 to 150
2000
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charge Device Model (Note 2)
Moisture Sensitivity Level
HBM
CDM
MSL
1000
V
Level 1
260
Lead Temperature Soldering
T
SLD
°C
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001−2017 (AEC−Q100−002)
ESD Charged Device Model tested per JEDEC standard JS−002−2014 (AEC−Q100−011)
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS (Note 4)
Package
q
JA
Y
JT
Y
JB
Unit
Junction−to−Ambient
Junction−to−Case Top
Junction−to−Board
Thermal Resistance
Thermal Characteristic
Thermal Characteristic
TSOP−5 / SOT23−5
SC−88A / SC−70−5 / SOT−353
SOT−553
254
902
238
78
70
14
150
810
134
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
SOIC−8
UDFN−8
SOIC−14
TSSOP−14
4. Thermal parameters are based on a 2s2p board following JESD51−7 (JEDEC)
RECOMMENDED OPERATING RANGES (Note 5)
Parameter
Symbol
Min
Max
36
Unit
V
Supply Voltage (V − V
)
V
S
2.7
DD
SS
Differential Input Voltage (V
− V )
IN−
V
ID
5 (Note 6)
V
IN+
Input Common−Mode Range (Note 7)
V
CM
V
SS
– 0.1
V − 2 V
DD
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area
6. The differential voltage may not exceed the supply voltage, V . For supplies greater than V = 5 V, differential voltages up to
V will
S
S
S
consume more input current. See APPLICATION INFORMATION.
7. The specified input common mode range yields the best performance. However, the input common mode range is functional up to V
0.1 V. See APPLICATION INFORMATION.
+
DD
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NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
ELECTRICAL CHARACTERISTICS (V = 2.7 V to 36 V)
S
At T = +25°C, R = 10 kW connected to midsupply, V
= V
= midsupply, unless otherwise noted.
A
L
CM
OUT
Boldface limits apply over the specified temperature range, guaranteed by characterization and/or design.
Supply
Voltage (V)
Parameter
Symbol
Conditions
Temp (°C)
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
V
V
= mid−supply
= mid−supply
2.7, 5, 10, 36
25
0.3
0.95
1.2
1.2
2
mV
OS
CM
−40 to 125
−40 to 150
−40 to 125
−40 to 150
25
Offset Voltage Drift
over Temperature
dV /dT
OS
2.7, 5, 10, 36
2.7, 5, 10, 36
0.5
0.5
5
mV/°C
CM
5
Input Bias Current
(Note 8)
I
60
pA
IB
−40 to 125
150
3000
10000
0.5
Input Offset Current
(Note 8)
I
2.7
5, 10
25
60
500
2000
60
pA
OS
−40 to 125
−40 to 150
25
0.5
0.5
−40 to 125
−40 to 150
25
800
2500
60
36
pA
−40 to 125
−40 to 150
25
2000
2500
Channel Separation
Input Capacitance
NCS20232,
NCS20234
2.7, 5, 10, 36
130
dB
pF
C
IN+
2.7, 36
2.7, 36
2.7
25
25
1
6
IN
IN−
Common Mode
Rejection Ratio
CMRR
V
= V − 0.1 V to
25
80
75
98
dB
CM
SS
V
DD
− 2 V
−40 to 125
−40 to 150
25
69
5
90
105
117
122
125
(Note 8)
−40 to 125
−40 to 150
25
85
80
10
(Note 8)
100
100
94
−40 to 125
−40 to 150
25
36
110
110
107
−40 to 125
−40 to 150
25
V
= V + 1.8 V
DD
36
117
(Note 8)
dB
dB
CM
SS
to V − 2.4 V
EMI Rejection Ratio
EMIRR
2.7, 36
25
See
Figure
29
8. Guaranteed by design and/or characterization.
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NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
ELECTRICAL CHARACTERISTICS (V = 2.7 V to 36 V) (continued)
S
At T = +25°C, R = 10 kW connected to midsupply, V
= V
= midsupply, unless otherwise noted.
A
L
CM
OUT
Boldface limits apply over the specified temperature range, guaranteed by characterization and/or design.
Supply
Voltage (V)
Parameter
Symbol
Conditions
Temp (°C)
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS
Open Loop Voltage
Gain
A
VOL
V
CM
= mid−supply
2.7
25
100
90
115
dB
−40 to 125
−40 to 150
25
90
5
120
115
115
130
120
120
135
130
130
135
145
154
(Note 9)
−40 to 125
−40 to 150
25
10
(Note 9)
−40 to 125
−40 to 150
25
36
−40 to 125
−40 to 150
Open Loop Output
Impedance
Z
OUT
See
Figure
28
W
High Level Output
Voltage Swing from
DD
V
−V
R = 10 kW
2.7, 5, 10, 36
2.7, 5, 10, 36
10
25
60
80
120
150
60
mV
DD
OH
L
−40 to 125
−40 to 150
25
V
R = 1 mA
L
40
−40 to 125
−40 to 150
25
80
100
200
350
400
30
R = 5 mA
L
165
16
−40 to 125
−40 to 150
25
Low Level Output
V
−V
SS
R = 10 kW
L
2.7, 5, 10
36
mV
OL
Voltage Swing from
−40 to 125
−40 to 150
25
50
V
SS
50
55
80
−40 to 125
−40 to 150
25
250
120
50
R = 1 mA
L
2.7, 5, 10, 36
35
−40 to 125
−40 to 150
25
80
80
R = 5 mA
10
150
170
300
300
L
−40 to 125
−40 to 150
25
Output Current
Capability
I
Output to V rail,
2.7, 5, 10, 36
2.7, 5, 10, 36
2.7 to 36
28
28
mA
pF
OUT
DD
sinking current
Output to V rail,
25
25
SS
sourcing current
Capacitive Load
Drive
C
Phase margin = 35°
140
L
9. Guaranteed by design and/or characterization.
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NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
ELECTRICAL CHARACTERISTICS (V = 2.7 V to 36 V) (continued)
S
At T = +25°C, R = 10 kW connected to midsupply, V
= V
= midsupply, unless otherwise noted.
A
L
CM
OUT
Boldface limits apply over the specified temperature range, guaranteed by characterization and/or design.
Supply
Voltage (V)
Parameter
Symbol
Conditions
Temp (°C)
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Gain Bandwidth
Product
GWBP
C = 25 pF
L
2.7, 5, 10, 36
25
3
MHz
Gain Margin
Phase Margin
Slew Rate
A
C = 25 pF
2.7, 5, 10, 36
25
25
25
25
25
25
25
25
25
25
25
16
60
4
dB
°
m
L
F
C = 25 pF
L
2.7, 5, 10, 36
m
SR
Unity gain, R = 2 kW
2.7, 5, 10, 36
V/ms
ms
L
Settling Time to
0.1 %
t
s
V
V
V
= 1 V step
= 3 V step
= 8 V step
= 10 V step
= 1 V step
= 3 V step
= 8 V step
= 10 V step
2.7
5
7
IN
IN
IN
7
10
36
2.7
5
7
V
6
IN
Settling Time to
0.01 %
t
s
V
V
V
20
10
9
ms
IN
IN
IN
10
36
V
9
IN
NOISE PERFORMANCE
Total Harmonic
THD+ N
V
= 0.5 V
,
2.7
25
25
25
25
25
0.009
0.0004
0.0002
0.0002
%
IN
pp
Distortion + Noise
f = 1 kHz, A = 1
V
V
IN
= 2.5 V
,
5
pp
f = 1 kHz, A = 1
V
V
IN
= 7.5 V
,
10
36
pp
f = 1 kHz, A = 1
V
V
IN
= 28.5 V ,
pp
f = 1 kHz, A = 1
V
Voltage Noise
Density
f = 1 kHz
f = 10 kHz
f = 1 kHz
2.7, 5, 10, 36
20
20
30
nV/√Hz
fA/√Hz
e
n
Current Noise
Density
i
n
2.7, 5, 10, 36
2.7, 5, 10, 36
25
25
Voltage Noise, Peak
to Peak
e
pp
f
= 0.1 Hz to 10 Hz
700
nV
pp
IN
POWER SUPPLY
Power Supply
Rejection Ratio
PSRR
Vs = 2.7 V to 36 V
2.7, 36
2.7, 5
10
25
125
120
120
138
dB
−40 to 125
−40 to 150
25
Quiescent Current
I
Q
No load, per channel
0.37
0.375
0.41
0.595
0.650
0.7
mA
−40 to 125
−40 to 150
25
0.595
0.650
0.75
−40 to 125
−40 to 150
25
36
0.595
0.650
0.8
−40 to 125
−40 to 150
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
TYPICAL CHARACTERISTICS
Typical Performance at T = 25°C, VCM = mid−supply, C = 20 pF, R = 10 kW to mid−supply, unless otherwise noted
A
L
L
20
18
16
14
12
10
8
50
45
40
35
30
25
20
15
10
150 Samples
over 5 Lots
60 Samples
over 2 Lots
T = −40 to 125°C
A
6
4
2
0
−1.0
5
0
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
−0.6
−0.2
0.2
0.6
1.0
INPUT OFFSET VOLTAGE (mV)
INPUT OFFSET DRIFT (mV/°C)
Figure 1. Input Offset Voltage Distribution
Figure 2. Input Offset Voltage Drift Distribution
10
8
0.30
0.25
0.20
0.15
0.10
T = −40°C
V
DD
V
SS
= 5 V
= 0 V
T = −40°C
A
A
V
DD
V
SS
= 5 V
= 0 V
T = 0°C
T = 0°C
A
A
T = 25°C
6
T = 25°C
A
A
T = 85°C
T = 85°C
A
A
4
T = 125°C
T = 125°C
A
A
2
T = 150°C
A
T = 150°C
A
0
−2
−4
−6
0.05
0
−8
−10
−0.5
0.5
1.5
2.5
3.5
4.5
5.5
−0.5
0.5
1.5
2.5
3.5
4.5
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
Figure 3. Input Offset Voltage vs. Common
Mode Voltage
Figure 4. Input Offset Voltage vs. Common
Mode Voltage, Performance Region
60
40
20
0
16000
14000
12000
10000
8000
V
S
= 36 V
V
S
= 36 V
I
I
I
IB+
IB−
OS
6000
−20
4000
I
I
I
IB+
IB−
OS
2000
−40
−60
0
−2000
−5
0
5
10
15
20
25
30
35
40
−50 −25
0
25
50
75
100
125 150
COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
Figure 5. Input Current vs. Common Mode
Voltage
Figure 6. Input Current vs. Temperature
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NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
TYPICAL CHARACTERISTICS
Typical Performance at T = 25°C, VCM = mid−supply, C = 20 pF, R = 10 kW to mid−supply, unless otherwise noted
A
L
L
120
100
80
60
40
20
0
120
100
80
60
40
20
Gain
Phase
0
−20
−40
−20
10
10
0
100
1K
10K
100K
1M
10M
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Open Loop Gain and Phase vs.
Frequency
Figure 8. CMRR vs. Frequency
140
120
100
80
70
60
R
R
R
= 0 W
= 25 W
= 50 W
S
S
S
PSRR+
V
S
= 10 V
50
40
PSRR−
60
40
20
30
20
0
−20
100
1K
10K
100K
1M
10M
0
20
40
60
80 100 120 140 160 180
FREQUENCY (Hz)
LOAD CAPACITANCE (pF)
Figure 9. PSRR vs. Frequency
Figure 10. Phase Margin vs. Capacitive Load
30
25
20
15
10
1.2
1.0
0.8
0.6
0.4
R
R
R
= 0 W
= 25 W
= 50 W
T = −40°C
S
S
S
A
V
S
= 10 V
T = 25°C
A
T = 125°C
A
5
0
0.2
0
20
40
60
80 100 120 140 160 180
0
5
10
15
LOAD CAPACITANCE (pF)
OUTPUT CURRENT (mA)
Figure 11. Gain Margin vs. Capacitive Load
Figure 12. Output Voltage Swing High vs.
Output Current at VS = 2.7 V
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NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
TYPICAL CHARACTERISTICS
Typical Performance at T = 25°C, VCM = mid−supply, C = 20 pF, R = 10 kW to mid−supply, unless otherwise noted
A
L
L
1.0
0.8
0.6
0.4
1.2
1.0
0.8
0.6
0.4
T = −40°C
T = −40°C
A
A
T = 25°C
T = 25°C
A
A
T = 125°C
A
T = 125°C
A
0.2
0
0.2
0
0
5
10
15
0
5
10
15
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 13. Output Voltage Swing vs. Output
Current at VS = 2.7 V
Figure 14. Output Voltage Swing vs. Output
Current at VS = 36 V
1.0
0.8
0.6
0.4
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
V
S
V
S
V
S
V
S
= 2.7 V
= 5 V
= 10 V
= 36 V
T = −40°C
A
T = 25°C
A
T = 125°C
A
0.2
0
0.32
0.30
0
5
10
15
−50 −25
0
25
50
75
100
125 150
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
Figure 15. Output Voltage Swing vs. Output
Current at VS = 36 V
Figure 16. Quiescent Current vs. Temperature
8
6
8
6
Output
Input
V = 10 V
S
A = 1
V
4
4
2
2
Output
Input
0
0
−2
−4
−2
−4
V
= 10 V
S
A = 1
V
−6
−8
−6
−8
TIME (2 ms/div)
TIME (2 ms/div)
Figure 17. Large Signal Step Response
Figure 18. Large Signal Step Response
www.onsemi.com
10
NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
TYPICAL CHARACTERISTICS
Typical Performance at T = 25°C, VCM = mid−supply, C = 20 pF, R = 10 kW to mid−supply, unless otherwise noted
A
L
L
0.075
0.050
0.075
0.050
Output
Input
Output
Input
0.025
0
0.025
0
V
= 10 V
V
= 10 V
S
S
−0.025
−0.025
A = −1
V
A = 1
V
−0.050
−0.075
−0.050
−0.075
TIME (1 ms/div)
TIME (1 ms/div)
Figure 19. Small Signal Step Response
Figure 20. Small Signal Step Response
6
4
100
20
15
10
5
V
= 18 V
S
A = −10 V/V
V
80
60
40
20
V
= 18 V
S
Input
Output
A = −1 V/V
V
2
0
Input (V)
Output (mV)
−2
0
−4
−6
0
−5
−20
−10
TIME (2 ms/div)
TIME (4 ms/div)
Figure 21. Settling Time
Figure 22. Output Overload Recovery
Response
8
6
0.001
V
= 36 V
S
Output
Input
R = 10 kW
L
V
IN
= 28.5 V
PP
4
A = 1
V
2
0.0001
0
−2
−4
V
= 10 V
S
−6
−8
A = 1
V
0.00001
10
100
1K
10K
TIME (2 ms/div)
FREQUENCY (Hz)
Figure 23. No Phase Reversal
Figure 24. THD+n vs. Frequency
www.onsemi.com
11
NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
TYPICAL CHARACTERISTICS
Typical Performance at T = 25°C, VCM = mid−supply, C = 20 pF, R = 10 kW to mid−supply, unless otherwise noted
A
L
L
1000
800
600
400
200
0
100
−200
−400
−600
−800
−1000
10
10
100
1K
10K
100K
1M
TIME (1 s/div)
FREQUENCY (Hz)
Figure 25. 0.1 Hz to 10 Hz Noise
Figure 26. Voltage Noise Density vs.
Frequency
100
10
1
10K
1K
V
S
V
S
V
S
= 2.7 V
= 10 V
= 36 V
V
S
V
S
V
S
V
S
= 2.7 V
= 5 V
= 10 V
= 36 V
100
0.1
10
1
0.01
0.001
100
1K
10K
100K
1M
10M
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27. Current Noise Density vs.
Frequency
Figure 28. Open Loop Output Impedance vs.
Frequency
120
100
80
0
−20
V
S
V
S
= 2.7 V
= 36 V
−40
−60
60
−80
40
−100
20
0
−120
−140
10M
100M
FREQUENCY (Hz)
1000M
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
Figure 29. EMIRR vs. Frequency
Figure 30. Channel Separation vs. Frequency
www.onsemi.com
12
NCS20231, NCV20231, NCS20232, NCV20232, NCS20234, NCV20234
APPLICATION INFORMATION
Input and ESD Structure
current should be expected. Internal current limiting
resistors in series with the input pins limit the current to
10 mA in scenarios where the differential voltage is as high
as 36 V.
The NCS20231 series amplifiers have back−to−back
Zener diodes, which allow for normal operation with the
differential voltage up to 5 V. Differential voltages beyond
this are permitted, up to V , but increased input leakage
S
VDD
1.5 k
IN+
+
ESD
OUT
1.5 k
−
IN−
VSS
Figure 31. Representative Schematic of the Op Amp
Each input pin is diode clamped to the rails. In case of an
input overvoltage, input currents must be limited to within
10 mA to prevent excessive current from damaging the
part.
shown
throughout
the
ELECTRICAL
CHARACTERISTICS table, is achieved in the V – 0.1 V
SS
to V
– 2 V common mode voltage range. The input
DD
common mode extends further up to V + 0.1 V to ensure
DD
functionality near the upper rail, though without precision
performance in that region. The typical performance within
Rail−to−Rail Performance
The functional common mode input voltage spans
100 mV beyond the rails. High precision performance, as
the V – 2 V to V + 0.1 V range is shown in the table
DD
DD
below.
Parameter
Input Offset Voltage
Symbol
Conditions
V = V – 0.5 V
CM
Typ
9
Units
mV
V
OS
DD
Input Offset Voltage over Temperature
Common Mode Rejection Ratio
Open Loop Voltage Gain
Gain Bandwidth Product
Slew Rate
dV /dT
24
mV/°C
dB
OS
CMRR
V
= V – 0.5 V to V + 0.1 V
75
CM
DD
DD
A
VOL
V
CM
= V − 0.5 V
90
dB
DD
GBWP
SR
V
= V − 0.5 V, C = 25 pF
2.5
1.2
1000
MHz
V/ms
nV/√Hz
CM
DD
L
Unity gain, V
= V – 1 V to V – 0.2 V
DD DD
CM
Voltage Noise Density
e
n
f = 1 kHz
The NCS2023x does not exhibit output phase reversal.
Phase reversal occurs in some amplifiers when the input
voltage exceeds the recommended input common mode
voltage range, causing the output to flip to the opposite rail.
Instead, when the input common mode voltage range is
exceeded on the NCS2023x, the output becomes clipped at
the output, limited by the output voltage swing.
www.onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE M
SCALE 2:1
DATE 11 APR 2023
GENERIC MARKING
DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
XXXMG
G
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
STYLE 1:
STYLE 2:
STYLE 3:
PIN 1. ANODE 1
2. N/C
STYLE 4:
STYLE 5:
PIN 1. BASE
PIN 1. ANODE
2. EMITTER
3. BASE
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
4. COLLECTOR
5. CATHODE
4. CATHODE 3
5. CATHODE 4
5. GATE 2
STYLE 9:
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
STYLE 7:
STYLE 8:
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
PIN 1. BASE
2. EMITTER
3. BASE
PIN 1. CATHODE
2. COLLECTOR
3. N/C
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
4. COLLECTOR
5. COLLECTOR
4. BASE
5. EMITTER
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
SC−88A (SC−70−5/SOT−353)
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−553, 5 LEAD
CASE 463B
ISSUE C
SCALE 4:1
DATE 20 MAR 2013
NOTES:
D
−X−
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
A
L
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
5
4
3
MILLIMETERS
INCHES
NOM
0.022
0.009
0.005
0.063
0.047
0.020 BSC
0.008
0.063
E
−Y−
DIM
A
b
c
D
E
e
L
H
MIN
0.50
0.17
0.08
1.55
1.15
NOM
0.55
0.22
0.13
1.60
MAX
MIN
MAX
0.024
0.011
0.007
0.065
0.049
H
E
0.60
0.27
0.18
1.65
1.25
0.020
0.007
0.003
0.061
0.045
1
2
b 5 PL
c
1.20
e
M
0.50 BSC
0.20
1.60
0.08 (0.003)
X Y
0.10
1.55
0.30
1.65
0.004
0.061
0.012
0.065
E
RECOMMENDED
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.3
0.0118
XXMG
G
0.45
0.0177
XX = Specific Device Code
1.0
0.0394
M
G
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
1.35
0.0531
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.5
0.5
0.0197 0.0197
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLE 1:
STYLE 2:
STYLE 3:
PIN 1. ANODE 1
2. N/C
STYLE 4:
STYLE 5:
PIN 1. BASE
PIN 1. CATHODE
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
PIN 1. ANODE
2. EMITTER
3. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
4. COLLECTOR
5. CATHODE
5. GATE 2
STYLE 9:
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
STYLE 7:
PIN 1. BASE
STYLE 8:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
PIN 1. CATHODE
2. COLLECTOR
3. N/C
2. EMITTER
3. EMITTER 1
4. COLLECTOR 1
5. COLLECTOR 2/BASE 1
3. BASE
4. COLLECTOR
5. COLLECTOR
4. BASE
5. EMITTER
98AON11127D
DOCUMENT NUMBER:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
ONSEMICONDUCTOR STANDARD
STATUS:
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: SOT−553, 5 LEAD
PAGE 1 OF2
DOCUMENT NUMBER:
98AON11127D
PAGE 2 OF 2
ISSUE
REVISION
ADDED STYLES 3−9. REQ. BY D. BARLOW
DATE
A
B
11 NOV 2003
27 MAY 2005
ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ.
BY HONG XIAO
C
UPDATED DIMENSIONS D, E, AND HE. REQ. BY J. LETTERMAN.
20 MAR 2013
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2013
Case Outline Number:
March, 2013 − Rev. C
463B
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
DATE 12 AUG 2020
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
C
D
MIN
2.85
1.35
0.90
0.25
MAX
3.15
1.65
1.10
0.50
DETAIL Z
J
G
H
J
K
M
S
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
2.50
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
1.9
5
1
5
0.074
0.95
XXXAYWG
XXX MG
0.037
G
G
1
Analog
Discrete/Logic
2.4
0.094
XXX = Specific Device Code XXX = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
M
G
= Date Code
= Pb−Free Package
1.0
0.039
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN8, 2x2
CASE 517AW
ISSUE A
1
SCALE 2:1
DATE 13 NOV 2015
B
E
A
NOTES:
D
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMI-
NALS AND IS MEASURED BETWEEN 0.15
AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
L1
PIN ONE
REFERENCE
DETAIL A
ALTERNATE
CONSTRUCTIONS
2X
0.10 C
2X
0.10
C
TOP VIEW
MILLIMETERS
MOLD CMPD
DIM MIN
MAX
0.55
0.05
EXPOSED Cu
A
A1
A3
b
D
D2
E
E2
e
L
L1
0.45
0.00
DETAIL B
A
0.13 REF
0.10
C
A3
C
0.18
2.00 BSC
1.50
0.30
1.70
A3
A1
0.08
C
DETAIL B
2.00 BSC
A1
SIDE VIEW
0.80
1.00
NOTE 4
ALTERNATE
SEATING
PLANE
0.50 BSC
CONSTRUCTION
0.20
−−−
0.45
0.15
D2
DETAIL A
8X L
1
4
GENERIC
MARKING DIAGRAM*
E2
b
1
XX MG
G
5
8
8X
e
e/2
XX = Specific Device Code
0.10
C
C
A
B
M
= Date Code
0.05
NOTE 3
G
= Pb−Free Package
BOTTOM VIEW
(Note: Microdot may be in either location)
RECOMMENDED
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
8X
1.73
0.50
PACKAGE
OUTLINE
2.30
1.00
1
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34462E
UDFN8, 2X2
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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