NCS3402DR2G [ONSEMI]
比较器，双路，低功耗;
| 型号： | NCS3402DR2G |
| 厂家： | 
ONSEMI |
| 描述： | 比较器，双路，低功耗 比较器 |
| 文件： | 总10页 (文件大小：732K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCS3402
Dual Nano-power Open
Drain Output Comparator
The NCS3402 is a nano−power comparator consuming only 470 nA
per channel supply current, which make this device ideal for battery
power and wireless handset applications.
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MARKING
The NCS3402 has a minimum operating supply voltage of 2.7 V
over the extended industrial temperature range (T = −40°C to 125°C),
A
while having an input common−mode range of −0.1 to V + 5 V.
DD
DIAGRAMS
The ultra low supply current makes the NCS3402 an ideal choice for
battery powered and portable applications where quiescent current is
the primary concern. Reverse battery protection guards the amplifier
from an over−current condition due to improper battery installation.
For harsh environments, the inputs can be taken 5 V above the positive
supply rail without damage to the device.
8
SOIC−8
D SUFFIX
CASE 751
N3402
8
ALYWG
G
1
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
• Low Supply Current: 470 nA/Per Channel
♦ Input Common−Mode Range exceeds the rails
♦ −0.1 V to VDD + 5 V
(Note: Microdot may be in either location)
• Supply Voltage Range: 2.7 V to 16 V
• Reverse Battery Protection Up to 18 V
• Open Drain CMOS Output Stage
PIN CONNECTIONS
• Specified Temperature Range
V
1
2
3
4
8
7
6
5
OUT1
DD
♦ −40°C to 125°C
OUT2
IN−2
IN−1
• This is a Pb−Free Device
IN+1
Typical Applications
V
IN +2
SS
• Voltage Sense Circuit
• PSU Monitoring Circuit
• Wireless Handsets
(Top View)
• Portable Medical Equipment
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
April, 2013 − Rev. 2
NCS3402/D
NCS3402
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
OUT1
IN−1
Description
1
2
3
4
5
6
7
8
Channel 1 Output
Channel 1 Inverting Input
Channel 2 Non−Inverting Input
Negative Power Supply
Channel 2 Non−Inverting Input
Channel 2 Inverting Input
Channel 2 Output
IN+2
V
SS
IN+2
IN−2
OUT2
V
DD
Positive Power Supply
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
17
Unit
V
Supply Voltage
V
DD
Differential Input Voltage
V
20
V
ID
IN
IN
Input Voltage Range (Notes 1 and 2)
Input Current Range
V
0 to V + 5
V
CC
I
10
10
mA
mA
°C
°C
°C
°C
Output Current Range
Io
Operating Free−Air Temperature Range
Maximum Junction Temperature
Storage Temperature Range
T
−40 to +125
150
A
T
J
T
STG
−65 to 150
260
Lead Temperature 1.6 mm (1/16 inch) from case for 10 seconds
T
SLD
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. All voltage values, except differential voltages, are respect to GND
2. Input voltage range is limited to 20V or V +5 V whichever is smaller
CC
ESD RATINGS
Rating
Symbol
HBM
Value
2000
200
Unit
V
Human Body Model
Machine Model
MM
V
THERMAL CHARACTERISTICS (Note 3)
Rating
Symbol
Value
Unit
Thermal Characteristics
°C/W
Thermal Resistance, Junction−to−Air SOIC8
R
176
q
JA
3. Power dissipation must be considered to ensure the maximum junction temperature (q ) is not exceeded.
JA
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Supply voltage
Single
supply
2.7
16
V
DD
V
Split supply
1.35
−0.1
− 40
8
Common−mode input voltage range
Operating free−air temperature
V
V
+5
V
ICR
DD
T
125
°C
A
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2
NCS3402
DC PERFORMANCE ELECTRICAL CHARACTERISTICS AT SPECIFIED OPERATING FREE−AIR TEMPERATURE,
V
S
= 2.7 V, 5 V, 15 V (unless otherwise noted)
Parameter
Symbol
Testing Conditions
T
A
Min
Typ
Max
Unit
25°C
250
3600
Input offset voltage
Offset voltage drift
V
mV
IO
Full
4400
V
CM
= V /2, R = 50 W, R = 1 MW
S S P
range
DV
25°C
25°C
3
mV/°C
IO
55
50
60
55
65
60
72
V
CM
= 0 to 2.7 V, R = 50 W
S
Full
range
25°C
76
88
Common−mode rejection
ratio
CMRR
dB
V
CM
= 0 to 5 V, R = 50 W
S
Full
range
25°C
V
CM
= 0 to 15 V, R = 50 W
S
Full
range
Large−signal differential
voltage amplification
A
VD
R
= 1 MW
P
25°C
1000
V/mV
INPUT/OUTPUT CHARACTERISTICS SPECIFIED OPERATING FREE−AIR TEMPERATURE,
= 2.7 V, 5 V, 15 V (unless otherwise noted)
V
S
25°C
20
80
100
1000
250
Input offset current
(Note 4)
I
pA
pA
IO
Full
range
V
CM
= V /2, R = 1 MW, R = 50 W
S
P
S
25°C
Input bias current
(Note 4)
I
IB
Full
range
3000
Differential input
resistance
R
V
= V /2
25°C
25°C
300
50
MW
ID
in
S
High−impedance output
leakage current
I
V
CM
= V /2, V = V , V = 1 V
pA
OZ
S
O
CC
ID
V
= V /2, I = 2 mA, V = −1 V
25°C
25°C
8
CM
S
OL
ID
80
200
300
Low−level output voltage
V
OL
mV
V
CM
= V /2, I = 50 mA, V = −1 V
S OL ID
Full
range
POWER SUPPLY SPECIFIED OPERATING FREE−AIR TEMPERATURE, V = 2.7 V, 5 V, 15 V (unless otherwise noted)
CC
25°C
470
560
100
105
550
750
640
950
Output state low
Output state high
Full
range
Supply current (per
channel)
I
R
= No pullup
nA
dB
CC
P
25°C
Full
range
25°C
75
70
85
80
V
CC
= 2.7 V to 5 V
= 5 V to 15 V
Full
range
Power supply rejection
ratio
V
CM
= V /2, No
S
PSRR
load
25°C
V
CC
Full
range
4. Guaranteed by design or characterization.
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3
NCS3402
SWITCHING CHARACTERISTICS AT RECOMMENDED OPERATING CONDITIONS,
VCC = 2.7 V, 5 V, 15 V, TA = 25°C (unless otherwise noted)
Parameter
Symbol
Testing Conditions
Overdrive = 2 mV
T
Min
Typ
220
85
Max
Unit
A
Propagation delay time,
low−to−high−level
Overdrive = 10 mV
Overdrive = 50 mV
Overdrive = 2 mV
Overdrive = 10 mV
Overdrive = 50 mV
t
25°C
(PLH)
f = 10 kHz,
30
VSTEP = 100 mV,
ms
ms
R
= 1 MW,
C = 10 pF
P
L
250
55
Propagation delay time,
high−to−low−level output
t
25°C
25°C
(PHL)
18
Fall time
tf
R
= 1 MW, C = 10 pF
5
P
L
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4
NCS3402
TYPICAL CHARACTERISTICS
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
V
R
= 15 V
= 1 MW
V
ID
= 1 V
DD
P
2.7 V
5 V
15 V
2.5
2.0
1.5
1.0
0.5
0
IIB−
IIB+
IIO
15 V
2.7 V
5 V
−40 −25 −10
5
20 35 50
65
80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
AMBIENT TEMPREATURE (°C)
AMBIENT TEMPREATURE (°C)
Figure 1. Input Bias/Offset Current vs.
Temperature
Figure 2. Open Drain Leakage Current vs.
Temperature
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
5
4.5
4
V
V
= 2.7 V
= −1 V
DD
V
= 5 V
= −1 V
DD
ID
V
ID
−40
0
25
70
125
−40
0
25
70
125
3.5
3
2.5
2
1.5
1
0.5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7 0.8
0
0.4
I , LOW LEVEL OUTPUT CURRENT (mA)
OL
0.8
1.2
1.6
2
2.4 2.8
I
OL
, LOW LEVEL OUTPUT CURRENT (mA)
Figure 3. Low Level Output Voltage vs. Low
Level Output Current
Figure 4. Low Level Output Voltage vs. Low
Level Output Current
15
13.5
12
10.5
9
800
700
600
500
400
300
200
100
0
V
ID
= −1 V
7.5
6
−40
0
25
70
125
−40
0
25
70
125
4.5
3
V
V
= 15 V
= −1 V
DD
1.5
0
ID
0
0.4
0.8
1.2
1.6
2
2.4
2.8
0
2
4
6
8
10
12
14
16
I
OL
, LOW LEVEL OUTPUT CURRENT (mA)
V
DD
SUPPLY (V)
Figure 5. Low Level Output Voltage vs. Low
Level Output Current
Figure 6. IDD vs. VDD vs. Temperature
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5
NCS3402
TYPICAL CHARACTERISTICS
700
600
500
400
300
200
100
0
V
= 2.7 V
DD
C = 10 pF
R
T = 25°C
A
L
= 1 MW to V
P
DD
5 V
15 V
50 mV
10 mV
2.7 V
2 mV
INPUT
−40 −25 −10
5
20 35 50 65 80 95 110 125
TIME (25 ms/div)
FREE−AIR TEMPERATURE (°C)
Figure 8. Propagation Delay L−H (2.7 V)
Figure 7. Supply Current vs. Free−Air
Temperature
V
= 2.7 V
V
= 15 V
DD
DD
C = 10 pF
R
T = 25°C
A
C = 10 pF
R
T = 25°C
A
L
L
= 1 MW to V
= 1 MW to V
P
DD
P
DD
50 mV
2 mV
10 mV
50 mV
INPUT
10 mV
2 mV
INPUT
TIME (25 ms/div)
TIME (25 ms/div)
Figure 9. Propagation Delay L−H (5 V)
Figure 10. Propagation Delay L−H (15 V)
2 mV
50 mV
50 mV
2 mV
10 mV
10 mV
INPUT
INPUT
= 5 V
V
DD
V
= 2.7 V
DD
C = 10 pF
L
C = 10 pF
R
T = 25°C
A
L
R
= 1 MW to V
P
DD
= 1 MW to V
P
DD
T = 25°C
A
TIME (25 ms/div)
TIME (25 ms/div)
Figure 11. Propagation Delay H−L (2.7 V)
Figure 12. Propagation Delay H−L (5 V)
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6
NCS3402
TYPICAL CHARACTERISTICS
8
V
= 15 V
DD
V
R
= 1 to -1V
= 1 MW to V
ID
C = 10 pF
R
T = 25°C
A
7
6
5
4
3
2
1
0
L
P
DD
= 1 MW to V
P
DD
3 Devices Shown
T = 25°C
A
50 mV
2 mV
10 mV
1 − 10 pF
1 − 50 pF
2 − 10 pF
2 − 50 pF
3 − 10 pF
3 − 50 pF
INPUT
2.7
3
4
5
6
7
8
9 10 11 12 13 14 15
TIME (25 ms/div)
SUPPLY VOLTAGE (V)
Figure 13. Propagation Delay H−L (15 V)
Figure 14. Output Fall Time vs. Power Supply
ORDERING INFORMATION
Device
†
Package
Shipping
NCS3402DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
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