NCT375DMR2G [ONSEMI]
Digital Temperature Sensor with 2‐wire Interface and SMBus Time-Out;
| 型号： | NCT375DMR2G |
| 厂家： | 
ONSEMI |
| 描述： | Digital Temperature Sensor with 2‐wire Interface and SMBus Time-Out |
| 文件： | 总18页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCT375
Industry Standard Digital
Temperature Sensor with
2‐wire Interface
The NCT375 is a two-wire serially programmable temperature
sensor with an over-temperature/interrupt output pin to signal out of
limit conditions. This is an open-drain pin and can operate in either
comparator or interrupt mode. Temperature measurements are
converted into digital form using a high resolution (12 bit),
sigma-delta, analog-to-digital converter (ADC). The device operates
over the –55°C to +125°C temperature range.
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DFN8
CASE 506AA
SOIC8
CASE 751
Micro8t
Communication with the NCT375 is accomplished via the
CASE 846A
2
SMBus/I C interface. Three address selection pins, A2, A1 and A0,
can be used to connect up to 8 NCT375s to a single bus. Through this
interface the NCT375s internal registers may be accessed. These
registers allow the user to read the current temperature, change the
configuration settings and adjust the temperature limits.
The NCT375 has a wide supply voltage range of 3.0 V to 5.5 V. The
average supply current is 575 mA at 3.3 V. It also offers a shutdown
mode to conserve power. The typical shutdown current is 3 mA.
The NCT375 is available in three, space saving packages – 8-lead
DFN, 8-lead Micro8t and 8-lead SOIC and is also fully pin and
register compatible with the NCT75, LM75 and TCN75.
PIN ASSIGNMENT
1
2
3
4
8
7
6
5
SDA
SCL
V
DD
A0
A1
A2
(Top View)
OS/ALERT
GND
MARKING DIAGRAMS
8
Features
• 12-bit Temperature-to-Digital Converter
1
T375
35MG
• Input Voltage Range from 3.0 V to 5.5 V
• Temperature Range from −55°C to +125°C
AYWG
G
G
1
2
• SMBus/I C Interface
DFN8
Micro8t
• Overtemperature Indicator
M
= Date Code
• Support for SMBus/ALERT
A
Y
W
G
= Assembly Location
= Year
= Work Week
• Shutdown Mode for Low Power Consumption
• One-shot Mode
= Pb-Free Package
• Available in 8-pin DFN, 8-pin Micro8t and SOIC Packages
(Note: Microdot may be in either location)
• These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
8
Compliant
NCT375
ALYW
Applications
• Computer Thermal Monitoring
G
1
• Thermal Protection
SOIC8
• Isolated Sensors
• Battery Management
• Office Electronics
• Electronic Test Equipment
• Thermostat Controls
• System Thermal Management
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
June, 2015 − Rev. 0
NCT375/D
NCT375
8
V
DD
1
2
SDA
SCL
REGISTERS
CONFIGURATION
TWO-WIRE
INTERFACE
T
HYST
5
6
7
A2
A1
A0
3
TEMPERATURE
ONE-SHOT
T
OS
OS/ALERT
DELTA-SIGMA
ADC
CONTROL
LOGIC
4
GND
Figure 1. Simplified Block Diagram
V
DD
3.0 V To 5.5 V
C
BYPASS
5
6
7
A2
A1
A0
ADDRESS
(SET AS DESIRED)
1
2
SDA
SCL
NCT375
SERIAL INTERFACE
3
OS/ALERT
NOTE: SDA, SCL AND OS/ALERT PINS
REQUIRE PULL-UP RESISTORS TO V
DD
4
GND
Figure 2. Typical Application Circuit
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
SDA
Description
2
1
2
3
4
5
6
7
8
SMBus/I C Serial Bi-directional Data Input/Output. Open-drain pin; needs a pull-up resistor.
Serial Clock Input. Open-drain pin; needs a pull-up resistor.
SCL
OS/ALERT
GND
A2
Over-temperature Indicator. Open-drain output; needs a pullup resistor. Active Low output.
Power Supply Ground.
2
2
SMBus/I C Serial Bus Address Selection Pin. Connect to GND or V to set the desired I C address.
DD
2
2
A1
SMBus/I C Serial Bus Address Selection Pin. Connect to GND or V to set the desired I C address.
DD
2
2
A0
SMBus/I C Serial Bus Address Selection Pin. Connect to GND or V to set the desired I C address.
DD
V
DD
Positive Supply Voltage, 3.0 V to 5.5 V. Bypass to ground with a 0.1 mF bypass capacitor.
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NCT375
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Supply Voltage
V
DD
−0.3 to +7
Input Voltage on SCL, SDA, A2, A1, A0 and OS/ALERT.
Input Current on SDA, A2, A1, A0 and OS/ALERT.
Maximum Junction Temperature
Operating Temperature Range
−0.3 to V + 0.3
V
DD
I
−1 to +50
150.7
mA
°C
°C
°C
V
IN
T
J(max)
T
OP
−55 to 125
−65 to 160
2,000
Storage Temperature Range
T
STG
ESD Capability, Human Body Model (Note 1)
ESD Capability, Machine Model (Note 1)
ESD
HBM
ESD
400
V
MM
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Table 3. OPERATING RANGES
Rating
Symbol
Min
3.0
Max
5.5
Unit
V
Operating Supply Voltage
V
IN
Operating Ambient Temperature Range
T
A
−55
125
°C
Table 4. SMBus TIMING SPECIFICATIONS
Parameter
Symbol
Test Conditions
Min
DC
0.6
100
1.3
0.6
100
100
0
Typ
−
Max
400
−
Unit
Serial Clock Frequency
f
kHz
ms
ns
ms
ms
ns
ns
ns
ns
ns
ms
ms
ms
SCL
Start Condition Hold Time
Stop Condition Setup Time
Clock Low Period
t
−
HD:STA
SU:STO
t
90% of SCL to 10% of SDA
−
−
t
−
−
LOW
Clock High Period
t
−
−
HIGH
Start Condition Setup Time
Data Setup Time
t
90% of SCL to 90% of SDA
10% of SDA to 10% of SCL
10% of SCL to 10% of SDA
−
−
SU:STA
SU:DAT
HD:DAT
t
−
−
Data Hold Time (Note 2)
t
−
76
−
SDA/SCL Rise Time
t
R
−
300
300
−
SDA/SCL Fall Time
t
F
−
−
Minimum RESET Pulse Width
Bus Free Time Between STOP & START Conditions
SDA Time Low for Reset of Serial Interface
t
1.3
1.3
75
−
RESET
t
−
−
BUF
TIMEOUT
t
−
325
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. This refers to the hold time when the NCT375 is writing data to the bus.
t
R
t
F
t
HD;STA
t
LOW
SCL
SDA
t
HIGH
t
t
SU;STA
HD;STA
t
SU;STO
t
t
HD;DAT
SU;DAT
t
BUF
STOP START
STOP
START
Figure 3. Serial Interface Timing
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NCT375
Table 5. ELECTRICAL CHARACTERISTICS
(T = T
to T , V = 3.0 V to 5.5 V. All specifications for −55°C to +125°C, unless otherwise noted.)
MAX DD
A
MIN
Parameter
TEMPERATURE SENSOR AND ADC
Test Conditions
Min
Typ
Max
Unit
Accuracy at V = 3.0 V to 5.5 V
T
= 0°C to +70°C
= −25°C to +100°C
= −55°C to +125°C
−
−
−
−
−
−
1
2
3
°C
DD
A
T
A
T
A
ADC Resolution
−
−
−
−
12
0.0625
48.5
80
−
−
−
−
Bits
°C
Temperature Resolution
Temperature Conversion Time
Update Rate
One-shot Mode
ms
ms
POWER REQUIREMENTS
Supply Voltage
3.0
2.75
−
−
−
−
5.5
−
V
V
POR Threshold
2
Supply Current
Peak Current while Converting and I C
Interface Inactive
0.8
mA
Average Current
Average Current over 1 Conversion Cycle
Supply Current in Shutdown Mode
−
−
0.44
3
0.575
12
mA
Shutdown Mode at 3.3 V
OS/ALERT OUTPUT (OPEN DRAIN)
mA
Output Low Voltage, V
Pin Capacitance
I
= 4 mA
−
−
−
0.15
10
0.4
−
V
OL
OL
pF
mA
High Output Leakage Current, IOH
DIGITAL INPUTS (SDA, SCL)
Input Current
OS/ALERT Pin Pulled Up to 5.5 V
0.1
5
V
V
V
= 0 V to V
−
−
−
−
−
−
1
mA
V
IN
DD
Input Low Voltage, V
= 3.3 V (Note 3)
= 3.3 V (Note 3)
0.3 x V
DD
IL
DD
DD
Input High Voltage, V
0.7xV
−
V
IH
DD
SCL, SDA Glitch Rejection
Input Filtering Suppresses Noise Spikes of
Less than 50 ns
−
50
ns
Pin Capacitance
−
3
−
pF
DIGITAL OUTPUT (SDA) (OPEN DRAIN)
Output High Current, I
V
= 5 V
−
−
−
−
−
3
1
0.4
−
mA
V
OH
OH
Output Low Voltage, V
I
OL
= 3 mA
OL
Output Capacitance, C
pF
OUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Guaranteed by characterization, not production tested.
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4
NCT375
APPLICATION INFORMATION
Functional Description
While the ADC of the NCT375 can theoretically measure
temperatures in the range of −128°C to 127°C, the NCT375
is guaranteed to measure from −55°C to +125°C.
Table 6 shows the relevant temperature bits for a 12 bit
temperature reading. A 2-byte read is required to obtain the
full 12 bit temperature reading. If an 8 bit (1°C resolution)
reading is required then a single byte read is sufficient.
The NCT375 temperature sensor converts an analog
temperature measurement to a digital representation by
using an on-chip measurement transistor and a 12 bit
Delta-Sigma ADC.
The device includes an open drain ALERT output which
can be used to signal that the programmed temperature limit
has been exceeded.
The two main modes of operation are normal and
shutdown mode. In normal mode the NCT375 performs
a new temperature conversion every 80 ms. This new value
is then updated to the temperature value register
Table 6. 12-BIT TEMPERATURE DATA FORMAT
Binary Value
D15 to D4
Temperature
Hex Value
0xC90
0xE70
0xFFF
0x000
0x001
0x190
0x4B4
0x640
0x7D0
−55°C
1100 1001 0000
1110 0111 0000
1111 1111 1111
0000 0000 0000
0000 0000 0001
0001 1001 0000
0100 1011 0100
0110 0100 0000
0111 1101 0000
(address 0x00) and also compared to the T register limit
OS
−25°C
(default = 80°C). If the temperature value register is read
during the conversion sequence the value returned is the
previously stored value. A bus read does not affect the
conversion that is in progress.
In shutdown mode temperature conversion is disabled and
the temperature value register holds the last valid
temperature reading. The NCT375 can still be
communicated with in this mode as the interface is still
active. The device mode is controlled via bit 0 of the
configuration register.
−0.0625°C
0°C
+0.0625°C
+25°C
+75.25°C
+100°C
+125°C
While in shutdown mode a conversion can be initiated by
writing an arbitrary value to the one-shot register (0x04).
This has the effect of powering up the NCT375, performing
a conversion, comparing the new temperature with the
programmed limit and then going back into shutdown mode.
The OS/ALERT pin can be configured in many ways to
allow it to be used in many different system configurations.
The overtemperature output can be configured to operate
as a comparator type output (which is self clearing once the
temperature has returned below the hysteresis value) or an
interrupt type output (which requires the master to read an
internal register AND the temperature to return below the
hysteresis value before going into an inactive state). The
ALERT pin can also be configured as an active high or active
low output.
Temperature Data Conversion
12-bit Temperature Data Format
Positive Temperature = ADC Code (decimal)/16
Example 190h = 400d/16 = +25°C
Negative Temperature = (ADC Code(decimal) − 4096)/16
Example E70h = (3696d – 4096)/16 = −25°C
One-shot Mode
One of the features of the NCT375 is a One-shot
Temperature Measurement Mode. This mode is useful if
reduced power consumption is a design requirement.
To enable one-shot mode bit 5 of the configuration
register needs to be set. Once, enabled, the NCT375 goes
immediately into shutdown mode. Here, the current
consumption is reduced to a typical value of 3 mA. Writing
address 0x04 to the address pointer register initiates a
one-shot temperature measurement. This powers up the
NCT375, carries out a temperature measurement, and then
powers down again. The data written to this register is
irrelevant and is not stored. It is the write operation that
causes the one-shot conversion.
Temperature Measurement Results
The results of the on chip temperature measurements are
stored in the temperature value register and compared with
the T and T
limit register.
OS
HYST
The temperature value, T and T
registers are
OS
HYST
16 bits wide and have a resolution of 0.0625°C. The data is
stored as a 12 bit 2s complement word. The data is left
justified, D15 is the MSB and is the sign bit. The four LSBs
(D3 to D0) are always 0 as they are not part of the result.
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5
NCT375
Registers
The NCT375 contains six registers for configuring and
reading the teperature: the address pointer register, 4 data
registers and a one-shot register. The configuration register,
the address pointer register and the one-shot register are all
82°C
81°C
80°C
79°C
78°C
77°C
76°C
75°C
74°C
73°C
72°C
T
OS
8 bits wide while the temperature register, T
and T
HYST
OS
registers are all 16 bits wide. All registers, except for the
temperature register, can be be read from and written to (the
temperature register is read only). The power on state and
address of each register are listed in Table 9.
T
HYST
Address Pointer Register
The address pointer register is used to select which
register is to respond to a read or write operation. The three
LSBs (P2, P1 & P0) of this write only register are used to
select the appropriate register. On power up this register is
loaded with a value of 0x00 and so points to the temperature
register. Table 7 shows the bits of the address pointer register
and Table 8 shows the pointer address selecting each of the
registers available.
OS/ALERT PIN
(COMPARATOR MODE)
POLARITY = 0
OS/ALERT PIN
(INTERRUPT MODE)
POLARITY = 0
Table 7. ADDRESS POINTER REGISTER
OS/ALERT PIN
(COMPARATOR MODE)
POLARITY = 1
P7
P6
P5
P4
P3
P2
P1
P0
Default
0
0
0
0
0
0
0
0
OS/ALERT PIN
Table 8. REGISTER ADDRESSES SELECTION
(INTERRUPT MODE)
POLARITY = 1
P2
0
P1
0
P0
0
Register Selected
Stored Temperature
Configuration
0
0
1
Figure 4. One-shot OS/ALERT Pin Operation
Fault Queue
A fault is defined as when the temperature exceeds
a pre-defined temperature limit. This limit can be
0
1
0
T
Setpoint
HYST
0
1
1
T Setpoint
OS
1
0
0
One-shot
Table 9. NCT375 REGISTER SET
programmed in the T
and the T setpoint registers.
HYST
OS
Power-on
Default Value
Bits 3 and 4 of the configuration register determine the
number of faults necessary to trigger the OS/ALERT pin. Up
to six faults can be programmed to prevent false tripping
when the NCT375 is used in a noisy temperature
environment. In order for the OS/ALERT output to be set
these faults must occur consecutively.
Register
Address
Hex
0x0000
0x00
5C
0
Register Name
0x00 (R)
Stored Temperature Value
Configuration
0x01 (R/W)
0x02 (R/W)
0x03 (R/W)
0x04 (R/W)
−
T
T
0x4B00
0x5000
0xXX
75
80
−
HYST
OS
One-shot
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6
NCT375
Temperature Register
The temperature measured by the parts internal sensor is
stored in this 16-bit read only register. The data is stored in
twos complement format with the MSB as the sign bit. The
8 MSBs must be read frist followed by the 8 LSBs.
Table 10. TEMPERATURE VALUE REGISTER
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
Configuration Register
D[4:3]: Fault Queue
This 8-bit read/write register is used to configure the
NCT375 into its various modes of operation. The different
modes are listed in Table 11 and explained in more detail
below.
D4 D3 These two bits determine how many
overtemperature conditions occur before the OS/Alert
pin is triggered. This helps to prevent false triggering of
the output.
0
0
1
2
0 = 1 Fault (Default)
1 = 2 Faults
0 = 4 Faults
Table 11. CONFIGURATION REGISTER
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Configuration
Reserved
Default Value
1 = 6 Faults
0
0
0
0
0
0
0
0
Reserved
D2: OS/Alert pin polarity
One-shot Mode
Fault-queue
This selects the polarity of the OS/Alert output pin.
D2 = 0 Output is active low. (Default)
D2 = 1 Output is active high.
Fault-queue
OS/ALERT Pin Polarity
Cmp/Int Mode
Shutdown Mode
D1: Cmp/Int
D1 = 0 Comparator mode. (Default)
D1 = 1 Interrupt mode.
D7: Reserved
D0: Shutdown
Write 0 to this bit.
D0 = 0 Normal mode – part is fully powered. (Default)
D0 = 1 Shutdown mode – all circuitry except for the
SMBus interface is powered down. Write a 0 to this bit to
power up again.
D6: Reserved
Write 0 to this bit.
D5: One-shot Mode
THYST Register
D5 = 0 Part is in normal mode and converting every
60 ms. (Default)
The T
register stores the temperature hysteresis
HYST
value for the overtemperature output. This value is picked to
stop the OS/Alert pin from being asserted and de-asserted in
noisy temperature environments. This limit is stored in the
16 bit register in twos complement format. The MSB is the
temperature sign bit. The 8 MSBs must be read first
followed by the 8 LSBs. The default value is +75°C.
D5 = 1 Setting this bit puts the part into one-shot mode.
The part is normally powered down in this mode until the
one shot register is written to. Once this register is written
to one conversion is performed and the part returns to its
shutdown state.
Table 12. THYST REGISTER
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
0
1
1
0
0
0
0
X
X
X
X
TOS Register
This register stores the temperature limit at which the part
asserts an OS/Alert. Once the measured temperature reaches
this value an alert or overtemperature output is generated.
The data is stored in twos complement format with the MSB
as the sign bit. The 8 MSBs must be read frist followed by
the 8 LSBs. The default limit +80°C.
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NCT375
Table 13. TOS REGISTER
MSB
LSB
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
0
1
0
1
0
0
0
0
0
0
0
0
X
X
X
X
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NCT375
Serial Interface
master writes to the slave device. If the R/W bit is
a one then the master reads from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
acknowledge bit from the receiver of data.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, since a low-to-high
transition when the clock is high can be interpreted
as a stop signal.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the tenth
clock pulse to assert a stop condition. In read
mode, the master overrides the acknowledge bit by
pulling the data line high during the low period
before the ninth clock pulse. This is known as no
acknowledge. The master takes the data line low
during the low period before the tenth clock pulse,
then high during the tenth clock pulse to assert a
stop condition.
2
Control of the NCT375 is carried out via the SMBus/I C
compatible serial interface. The NCT375 is connected to this
bus as a slave device, under the control of a master device.
Serial Bus Address
Control of the NCT375 is carried out via the serial bus.
The NCT375 is connected to this bus as a slave device under
the control of a master device. The NCT375 has a 7-bit
serial address. The four MSBs are fixed and set to 1001
while the 3 LSBs can be configured by the user using pins
5, 6 and 7 (A2, A1 and A0). Each of these pins can be
configured in one of two ways low or high. This gives eight
different address options listed in Table 14 below. The state
of these pins is continually sampled and so can be changed
after power up.
Table 14. SERIAL BUS ADDRESS OPTIONS
MSBs
LSBs
Address
Hex
A6
1
A5
A4
0
A3
1
A2
0
A1
0
A0
0
0
0
0
0
0
0
0
0
0x48
1
0
1
0
0
1
0x49
Any number of bytes of data can be transferred over the
serial bus in one operation. However, it is not possible to mix
read and write in one operation because the type of operation
is determined at the beginning and cannot subsequently be
changed without starting a new operation.
1
0
1
0
1
0
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
1
1
1
0
Writing Data
There are two types of writes used in the NCT375:
1
0
1
1
1
1
2
Setting up the Address Pointer Register for a Register
Read
The NCT375 also features a SMBus/I C timeout function
2
whereby the SMBus/I C interface times out after the
To read data from a particular register, the address pointer
register must hold the address of the register being read. To
configure the address pointer register a single write
operation (shown in Figure 5). It consists of the device
address followed by the address being written to the address
pointer register. This will then be followed by a read
operation.
specified time when there is no activity on the SDA line. After
this time, the NCT375 resets the SDA line back to its idle state
(high impedance) and waits for the next start condition.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing
a start condition, defined as a high to low
transition on the serial data line SDA, while the
serial clock line SCL remains high. This indicates
that an address/data stream is going to follow. All
slave peripherals connected to the serial bus
Writing Data to a Register
Due to the different size registers used by the NCT375,
there are two types of write operations. One is for the 8 bit
wide configuration register and the other for the 16 bit wide
limit registers.
Figure 6 shows the sequence required to write to the
configuration register. It consists of the device address, the
data register being written to and the data being written the
selected register.
respond to the start condition and shift in the next
eight bits, consisting of a 7-bit address (MSB first)
plus a read/write (R/W) bit, which deternimes the
direction of the data transfer i.e. whether data is
written to, or read from, the slave device. The
peripheral with the address corresponding to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the acknowledge bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W bit is a zero then the
The two temperature limit registers (T
and T ) are
HYST
OS
16 bits wide and require two data bytes to be written to these
registers. This sequence is shown in Figure 7. It consists of
the device address, the data register being written to and the
two data byes being written to the selected register.
www.onsemi.com
9
NCT375
1
9
1
9
SCL
SDA
R/W
A6
A5
A4 A3 A2
FRAME 1
A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
STOP BY
MASTER
ACK. BY
NCT375
ACK. BY
NCT375
START BY
MASTER
FRAME 2
SERIAL BUS ADDRESS BYTE
ADDRESS POINTER REGISTER BYTE
Figure 5. Writing to the Address Pointer Register
1
9
1
9
SCL
SDA
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
NCT375
ACK. BY
NCT375
START BY
MASTER
FRAME 2
FRAME 1
SERIAL BUS ADDRESS BYTE
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
SDA (CONTINUED)
STOP BY
MASTER
NCT375
FRAME 3
DATA BYTE
Figure 6. Writing a Register Address to the Address Pointer Register, then
Writing a Single Byte of Data to the Configuration Register
1
9
1
9
SCL
SDA
R/W
A6 A5 A4 A3 A2
FRAME 1
A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
NCT375
ACK. BY
NCT375
START BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
SERIAL BUS ADDRESS BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D15 D14 D13 D12 D11 D10 D9
D8
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY STOP BY
ACK. BY
NCT375
NCT375
MASTER
FRAME 4
DATA BYTE
FRAME 3
DATA BYTE
Figure 7. Writing to the Address Pointer Register Followed by
Two Bytes of Data to a 16 Bit Limit Register
1
9
1
9
SCL
SDA
A6 A5
A4 A3 A2
FRAME 1
A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
R/W
ACK. BY
STOP BY
MASTER
NO ACK. BY
START BY
MASTER
NCT375
MASTER
DATA BYTE FROM REGISTER
FRAME 2
SERIAL BUS ADDRESS BYTE
Figure 8. Reading Data from the Configuration Register
www.onsemi.com
10
NCT375
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
R/W
ACK. BY
MASTER
ACK. BY
NCT375
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MSB DATA FROM TEMPERATURE
VALUE REGISTER
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
STOP BY
MASTER
NO ACK. BY
MASTER
FRAME 3
LSB DATA FROM TEMPERATURE
VALUE REGISTER
Figure 9. Reading Data from the Temperature Value Register with Preset Pointer Register
1
9
1
9
SCL
SDA
START BY
A6
A5
A4
A3
A2
A1
A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
NCT375
ACK. BY
NCT375
MASTER
FRAME 2
FRAME 1
SERIAL BUS ADDRESS BYTE
ADDRESS POINTER REGISTER BYTE
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
D15 D14 D13 D12 D11 D10 D9
FRAME 2
D8
ACK. BY
MASTER
ACK. BY
REPEATED START BY
MASTER
NCT375
1
FRAME 1
MSB DATA FROM TEMPERATURE
VALUE REGISTER
SERIAL BUS ADDRESS BYTE
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK. BY
MASTER
STOP BY
MASTER
FRAME 3
LSB DATA FROM TEMPERATURE
VALUE REGISTER
Figure 10. Typical Pointer Set followed by Two Bytes Register Read
www.onsemi.com
11
NCT375
Reading Data
More information on comparator and interrupt modes
alsong with the SMBus alert mode are explained below.
Reading data from the NCT375 is done in two different
ways depending on the register being read. The
configuration register is only 8 bits wide so a single byte
read is used for this (shown in Figure 8). This consists of the
device address followed by the data from the register.
Reading the data in the temperature value register requires
a two byte read (shown in Figure 9). This consists of the
device address, followed by two bytes of data from the
temperature register (the first byte is the MSB). In both cases
the address pointer register of the register being read must
be written to prior to performing a read operation.
Comparator Mode
In Comparator Mode, the OS/ALERT pin becomes active
when the measured temperature equals or exceeds the limit
stored in the T setpoint register. The pin returns to its
OS
inactive status when the temperature drops below the T
setpoint register value.
HYST
NOTE: Shutdown mode does not reset the output state for
comparator mode.
Interrupt Mode
In the interrupt mode, the OS/ALERT pin becomes active
OS/ALERT Output Overtemperature Modes
The OS/ALERT output pin can operate in two different
modes – overtemperature mode and SMBus alert mode. The
pin defaults to overtemperature mode on power up. This
means that it becomes active when the measured
when the temperature equals or exceeds the T limit for
a consecutive number of faults. It can be reset by performing
a read operation on any register in the NCT375. The output
OS
can only become active again when the T limit has been
OS
temperature meets or exceeds the limit stored in the T
OS
equalled or exceeded.
setpoint register. At this point it can deal with the event in
one of two ways which depends on the mode it is in. The two
overtemperature modes are: comparator mode and interrupt
mode. Comparator mode is the default mode on power up.
Figure 11 shows how both the interrupt and comparator
modes operate in relation to the output pin (OS/ALERT). It
also shows the operation of the polarity bit in the
configuration register.
www.onsemi.com
12
NCT375
82°C
81°C
80°C
79°C
78°C
77°C
76°C
75°C
74°C
73°C
72°C
T
OS
T
HYST
OS/ALERT PIN
(COMPARATOR MODE)
POLARITY = 0
OS/ALERT PIN
(INTERRUPT MODE)
POLARITY = 0
OS/ALERT PIN
(COMPARATOR MODE)
POLARITY = 1
OS/ALERT PIN
(INTERRUPT MODE)
POLARITY = 1
Figure 11. OS/ALERT Output Temperature Response Diagram
Table 15. ORDERING INFORMATION
†
Model Number
Temperature Range
Temperature Accuracy
Package Description
Package Option
NCT375DMR2G
−55°C to +125°C
1°C
Micro8
3,000 / Tape & Reel
2,500 / Tape & Reel
3,000 / Tape & Reel
(Pb−Free)
NCT375DR2G
−55°C to +125°C
−55°C to +125°C
1°C
1°C
SOIC−8
(Pb−Free)
NCT375MNR2G
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Micro8 is a trademark of International Rectifier.
www.onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE F
DATE 04 MAY 2016
1
SCALE 4:1
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
MILLIMETERS
2X
0.10
C
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
2.00 BSC
A3
2X
0.10
C
EXPOSED Cu
MOLD CMPD
TOP VIEW
0.30
D
D2
E
E2
e
K
L
L1
1.10
2.00 BSC
0.70
0.50 BSC
0.30 REF
0.25
−−−
1.30
A
C
DETAIL B
0.10
0.08
C
C
A1
0.90
DETAIL B
ALTERNATE
0.35
0.10
CONSTRUCTIONS
(A3)
A1
NOTE 4
SEATING
PLANE
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
8X
0.50
D2
1.30
8X
L
PACKAGE
OUTLINE
4
5
1
E2
0.90
2.30
8
K
8X b
1
e/2
e
0.10
0.05
C
C
A
B
8X
0.30
0.50
PITCH
NOTE 3
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
1
XXMG
G
XX = Specific Device Code
M
= Date Code
G
= Pb−Free Device
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON18658D
DFN8, 2.0X2.0, 0.5MM PITCH
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2016
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX = Specific Device Code
A
Y
W
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
STYLE 1:
STYLE 2:
PIN 1. SOURCE 1
STYLE 3:
PIN 1. SOURCE
PIN 1. N-SOURCE
2. N-GATE
(Note: Microdot may be in either location)
2. SOURCE
3. SOURCE
4. GATE
2. GATE 1
3. SOURCE 2
4. GATE 2
3. P-SOURCE
4. P-GATE
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. P-DRAIN
6. P-DRAIN
7. N-DRAIN
8. N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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