NCV3025833MTW [ONSEMI]
Smart Power Stage (SPS) Module with Integrated Thermal Warning and Thermal Shutdown;
| 型号： | NCV3025833MTW |
| 厂家： | 
ONSEMI |
| 描述： | Smart Power Stage (SPS) Module with Integrated Thermal Warning and Thermal Shutdown |
| 文件： | 总27页 (文件大小：767K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Smart Power Stage (SPS)
Module with Integrated
Thermal Warning and
Thermal Shutdown
WQFNW33
CASE 512AE
NCV3025833
Description
MARKING DIAGRAM
The SPS family is onsemi’s next-generation, fully optimized,
ultra-compact, integrated MOSFET plus driver power stage solution
for high-current, high-frequency, synchronous buck, DC−DC
applications. The NCV3025833 integrates a driver IC with a bootstrap
Schottky diode, two power MOSFETs, and a thermal monitor into a
thermally enhanced, ultra-compact 5 mm × 5 mm package.
With an integrated approach, the SPS switching power stage is
optimized for driver and MOSFET dynamic performance, minimized
NCV
3025833
AWLYYWW
G
3025833 = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
system inductance, and power MOSFET R
. The SPS family
DS(ON)
®
uses onsemi’s high-performance POWERTRENCH MOSFET
technology, which reduces switch ringing, eliminating the need for a
snubber circuit in most buck converter applications.
A driver IC with reduced dead times and propagation delays further
enhances the performance. A thermal warning function warns of a
potential over-temperature situation. A thermal shutdown function
turns off the driver if an over-temperature condition occurs. The
NCV3025833 incorporates an Auto-DCM Mode (ZCD#) for
improved light-load efficiency.
ORDERING INFORMATION
See detailed ordering and shipping information on page 25 of
this data sheet.
The NCV3025833 also provides a 3-state 5 V PWM input for
compatibility with a wide range of PWM controllers.
Features
• Ultra-compact 5 mm × 5 mm WQFN Copper-clip Package with
Flip Chip Low-Side MOSFET
• High Current Handling: 50 A
• 3-State 5 V PWM Input Gate Driver
• Dynamic Resistance Mode for Low-side Drive (LDRV) Slows
Low-side MOSFET during Negative Inductor Current Switching
• Auto DCM (Low-side Gate Turn Off) Using ZCD# Input
• Thermal Warning (THWN#) to Warn Over-temperature of Gate
Driver IC
• Thermal Shutdown (THDN)
• HS-short Detect Fault# / Shutdown
• Dual Mode Enable / Fault# Pin
• Internal Pull-up and Pull-down for ZCD# and EN Inputs,
respectively
• onsemi POWERTRENCH MOSFETs for Clean
Voltage Waveforms and Reduced Ringing
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
September, 2021 − Rev. 1
NCV3025833/D
NCV3025833
Features (continued)
Requirements; AEC−Q100 Qualified and PPAP
Capable
• onsemi SyncFETt Technology
(Integrated Schottky Diode) in Low-side MOSFET
• Integrated Bootstrap Schottky Diode
• Optimized / Extremely Short Dead-times
• Under-voltage Lockout (UVLO) on VCC
• Optimized for Switching Frequencies up to 1.5 MHz
• PWM Minimum Controllable On-time: 30 ns
• These Devices are Pb-Free, Halogen Free/BFR Free
and are RoHS Compliant
Applications
• Notebook, Tablet PC and Ultrabook
• Servers and Workstations, V-Core and Non-V-Core
DC−DC Converters
• Low Shutdown Current: < 3 mA
• Optimized FET Pair for Highest Efficiency: 10~15%
Duty Cycle
• Desktop and All-in-One Computers, V-Core and
Non-V-Core DC−DC Converters
• High-performance Gaming Motherboards
• High-current DC−DC Point-of-Load Converters
• Networking and Telecom Microprocessor Voltage
Regulators
• Small Form-factor Voltage Regulator Modules
• Automotive-qualified Systems
• Operating Junction Temperature Range: −40°C to
+125°C
• onsemi Green Packaging
• Automotive Qualified to AEC−Q100 with Wettable
Flanks
• NCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
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2
NCV3025833
PIN CONFIGURATION
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
EN/
VIN
VIN
VIN
9
31
30
29
28
27
26
25
24
FAULT#
THWN#
PVCC
PGND
GL
10
11
32
AGND
33
GL
12
13
14
15
PGND
PGND
PGND
PGND
SW
SW
SW
16
17
18
19
20
21
22
23
16
17
18
19
20
21
22
23
Figure 1. Pin Configuration − Top View and Transparent View
PIN DESCRIPTION
Pin No.
Symbol
PWM
Description
PWM input to the gate driver IC
1
2
ZCD#
VCC
Enable input for the ZCD (Auto DCM) comparator
Power supply input for all analog control functions; this is the “quiet” V
3
CC
4, 32
5
AGND
BOOT
Analog ground for analog portions of the IC and for substrate, internally tied to PGND
Supply for the high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies the charge to
turn on the N-channel high-side MOSFET.
6
7
NC
PHASE
VIN
No connect
Return connection for the boot capacitor, internally tied to SW node
Power input for the power stage
8~11
12~15, 28
16~26
PGND
SW
Power return for the power stage
Switching node junction between high-side and low-side MOSFETs; also input to the gate driver SW node
comparator and input into the ZCD comparator
27, 33
29
GL
Gate Low, Low-side MOSFET gate monitor
PVCC
THWN#
Power supply input for LS (Note1) gate driver and boot diode
30
125°C Thermal Warning Flag – pulls LOW upon detection of 125°C thermal warning preset temperature
Dual-functionality, enable input to the gate driver IC. FAULT# − internal pull-down physically pulls this pin
LOW upon detection of fault condition (HS (Note 2 MOSFET short or 150°C THDN).
31
EN / FAULT#
)
1. LS = Low Side
2. HS = High Side
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3
NCV3025833
DIAGRAMS
V5V
VIN
CVCC
CVIN
RVCC
CPVCC
PVCC
VCC
VIN
GL
EN
EN/FAULT#
PWM
RBOOT
BOOT
PHASE
SW
PWM Input
CBOOT
NCV3025833
OFF
ON
ZCD#
LOUT
THWN#
THWN#
VOUT
AGND
PGND
COUT
Figure 2. Typical Application Diagram
EN/
PVCC
FAULT#
BOOT
VIN
THWN#
0.8 V/ 2.0 V
FAULT
LATCH
VCC
THWN /
THDN
FAULT
PHASE
VCC
LEVEL
SHIFT
EN/UVLO
HDRV
POR
RUP_PWM
SW
PVCC
PWM CONTROL
LOGIC
PWM
PWM INPUT
RDN_PWM
LDRV1
PVCC
LDRV2
POR
VCC
GL
10 mA
ZCD/CCM/DCM
LOGIC
ZCD#
0.8 V/ 2.0 V
AGND
PGND
Figure 3. Functional Block Diagram
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4
NCV3025833
ABSOLUTE MAXIMUM RATINGS (T = T = 25°C)
A
J
Symbol
Parameter
Min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−3.0
−0.3
−0.3
−0.3
−7.0
−0.3
−7.0
−0.3
−5.0
−0.3
−0.3
−7.0
−
Max
6.0
6.0
6.0
Unit
V
V
CC
Supply Voltage
Referenced to AGND
PV
Drive Voltage
Referenced to AGND
V
CC
VEN/FAULT#
Output Enable / Disable
PWM Signal Input
ZCD Mode Input
Referenced to AGND
V
V
PWM
Referenced to AGND
V
+0.3
V
CC
V
ZCD#
Referenced to AGND
6.0
V
V
GL
Low Gate Manufacturing Test Pin
V
Referenced to AGND (DC Only)
Referenced to AGND, AC < 20 ns
Referenced to AGND
6.0
6.0
V
V
Thermal Warning
Power Input
PHASE
6.0
V
V
V
THWN#
V
IN
Referenced to PGND, AGND
Referenced to PGND, AGND (DC Only)
Referenced to PGND, AC < 20 ns
Referenced to PGND, AGND (DC Only)
Referenced to PGND, AC < 20 ns
Referenced to AGND (DC Only)
Referenced to AGND, AC < 20 ns
Referenced to PVCC
30.0
30.0
35.0
30.0
35.0
35.0
40.0
6.0
PHASE
V
SW
Switch Node Input
Bootstrap Supply
V
V
V
BOOT
VBOOT−PHASE Boot to PHASE Voltage
V
V
V
A
V
VIN to Phase Voltage
DC only
30.0
35
IN−PHASE
AC < 5ns
I
Output Current
f
f
= 300 kHz, V = 12 V, V = 1.8 V
OUT
50
O(AV)
SW
SW
IN
(Note 3)
= 1 MHz, V = 12 V, V
= 1.8 V
−
45
IN
OUT
I
EN / FAULT# Sink Current
−0.1
−
7.0
mA
mJ
FAULT
EAV
Single−Pulse Drain−to−Source Avalanche Energy, High−Side FET
(T = 25 °C, V = 5 V, L = 1.65 mH, I = 97.0 A
21.4
DS
)
PK
J
GS
L
ESD
Electrostatic Discharge Protection
V
Human Body Model, AEC−Q100−002
Charged Device Model, AEC−Q100−011
2000
2000
−
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. I
is rated with testing onsemi’s SPS evaluation board at T = 25°C with natural convection cooling. This rating is limited by the peak
O(AV)
A
SPS temperature, T = 150°C, and varies depending on operating conditions and PCB layout. This rating may be changed with different
J
application settings.
THERMAL INFORMATION
Symbol
Parameter
Value
Unit
q
Junction-to-Lead Thermal Resistance
2.9
°C/W
J−Lead
(Note 4)
(Mounted on 2S2P test board with 0 LFM at T = 25°C)
A
q
Junction-to-Top of Case Thermal Resistance
13.4
°C/W
J−CaseTop
(Mounted on 2S2P test board with 0 LFM at T = 25°C)
A
T
Ambient Temperature Range
Maximum Junction Temperature
Storage Temperature Range
−40 to +125
+150
°C
°C
°C
A
T
J
T
−55 to +150
STG
4. Measured at PGND Pad (Pins 12 – 15)
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Control Circuit Supply Voltage
Min
4.5
Typ
5.0
Max
5.5
Unit
V
V
CC
PV
Gate Drive Circuit Supply Voltage
Output Stage Supply Voltage
4.5
5.0
5.5
V
CC
V
IN
4.5 (Note 5)
19.0
24.0 (Note 6)
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. 3.0 V V is possible according to the application condition.
IN
6. Operating at high V can create excessive AC voltage overshoots on the SW-to-GND and BOOT-to-GND nodes during MOSFET switching
IN
transient. For reliable SPS operation, SW to GND and BOOT to GND must remain at or below the Absolute Maximum Ratings in the table
above.
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5
NCV3025833
ELECTRICAL CHARACTERISTICS
(V = 12 V, V = PV = 5 V and T = T = +25°C unless otherwise noted. Min/Max values are valid for V = 12 V, V = PV = 5 V
IN
CC
CC
A
J
IN
CC
CC
10% and T = T = −40°C ~ +125°C and are guarenteed by test, design, or statistical correlation)
J
A
Symbol
BASIC OPERATION
Quiescent Current
Parameter
Test Conditions
Min
Typ
Max
Unit
I
Q
I
Q
= I
VCC
+ I , EN = HIGH, PWM = LOW
PVCC
or HIGH or Float (Non-Switching)
−
−
2
mA
I
Shutdown Current
UVLO Threshold
I
= I + I , EN = GND
−
3.5
−
−
3.8
0.4
−
3
4.1
−
mA
V
SHDN
SHDN
VCC
PVCC
V
V
Rising
UVLO
UVLO_HYST
CC
V
UVLO Hysteresis
V
t
POR Delay to Enable IC
V
UVLO Rising to Internal PWM Enable
−
20
ms
D_POR
CC
EN INPUT
V
High-Level Input Voltage
Low-Level Input Voltage
Pull-Down Resistance
2.0
−
−
−
−
0.8
−
V
V
IH_EN
V
IL_EN
R
−
250
25
kW
ns
PLD_EN
PD_ENL
t
EN LOW Propagation Delay
PWM = GND, EN Going LOW to GL Going
LOW
−
45
t
EN HIGH Propagation Delay
PWM = GND, EN Going HIGH to GL Going
HIGH
−
−
25
ms
PD_ENH
ZCD# INPUT
V
High-Level Input Voltage
Low-Level Input Voltage
Pull-Up Current
2.0
−
−
−
−
0.8
−
V
V
IH_ZCD#
V
IL_ZCD#
I
−
10
10
mA
ns
PLU_ZCD#
t
ZCD# LOW Propagation Delay
PWM = GND, ZCD# Going LOW to GL
−
−
PD_ZLGLL
Going LOW (assume I ≤ 0)
L
t
ZCD# HIGH Propagation Delay
PWM = GND, ZCD# Going HIGH to GL
Going HIGH
−
10
−
ns
PD_ZHGLH
PWM INPUT
R
Pull-Up Impedance
−
−
10
10
−
−
−
kW
kW
V
UP_PWM
DN_PWM
R
Pull-Down Impedance
PWM High Level Voltage
3-State Window
V
3.8
1.2
−
−
IH_PWM
V
−
3.1
0.8
130
2.9
V
TRI_Window
V
PWM Low Level Voltage
3-State Shut-Off Time
3-State Open Voltage
−
V
IL_PWM
D_HOLD−OFF
t
−
90
2.5
ns
V
V
2.1
HIZ_PWM
MINIMUM CONTROLLABLE ON−TIME
t
PWM Minimum Controllable
On-Time
Minimum PWM HIGH Pulse Required for
SW Node to Switch from GND to VIN
30
−
−
−
ns
ns
MIN_PWM_ON
FORCED MINIMUM GL HIGH TIME
Forced Minimum GL HIGH
t
Minimum GL HIGH Time when LOW
VBOOT−SW detected and PWM LOW ≤ 100 ns
−
100
MIN_GL_HIGH
PWM INPUT PROPAGATION DELAYS AND DEAD TIMES (V = 12 V, V = PV = 5 V, f = 1 MHz, I
= 20 A, T = 25°C)
A
IN
CC
CC
sw
OUT
t
PWM HIGH Propagation Delay
PWM Going HIGH to GL Going LOW,
to 90% GL
−
15
30
10
−
−
−
ns
ns
ns
PD_PHGLL
V
IH_PWM
t
PWM LOW Propagation Delay
PWM Going LOW to GH (Note 7) Going
LOW, V to 90% GH
−
−
PD_PLGHL
IL_PWM
t
t
PWM LOW Propagation Delay
(ZCD# Held LOW)
PWM Going HIGH to GH Going HIGH,
PD_PHGHH
V
to 10% GH (ZCD# = LOW, I = 0,
IH_PWM
L
assumes DCM)
LS Off to HS On Dead Time
GL Going LOW to GH Going HIGH, 10%
GL to 10% GH, PWM Transition LOW to
HIGH (See Figure 30)
−
10
−
ns
D_DEADON
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6
NCV3025833
ELECTRICAL CHARACTERISTICS (continued)
(V = 12 V, V = PV = 5 V and T = T = +25°C unless otherwise noted. Min/Max values are valid for V = 12 V, V = PV = 5 V
IN
CC
CC
A
J
IN
CC
CC
10% and T = T = −40°C ~ +125°C and are guarenteed by test, design, or statistical correlation)
J
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
PWM INPUT PROPAGATION DELAYS AND DEAD TIMES (V = 12 V, V = PV = 5 V, f = 1 MHz, I
= 20 A, T = 25°C)
IN
CC
CC
sw
OUT
A
t
HS Off to LS On Dead Time
GH Going LOW to GL Going HIGH, 10%
GH to 10% GL, PWM Transition HIGH to
LOW (See Figure 30)
−
5
−
ns
D_DEADOFF
t
GH Rise Time under 20 A I
10% GH to 90% GH, I
90% GH to 10% GH, I
= 20 A
= 20 A
−
−
−
−
−
9
9
9
6
−
−
−
ns
ns
ns
ns
ns
R_GH_20A
OUT
OUT
OUT
t
GH Fall Time under 20 A I
F_GH_20A
OUT
t
GL Rise Time under 20 A I
10% GL to 90% GL, I
90% GL to 10% GL, I
= 20 A
= 20 A
−
R_GL_20A
OUT
OUT
OUT
OUT
t
GL Fall Time under 20 A I
−
F_GL_20A
t
Exiting 3-State Propagation Delay
PWM (from 3-State) Going HIGH to GH
Going HIGH, V to 10% GH
45
PD_TSGHH
IH_PWM
t
Exiting 3-State Propagation Delay
PWM (from 3-State) Going LOW to GL
Going HIGH, V to 10% GL
−
−
45
ns
PD_TSGLH
IL_PWM
WEAK LOW−SIDE DRIVER (LDRV2 Only under CCM2 Mode Operation, V = PV = 5 V)
CC
CC
R
Output Impedance, Sourcing
Output Impedance, Sinking
Source Current = 100 mA
−
−
0.82
0.86
−
−
W
W
SOURCE_GL
R
Sink Current = 100 mA
SINK_GL
LOW−SIDE DRIVER (Paralleled LDRV1 + LDRV2 under CCM1 Mode Operation, V = PV = 5 V)
CC
CC
R
Output Impedance, Sourcing
Output Impedance, Sinking
GL Rise Time
Source Current = 100 mA
Sink Current = 100 mA
−
−
−
−
0.47
0.29
9
−
−
−
−
W
W
SOURCE_GL
R
SINK_GL
t
10% GL to 90% GL, C
= 7.0 nF
= 7.0 nF
ns
ns
R_GL
LOAD
LOAD
t
GL Fall Time
90% GL to 10% GL, C
6
F_GL
THERMAL WARNING FLAG (125°C)
T
Activation Temperature
Reset Temperature
Measured on the driver IC with T = T
A
−
−
−
125
110
40
−
−
−
°C
°C
W
ACT_THWN_125
J
T
RST_THWN_125
R
Pull-Down Resistance
I
= 1 mA
PLD_THWN
PLD_THWN
THERMAL SHUTDOWN (150°C)
T
Activation Temperature
Pull-Down Resistance
Measured on the driver IC with T = T
A
−
−
150
100
−
−
°C
ACT_THDN
J
R
I
= 1 mA
W
PLD_EN−THDN
PLD_EN−THDN
CATASTROPHIC FAULT (SW Monitor)
V
SW Monitor Reference Voltage
−
−
1.3
20
2
V
SW_MON
D_FAULT
t
Propagation Delay to Pull EN /
FAULT# Signal = LOW
−
ns
BOOT DIODE
V
Forward-Voltage Drop
Breakdown Voltage
I = 10 mA
−
0.4
−
−
V
V
F
F
V
R
I = 1 mA
R
30
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. GH = Gate High, internal gate pin of the high-side MOSFET.
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7
NCV3025833
TYPICAL PERFORMANCE CHARACTERISTICS
(Test Conditions: V = 12 V, V = PV = 5 V, V
= 1 V, L
= 250 nH, T = 25°C and natural convection cooling,
IN
CC
CC
OUT
OUT A
unless otherwise noted.)
60
55
50
45
40
35
30
25
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
5
FSW = 300kHz
FSW = 300kHz
SW = 1000kHz
FSW = 1000kHz
F
V
IN = 12V, PVCC & VCC = 5V, VOUT = 1V
VIN = 19V, PV CC & VCC = 5V, V OUT = 1V
25 50 75 100
0
0
0
25 50 75 100
125
150
0
125
150
PCB Temperature, TPCB [5C]
[5C]
PCB Temperature, TPCB
Figure 4. Safe Operating Area 12 VIN
Figure 5. Safe Operating Area 19 VIN
13
14
13
12
11
10
9
19Vin,
12Vin,
PVCC & VCC = 5V, VOUT = 1V
PVCC & VCC = 5V, VOUT = 1V
12
11
10
9
8
7
6
5
4
3
300kHz
19Vin,
300kHz
12Vin,
500kHz
12Vin,
500kHz
19Vin,
800kHz
12Vin,
800kHz
19Vin,
1000kHz
1000kHz
8
7
6
5
4
3
2
1
0
2
1
0
0
5
10 15 20 25 30 35 40 45 50 55
[A]
0
5
10 15 20 25 30 35 40 45 50 55
Module Output Current, IOUT [A]
Module Output Current, IOUT
Figure 6. Power Loss vs. Output Current with 12 VIN
Figure 7. Power Loss vs. Output Current with 19 VIN
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NCV3025833
TYPICAL PERFORMANCE CHARACTERISTICS
(Test Conditions: V = 12 V, V = PV = 5 V, V
= 1 V, L
= 250 nH, T = 25°C and natural convection cooling,
IN
CC
CC
OUT
OUT A
unless otherwise noted.)
1.20
1.4
1.3
1.2
1.1
1.0
0.9
0.8
PVCC & VVCC= 5V, VOUT = 1V, FSW = 500kHz,
OUT = 30A
V
IN = 19V, PVCC & VCC = 5V, VOUT = 1V, IOUT = 30A
I
1.15
1.10
1.05
1.00
0.95
4
6
8
10
12
14
16
18
20
300
400
500
600
700
800
900
1000
Module Input Voltage, VIN [V]
Module Switching Frequency, FSW [kHz]
Figure 8. Power Loss vs. Switching Frequency
Figure 9. Power Loss vs. Input Voltage
1.5
1.4
1.3
1.2
1.1
1.0
VIN = 12V, VOUT = 1V, FSW = 500kHz, IOUT = 30A
1.15
1.10
1.05
1.00
0.95
0.90
VIN = 12V, PVCC & VVCC = 5V,
FSW = 500kHz, IOUT = 30A
1.0
1.5
2.0
2.5
3.0
4.0
4.5
5.0
5.5
6.0
Module Output Voltage, VOUT [V]
Driver Supply Voltage, PVCC & VCC [V]
Figure 10. Power Loss vs. Driver Supply Voltage
Figure 11. Power Loss vs. Output Voltage
1.014
1.012
1.010
1.008
1.006
1.004
1.002
1.000
0.04
0.035
0.03
V
IN = 12V, PVCC& VCC = 5V, VOUT = 1V, IOUT = 0A
V
V
IN = 12V, PVCC & VVCC = 5V, FSW = 500kHz,
OUT = 1V, IOUT = 30A
0.025
0.02
0.015
0.01
250
300
350
400
450
300
400
500
600
700
800
900 1000
Output Inductor, LOUT [nH]
Module Switching Frequency, FSW [kHz]
Figure 13. Driver Supply Current vs. Switching
Frequency
Figure 12. Power Loss vs. Output Inductor
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9
NCV3025833
TYPICAL PERFORMANCE CHARACTERISTICS
(Test Conditions: V = 12 V, V = PV = 5 V, V
= 1 V, L
= 250 nH, T = 25°C and natural convection cooling,
IN
CC
CC
OUT
OUT A
unless otherwise noted.)
0.023
0.022
0.021
0.020
0.019
0.018
0.017
0.016
1.06
VIN = 12V, PVCC & VVCC = 5V, VOUT = 1V
VIN = 12V, VOUT = 1V, FSW = 500kHz, IOUT = 0A
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
F
SW= 800kHz
FSW= 300kHz
4.5
5.0
5.5
6.0
0
5
10 15 20 25 30 35 40 45 50
Module Output Current, IOUT [A]
Driver Supply Voltage, PVCC & VVCC [V]
Figure 15. Driver Supply Current vs. Output
Current
Figure 14. Driver Supply Current vs. Driver
Supply Voltage
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIH_PWM
UVLOUP
T
A
= 25°C
VTRI_HI_PWM
VHIZ_PWM
VTRI_LO_PWM
VIL_PWM
UVLODN
4.50
4.75
5.00
5.25
5.50
−50
−25
0
25
50
75
100
125
Driver IC Junction Temperature, T [oC]
Driver Supply Voltage, VCC [V]
J
Figure 16. UVLO Threshold vs. Temperature
Figure 17. PWM Threshold vs. Driver Supply
Voltage
4.0
2.0
1.5
1.0
VIH_PWM
VCC = 5V
TA = 25°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIH
TRI_HI_PWM
V
VHIZ_PWM
VTRI_LO_PWM
VIL_PWM
V IL
−50
−25
0
25
50
75
100
125
4.50
4.75
5.00
5.25
5.50
Driver IC Junction Temperature, T [oC]
Driver Supply Voltage, VCC [V]
J
Figure 18. PWM Threshold vs. Temperature
Figure 19. ZCD# Threshold vs. Driver Supply
Voltage
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10
NCV3025833
TYPICAL PERFORMANCE CHARACTERISTICS
(Test Conditions: V = 12 V, V = PV = 5 V, V
= 1 V, L
= 250 nH, T = 25°C and natural convection cooling,
IN
CC
CC
OUT
OUT A
unless otherwise noted.)
2
1.5
1
15
13
11
9
VCC = 5V
VCC = 5V
VIH
V
IL
7
0.5
−50
5
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Driver IC Junction Temperature, T [oC]
J
Driver IC Junction Temperature, T [oC]
J
Figure 20. ZCD# Threshold vs. Temperature
Figure 21. ZCD# Pull−up Current vs. Temperature
1.8
1.6
1.5
1.4
1.3
1.2
VCC = 5V
TA
= 25°C
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
V
IH_EN
V
IH_EN
V
IL_EN
V
IL_EN
4.50
4.75
Driver Supply Voltage, VCC [V]
Figure 22. EN Threshold vs. Driver Supply Voltage
5.00
5.25
5.50
−50
−25
0
25
50
75
100
125
Driver IC Junction Temperature, T [oC]
J
Figure 23. EN Threshold vs. Temperature
500
450
400
350
300
9
8.5
8
IF = 10mA
V
CC = 5V
7.5
7
6.5
6
−50
−25
0
25
50
75
100
125
−50
0
50
100
J
150
Driver IC Junction Temperature, TJ [oC]
Driver IC Junction Temperature, T [oC]
Figure 25. Boot Diode Forward Voltage vs.
Temperature
Figure 24. EN Pull−Down Current vs. Temperature
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11
NCV3025833
TYPICAL PERFORMANCE CHARACTERISTICS
(Test Conditions: V = 12 V, V = PV = 5 V, V
= 1 V, L
= 250 nH, T = 25°C and natural convection cooling,
IN
CC
CC
OUT
OUT A
unless otherwise noted.)
1.5
3
2.75
2.5
VCC = 5V, EN = High
VCC = 5V, EN = GND
1.4
1.3
1.2
1.1
1
PWM = Float
PWM = High
2.25
2
1.75
1.5
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Driver IC Junction Temperature, TJ [oC]
Driver IC Junction Temperature, TJ [oC]
Figure 27. Driver Quiescent Current vs.
Temperature
Figure 26. Driver Shutdown vs. Temperature
FUNCTIONAL DESCRIPTION
The SPS NCV3025833 is a driver-plus-MOSFET module
optimized for the synchronous buck converter topology.
A PWM input signal is required to properly drive the
high-side and the low-side MOSFETs. The part is capable of
driving speed up to 1.5 MHz.
and ready to operate. Two VCC pins are provided: PVCC
and VCC. The gate driver circuitry is powered from the
PVCC rail. The user should connect VCC to PVCC through
a low-pass R−C filter. This provides a filtered 5 V bias to the
analog circuitry on the IC.
Power-On Reset (POR)
Driver State
Enable
The PWM input stage incorporates a POR feature to
ensure both LDRV and HDRV are forced inactive (LDRV =
HDRV = 0) until UVLO > ~3.8 V (rising threshold). After
all gate drive blocks are fully powered on and have finished
the startup sequence, the internal driver IC EN_PWM signal
is released HIGH, enabling the driver outputs. Once the
driver POR has finished (< 20 ms maximum), the driver
follows the state of the PWM signal (it is assumed that at
startup the controller is either in a high-impedance state or
forcing the PWM signal to be within the driver 3-state
window).
Disable
3.4
3.8
VCC [ V]
* EN pin keeps HIGH
Figure 28. UVLO on VCC
Three conditions below must be supported for normal
startup / power-up.
EN / FAULT# (Enable / Fault Flag)
The driver can be disabled by pulling the EN / FAULT#
),
• V rises to 5 V, then EN goes HIGH:
CC
pin LOW (EN < V
which holds both GL and GH
IL_EN
• EN pin is tied to the VCC pin:
LOW regardless of the PWM input state. The driver can be
enabled by raising the EN / FAULT# pin voltage HIGH (EN
• EN is commanded HIGH prior to 5 V V reaching the
CC
> V
). The driver IC has less than 3 mA shutdown
IH_EN
UVLO rising threshold.
current when it is disabled. Once the driver is re-enabled, it
takes a maximum of 20 ms startup time.
Under-Voltage Lockout (UVLO)
UVLO is performed on V only, not on PV or V .
EN / FAULT# pin is an open-drain output for fault flag
with an internal 250 kW pull-down resistor. Logic HIGH
signal from PWM controller or ~10 kW external pull-up
resistor from EN / FAULT# pin to VCC is required to start
driver operation.
CC
CC
IN
When the EN is set HIGH and V is rising over the UVLO
CC
threshold level (3.8 V), the part starts switching operation
after a maximum 20 ms POR delay. The delay is
implemented to ensure the internal circuitry is biased, stable,
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12
NCV3025833
3-State PWM Input
Table 1. UVLO AND DRIVER STATE
The NCV3025833 incorporates a 3-state 5 V PWM input
gate drive design. The 3-state gate drive has both logic
HIGH and LOW levels, along with a 3-state shutdown
window. When the PWM input signal enters and remains
within the 3-state window for a defined hold-off time
UVLO
EN
X
Driver State
Disabled (GH & GL = 0)
Disabled (GH & GL = 0)
Enabled (see Table 2)
Disabled (GH & GL = 0)
0
1
1
1
0
1
(t
), both GL and GH are pulled LOW. This
D_HOLD−OFF
Open
feature enables the gate drive to shut down both the
high-side and the low-side MOSFETs to support features
such as phase shedding, a common feature on multi-phase
voltage regulators.
The EN / FAULT# pin has two functions; enabling /
disabling driver and fault flag. The fault flag signal is active
LOW. When the driver detects a fault condition during
operation, it turns on the open-drain on the EN / FAULT# pin
and the pin voltage is pulled LOW. The fault conditions are:
• High-side MOSFET false turn-on or VIN ~ SW short
during low-side MOSFET turn on:
Table 2. EN / PWM / 3-STATE / ZCD# LOGIC STATES
EN
0
PWM
ZCD#
GH
0
GL
X
X
X
0
0
1
1
0
1
3-State
0
0
• Thermal Shutdown (THDN) when the driver internal
junction temperature (T ) reaches 150°C.
J
1
0
1
0
1
0
1 (IL > 0), 0 (IL < 0)
1
1
0
1
0
When the driver detects a fault condition and disables
itself, a POR event on VCC is required to restart the driver
operation.
1
0
1
1
V
IH_PWM
V
IL_PWM
PWM
90%
10%
90%
10%
GL
90%
10%
90%
10%
GH−PHASE
(intenal)
BOOT−GND
PV − V
− 1 V
CC
F_DBOOT
90%
SW
tPD_PHGLL tD_DEADON tRISE_GH
tFALL_GL
tPD_PLGHL tD_DEADOFF tRISE_GL
tFALL_GH
tPD_PLGLH
t
t
t
t
= PWM HI to GL LO, V
= 90% GL to 10% GL
= LS Off to HS On Dead Time, 10% GL to V
= 10% GH to 90% GH, V
to 90% GL
PD_PHGLL
IH_PWM
FALL_GL
≤ PV − V
− 1V or BOOT−GND dip start point
D_DEADON
BOOT−GND
CC
F_DBOOT
≤ PV − V
− 1V or BOOT−GND dip start point to GL bounce start point
RISE_GH
BOOT−GND
CC
F_DBOOT
t
t
t
t
t
= PWM LO to GH LO, V
= 90% GH to 10% GH, BOOT−GND decrease start point to 90% V
to 90% GH or BOOT−GND decrease start point, t
− t
− t
PD_PLGHL
IL_PWM
PD_PLGLH
D_DEADOFF FALL_GH
or GL dip start point
FALL_GH
SW
= HS Off to LS On Dead Time, 90% V
or GL dip start point to 10% GL
D_DEADOFF
SW
= 10% GL to 90% GL
RISE_GL
= PWM LO to GL HI, V
to 10% GL
PD_PLGLH
IL_PWM
Figure 30. PWM Timing Diagram
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13
NCV3025833
(8)
(8)
VIH_PWM
VIH_PWM
(12)
(11)
VTRI_HI
VTRI_HI
(10
)
VTRI_LO
VTRI_LO
VIL_PWM
PWM
VIL_PWM (13)
3−State
Window
3−State
Window
(9)
(9)
GH−PHASE
GL
Figure 31. PWM Threshold Definition
NOTE:
8. The timing diagram in Figure 31 assumes very slow ramp on PWM.
9. Slow ramp of PWM implies the PWM signal remains within the 3-state window for a time >>> t
.
D_HOLD−OFF
10.V
11. V
12.V
13.V
= PWM trip level to enter 3-state on PWM falling edge.
= PWM trip level to enter 3-state on PWM rising edge.
= PWM trip level to exit 3-state on PWM rising edge and enter the PWM HIGH logic state.
= PWM trip level to exit 3-state on PWM falling edge and enter the PWM LOW logic state.
TRI_HI
TRI_LO
IH_PWM
IL_PWM
Power Sequence
SPS NCV3025833 requires four (4) input signals to
conduct normal switching operation: V , V / PV ,
PWM, and EN. PWM should not be applied before V and
the amplitude of PWM should not be higher than V . The
below example of a power sequence is for a reference
application design:
PVCC through the internal bootstrap diode. When the PWM
input goes HIGH, HDRV begins to charge the gate of the
high-side MOSFET (internal GH pin). During this
IN
CC
CC
transition, the charge is removed from the C
and
IN
CC
BOOT
,
delivered to the gate of Q1. As Q1 turns on, SW rises to V
CC
+
forcing the BOOT pin to V
V
, which provides
BOOT
IN
sufficient V
enhancement for Q1. To complete the
GS
switching cycle, Q1 is turned off by pulling HDRV to SW.
is then recharged to PVCC when the SW falls to
• From no input signals
♦ V On: Typical 12 V
C
BOOT
IN
DC
PGND. HDRV output is in phase with the PWM input. The
high-side gate is held LOW when the driver is disabled or the
PWM signal is held within the 3-state window for longer
♦ V / PV On: Typical 5 V
CC
CC
DC
♦ EN HIGH: Typical 5 V
DC
♦ PWM Signaling: 5 V HIGH / 0 V LOW
than the 3-state hold-off time, t
.
D_HOLD−OFF
The VIN pins are tied to the system main DC power rail.
PVCC and VCC pins are tied together to supply gate
driving and logic circuit powers from the system V rail.
Low-Side Driver
The low-side driver (LDRV) is designed to drive the
CC
,
gate-source of
a
ground-referenced, low-R
Or the PVCC pin can be directly tied to the system V rail,
DS(ON)
CC
N-channel MOSFET (Q2). The bias for LDRV is internally
connected between the PVCC and AGND. When the driver
is enabled, the driver output is 180° out of phase with the
PWM input. When the driver is disabled (EN = 0 V), LDRV
is held LOW.
and the VCC pin is powered by PVCC pin through a filter
resistor located between PVCC pin and VCC pin. The filter
resistor reduces switching noise impact from PV to V
.
CC
CC
The EN pin can be tied to the V rail with an external
CC
pull-up resistor and it will maintain HIGH once the V rail
CC
turns on. Or the EN pin can be directly tied to the PWM
controller for other purposes.
Continuous Current Mode 2 (CCM2) Operation
A main feature of the low-side driver design in SPS
NCV3025833 is the ability to control the part of the low-
side gate driver upon detection of negative inductor current,
called CCM2 operation. This is accomplished by using the
ZCD comparator signal. The primary reason for scaling
High-Side Driver
The high-side driver (HDRV) is designed to drive
a floating N-channel MOSFET (Q1). The bias voltage for
the high-side driver is developed by a bootstrap supply
circuit, consisting of the internal Schottky diode and
back on the drive strength is to limit the peak V stress
when the low-side MOSFET hard-switches inductor
DS
external bootstrap capacitor (C ). During startup, the
BOOT
current. This peak V
stress has been an issue with
DS
SW node is held at PGND, allowing C
to charge to
BOOT
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14
NCV3025833
applications with large amounts of load transient and fast
and wide output voltage regulation.
The MOSFET gate driver in SPS NCV3025833 operates
in one of three modes, described below.
CCM2 alters the gate drive impedance while operating the
power MOSFETs in a different mode versus CCM1 / DCM.
Altered dead-time operation must be considered.
Low-Side MOSFET Off to High-Side MOSFET On Dead
Time in CCM1 / DCM
To prevent overlap during the low-side MOSFET off to
high-side MOSFET on switching transition, an adaptive
circuitry monitors the voltage at the GL pin. When the PWM
signal goes HIGH, GL goes LOW after a propagation delay
Continuous Current Mode 1 (CCM1) with Positive
Inductor Current
In this mode, inductor current is always flowing towards
the output capacitor, typical of a heavily loaded power stage.
The high-side MOSFET turns on with the low-side body
diode conducting inductor current and SW is approximately
(t
). Once the GL pin is discharged below ~ 1 – 2 V,
PD_PHGLL
V below ground, meaning hard-switched turn on and off
F
GH is pulled HIGH after an adaptive delay, t
.
D_DEADON
the high-side MOSFET.
Some situations where the ZCD# rising-edge signal leads
the PWM rising edge by tens of nanoseconds, can cause GH
and GL overlap. This event can occur when the PWM
controller sends PWM and ZCD# signals that lead, lag, or
are synchronized. To avoid this phenomenon, a secondary
Discontinuous Current Mode (DCM)
Typical of lightly loaded power stage; the high-side
MOSFET turns on with zero inductor current, ramps the
inductor current, then returns to zero every switching cycle.
When the high-side MOSFET turns on under DCM
fixed propagation delay (t
) is added to ensure there
FD_ON1
is always a minimum delay between low-side MOSFET off
to high-side MOSFET on.
operation, the SW node may be at any voltage from a V
F
below ground to a V above V . This is because after the
F
IN
low-side MOSFET turns off, the SW node capacitance
resonates with the inductor current.
Low-Side MOSFET Off to High-Side MOSFET On Dead
Time in CCM2
The level shifter in driver IC should be able to turn on the
high-side MOSFET regardless of the SW node voltage. In
this case, the high-side MOSFET turns off a positive current.
During this mode, both LDRV1 and LDRV2 operate in
parallel and the low-side gate driver pull-up and pull-down
resistors are operating at full strength.
As noted in the CCM2 Operation section, the low-side
driver strength is scale-able upon detection of CCM2.
CCM2 feature slows the charge and discharge of the
low-side MOSFET gate to minimize peak switching voltage
overshoots during low-side MOSFET hardswitching
(negative inductor current). To avoid cross-conduction, the
slowing of the low-side gate also requires an adjustment
(increase) of the dead time between low-side MOSFET off
to high-side MOSFET on. A fairly long fixed dead time
Continuous Current Mode 2 (CCM2) with Negative
Inductor Current
This mode is typical in a synchronous buck converter
pulling energy from the output capacitors and delivering the
energy to the input capacitors (Boost Mode). In this mode,
the inductor current is negative (meaning towards the
MOSFETs) when the low-side MOSFET is turned off (may
be negative when the high-side MOSFET turns on as well).
This situation causes the low-side MOSFET to hard switch
while the high-side MOSFET acts as a synchronous rectifier
(temporarily operated in synchronous Boost Mode).
During this mode, only the “weak” LDRV2 is used for
low-side MOSFET turn-on and turn-off. The intention is to
slow down the low-side MOSFET switching speed when it
(t
) is implemented to ensure there is no cross
FD_ON2
conduction during this CCM2 operation.
High-Side MOSFET Off to Low-Side MOSFET On Dead
Time in CCM1 / DCM
To get very short dead time during high-side MOSFET off
to low-side MOSFET on transition, a fixed dead time
method is implemented in the SPS gate driver. The
fixed-dead-time circuitry monitors the internal HS signal
and adds a fixed delay long enough to gate on GL after
a desired tD_DEADOFF (~5 ns, tD_DEADOFF = t
of SW node state.
) regardless
FD_OFF1
is hard switching to reduce peak V stress.
DS
Exiting 3-State Condition
When exiting a valid 3-state condition, the gate driver of
the NCV3025833 follows the PWM input command. If the
PWM input goes from 3-state to LOW, the low-side
MOSFET is turned on. If the PWM input goes from 3- state
to HIGH, the high-side MOSFET is turned on. This is
illustrated in Figure 32 below.
Dead-Times in CCM1 / DCM / CCM2
The driver IC design ensures minimum MOSFET dead
times, while eliminating potential shoot-through (cross-
conduction) currents. To ensure optimal module efficiency,
body diode conduction times must be reduced to the low
nano-second range during CCM1 and DCM operation.
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15
NCV3025833
VIH_PWM
3−State
Window
VIH_PWM
VTRI_HI
VIH_PWM
VIL_PWM
VTRI_HI
VTRI_LO
VTRI_HI
VTRI_LO
PWM
VIL_PWM
VIL_PWM
90%
10%
GH to SW
10%
10%
10%
90%
90%
10%
GL
10%
10%
tPD_TLGLH
tPD_THGHH
tPD_PHGLL
tPD_PLGHL
tPD_PHGLL
tD_HOLD−OFF
tD_DEADON
tD_DEADON2
tD_HOLD−OFF
tD_DEADOFF
SW
Less than
tD_HOLD−OFF
Less than
tD_HOLD−OFF
Inductor
Current
3−State
3−State
tHOLD_OFF
Window
GL / GH
off
GL / GH
off
tHOLD_OFF
Window
NOTES:
t
= propagation delay from external signal (PWM, ZCD#, etc.) to IC generated signal. Example : t
– PWM going HIGH to
PD_PHGLL
PD_XXX
low-side MOSFET V (GL) going LOW
GS
t
= delay from IC generated signal to IC generated signal. Example: t
– low-side MOSFET V LOW to high-side
D_DEADON GS
D_XXX
MOSFET V HIGH
GS
PWM
t
t
t
= PWM rise to LS V fall, V
to 90% LS V
PD_PHGLL
PD_PLGHL
PD_PHGHH
GS
IH_PWM
IL_PWM
GS
GS
GS
= PWM fall to HS V fall, V
to 90% HS V
GS
= PWM rise to HS V rise, V
to 10% HS V (ZCD# held LOW)
GS
IH_PWM
ZCD#
t
t
= ZCD# fall to LS V fall, V
to 90% LS V
IH_ZCD#
PD_ZLGLL
PD_ZHGLH
GS
IL_ZCD# GS
= ZCD# rise to LS V rise, V
to 10% LS V
GS
GS
Exiting 3-State
t
t
= PWM 3-State to HIGH to HS V rise, V
to 10% HS V
PD_TSGHH
PD_TSGLH
GS
IH_PWM
GS
= PWM 3-State to LOW to LS V rise, V
to 10% LS V
GS
IL_PWM
GS
Dead Times
t
t
= LS V fall to HS V rise, LS-Comp trip value to 10% HS V
D_DEADON
D_DEADOFF
GS GS
GS
= SW fall to LS V rise, SW-Comp trip value to 10% LS V
GS
GS
Figure 32. PWM HIGH / LOW / 3-State Timing Diagram
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16
NCV3025833
Exiting 3-State with Low BOOT−SW Voltage
The SPS module is used in multi-phase VR topologies
requiring the module to wait in 3-state condition for an
indefinite time. These long idle times can bleed the boot
capacitor down until eventual clamping occurs based on
• If the part exits 3-state with a low BOOT−SW voltage
condition and the controller commands PWM = HIGH,
the SPS outputs a 100 ns GL pulse and follows the
PWM = HIGH command (see Figure 33).
• If the part exits 3-state with a low BOOT−SW voltage
condition and the controller commands PWM = LOW
for 100 ns or more, the SPS follows the PWM input. If
PWM = LOW for less than 100 ns, GL remains on for
100 ns then follows the PWM input (see Figure 34 and
Figure 35).
PV
and V . Low BOOT−SW can cause increased
OUT
CC
propagation delays in the level-shift circuit as well as all
HDRV floating circuitry, which is biased from the
BOOT−SW rail. Another issue with a depleted BOOT−SW
capacitor voltage is the voltage applied to the HS MOSFET
gate during turn-on. A low BOOT−SW voltage results in
a very weak HS gate drive, hence, much larger HS R
DS(ON)
• If no low BOOT−SW condition is detected, the SPS
follows the PWM command when exiting 3-state
(see Figure 36).
and increased risk for unreliable operation since the HS
MOSFET may not turn-on if BOOT−SW falls too low.
To address this issue, the SPS monitors for a low
BOOT−SW voltage when the module is in 3-state condition.
When the module exits 3-state condition with a low
BOOT−SW voltage, a 100 ns minimum GL on time is output
regardless of the PWM input. This ensures the boot
capacitor is adequately charged to a safe operating level and
has minimal impact on transient response of the system.
Scenarios of exiting 3-state condition are listed below.
The SPS momentarily stays in an adaptive dead time
mode when exiting 3-state condition or at initial power-up.
This adaptive dead time mode lasts for no more than two (2)
consecutive switching cycles, giving the boot capacitor
ample time to recharge to a safe level. The module switches
back to fixed dead time control for maximum efficiency.
PWM LOW
> 100 ns
V
IH_PWM
V
IL_PWM
PWM
PWM
GH to
GH to
PHASE
PHASE
GL
GL
GL / GH
off
GL / GH
off
> 100 ns
GL pulse
100 ns
GL pulse
LOW
BOOT−SW
detect
LOW
BOOT−SW
detect
Low BOOT−SW voltage detected
Low BOOT−SW voltage detected
Figure 33. Low BOOT−SW Voltage Detected and
Figure 34. Low BOOT−SW Voltage Detected and
PWM from 3-State to HIGH
PWM from 3-State to LOW for more than 100 ns
PWM LOW
< 100 ns
V
IH_PWM
I
V
V
IL_PWM
IL_PWM
PWM
PWM
GH to
GH to
PHASE
PHASE
GL
GL
GL / GH
off
GL / GH
off
GL / GH
off
100 ns
GL pulse
LOW
BOOT−SW
detect
LOW
BOOT−SW
detect
Low BOOT−SW voltage detected
Low BOOT−SW voltage NOT detected
Figure 35. Low BOOT−SW voltage Detected and
Figure 36. Low BOOT−SW Voltage NOT Detected and
PWM from 3-State to LOW for Less than 100 ns
PWM from 3-State to HIGH or LOW
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17
NCV3025833
Zero Cross Detect (ZCD) Operation
The ZCD control block houses the circuitry that
determines when the inductor current reverses direction and
controls when to turn off the low-side MOSFET. A low
offset comparator monitors the SW-to-PGND voltage of the
low-side MOSFET during the LS MOSFET on-time. When
the sensed voltage switches polarity from negative to
positive, the comparator changes state and reverse current
has been detected. This comparator offset must sense the
negative offset is to ensure the inductor current never
reverses; some small body-diode conduction is preferable to
having negative current.
The comparator is switched on after the rising edge of the
low-side gate drive and turned off by the signal at the input
to the low-side gate driver. In this way, the zero-current
comparator is connected with a break-before-make
connection, allowing the comparator to be designed with all
low-voltage transistors.
negative V
within a 0.5 mV worst-case range. The
SW
VIH_ZCD#
VIL_ZCD#
ZCD#
VIH_PWM
VIH_PWM
VIH_PWM
VIL_PWM
PWM
90%
10%
GH to
SW
10%
90%
10%
90%
90%
90%
10%
GL
10%
tPD_PLGHL
10%
tPD_PHGLL
tD_DEADON
tPD_PHGLL
tD_DEADON2
tPD_ZCD
tPD_PHGHH
tPD_ZHGLH
tPD_ZLGLL
Delay from PWM going
HIGH to HS VGS HIGH
(HS turn−on in DCM)
Delay from ZCD# going Delay from ZCD# going
HIGH to LS VGS HIGH
LOW to LS VGS LOW
VIN
tD_DEADOFF
CCM
CCM
DCM
DCM
(Negative inductor current)
VOUT
SW
Inductor
Current
(simplified
slopes)
SW
(zoom)
VZCD_OFF
−0.5 mV
:
DCM operation: Diode
Emulation using the GL (LS
MOSFET VGS) to eliminate
negative inductor current
DCM operation: Diode
Emulation using the GL (LS
MOSFET VGS) to eliminate
negative inductor current
ZCD# used to
control negative
inductor current
(fault condition)
CCM operation with
positive inductor current
CCM operation with
negative inductor current
Figure 37. ZCD# & PWM Timing Diagram
Thermal Warning Flag (THWN#)
Recycling 5 V V (POR event) is required to re-enable
CC
The NCV3025833 provides a thermal warning (THWN)
for over-temperature conditions. The THWN flag pulls
THWN# pin LOW (to AGND) if the driver IC detects the
125°C activation temperature. The THWN# pin output
returns to high-impedance state once the temperature falls to
the 110°C reset temperature. Figure 38 shows the THWN#
operation. THWN does not disable the SPS module and
works independently of other features.
the driver IC.
VTHWN#
[V]
5
0
The THWN mode of operation requires a pull-up resistor
to V rail. THWN# flag is active LOW.
CC
Thermal Shutdown (THDN)
A programmed thermal shutdown engages once thedriver
TJ reaches 150°C. The shutdown event is a latched shut
down, where the THDN signal clocks the fault latch and
physically pulls down the EN pin.
[°C]
T
110
THWN#
125
= 10 kW to 5 VCC
* R
Figure 38. Gate Driver TJ vs. VTHWN#
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18
NCV3025833
Catastrophic Fault
The 150°C THDN feature is combined with a 125°C
THWN# flag. If the driver temperature reaches 125°C, the
THWN# pin is pulled LOW. If the driver continues
operation and its temperature increases up to 150°C, thermal
shutdown is activated. The SPS module is shut down by EN
SPS NCV3025833 includes a catastrophic fault feature. If
a HS MOSFET short is detected, the driver internally pulls
the EN / FAULT# pin LOW and shuts down the SPS driver.
The intention is to implement a basic circuit to test the HS
MOSFET short by monitoring LDRV and the state of SW
node.
LOW and the THWN# flag is de-asserted, so the V
THWN#
returns HIGH. Figure 40 shows the relationship among
THWN#, EN, and driver temperature.
If a HS short fault is detected, the SPS module clocks the
fault latch shutting down the module. The module requires
VTHWN#
a V POR event to restart.
CC
[V]
5
0
VEN [V]
5
0
125
150
T [°C]
J
* R
= 10 kW to 5 VCC
THWN#
* R = 10 kW to 5 VCC
EN
Figure 40. VTHWN#, VEN vs. Driver Temperature
PWM
LDRV
(internal)
HS FET short during
LS FET turning on
SW
Potential noise from
adjacent phases switching
SW−Fault
(internal)
false trigger
FAULT
(internal)
EN/FAULT#
Normal switching operation
EN/FAULT#
pulled LOW and
driver IC disabled
Figure 42. Catastrophic Fault Waveform
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19
NCV3025833
APPLICATION INFORMATION
PWM (Input)
Decoupling Capacitor for PVCC & VCC
For the supply inputs (PVCC and VCC pins), local
decoupling capacitors are required to supply the peak
driving current and to reduce noise during switching
operation. Use at least 0.68 ~ 1 mF / 0402 ~ 0603 / X5R ~
X7R multi-layer ceramic capacitors for both power rails.
Keep these capacitors close to the PVCC and VCC pins and
PGND and AGND copper planes. If they need to be located
on the bottom side of board, put through-hole vias on each
pads of the decoupling capacitors to connect the capacitor
pads on bottom with PVCC and VCC pins on top.
The PWM pin recognizes three different logic levels from
PWM controller: HIGH, LOW, and 3-state. When the PWM
pin receives a HIGH command, the gate driver turns on the
high-side MOSFET. When the PWM pin receives a LOW
command, the gate driver turns on the low-side MOSFET.
When the PWM pin receives a voltage signal inside of the
3-state window (V ) and exceeds the 3-state
TRI_Window
hold-off time, the gate driver turns off both high-side and
low-side MOSFETs. To recognize the high-impedance
3-state signal from the controller, the PWM pin has an
internal resistor divider from VCC to PWM to AGND. The
resistor divider sets a voltage level on the PWM pin inside
the 3-state window when the PWM signal from the
controller is high-impedance.
The supply voltage range on PVCC and VCC is 4.5 V ~
5.5 V, and typically 5 V for normal applications.
R−C Filter on VCC
The PVCC pin provides power to the gate drive of the
high-side and low-side power MOSFETs. In most cases,
PVCC can be connected directly to VCC, which is the pin
that provides power to the analog and logic blocks of the
driver. To avoid switching noise injection from PVCC into
VCC, a filter resistor can be inserted between PVCC and
VCC decoupling capacitors.
ZCD# (Input)
When the ZCD# pin sets HIGH, the ZCD function is
disabled and high-side and low-side MOSFETs switch in
CCM (or FCCM, Forced CCM) by PWM signal. When the
ZCD# pin is LOW, the low-side MOSFET turns off when the
SPS driver detects negative inductor current during the
low-side MOSFET turn-on period. This ZCD feature allows
higher converter efficiency under light-load condition and
PFM / DCM operation.
Recommended filter resistor value range is 0 ~ 10 W,
typically 0 W for most applications.
Bootstrap Circuit
The ZCD# pin has an internal current source from VCC,
The bootstrap circuit uses a charge storage capacitor
(CBOOT). A bootstrap capacitor of 0.1 ~ 0.22 mF / 0402 ~
0603 / X5R ~ X7R is usually appropriate for most switching
applications. A series bootstrap resistor may be needed for
specific applications to lower high-side MOSFET switching
speed. The boot resistor is required when the SPS is
switching above 15 V VIN; when it is effective at controlling
so it may not need an external pull-up resistor. Once V is
CC
supplied and the driver is enabled, the ZCD# pin holds logic
HIGH without external components and the driver operates
switching in CCM or FCCM. The ZCD# pin can be
grounded for automatic diode emulation in DCM by the SPS
itself, or it can be connected to the controller or system to
follow the command from them.
The typical pull-up resistor value on ZCD# ~ VCC is
10 kW for stable ZCD# HIGH level. If not using the ZCD
feature, tie the ZCD# pin to VCC with a pull-up resistor. Do
not add any noise filter capacitor on the ZCD# pin.
VSW overshoot. R
value from zero to 6 W is typically
BOOT
recommended to reduce excessive voltage spike and ringing
on the SW node. A higher R value can cause lower
BOOT
efficiency due to high switching loss of high-side MOSFET.
Do not add a capacitor or resistor between the BOOT pin
and GND.
THWN# (Output) / THDN
The THWN# pin is an open-drain, so needs an external
pull-up resistor to VCC. If the driver temperature reaches
EN / FAULT# (Input / Output)
The driver in SPS is enabled by pulling the EN pin HIGH.
The EN pin has internal 250 kW pull-down resistor, so it
125°C, the V
is pulled LOW. When the driver T
THWN#
J
cools to less than 110°C, the V
returns HIGH. This
THWN#
needs to be pulled-up to V with an external resistor or
CC
THWN# flag operates when the driver T is below 150°C.
If the driver T continuously increases over 150°C after
J
connected to the controller or system to follow up the
command from them. If the EN pin is floated, it cannot turn
on the driver.
The fault flag LOW signal is asserted on the EN / FAULT#
pin when the driver temperature reaches THDN temperature
or a high-side MOSFET fault occurs. Then the driver shuts
down.
J
asserting the 125°C THWN flag, the thermal shutdown
feature activates and the SPS module is turned off. This
shutdown is a latch function, so the driver remains shut
down even if its temperature cools down to 25°C. The SPS
module needs to be re-enabled by V POR once the THDN
CC
is activated.
The typical pull-up resistor value on EN ~ VCC is 10 kW.
Do not add a noise filter capacitor on the EN pin.
www.onsemi.com
20
NCV3025833
A typical pull-up resistor on THWN# ~ VCC is 10 kW. If
Power loss calculation and equation examples:
not using THWN#/THDN features, tie THWN# to GND. Do
not add a noise filter capacitor on the THWN# pin.
P
P
P
P
P
= (V ∗ I ) + (V ∗ I )
[W]
[W]
[W]
[W]
[W]
[%]
[%]
IN
IN
IN
CC
CC
= V ∗ I
SW
OUT
SW
OUT
= V
∗ I
OUT
OUT
Power Loss and Efficiency
Figure 43 shows an example diagram for power loss and
efficiency measurement.
= P – P
SW
LOSS_MODULE
IN
= P – P
LOSS_TOTAL
IN
OUT
EFFI
EFFI
= (P / P ) ∗ 100
SW IN
OUT
MODULE
= (P
/ P ) ∗ 100
IN
TOTAL
Pulse
Generator
PWM
VIN / IIN
Power
VIN
Supply 1
HS
GD
VCC / ICC
Power
Supply 2
Electronic
Load
PVCC
VCC
VOUT
VSW / IOUT
LS
VOUT / IOUT
ON Semiconductor SPS
Evaluation Board
Figure 43. Power Loss and Efficiency Measurement Diagram
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21
NCV3025833
PCB LAYOUT GUIDELINE
Figure 44 through Figure 47 provide examples of single-
MOSFET turn-on slew rate and SW voltage overshoot.
R can improve noise operating margin in synchronous
BOOT
buck designs that may have noise issues due to ground
phase and multi-phase layouts for the NCV3025833 and
critical components. All of the high-current paths; such as
VIN, SW, VOUT, and GND coppers; should be short and
wide for low parasitic inductance and resistance. This helps
achieve a more stable and evenly distributed current flow,
along with enhanced heat radiation and system
performance.
bounce orhigh positive and negative V ringing. Inserting
SW
a boot resistance lowers the SPS module efficiency.
Efficiency versus switching noise must be considered.
R
BOOT
values from 0.5 W to 0.6 W are typically effective in
reducing V overshoot.
SW
Input ceramic bypass capacitors must be close to the VIN
and PGND pins. This reduces the high-current power loop
inductance and the input current ripple induced by the power
MOSFET switching operation.
The VIN and PGND pins handle large current transients
with frequency components greater than 100 MHz. If
possible, these pins should be connected directly to the VIN
and board GND planes. The use of thermal relief traces in
series with these pins is not recommended since this adds
extra parasitic inductance to the power path. This added
inductance in series with either the VIN or PGND pin
degrades system noise immunity by increasing positive and
The SW copper trace serves two purposes. In addition to
being the high-frequency current path from the SPS package
to the output inductor, it serves as a heat sink for the low-side
MOSFET. The trace should be short and wide enough to
present a low-impedance path for the high-frequency,
high-current flow between the SPS and the inductor. The
short and wide trace minimizes electrical losses and SPS
temperature rise. The SW node is a high-voltage and
high-frequency switching node with high noise potential.
Care should be taken to minimize coupling to adjacent
traces. Since this copper trace acts as a heat sink for the
low-side MOSFET, balance using the largest area possible
to improve SPS cooling while maintaining acceptable noise
emission.
An output inductor should be located close to the
NCV3025833 to minimize the power loss due to the SW
copper trace. Care should also be taken so the inductor
dissipation does not heat the SPS.
POWERTRENCH MOSFETs are used in the output stage
and are effective at minimizing ringing due to fast switching.
In most cases, no RC snubber on SW node is required. If
a snubber is used, it should be placed close to the SW and
PGND pins. The resistor and capacitor of the snubber must
be sized properly to not generate excessive heating due to
high power dissipation.
negative V ringing.
SW
PGND pad and pins should be connected to the GND
copper plane with multiple vias for stable grounding. Poor
grounding can create a noisy and transient offset voltage
level between PGND and AGND. This could lead to faulty
operation of gate driver and MOSFETs.
Ringing at the BOOT pin is most effectively controlled by
close placement of the boot capacitor. Do not add any
additional capacitors between BOOT to PGND. This may
lead to excess current flow through the BOOT diode,
causing high power dissipation.
The ZCD# and EN pins have weak internal pull-up and
pull-down current sources, respectively. These pins should
not have any noise filter capacitors. Do not float these pins
unless absolutely necessary.
Put multiple vias on the VIN and VOUT copper areas to
interconnect top, inner, and bottom layers to evenly
distribute current flow and heat conduction. Do not put too
many vias on the SW copper to avoid extra parasitic
inductance and noise on the switching waveform. As long as
efficiency and thermal performance are acceptable, place
only one SW node copper on the top layer and put no vias on
the SW copper to minimize switch node parasitic noise. Vias
should be relatively large and of reasonably low inductance.
Decoupling capacitors on PVCC, VCC, and BOOT
capacitors should be placed as close as possible to the PVCC
~ PGND, VCC ~ AGND, and BOOT ~ PHASE pin pairs to
ensure clean and stable power supply. Their routing traces
should be wide and short to minimize parasitic PCB
resistance and inductance.
Critical high-frequency components; such as R
,
BOOT
C , RC snubber, and bypass capacitors; should be
BOOT
located as close to the respective SPS module pins as
possible on the top layer of the PCB. If this is not feasible,
they can be placed on the board bottom side and their pins
connected from bottom to top through a network of
low-inductance vias.
The board layout should include a placeholder for
small-value series boot resistor on BOOT ~ PHASE. The
boot-loop size, including series R
be as small as possible.
and C , should
BOOT
BOOT
A boot resistor may be required when the SPS isoperating
above 15 V V and it is effective to control the high-side
IN
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22
NCV3025833
PCB LAYOUT GUIDELINE
Figure 44. Single-Phase Board Layout Example – Top View
Figure 45. Single-Phase Board Layout Example – Bottom View (Mirrored)
www.onsemi.com
23
NCV3025833
PCB LAYOUT GUIDELINE (continued)
Figure 46. 6-Phase Board Layout Example with 6 mm x 6 mm Inductor – Top View
Figure 47. 6-Phase Board Layout Example with 6 mm x 6 mm Inductor – Bottom View (Mirrored)
www.onsemi.com
24
NCV3025833
PACKAGE MARKING AND ORDERING INFORMATION
†
Part Number
Top Marking
Current Rating
50 A
Package
Shipping (Qty / Packing)
NCV3025833MTW
NCV
3025833
3000 / Tape & Reel
31-Lead, Clip Bond WQFN31 5x5, 0.5P
(Pb-Free/Halogen Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark and SyncFET is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its
subsidiaries in the United States and/or other countries.
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25
NCV3025833
PACKAGE DIMENSIONS
WQFNW33, 5x5, 0.5P
CASE 512AE
ISSUE A
A
B
EXPOSED
COPPER
15
15
9
9
8
8
16
16
32
32
33
33
23
23
1
1
31
24
31
24
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26
NCV3025833
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