NCV308SN500T1G [ONSEMI]
Low Quiescent Current, Programmable Delay Time, Supervisory Circuit;
| 型号： | NCV308SN500T1G |
| 厂家： | 
ONSEMI |
| 描述： | Low Quiescent Current, Programmable Delay Time, Supervisory Circuit |
| 文件： | 总10页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV308
Low Quiescent Current,
Programmable Delay Time,
Supervisory Circuit
The NCV308 series is one of the ON Semiconductor Supervisory
circuit IC families. It is optimized to monitor system voltages from
0.405 V to 5.5 V, asserting an active low open−drain RESET output,
together with Manual Reset (MR) Input. The part comes with both
fixed and externally adjustable versions.
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MARKING
DIAGRAM
Features
• Wide Supply Voltage Range 1.6 to 5.5 V
• Very Low Quiescent Current 1.6 mA
• Fixed Threshold Voltage Versions for Standard Voltage Rails
Including 1.8 V, 3.3 V, 5.0 V
TSOP−6
CASE 318G
XXXAYWG
G
1
1
XXX
A
Y
= Specific Device Code
=Assembly Location
= Year
= Work Week
= Pb−Free Package
• Adjustable Version with Low Threshold Voltage 0.405 V (min)
• High Threshold Voltage Accuracy: 0.15% typ
• Support Manual Reset Input ( MR)
• Open−Drain RESET Output (Push−pull Output upon Request)
• Flexible Delay Time Programmability: 1.25 ms to 10 s
• Temperature Range: −40°C to +125°C
• Small TSOP−6 Pb−Free Package
W
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
ordering information section on page 9 of this data sheet.
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100 Grade 1
Qualified and PPAP Capable
• These are Pb−Free Devices
Typical Applications
• DSP or Microcontroller Applications
• Notebook/Desktop Computers
• PDAs/Hand−Held Products
• Portable/Battery−Powered Products
• FPGA/ASIC Applications
VIN
VDD
VIN
VDD
NCV308SNADJ
Rpullup
RESET
Rpullup
RESET
RESET
VDD
RESET
VDD
DSP/
Processor
DSP/
Processor
R1
R2
SENSE
MR
CT
SENSE
MR
CT
CT
(Optional)
CT
(Optional)
1 nF
MR
MR
(Optional)
GND
GND
Figure 1. Typical Application Circuit for Adjustable
Versions
Figure 2. Typical Application Circuit for Fixed
Versions
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
June, 2019 − Rev. 0
NCV308/D
NCV308
VDD
VDD
VDD
NCV308SNADJ
Adjustable Version
VDD
NCV308SNXXX
Fixed Versions
90k
CT
CT
90k
MR
MR
RESET
RESET
−
−
SENSE
SENSE
Control Logic
and Timer
Control Logic
and Timer
+
+
R1
R2
Vref
Vref
Figure 3. Functional Block Diagrams of Adjustable and Fixed Versions
1
2
3
6
5
4
RESET
GND
VDD
SENSE
CT
MR
Figure 4. Pin Connections Diagram (Top View)
Description
Table 1. PIN OUT DESCRIPTION
Name
VDD
Pin Number
6
5
Supply Voltage. A 0.1uF ceramic capacitor placed close to this pin is helpful for transient and parasitic.
Sense Input, this is the voltage to be monitored. If the voltage at this terminal drops below the threshold
voltage V , then RESET is asserted. SENSE does not necessary monitor VDD, it can monitor any voltage
lower than VDD.
SENSE
IT
CT
4
Reset Delay Time Setting Pin. Connecting this pin to VDD through a 40 kW to 200 kW resistor or leaving it
open results in fixed reset delay times. Connecting this pin to a ground referenced capacitor (≥ 100 pF)
gives a user−programmable reset delay time. See the Setting Reset Delay Time section for more
information.
MR
3
1
Manual Reset input, MR low asserts RESET. MR is internally tied to VDD by a 90 kW pull−up Resistor.
RESET Output, is an Active low open drain N−Channel MOSFET output, it is driven to a low impedance
RESET
state when RESET is asserted (either the SENSE input is lower than the threshold voltage (V ) or the MR
IT
pin is set to a logic low). RESET will keep low (asserted) for the reset delay time after both SENSE is above
V
and MR is set to a logic high. A pull−up resistor from 10kW to 1MW should be used on this pin. See
IT
Figure 5 for behavior of RESET depends on VDD, SENSE and MR conditions.
GND
2
Ground terminal. Should be connected to PCB ground reference
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2
NCV308
Uncertain State
V
DD
V
DD(min)
0.0 V
RESET
tD
tD
tP2
SENSE
V
+ V
HYS
IT
V
IT
tP1
tD
MR
0.7 V
0.3 V
DD
DD
Figure 5. Timing Diagram Showing MR and SENSE Reset Timing
Table 2. TRUTH TABLE
MR
L
SENSE > V
RESET
IT
N
Y
N
Y
L
L
L
H
L
H
H
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3
NCV308
Table 3. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage Range, V
V
−0.3 to + 6.0
V
DD
DD
CT
CT Voltage Range V , RESET, MR
I
−0.3 to V +0.3 ≤ 6.0
V
mA
CT
DD
Current through CT pin
SENSE Pin Voltage
RESET Pin Current
10
−0.3 to + 8.0
5
V
mA
Thermal Resistance Junction−to−Air
TSOP−6
R
°C/W
q
JA
305
2000
Human Body Model (HBM) ESD Rating (Note 1)
Charged Device Model (CDM) ESD Rating (Note 1)
Latch up Current: (Note 2)
ESD HBM
ESD CDM
V
V
1000
I
LU
100
mA
°C
°C
Storage Temperature Range
T
STG
−65 to + 150
−40 to +150
Level 1
Maximum Junction Temperature
T
J
Moisture Sensitivity (Note 3)
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2017)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes smaller than
2 x 2 mm due to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current
waveform characteristic defined in JEDEC JS−002−2018
2. Latch up Current per JEDEC standard: JESD78 class II.
3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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4
NCV308
Table 4. ELECTRICAL CHARACTERISTICS 1.6 V ≤ V ≤ 5.5 V, R
= 100 kW, C
= 50 pF, over operating
DD
pullup
LRESET
temperature range (T = −40°C to +125°C), unless otherwise specified. Typical values are at T = +25°C.
J
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
DD
Supply Operating Voltage Range
(Note 4)
1.6
5.5
V
V
(min)
Minimum V Guaranteed RESET
0.5
1.6
1.6
0.8
5.0
6.0
V
DD
DD
Output Valid (Note 5)
I
Supply Current (Current into VDD pin)
V
V
= 3.3V, RESET not asserted
MR, RESET, CT open
mA
DD
DD
= 5.5V, RESET not asserted
MR, RESET, CT open
DD
V
OL
Low−level output voltage of RESET
1.3V ≤ V < 1.6V, I = 0.4 mA
0.3
0.4
V
DD
OL
1.6V ≤ V ≤ 5.5V, I = 1.0 mA
DD
OL
V %
Negative going SENSE threshold
voltage accuracy
−2.8
−1.5
−2.4
+2.8
+1.5
+2.4
3.75
%
IT
T = +25°C
0.15
J
−20°C < T < +85°C
J
V
HYS
Hysteresis on V
1.75
90
%V
IT
IT
R
MR
SENSE
MR Internal pull−up resistance
kW
I
Input current at
SENSE pin
NCV308SNADJ
Fixed versions
V
= V
nA
10
SENSE
IT
V
= 5.5 V
110
SENSE
I
RESET leakage Current
MR logic low input
V
= 5.5 V, RESET not asserted
300
nA
V
OH
RESET
V
0
0.3 V
DD
IL
V
IH
MR logic high input
0.7 V
V
DD
V
DD
tw
Input pulse width
to assert RESET
(Note 4)
SENSE
MR
C = Open
V
= 1.05 V , V = 0.95 V
30
ms
ns
ms
IH
IT IL
IT
V
= 0.7 V , V = 0.3 V
150
IH
DD
IL
DD
t
D
Reset delay time
(Guaranteed by design and
characterization)
20
300
1.25
1200
T
C = V
T
DD
C = 100 pF
T
C = 180 nF
T
t
t
Propagation
MR to RESET
V
= 0.7 V , V = 0.3 V
DD
150
ns
P1
IH
DD
IL
delay from MR
Propagation delay SENSE to
from SENSE RESET
V
IH
= 1.05 V , V = 0.95 V
30
ms
P2
IT IL
IT
4. Not tested in production
5. The lowest supply voltage (VDD) at which RESET becomes active.
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5
NCV308
TYPICAL OPERATING CHARACTERISTICS
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10000
1000
+125°C
+125°C
+25°C
100
10
1
−40°C
+85°C
+85°C
−40°C
+25°C
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
INPUT VOLTAGE (V)
0.1
1.0
10.0
100.0
1000.0
DELAY CAPACITOR VALUE (nF)
Figure 6. Supply Current vs. Input Voltage
Figure 7. RESET Timeout Period vs. CT
25
20
15
10
5
1000
100
10
1
0
−5
−50 −30 −10 10
30
50 70
90
110 130
0
5
10 15 20
25 30
35 40 45 50
TEMPERATURE (°C)
OVERDRIVE (%V )
IT
Figure 8. Normalized RESET Timeout Period vs.
Temperature
Figure 9. Maximum Transient Duration at Sense
vs. Sense Threshold Overdrive Voltage
0.5
0.4
0.3
0.2
0.1
0.0
2.5
2.0
1.5
V
DD
= 1.6 V
1.0
0.5
0
V
DD
= 5.5 V
−0.5
−1.0
−1.5
V
DD
= 3.3 V
−2.0
−2.5
−50 −30 −10
10
30
50
70
90
110 130
0.0
0.5
1.0
1.5
2.0
TEMPERATURE (°C)
RESET CURRENT (mA)
Figure 10. Normalized Sense Threshold Voltage
(VIT) vs. Temperature
Figure 11. Low−Level RESET Voltage vs. RESET
Current
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6
NCV308
DETAILED DESCRIPTION
SENSE Input
The NCV308 microprocessor supervisory product family
is designed to assert a RESET signal when either the SENSE
The SENSE input should be connected to the monitored
voltage directly. If the voltage on this pin drops below V ,
pin voltage drops below V or the Manual Reset input (MR)
IT
IT
then RESET is asserted. The comparator has a built−in
hysteresis to prevent erratic reset operation. It is good
practice to put a 1 nF to 10 nF bypass capacitor on the
SENSE input to reduce its sensitivity to transients and layout
parasitic.
is driven low. The RESET output remains asserted for a
programmable delay time after both MR and SENSE
voltages return above the respective thresholds. A broad
range of voltage threshold and reset delay time options are
available, allowing NCV308 series to be used in a wide
range of applications.
Reset threshold voltages can be factory−set from 1.67 V
to 4.65 V while the NCV308SNADJ can be used for any
voltage above 0.405 V using an external resistor divider.
Flexible delay time can be easily got with CT pin
according to Table 5:
The NCV308SNADJ can be used to monitor any voltage
rail down to 0.405 V by the circuit shown in Figure 12. The
new V ’ can be derived from resistor divider network of R1
IT
and R2 by:
R1
ǒ
Ǔ
(eq. 1)
VITȀ +
) 1 VIT
R2
VDD
Table 5. DELAY TIME SETTING TABLE
VIN
CT pin Configuration
CT = VDD
Delay Time (tD)
300 ms (fixed)
20 ms (fixed)
NCV308SNADJ
Rpullup
CT = Open
VDD
RESET
Connecting a capacitor be-
tween pin CT and GND
(Capacitor CT value >
100 pF)
1.25 ms ~ 10 s, depends on
capacitor value (Refer to the
Setting Reset Delay Time
Section)
R1
R2
SENSE
MR
CT
CT
1 nF
(Optional)
MR
(Optional)
GND
Output
The RESET output is typically connected to the RESET
control pin of a microprocessor. For Open−Drain output
versions, a pull−up resistor must be used to hold this line
high when RESET is not asserted. The RESET output is
Figure 12. Using NCV308SNADJ to Monitor a
User−Defined Threshold Voltage
active once V
is over V (min), this voltage is much
DD
DD
Manual Reset Input (MR)
lower than most microprocessors’ functional voltage range.
RESET remains high as long as SENSE is above its
The Manual Reset input (MR) allows a processor or other
logic circuits to initiate a reset. A logic low on MR causes
RESET to assert. After MR returns to a logic high and
SENSE is above its reset threshold, RESET is de−asserted
after the delay time set by CT pin. MR is internally tied to
threshold (V ) and the Manual Reset input (MR) is logic
IT
high. If either SENSE falls below V or MR is driven low,
RESET is asserted.
Once MR is again logic high and SENSE is above (V
IT
+
IT
V
DD
by a 90 kW resistor so this pin can be left unconnected
V ), the RESET pin goes to a high impedance state after
HYS
if MR will not be used.
delay time (tD). The open−drain structure of RESET is
capable to allow the reset signal for the microprocessor to
have a voltage higher than V (up to 5.5 V). The pull−up
resistor should be no smaller than 10 kW as a result of the
Figure 13 shows how MR can be used to monitor multiple
system voltages (e.g. I/O supply voltage of some
DSP/processors should be setup before core voltage, and
DSP/processor can only start after both I/O and core
voltages setup).
DD
finite impedance of the RESET line.
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7
NCV308
1.2 V
3.3 V
RESET
VDD
VDD
RESET
RESET
DSP/
Processor
SENSE
MR
CT
SENSE
MR
CT
GND
GND
NCV308SN120
NCV308SN330
Figure 13. Using MR to Monitor Multiple System Voltages
3.3V
Setting Reset Delay Time
The NCV308 has three options for setting the reset delay
time as shown in Table 5. Figure 14 shows the configuration
for a fixed 300 ms typical delay time by tying CT to V
;
DD
Rpullup
a resistor from 40 kW to 200 kW must be used. Figure 15
shows a fixed 20 ms delay time by leaving the CT pin
unconnected.
VDD
RESET
Figure 16 shows a user−defined program time between
1.25 ms and 10 s by connecting a capacitor between CT pin
and ground.
SENSE
MR
CT
3.3 V
MR
GND
Figure 15. Delay Time Fixed to 20 ms when CT is
Open
Rpullup
50k
RESET
VDD
3.3 V
SENSE
MR
CT
Rpullup
MR
GND
RESET
VDD
Figure 14. Delay Time Fixed to 300 ms when CT
Connected to VDD by Resistor
SENSE
MR
CT
CT
MR
GND
Figure 16. Delay Time Set by Capacitor
The capacitor CT should be ≥ 100 pF for NCV308 to
recognize that the capacitor is present. The capacitor value
for a given delay time can be calculated using the following
equation:
−3
CT(nF) + ǒtD(s) * 0.5 10 (s)Ǔ 175
(eq. 2)
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NCV308
Parasitic capacitances of CT pin should be considered to
avoid reset delay time deviation or error.
Immunity to Sense Pin Voltage Transients
NCV308 is relatively immune to short negative transients
on SENSE pin. Sensitivity to transients is dependent on
threshold overdrive, as shown in the Maximum Transient
Duration at Sense vs. Sense Threshold Overdrive Voltage
graph (Figure 9) in Typical Operating Characteristics
section.
Figure 17. External Capacitor Placement Example
Table 6. RECOMMENDED CAPACITOR VALUES
Hints
If better EMC performance is needed, add small external
capacitors as close to the pins as possible according to
Figure 17 and Table 6:
Device Pins
VDD connected to SENSE
RESET
Recommended Capacitor
10 nF
47 nF
47 nF
MR
ORDERING INFORMATION
Threshold
Voltage
Nominal
Monitored
Voltage
†
(V )
IT
Device
Status (Note 6)
Active
Marking
CV3
Package
Shipping
NCV308SN180T1G*
NCV308SN500T1G*
1.67 V
4.65 V
1.8 V
5.0 V
TSOP−6
(Pb−Free)
3000 / Tape & Reel
Active
CV5
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
6. The marketing status are defined as below:
Active: Products in production and recommended for new designs;
Under Request: Device has been announced but is not in production. Samples may or may not be available.
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9
NCV308
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
H
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
6
1
5
4
L2
GAUGE
PLANE
E1
E
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
2
3
L
MILLIMETERS
SEATING
M
C
NOTE 5
DIM
A
A1
b
c
D
E
E1
e
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
NOM
1.00
MAX
1.10
0.10
0.50
0.26
3.10
3.00
1.70
1.05
0.60
PLANE
b
DETAIL Z
e
0.06
0.38
0.18
3.00
c
2.75
A
0.05
1.50
0.95
L
0.40
A1
L2
M
0.25 BSC
−
DETAIL Z
0°
10°
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
0.95
3.20
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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◊
NCV308/D
相关型号：
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