NCV33204DR2 [ONSEMI]
Rail-to-Rail Operational Amplifiers; 轨至轨运算放大器
| 型号： | NCV33204DR2 |
| 厂家： | 
ONSEMI |
| 描述： | Rail-to-Rail Operational Amplifiers |
| 文件： | 总16页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC33201, MC33202,
MC33204, NCV33202,
NCV33204
Low Voltage, Rail−to−Rail
Operational Amplifiers
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The MC33201/2/4 family of operational amplifiers provide
rail−to−railoperation on both the input and output. The inputs can be
driven as high as 200 mV beyond the supply rails without phase
reversal on the outputs, and the output can swing within 50 mV of each
rail. This rail−to−rail operation enables the user to make full use of the
supply voltage range available. It is designed to work at very low
supply voltages (± 0.9 V) yet can operate with a supply of up to +12 V
and ground. Output current boosting techniques provide a high output
current capability while keeping the drain current of the amplifier to a
minimum. Also, the combination of low noise and distortion with a
high slew rate and drive capability make this an ideal amplifier for
audio applications.
PDIP−8
P, VP SUFFIX
CASE 626
8
1
SOIC−8
D, VD SUFFIX
CASE 751
8
1
Micro8]
DM SUFFIX
CASE 846A
• Low Voltage, Single Supply Operation
(+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
8
1
• Output Voltage Swings within 50 mV of both Rails
• No Phase Reversal on the Output for Over−driven Input Signals
PDIP−14
P, VP SUFFIX
CASE 646
• High Output Current (I = 80 mA, Typ)
SC
• Low Supply Current (I = 0.9 mA, Typ)
D
14
• 600 W Output Drive Capability
1
• Extended Operating Temperature Ranges
(−40° to +105°C and −55° to +125°C)
SOIC−14
D, VD SUFFIX
CASE 751A
• Typical Gain Bandwidth Product = 2.2 MHz
• Pb−Free Packages are Available
14
1
TSSOP−14
DTB SUFFIX
CASE 948G
14
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 11 of this data sheet.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
March, 2004 − Rev. 12
MC33201/D
MC33201, MC33202, MC33204, NCV33202, NCV33204
PIN CONNECTIONS
MC33201
MC33204
All Case Styles
All Case Styles
Output 1
Inputs 1
1
2
3
4
5
6
7
14 Output 4
1
2
3
4
8
7
6
5
NC
V
NC
13
Inputs 4
12
1
2
4
3
CC
Inputs
Output
NC
V
CC
11
10
9
V
EE
V
EE
Inputs 2
Output 2
Inputs 3
Output 3
(Top View)
8
MC33202
All Case Styles
(Top View)
Output 1
1
2
3
4
8
7
6
5
V
CC
Output 2
1
Inputs 1
Inputs 2
2
V
EE
(Top View)
V
CC
V
CC
V
EE
V
CC
V
inꢀ−
V
out
V
CC
V
inꢀ+
V
EE
This device contains 70 active transistors (each amplifier).
Figure 1. Circuit Schematic
(Each Amplifier)
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2
MC33201, MC33202, MC33204, NCV33202, NCV33204
MAXIMUM RATINGS
Rating
Symbol
Value
+13
Unit
V
Supply Voltage (V to V
)
V
S
CC
EE
Input Differential Voltage Range
V
IDR
Note 1
V
Common Mode Input Voltage Range (Note 2)
V
CM
V
CC
+ 0.5 V to
V
V
EE
− 0.5 V
Output Short Circuit Duration
Maximum Junction Temperature
Storage Temperature
t
Note 3
+150
sec
°C
s
T
J
T
stg
− 65 to +150
Note 3
°C
Maximum Power Dissipation
P
mW
D
DC ELECTRICAL CHARACTERISTICS (T = 25°C)
A
Characteristic
V
CC
= 2.0 V
V
CC
= 3.3 V
V = 5.0 V
CC
Unit
Input Offset Voltage
mV
V
IO (max)
MC33201
± 8.0
± 8.0
± 6.0
MC33202, NCV33202
MC33204
±10
±12
±10
±12
± 8.0
±10
Output Voltage Swing
V
OH
V
OL
(R = 10 kW)
(R = 10 kW)
L
1.9
0.10
3.15
0.15
4.85
0.15
V
min
V
max
L
Power Supply Current
per Amplifier (I )
mA
1.125
1.125
1.125
D
Specifications at V = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. V = GND.
CC
EE
DC ELECTRICAL CHARACTERISTICS (V = + 5.0 V, V = Ground, T = 25°C, unless otherwise noted.)
CC
EE
A
Characteristic
Figure
Symbol
Min
Typ
Max
Unit
Input Offset Voltage (V
0 V to 0.5 V, V
1.0 V to 5.0 V)
3
V
IO
mV
CM
CM
MC33201: T = + 25°C
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6.0
9.0
13
8.0
11
14
14
10
13
17
A
MC33201: T = − 40° to +105°C
A
MC33201V: T = − 55° to +125°C
A
MC33202: T = + 25°C
A
MC33202: T = − 40° to +105°C
A
MC33202V: T = − 55° to +125°C
A
NCV33202V: T = − 55° to +125°C (Note 4)
A
MC33204: T = + 25°C
A
MC33204: T = − 40° to +105°C
A
MC33204V: T = − 55° to +125°C
A
Input Offset Voltage Temperature Coefficient (R = 50 W)
4
DV /DT
mV/°C
S
IO
T = − 40° to +105°C
T = − 55° to +125°C
A
−
−
2.0
2.0
−
−
A
Input Bias Current (V
= 0 V to 0.5 V, V
= 1.0 V to 5.0 V)
5, 6
I
IB
nA
CM
CM
T = + 25°C
−
−
−
80
100
−
200
250
500
A
T = − 40° to +105°C
A
T = − 55° to +125°C
A
Input Offset Current (V
= 0 V to 0.5 V, V
= 1.0 V to 5.0 V)
−
−
I
nA
V
CM
CM
IO
T = + 25°C
−
−
−
5.0
10
−
50
100
200
A
T = − 40° to +105°C
A
T = − 55° to +125°C
A
Common Mode Input Voltage Range
V
ICR
V
EE
−
V
CC
1. The differential input voltage of each amplifier is limited by two internal parallel back−to−back diodes. For additional differential input voltage
range, use current limiting resistors in series with the input pins.
2. The input common mode voltage range is limited by internal diodes connected from the inputs to both supply rails. Therefore, the voltage
on either input must not exceed either supply rail by more than 500 mV.
3. Power dissipation must be considered to ensure maximum junction temperature (T ) is not exceeded. (See Figure 2)
J
4. NCV33202 and NCV33204 are qualified for automotive use.
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3
MC33201, MC33202, MC33204, NCV33202, NCV33204
DC ELECTRICAL CHARACTERISTICS (cont.) (V = + 5.0 V, V = Ground, T = 25°C, unless otherwise noted.)
CC
EE
A
Characteristic
Figure
Symbol
Min
Typ
Max
Unit
Large Signal Voltage Gain (V = + 5.0 V, V = − 5.0 V)
7
A
VOL
kV/V
CC
EE
R = 10 kW
R = 600 W
L
50
25
300
250
−
−
L
Output Voltage Swing (V = ± 0.2 V)
8, 9, 10
V
ID
R = 10 kW
V
V
4.85
−
4.75
−
4.95
0.05
4.85
0.15
−
0.15
−
L
OH
R = 10 kW
L
OL
R = 600 W
V
OH
L
R = 600 W
L
V
0.25
OL
Common Mode Rejection (V = 0 V to 5.0 V)
11
12
CMR
60
90
−
dB
in
Power Supply Rejection Ratio
PSRR
mV/V
V
/V = 5.0 V/GND to 3.0 V/GND
500
50
25
80
−
−
CC EE
Output Short Circuit Current (Source and Sink)
Power Supply Current per Amplifier (V = 0 V)
13, 14
15
I
mA
mA
SC
I
O
D
T = − 40° to +105°C
T = − 55° to +125°C
A
−
−
0.9
0.9
1.125
1.125
A
AC ELECTRICAL CHARACTERISTICS (V = + 5.0 V, V = Ground, T = 25°C, unless otherwise noted.)
CC
EE
A
Characteristic
Figure
Symbol
Min
Typ
Max
Unit
Slew Rate
(V = ± 2.5 V, V = − 2.0 V to + 2.0 V, R = 2.0 kW, A = +1.0)
16, 26
SR
V/ms
0.5
−
1.0
2.2
12
65
90
28
−
−
−
−
−
−
S
O
L
V
Gain Bandwidth Product (f = 100 kHz)
Gain Margin (R = 600 W, C = 0 pF)
17
GBW
MHz
dB
20, 21, 22
20, 21, 22
23
A
M
−
L
L
Phase Margin (R = 600 W, C = 0 pF)
O
−
Deg
dB
L
L
M
Channel Separation (f = 1.0 Hz to 20 kHz, A = 100)
CS
−
V
Power Bandwidth (V = 4.0 V , R = 600 W, THD ≤ 1 %)
BW
P
−
kHz
%
O
pp
L
Total Harmonic Distortion (R = 600 W, V = 1.0 V , A = 1.0)
24
THD
L
O
pp
V
f = 1.0 kHz
f = 10 kHz
−
−
0.002
0.008
−
−
Open Loop Output Impedance
(V = 0 V, f = 2.0 MHz, A = 10)
Z
W
O
−
−
−
100
200
8.0
−
−
−
O
V
Differential Input Resistance (V
= 0 V)
R
C
e
kW
CM
in
in
n
Differential Input Capacitance (V
= 0 V)
pF
CM
Equivalent Input Noise Voltage (R = 100 W)
25
25
S
nV/
Hz
f = 10 Hz
f = 1.0 kHz
−
−
25
20
−
−
Equivalent Input Noise Current
f = 10 Hz
i
n
pA/
Hz
−
−
0.8
0.2
−
−
f = 1.0 kHz
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MC33201, MC33202, MC33204, NCV33202, NCV33204
2500
2000
1500
1000
500
40
35
30
360 amplifiers tested from
3 (MC33204) wafer lots
ꢁV = +ꢀ5.0 V
ꢁV = Gnd
EE
ꢁT = 25°C
A
ꢁDIP Package
8 and 14 Pin DIP Pkg
CC
TSSOP−14 Pkg
25
SO−14 Pkg
20
15
10
5.0
0
SOIC−8
Pkg
0
−ꢀ55 −ꢀ40 −ꢀ25
0
25
50
85
125
−10 −ꢀ8.0 −ꢀ6.0 −ꢀ4.0 −ꢀ2.0
0
2.0 4.0 6.0 8.0
10
T , AMBIENT TEMPERATURE (°C)
A
V , INPUT OFFSET VOLTAGE (mV)
IO
Figure 2. Maximum Power Dissipation
versus Temperature
Figure 3. Input Offset Voltage Distribution
50
40
30
20
200
160
120
80
V
V
= +ꢀ5.0 V
= Gnd
360 amplifiers tested from
3 (MC33204) wafer lots
ꢁV = +ꢀ5.0 V
ꢁV = Gnd
EE
ꢁT = 25°C
A
ꢁDIP Package
CC
EE
CC
V
CM
= 0 V to 0.5 V
V
CM
> 1.0 V
10
0
40
0
−ꢀ55
−ꢀ40 −ꢀ25
0
25
70
85
125
−ꢀ50 −ꢀ40 −ꢀ30 −ꢀ20 −10
0
10
20
30
40
50
m
°
, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT ( V/ C)
TC
V
IO
T , AMBIENT TEMPERATURE (°C)
A
Figure 4. Input Offset Voltage
Temperature Coefficient Distribution
Figure 5. Input Bias Current
versus Temperature
150
100
300
260
50
0
220
180
140
100
−ꢀ50
−100
−150
−ꢀ200
−ꢀ250
V
V
= +ꢀ5.0 V
= Gnd
CC
V
V
= 12 V
= Gnd
CC
EE
EE
R = 600 W
L
DV = 0.5 V to 4.5 V
T = 25°C
A
O
0
2.0
V
4.0
6.0
8.0
10
12
−ꢀ55 −ꢀ40 −ꢀ25
0
25
70
85
105 125
, INPUT COMMON MODE VOLTAGE (V)
T , AMBIENT TEMPERATURE (°C)
CM
A
Figure 6. Input Bias Current
versus Common Mode Voltage
Figure 7. Open Loop Voltage Gain versus
Temperature
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MC33201, MC33202, MC33204, NCV33202, NCV33204
V
V
12
10
CC
R = 600 W
L
T = 25°C
A
T = −ꢀ55°C
A
T = 125°C
A
− 0.2 V
− 0.4 V
+ 0.4 V
+ 0.2 V
CC
T = 25°C
A
8.0
6.0
4.0
2.0
0
V
V
V
CC
EE
V
CC
V
EE
= +ꢀ5.0 V
= −ꢀ5.0 V
T = 25°C
A
EE
T = 125°C
A
T = −ꢀ55°C
A
V
EE
20
±1.0
±ꢀ2.0
±ꢀ3.0
, V SUPPLY VOLTAGE (V)
EE
±ꢀ4.0
±ꢀ5.0
±ꢀ6.0
0
5.0
10
I , LOAD CURRENT (mA)
15
V
CC
L
Figure 8. Output Voltage Swing
versus Supply Voltage
Figure 9. Output Saturation Voltage
versus Load Current
12
9.0
6.0
100
80
60
40
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
CC
EE
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
CC
R = 600 W
L
A = +1.0
T = 25°C
A
3.0
0
EE
20
0
V
T = −ꢀ55° to +125°C
A
10
1.0 k
10 k
100 k
1.0 M
100
1.0 k
10 k
100 k
1.0 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 10. Output Voltage
versus Frequency
Figure 11. Common Mode Rejection
versus Frequency
120
100
80
60
40
20
0
100
80
60
40
20
0
Source
PSR+
PSR−
Sink
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
CC
EE
CC
EE
T = 25°C
A
T = −ꢀ55° to +125°C
A
10
0
1.0
2.0
3.0
4.0
5.0
6.0
100
1.0 k
10 k
100 k
1.0 M
f, FREQUENCY (Hz)
V
out
, OUTPUT VOLTAGE (V)
Figure 12. Power Supply Rejection
versus Frequency
Figure 13. Output Short Circuit Current
versus Output Voltage
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MC33201, MC33202, MC33204, NCV33202, NCV33204
2.0
1.6
150
125
V
CC
V
EE
= +ꢀ5.0 V
= Gnd
T = 125°C
100
75
50
25
0
A
Source
Sink
1.2
T = 25°C
A
0.8
0.4
0
T = −ꢀ55°C
A
−ꢀ55 −ꢀ40 −ꢀ25
0
25
70 85
105 125
±ꢀ0
±1.0
±ꢀ2.0
±ꢀ3.0
±ꢀ4.0
±ꢀ5.0
±ꢀ6.0
T , AMBIENT TEMPERATURE (°C)
A
V
CC
,
V
EE
, SUPPLY VOLTAGE (V)
Figure 14. Output Short Circuit Current
versus Temperature
Figure 15. Supply Current per Amplifier
versus Supply Voltage with No Load
2.0
4.0
3.0
2.0
1.0
0
V
V
V
= +ꢀ2.5 V
= −ꢀ2.5 V
= ±ꢀ2.0 V
V
V
= +ꢀ2.5 V
= −ꢀ2.5 V
CC
CC
EE
EE
f = 100 kHz
O
1.5
1.0
0.5
0
+Slew Rate
−Slew Rate
−ꢀ55 −ꢀ40 −ꢀ25
0
25
70 85
105 125
−ꢀ55 −ꢀ40 −ꢀ25
0
25
70 85
105 125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 16. Slew Rate
versus Temperature
Figure 17. Gain Bandwidth Product
versus Temperature
70
50
40
80
70
50
40
80
V = ±ꢀ6.0 V
C = 0 pF
L
S
T = 25°C
T = 25°C
A
R = 600 W
A
R = 600 W
L
L
30
10
120
160
200
240
30
10
120
160
1A
1A
2A
2A
2B
1B
1A − Phase, C = 0 pF
L
1B − Gain, C = 0 pF
1A − Phase, V = ±ꢀ6.0 V
S
2B
1B
L
2A − Phase, C = 300 pF
1B − Gain, V = ±ꢀ6.0 V
−10
S
−10
200
240
L
2B − Gain, C = 300 pF
2A − Phase, V = ±ꢀ1.0 V
S
L
2B − Gain, V = ±ꢀ1.0 V
S
−ꢀ30
−ꢀ30
10 k
100 k
1.0 M
10 M
10 k
100 k
1.0 M
10 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 18. Voltage Gain and Phase
versus Frequency
Figure 19. Voltage Gain and Phase
versus Frequency
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MC33201, MC33202, MC33204, NCV33202, NCV33204
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
75
60
75
60
Phase Margin
Phase Margin
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
T = 25°C
CC
45
30
45
30
15
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
CC
EE
EE
A
R = 600 W
L
C = 100 pF
L
15
0
Gain Margin
Gain Margin
0
100 k
−ꢀ55 −ꢀ40 −ꢀ25
0
25
70 85
105 125
10
100
1.0 k
10 k
T , AMBIENT TEMPERATURE (°C)
A
R , DIFFERENTIAL SOURCE RESISTANCE (W)
T
Figure 20. Gain and Phase Margin
versus Temperature
Figure 21. Gain and Phase Margin
versus Differential Source Resistance
80
70
60
50
40
30
20
10
0
16
14
12
10
8.0
6.0
4.0
2.0
0
150
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
CC
EE
A = 100
V
Phase Margin
Gain Margin
R = 600 W
L
A = 100
120
90
60
30
0
V
T = 25°C
A
A = 10
V
V
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
CC
EE
= 8.0 V
O
pp
T = 25°C
A
10
100
C , CAPACITIVE LOAD (pF)
1.0 k
100
1.0 k
f, FREQUENCY (Hz)
10 k
L
Figure 22. Gain and Phase Margin
versus Capacitive Load
Figure 23. Channel Separation
versus Frequency
10
50
40
5.0
4.0
V
= −ꢀ5.0 V
R = 600 W
V
= +ꢀ5.0 V
EE
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
CC
CC
T = 25°C
L
A
EE
V
O
= 2.0 V
T = 25°C
A
pp
1.0
A = 1000
V
30
20
10
3.0
2.0
1.0
0
A = 100
V
0.1
0.01
Noise Voltage
Noise Current
A = 10
V
A = 1.0
V
0
10
0.001
10
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
Figure 24. Total Harmonic Distortion
versus Frequency
Figure 25. Equivalent Input Noise Voltage
and Current versus Frequency
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MC33201, MC33202, MC33204, NCV33202, NCV33204
DETAILED OPERATING DESCRIPTION
General Information
Circuit Information
The MC33201/2/4 family of operational amplifiers are
unique in their ability to swing rail−to−rail on both the input
and the output with a completely bipolar design. This offers
low noise, high output current capability and a wide
common mode input voltage range even with low supply
voltages. Operation is guaranteed over an extended
temperature range and at supply voltages of 2.0 V, 3.3 V and
5.0 V and ground.
Rail−to−rail performance is achieved at the input of the
amplifiers by using parallel NPN−PNP differential input
stages. When the inputs are within 800 mV of the negative
rail, the PNP stage is on. When the inputs are more than 800
mV greater than V , the NPN stage is on. This switching of
EE
input pairs will cause a reversal of input bias currents (see
Figure 6). Also, slight differences in offset voltage may be
noted between the NPN and PNP pairs. Cross−coupling
techniques have been used to keep this change to a minimum.
In addition to its rail−to−rail performance, the output stage
is current boosted to provide 80 mA of output current,
enabling the op amp to drive 600 W loads. Because of this
high output current capability, care should be taken not to
exceed the 150°C maximum junction temperature.
Since the common mode input voltage range extends from
V
CC
to V , it can be operated with either single or split
EE
voltage supplies. The MC33201/2/4 are guaranteed not to
latch or phase reverse over the entire common mode range,
however, the inputs should not be allowed to exceed
maximum ratings.
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
V
V
= +ꢀ6.0 V
= −ꢀ6.0 V
CC
CC
EE
EE
R = 600 W
L
C = 100 pF
R = 600 W
L
C = 100 pF
L
L
T = 25°C
A
T = 25°C
A
t, TIME (5.0 ms/DIV)
t, TIME (10 ms/DIV)
Figure 26. Noninverting Amplifier Slew Rate
Figure 27. Small Signal Transient Response
V
CC
V
EE
= +ꢀ6.0 V
= −ꢀ6.0 V
R = 600 W
L
C = 100 pF
L
A = 1.0
V
T = 25°C
A
t, TIME (10 ms/DIV)
Figure 28. Large Signal Transient Response
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self−align when subjected to a
solder reflow process.
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9
MC33201, MC33202, MC33204, NCV33202, NCV33204
ORDERING INFORMATION
Operational
Amplifier Function
Operating
Temperature Range
†
Device
MC33201D
Package
SOIC−8
SOIC−8
PDIP−8
SOIC−8
SOIC−8
Shipping
Single
T = −40° to +105°C
98 Units / Rail
2500 Units / Tape & Reel
50 Units / Rail
A
MC33201DR2
MC33201P
MC33201VD
MC33202D
T = −55° to 125°C
98 Units / Rail
A
Dual
T = −40 ° to +105°C
98 Units / Rail
A
SOIC−8
(Pb−Free)
MC33202DG
MC33202DR2
MC33202DR2G
SOIC−8
2500 Units / Tape & Reel
SOIC−8
(Pb−Free)
Dual
MC33202DMR2
MC33202P
T = −40 ° to +105°C
Micro−8
PDIP−8
SOIC−8
SOIC−8
SOIC−8
PDIP−8
SO−14
4000 Units / Tape & Reel
50 Units / Rail
A
MC33202VD
T = −55° to 125°C
A
98 Units / Rail
MC33202VDR2
NCV33202VDR2*
MC33202VP
2500 Units / Tape & Reel
2500 Units / Tape & Reel
50 Units / Rail
Quad
MC33204D
T = −40 ° to +105°C
A
55 Units / Rail
MC33204DR2
MC33204DTB
MC33204DTBR2
MC33204P
SO−14
2500 Units / Tape & Reel
96 Units / Rail
TSSOP−14
TSSOP−14
PDIP−14
SO−14
2500 Units / Tape & Reel
25 Units / Rail
MC33204VD
T = −55° to 125°C
A
55 Units / Rail
MC33204VDR2
NCV33204DR2*
NCV33204DTBR2*
MC33204VP
SO−14
2500 Units / Tape & Reel
2500 Units / Tape & Reel
2500 Units / Tape & Reel
25 Units / Rail
SO−14
TSSOP−14
PDIP−14
*NCV33202 and NCV33204 are qualified for automotive use.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
MC33201, MC33202, MC33204, NCV33202, NCV33204
MARKING DIAGRAMS
PDIP−8
P SUFFIX
CASE 626
PDIP−8
VP SUFFIX
CASE 626
Micro−8
DM SUFFIX
CASE 846A
SOIC−8
D SUFFIX
CASE 751
SOIC−8
VD SUFFIX
CASE 751
SO−14
D SUFFIX
CASE 751A
8
1
8
8
1
8
1
8
14
*
MC3320xP
AWL
MC33202VP
AWL
3320x
ALYW
320xV
ALYW
3202
AYW
MC33204D
AWLYWW
YYWW
YYWW
1
1
1
SO−14
VD SUFFIX
CASE 751A
PDIP−14
P SUFFIX
CASE 646
PDIP−14
VP SUFFIX
CASE 646
TSSOP−14
DTB SUFFIX
CASE 948G
14
14
14
1
14
1
14
1
*
*
MC33204P
AWLYYWW
MC33204VP
AWLYYWW
MC33204VD
AWLYWW
MC33
204
ALYW
MC33
204V
ALYW
1
1
x
= 1 or 2
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
*This marking diagram applies to NCV3320x
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11
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
PDIP−8
P, VP SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
8
5
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−B−
MILLIMETERS
INCHES
MIN
0.370
1
4
DIM MIN
MAX
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
10.16
6.60 0.240
4.45 0.155
0.51 0.015
1.78 0.040
F
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27 0.030
0.30 0.008
3.43
0.050
0.012
0.135
K
L
0.115
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
−−−
1.01 0.030
10
0.040
_
_
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
B
0.13 (0.005)
T
A
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12
MC33201, MC33202, MC33204, NCV33202, NCV33204
SOIC−8
D, VD SUFFIX
CASE 751−07
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
G
MILLIMETERS
INCHES
DIM MIN
MAX
5.00
4.00
1.75
0.51
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
4.80
3.80
1.35
0.33
0.189
0.150
0.053
0.013
0.050 BSC
0.004
0.007
0.016
0
0.010
0.228
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25
0.25
1.27
8
0.010
0.010
0.050
8
M
J
H
D
K
M
N
S
_
_
_
_
0.25
5.80
0.50
6.20
0.020
0.244
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
SOIC−8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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13
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
Micro8
DM SUFFIX
CASE 846A−02
ISSUE F
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
−B−
K
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
PIN 1 ID
5. 846A−01 OBSOLETE, NEW STANDARD 846A−02.
G
D 8 PL
MILLIMETERS
INCHES
M
S
S
0.08 (0.003)
T
B
A
DIM MIN
MAX
3.10
3.10
1.10
MIN
MAX
0.122
0.122
0.043
0.016
A
B
C
D
G
H
J
2.90
2.90
−−−
0.25
0.65 BSC
0.05
0.13
4.75
0.40
0.114
0.114
−−−
0.40 0.010
SEATING
PLANE
0.026 BSC
−T−
0.15 0.002
0.23 0.005
5.05 0.187
0.70 0.016
0.006
0.009
0.199
0.028
C
0.038 (0.0015)
K
L
L
J
H
STYLE 1:
STYLE 2:
STYLE 3:
PIN 1. SOURCE
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
SOLDERING FOOTPRINT*
1.04
8X 0.041
0.38
8X
0.015
3.20
4.24
5.28
0.126
0.167 0.208
0.65
6X0.0256
SCALE 8:1
mm
inches
ǒ
Ǔ
Micro8E
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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14
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
PDIP−14
P, VP SUFFIX
CASE 646−06
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
8
7
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
INCHES
DIM MIN MAX
MILLIMETERS
A
F
MIN
18.16
6.10
3.69
0.38
1.02
MAX
18.80
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
0.770
0.260
0.185
0.021
0.070
L
N
C
G
H
J
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10 −−−
_
1.32
0.20
2.92
7.37
2.41
0.38
3.43
7.87
−T−
SEATING
PLANE
K
L
J
K
M
N
10
_
0.015
0.039
0.38
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
SOIC−14
D, VD SUFFIX
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
14
8
7
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.344
0.157
0.068
0.019
0.049
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
G
F
R X 45
_
C
G
J
1.27 BSC
0.050 BSC
−T−
SEATING
PLANE
J
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
M
K
D 14 PL
K
M
P
R
7
0
_
_
_
_
M
S
S
A
0.25 (0.010)
T
B
5.80
0.25
6.20 0.228
0.50 0.010
0.244
0.019
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15
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
TSSOP−14
DTB SUFFIX
CASE 948G−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
14X K REF
M
S
S
0.10 (0.004)
T
U
V
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
−U−
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
L
N
PIN 1
IDENT.
F
7
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN
K1
MAX
0.200
0.177
0.047
0.006
0.030
−V−
A
B
4.90
4.30
−−−
5.10 0.193
4.50 0.169
1.20
J J1
C
−−−
D
0.05
0.50
0.15 0.002
0.75 0.020
F
SECTION N−N
G
H
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60 0.020
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.024
0.008
0.006
0.012
0.010
J
J1
K
−W−
C
K1
L
6.40 BSC
_
0.252 BSC
0
0.10 (0.004)
M
0
8
8
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
Micro8 is a trademark of International Rectifier.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC33201/D
相关型号：
NCV33269DTRK-012
IC VREG 12 V FIXED POSITIVE LDO REGULATOR, 1.35 V DROPOUT, PSSO2, DPAK-3, Fixed Positive Single Output LDO Regulator
ONSEMI
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